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1/*
2 * Copyright (C) 2015 Phytec Messtechnik GmbH
3 * Author: Teresa Remmet <t.remmet@phytec.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "am33xx.dtsi"
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 model = "Phytec AM335x phyCORE";
15 compatible = "phytec,am335x-phycore-som", "ti,am33xx";
16
17 aliases {
18 rtc0 = &i2c_rtc;
19 rtc1 = &rtc;
20 };
21
22 cpus {
23 cpu@0 {
24 cpu0-supply = <&vdd1_reg>;
25 };
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x80000000 0x10000000>; /* 256 MB */
31 };
32
33 regulators {
34 compatible = "simple-bus";
35
36 vcc5v: fixedregulator@0 {
37 compatible = "regulator-fixed";
38 regulator-name = "vcc5v";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 regulator-boot-on;
42 regulator-always-on;
43 };
44 };
45};
46
47/* Crypto Module */
48&aes {
49 status = "okay";
50};
51
52&sham {
53 status = "okay";
54};
55
56/* Ethernet */
57&am33xx_pinmux {
58 ethernet0_pins: pinmux_ethernet0 {
59 pinctrl-single,pins = <
60 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
61 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
62 AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
63 AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
64 AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
65 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
66 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
67 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
68 >;
69 };
70
71 mdio_pins: pinmux_mdio {
72 pinctrl-single,pins = <
73 /* MDIO */
74 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
75 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
76 >;
77 };
78};
79
80&cpsw_emac0 {
81 phy_id = <&davinci_mdio>, <0>;
82 phy-mode = "rmii";
83 dual_emac_res_vlan = <1>;
84};
85
86&davinci_mdio {
87 pinctrl-names = "default";
88 pinctrl-0 = <&mdio_pins>;
89 status = "okay";
90};
91
92&mac {
93 slaves = <1>;
94 pinctrl-names = "default";
95 pinctrl-0 = <ðernet0_pins>;
96 status = "okay";
97};
98
99&phy_sel {
100 rmii-clock-ext;
101};
102
103/* I2C Busses */
104&am33xx_pinmux {
105 i2c0_pins: pinmux_i2c0 {
106 pinctrl-single,pins = <
107 AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
108 AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
109 >;
110 };
111};
112
113&i2c0 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&i2c0_pins>;
116 clock-frequency = <400000>;
117 status = "okay";
118
119 tps: pmic@2d {
120 reg = <0x2d>;
121 };
122
123 i2c_eeprom: eeprom@52 {
124 compatible = "atmel,24c32";
125 pagesize = <32>;
126 reg = <0x52>;
127 status = "disabled";
128 };
129
130 i2c_rtc: rtc@68 {
131 compatible = "rv4162";
132 reg = <0x68>;
133 status = "disabled";
134 };
135};
136
137/* NAND memory */
138&am33xx_pinmux {
139 nandflash_pins: pinmux_nandflash {
140 pinctrl-single,pins = <
141 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
142 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
143 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
144 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
145 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
146 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
147 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
148 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
149 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
150 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
151 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
152 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
153 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
154 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
155 >;
156 };
157};
158
159&elm {
160 status = "okay";
161};
162
163&gpmc {
164 status = "okay";
165 pinctrl-names = "default";
166 pinctrl-0 = <&nandflash_pins>;
167 ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
168 nandflash: nand@0,0 {
169 compatible = "ti,omap2-nand";
170 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
171 interrupt-parent = <&gpmc>;
172 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
173 <1 IRQ_TYPE_NONE>; /* termcount */
174 nand-bus-width = <8>;
175 ti,nand-ecc-opt = "bch8";
176 gpmc,device-nand = "true";
177 gpmc,device-width = <1>;
178 gpmc,sync-clk-ps = <0>;
179 gpmc,cs-on-ns = <0>;
180 gpmc,cs-rd-off-ns = <30>;
181 gpmc,cs-wr-off-ns = <30>;
182 gpmc,adv-on-ns = <0>;
183 gpmc,adv-rd-off-ns = <30>;
184 gpmc,adv-wr-off-ns = <30>;
185 gpmc,we-on-ns = <0>;
186 gpmc,we-off-ns = <20>;
187 gpmc,oe-on-ns = <10>;
188 gpmc,oe-off-ns = <30>;
189 gpmc,access-ns = <30>;
190 gpmc,rd-cycle-ns = <30>;
191 gpmc,wr-cycle-ns = <30>;
192 gpmc,bus-turnaround-ns = <0>;
193 gpmc,cycle2cycle-delay-ns = <50>;
194 gpmc,cycle2cycle-diffcsen;
195 gpmc,clk-activation-ns = <0>;
196 gpmc,wr-access-ns = <30>;
197 gpmc,wr-data-mux-bus-ns = <0>;
198
199 elm_id = <&elm>;
200
201 #address-cells = <1>;
202 #size-cells = <1>;
203
204 partition@0 {
205 label = "xload";
206 reg = <0x0 0x20000>;
207 };
208 partition@1 {
209 label = "xload_backup1";
210 reg = <0x20000 0x20000>;
211 };
212 partition@2 {
213 label = "xload_backup2";
214 reg = <0x40000 0x20000>;
215 };
216 partition@3 {
217 label = "xload_backup3";
218 reg = <0x60000 0x20000>;
219 };
220 partition@4 {
221 label = "barebox";
222 reg = <0x80000 0x80000>;
223 };
224 partition@5 {
225 label = "bareboxenv";
226 reg = <0x100000 0x40000>;
227 };
228 partition@6 {
229 label = "oftree";
230 reg = <0x140000 0x40000>;
231 };
232 partition@7 {
233 label = "kernel";
234 reg = <0x180000 0x800000>;
235 };
236 partition@8 {
237 label = "root";
238 reg = <0x980000 0x0>;
239 };
240 };
241};
242
243/* Power */
244#include "tps65910.dtsi"
245
246&tps {
247 vcc1-supply = <&vcc5v>;
248 vcc2-supply = <&vcc5v>;
249 vcc3-supply = <&vcc5v>;
250 vcc4-supply = <&vcc5v>;
251 vcc5-supply = <&vcc5v>;
252 vcc6-supply = <&vcc5v>;
253 vcc7-supply = <&vcc5v>;
254 vccio-supply = <&vcc5v>;
255
256 regulators {
257 vrtc_reg: regulator@0 {
258 regulator-always-on;
259 };
260
261 vio_reg: regulator@1 {
262 regulator-always-on;
263 };
264
265 vdd1_reg: regulator@2 {
266 /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
267 regulator-name = "vdd_mpu";
268 regulator-min-microvolt = <912500>;
269 regulator-max-microvolt = <1378000>;
270 regulator-boot-on;
271 regulator-always-on;
272 };
273
274 vdd2_reg: regulator@3 {
275 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
276 regulator-name = "vdd_core";
277 regulator-min-microvolt = <912500>;
278 regulator-max-microvolt = <1150000>;
279 regulator-boot-on;
280 regulator-always-on;
281 };
282
283 vdd3_reg: regulator@4 {
284 regulator-always-on;
285 };
286
287 vdig1_reg: regulator@5 {
288 regulator-name = "vdig1_1p8v";
289 regulator-min-microvolt = <1800000>;
290 regulator-max-microvolt = <1800000>;
291 };
292
293 vdig2_reg: regulator@6 {
294 regulator-always-on;
295 };
296
297 vpll_reg: regulator@7 {
298 regulator-always-on;
299 };
300
301 vdac_reg: regulator@8 {
302 regulator-always-on;
303 };
304
305 vaux1_reg: regulator@9 {
306 regulator-always-on;
307 };
308
309 vaux2_reg: regulator@10 {
310 regulator-always-on;
311 };
312
313 vaux33_reg: regulator@11 {
314 regulator-always-on;
315 };
316
317 vmmc_reg: regulator@12 {
318 regulator-min-microvolt = <3300000>;
319 regulator-max-microvolt = <3300000>;
320 regulator-always-on;
321 };
322 };
323};
324
325/* SPI Busses */
326&am33xx_pinmux {
327 spi0_pins: pinmux_spi0 {
328 pinctrl-single,pins = <
329 AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
330 AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
331 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
332 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
333 >;
334 };
335};
336
337&spi0 {
338 pinctrl-names = "default";
339 pinctrl-0 = <&spi0_pins>;
340 status = "okay";
341
342 serial_flash: m25p80@0 {
343 compatible = "m25p80";
344 spi-max-frequency = <48000000>;
345 reg = <0x0>;
346 m25p,fast-read;
347 status = "disabled";
348 #address-cells = <1>;
349 #size-cells = <1>;
350
351 partition@0 {
352 label = "xload";
353 reg = <0x0 0x20000>;
354 };
355 partition@1 {
356 label = "barebox";
357 reg = <0x20000 0x80000>;
358 };
359 partition@2 {
360 label = "bareboxenv";
361 reg = <0xa0000 0x20000>;
362 };
363 partition@3 {
364 label = "oftree";
365 reg = <0xc0000 0x20000>;
366 };
367 partition@4 {
368 label = "kernel";
369 reg = <0xe0000 0x0>;
370 };
371 };
372};