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1// SPDX-License-Identifier: GPL-2.0-only
2/* Low-level parallel-port routines for 8255-based PC-style hardware.
3 *
4 * Authors: Phil Blundell <philb@gnu.org>
5 * Tim Waugh <tim@cyberelk.demon.co.uk>
6 * Jose Renau <renau@acm.org>
7 * David Campbell
8 * Andrea Arcangeli
9 *
10 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11 *
12 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
13 * DMA support - Bert De Jonghe <bert@sophis.be>
14 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
15 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
16 * Various hacks, Fred Barnes, 04/2001
17 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
18 */
19
20/* This driver should work with any hardware that is broadly compatible
21 * with that in the IBM PC. This applies to the majority of integrated
22 * I/O chipsets that are commonly available. The expected register
23 * layout is:
24 *
25 * base+0 data
26 * base+1 status
27 * base+2 control
28 *
29 * In addition, there are some optional registers:
30 *
31 * base+3 EPP address
32 * base+4 EPP data
33 * base+0x400 ECP config A
34 * base+0x401 ECP config B
35 * base+0x402 ECP control
36 *
37 * All registers are 8 bits wide and read/write. If your hardware differs
38 * only in register addresses (eg because your registers are on 32-bit
39 * word boundaries) then you can alter the constants in parport_pc.h to
40 * accommodate this.
41 *
42 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
43 * but rather will start at port->base_hi.
44 */
45
46#include <linux/module.h>
47#include <linux/init.h>
48#include <linux/sched/signal.h>
49#include <linux/delay.h>
50#include <linux/errno.h>
51#include <linux/interrupt.h>
52#include <linux/ioport.h>
53#include <linux/kernel.h>
54#include <linux/slab.h>
55#include <linux/dma-mapping.h>
56#include <linux/pci.h>
57#include <linux/pnp.h>
58#include <linux/platform_device.h>
59#include <linux/sysctl.h>
60#include <linux/io.h>
61#include <linux/uaccess.h>
62
63#include <asm/dma.h>
64
65#include <linux/parport.h>
66#include <linux/parport_pc.h>
67#include <linux/via.h>
68#include <asm/parport.h>
69
70#define PARPORT_PC_MAX_PORTS PARPORT_MAX
71
72#ifdef CONFIG_ISA_DMA_API
73#define HAS_DMA
74#endif
75
76/* ECR modes */
77#define ECR_SPP 00
78#define ECR_PS2 01
79#define ECR_PPF 02
80#define ECR_ECP 03
81#define ECR_EPP 04
82#define ECR_VND 05
83#define ECR_TST 06
84#define ECR_CNF 07
85#define ECR_MODE_MASK 0xe0
86#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
87
88#undef DEBUG
89
90#define NR_SUPERIOS 3
91static struct superio_struct { /* For Super-IO chips autodetection */
92 int io;
93 int irq;
94 int dma;
95} superios[NR_SUPERIOS] = { {0,},};
96
97static int user_specified;
98#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
99 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
100static int verbose_probing;
101#endif
102static int pci_registered_parport;
103static int pnp_registered_parport;
104
105/* frob_control, but for ECR */
106static void frob_econtrol(struct parport *pb, unsigned char m,
107 unsigned char v)
108{
109 const struct parport_pc_private *priv = pb->physport->private_data;
110 unsigned char ecr_writable = priv->ecr_writable;
111 unsigned char ectr = 0;
112 unsigned char new;
113
114 if (m != 0xff)
115 ectr = inb(ECONTROL(pb));
116
117 new = (ectr & ~m) ^ v;
118 if (ecr_writable)
119 /* All known users of the ECR mask require bit 0 to be set. */
120 new = (new & ecr_writable) | 1;
121
122 pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", m, v, ectr, new);
123
124 outb(new, ECONTROL(pb));
125}
126
127static inline void frob_set_mode(struct parport *p, int mode)
128{
129 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
130}
131
132#ifdef CONFIG_PARPORT_PC_FIFO
133/* Safely change the mode bits in the ECR
134 Returns:
135 0 : Success
136 -EBUSY: Could not drain FIFO in some finite amount of time,
137 mode not changed!
138 */
139static int change_mode(struct parport *p, int m)
140{
141 const struct parport_pc_private *priv = p->physport->private_data;
142 unsigned char oecr;
143 int mode;
144
145 pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m);
146
147 if (!priv->ecr) {
148 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
149 return 0;
150 }
151
152 /* Bits <7:5> contain the mode. */
153 oecr = inb(ECONTROL(p));
154 mode = (oecr >> 5) & 0x7;
155 if (mode == m)
156 return 0;
157
158 if (mode >= 2 && !(priv->ctr & 0x20)) {
159 /* This mode resets the FIFO, so we may
160 * have to wait for it to drain first. */
161 unsigned long expire = jiffies + p->physport->cad->timeout;
162 int counter;
163 switch (mode) {
164 case ECR_PPF: /* Parallel Port FIFO mode */
165 case ECR_ECP: /* ECP Parallel Port mode */
166 /* Busy wait for 200us */
167 for (counter = 0; counter < 40; counter++) {
168 if (inb(ECONTROL(p)) & 0x01)
169 break;
170 if (signal_pending(current))
171 break;
172 udelay(5);
173 }
174
175 /* Poll slowly. */
176 while (!(inb(ECONTROL(p)) & 0x01)) {
177 if (time_after_eq(jiffies, expire))
178 /* The FIFO is stuck. */
179 return -EBUSY;
180 schedule_timeout_interruptible(
181 msecs_to_jiffies(10));
182 if (signal_pending(current))
183 break;
184 }
185 }
186 }
187
188 if (mode >= 2 && m >= 2) {
189 /* We have to go through mode 001 */
190 oecr &= ~(7 << 5);
191 oecr |= ECR_PS2 << 5;
192 ECR_WRITE(p, oecr);
193 }
194
195 /* Set the mode. */
196 oecr &= ~(7 << 5);
197 oecr |= m << 5;
198 ECR_WRITE(p, oecr);
199 return 0;
200}
201#endif /* FIFO support */
202
203/*
204 * Clear TIMEOUT BIT in EPP MODE
205 *
206 * This is also used in SPP detection.
207 */
208static int clear_epp_timeout(struct parport *pb)
209{
210 unsigned char r;
211
212 if (!(parport_pc_read_status(pb) & 0x01))
213 return 1;
214
215 /* To clear timeout some chips require double read */
216 parport_pc_read_status(pb);
217 r = parport_pc_read_status(pb);
218 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
219 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
220 r = parport_pc_read_status(pb);
221
222 return !(r & 0x01);
223}
224
225/*
226 * Access functions.
227 *
228 * Most of these aren't static because they may be used by the
229 * parport_xxx_yyy macros. extern __inline__ versions of several
230 * of these are in parport_pc.h.
231 */
232
233static void parport_pc_init_state(struct pardevice *dev,
234 struct parport_state *s)
235{
236 s->u.pc.ctr = 0xc;
237 if (dev->irq_func &&
238 dev->port->irq != PARPORT_IRQ_NONE)
239 /* Set ackIntEn */
240 s->u.pc.ctr |= 0x10;
241
242 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
243 * D.Gruszka VScom */
244}
245
246static void parport_pc_save_state(struct parport *p, struct parport_state *s)
247{
248 const struct parport_pc_private *priv = p->physport->private_data;
249 s->u.pc.ctr = priv->ctr;
250 if (priv->ecr)
251 s->u.pc.ecr = inb(ECONTROL(p));
252}
253
254static void parport_pc_restore_state(struct parport *p,
255 struct parport_state *s)
256{
257 struct parport_pc_private *priv = p->physport->private_data;
258 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
259 outb(c, CONTROL(p));
260 priv->ctr = c;
261 if (priv->ecr)
262 ECR_WRITE(p, s->u.pc.ecr);
263}
264
265#ifdef CONFIG_PARPORT_1284
266static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
267 size_t length, int flags)
268{
269 size_t got = 0;
270
271 if (flags & PARPORT_W91284PIC) {
272 unsigned char status;
273 size_t left = length;
274
275 /* use knowledge about data lines..:
276 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
277 * pError is 1 if there are 16 bytes in the Warp's FIFO
278 */
279 status = inb(STATUS(port));
280
281 while (!(status & 0x08) && got < length) {
282 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
283 /* can grab 16 bytes from warp fifo */
284 if (!((long)buf & 0x03))
285 insl(EPPDATA(port), buf, 4);
286 else
287 insb(EPPDATA(port), buf, 16);
288 buf += 16;
289 got += 16;
290 left -= 16;
291 } else {
292 /* grab single byte from the warp fifo */
293 *((char *)buf) = inb(EPPDATA(port));
294 buf++;
295 got++;
296 left--;
297 }
298 status = inb(STATUS(port));
299 if (status & 0x01) {
300 /* EPP timeout should never occur... */
301 printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n",
302 port->name);
303 clear_epp_timeout(port);
304 }
305 }
306 return got;
307 }
308 if ((length > 1) && ((flags & PARPORT_EPP_FAST_32)
309 || flags & PARPORT_EPP_FAST_16
310 || flags & PARPORT_EPP_FAST_8)) {
311 if ((flags & PARPORT_EPP_FAST_32)
312 && !(((long)buf | length) & 0x03))
313 insl(EPPDATA(port), buf, (length >> 2));
314 else if ((flags & PARPORT_EPP_FAST_16)
315 && !(((long)buf | length) & 0x01))
316 insw(EPPDATA(port), buf, length >> 1);
317 else
318 insb(EPPDATA(port), buf, length);
319 if (inb(STATUS(port)) & 0x01) {
320 clear_epp_timeout(port);
321 return -EIO;
322 }
323 return length;
324 }
325 for (; got < length; got++) {
326 *((char *)buf) = inb(EPPDATA(port));
327 buf++;
328 if (inb(STATUS(port)) & 0x01) {
329 /* EPP timeout */
330 clear_epp_timeout(port);
331 break;
332 }
333 }
334
335 return got;
336}
337
338static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
339 size_t length, int flags)
340{
341 size_t written = 0;
342
343 if ((length > 1) && ((flags & PARPORT_EPP_FAST_32)
344 || flags & PARPORT_EPP_FAST_16
345 || flags & PARPORT_EPP_FAST_8)) {
346 if ((flags & PARPORT_EPP_FAST_32)
347 && !(((long)buf | length) & 0x03))
348 outsl(EPPDATA(port), buf, (length >> 2));
349 else if ((flags & PARPORT_EPP_FAST_16)
350 && !(((long)buf | length) & 0x01))
351 outsw(EPPDATA(port), buf, length >> 1);
352 else
353 outsb(EPPDATA(port), buf, length);
354 if (inb(STATUS(port)) & 0x01) {
355 clear_epp_timeout(port);
356 return -EIO;
357 }
358 return length;
359 }
360 for (; written < length; written++) {
361 outb(*((char *)buf), EPPDATA(port));
362 buf++;
363 if (inb(STATUS(port)) & 0x01) {
364 clear_epp_timeout(port);
365 break;
366 }
367 }
368
369 return written;
370}
371
372static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
373 size_t length, int flags)
374{
375 size_t got = 0;
376
377 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
378 insb(EPPADDR(port), buf, length);
379 if (inb(STATUS(port)) & 0x01) {
380 clear_epp_timeout(port);
381 return -EIO;
382 }
383 return length;
384 }
385 for (; got < length; got++) {
386 *((char *)buf) = inb(EPPADDR(port));
387 buf++;
388 if (inb(STATUS(port)) & 0x01) {
389 clear_epp_timeout(port);
390 break;
391 }
392 }
393
394 return got;
395}
396
397static size_t parport_pc_epp_write_addr(struct parport *port,
398 const void *buf, size_t length,
399 int flags)
400{
401 size_t written = 0;
402
403 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
404 outsb(EPPADDR(port), buf, length);
405 if (inb(STATUS(port)) & 0x01) {
406 clear_epp_timeout(port);
407 return -EIO;
408 }
409 return length;
410 }
411 for (; written < length; written++) {
412 outb(*((char *)buf), EPPADDR(port));
413 buf++;
414 if (inb(STATUS(port)) & 0x01) {
415 clear_epp_timeout(port);
416 break;
417 }
418 }
419
420 return written;
421}
422
423static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
424 size_t length, int flags)
425{
426 size_t got;
427
428 frob_set_mode(port, ECR_EPP);
429 parport_pc_data_reverse(port);
430 parport_pc_write_control(port, 0x4);
431 got = parport_pc_epp_read_data(port, buf, length, flags);
432 frob_set_mode(port, ECR_PS2);
433
434 return got;
435}
436
437static size_t parport_pc_ecpepp_write_data(struct parport *port,
438 const void *buf, size_t length,
439 int flags)
440{
441 size_t written;
442
443 frob_set_mode(port, ECR_EPP);
444 parport_pc_write_control(port, 0x4);
445 parport_pc_data_forward(port);
446 written = parport_pc_epp_write_data(port, buf, length, flags);
447 frob_set_mode(port, ECR_PS2);
448
449 return written;
450}
451
452static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
453 size_t length, int flags)
454{
455 size_t got;
456
457 frob_set_mode(port, ECR_EPP);
458 parport_pc_data_reverse(port);
459 parport_pc_write_control(port, 0x4);
460 got = parport_pc_epp_read_addr(port, buf, length, flags);
461 frob_set_mode(port, ECR_PS2);
462
463 return got;
464}
465
466static size_t parport_pc_ecpepp_write_addr(struct parport *port,
467 const void *buf, size_t length,
468 int flags)
469{
470 size_t written;
471
472 frob_set_mode(port, ECR_EPP);
473 parport_pc_write_control(port, 0x4);
474 parport_pc_data_forward(port);
475 written = parport_pc_epp_write_addr(port, buf, length, flags);
476 frob_set_mode(port, ECR_PS2);
477
478 return written;
479}
480#endif /* IEEE 1284 support */
481
482#ifdef CONFIG_PARPORT_PC_FIFO
483static size_t parport_pc_fifo_write_block_pio(struct parport *port,
484 const void *buf, size_t length)
485{
486 int ret = 0;
487 const unsigned char *bufp = buf;
488 size_t left = length;
489 unsigned long expire = jiffies + port->physport->cad->timeout;
490 const unsigned long fifo = FIFO(port);
491 int poll_for = 8; /* 80 usecs */
492 const struct parport_pc_private *priv = port->physport->private_data;
493 const int fifo_depth = priv->fifo_depth;
494
495 port = port->physport;
496
497 /* We don't want to be interrupted every character. */
498 parport_pc_disable_irq(port);
499 /* set nErrIntrEn and serviceIntr */
500 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
501
502 /* Forward mode. */
503 parport_pc_data_forward(port); /* Must be in PS2 mode */
504
505 while (left) {
506 unsigned char byte;
507 unsigned char ecrval = inb(ECONTROL(port));
508 int i = 0;
509
510 if (need_resched() && time_before(jiffies, expire))
511 /* Can't yield the port. */
512 schedule();
513
514 /* Anyone else waiting for the port? */
515 if (port->waithead) {
516 printk(KERN_DEBUG "Somebody wants the port\n");
517 break;
518 }
519
520 if (ecrval & 0x02) {
521 /* FIFO is full. Wait for interrupt. */
522
523 /* Clear serviceIntr */
524 ECR_WRITE(port, ecrval & ~(1<<2));
525false_alarm:
526 ret = parport_wait_event(port, HZ);
527 if (ret < 0)
528 break;
529 ret = 0;
530 if (!time_before(jiffies, expire)) {
531 /* Timed out. */
532 printk(KERN_DEBUG "FIFO write timed out\n");
533 break;
534 }
535 ecrval = inb(ECONTROL(port));
536 if (!(ecrval & (1<<2))) {
537 if (need_resched() &&
538 time_before(jiffies, expire))
539 schedule();
540
541 goto false_alarm;
542 }
543
544 continue;
545 }
546
547 /* Can't fail now. */
548 expire = jiffies + port->cad->timeout;
549
550poll:
551 if (signal_pending(current))
552 break;
553
554 if (ecrval & 0x01) {
555 /* FIFO is empty. Blast it full. */
556 const int n = left < fifo_depth ? left : fifo_depth;
557 outsb(fifo, bufp, n);
558 bufp += n;
559 left -= n;
560
561 /* Adjust the poll time. */
562 if (i < (poll_for - 2))
563 poll_for--;
564 continue;
565 } else if (i++ < poll_for) {
566 udelay(10);
567 ecrval = inb(ECONTROL(port));
568 goto poll;
569 }
570
571 /* Half-full(call me an optimist) */
572 byte = *bufp++;
573 outb(byte, fifo);
574 left--;
575 }
576 dump_parport_state("leave fifo_write_block_pio", port);
577 return length - left;
578}
579
580#ifdef HAS_DMA
581static size_t parport_pc_fifo_write_block_dma(struct parport *port,
582 const void *buf, size_t length)
583{
584 int ret = 0;
585 unsigned long dmaflag;
586 size_t left = length;
587 const struct parport_pc_private *priv = port->physport->private_data;
588 struct device *dev = port->physport->dev;
589 dma_addr_t dma_addr, dma_handle;
590 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
591 unsigned long start = (unsigned long) buf;
592 unsigned long end = (unsigned long) buf + length - 1;
593
594 dump_parport_state("enter fifo_write_block_dma", port);
595 if (end < MAX_DMA_ADDRESS) {
596 /* If it would cross a 64k boundary, cap it at the end. */
597 if ((start ^ end) & ~0xffffUL)
598 maxlen = 0x10000 - (start & 0xffff);
599
600 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
601 DMA_TO_DEVICE);
602 } else {
603 /* above 16 MB we use a bounce buffer as ISA-DMA
604 is not possible */
605 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
606 dma_addr = priv->dma_handle;
607 dma_handle = 0;
608 }
609
610 port = port->physport;
611
612 /* We don't want to be interrupted every character. */
613 parport_pc_disable_irq(port);
614 /* set nErrIntrEn and serviceIntr */
615 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
616
617 /* Forward mode. */
618 parport_pc_data_forward(port); /* Must be in PS2 mode */
619
620 while (left) {
621 unsigned long expire = jiffies + port->physport->cad->timeout;
622
623 size_t count = left;
624
625 if (count > maxlen)
626 count = maxlen;
627
628 if (!dma_handle) /* bounce buffer ! */
629 memcpy(priv->dma_buf, buf, count);
630
631 dmaflag = claim_dma_lock();
632 disable_dma(port->dma);
633 clear_dma_ff(port->dma);
634 set_dma_mode(port->dma, DMA_MODE_WRITE);
635 set_dma_addr(port->dma, dma_addr);
636 set_dma_count(port->dma, count);
637
638 /* Set DMA mode */
639 frob_econtrol(port, 1<<3, 1<<3);
640
641 /* Clear serviceIntr */
642 frob_econtrol(port, 1<<2, 0);
643
644 enable_dma(port->dma);
645 release_dma_lock(dmaflag);
646
647 /* assume DMA will be successful */
648 left -= count;
649 buf += count;
650 if (dma_handle)
651 dma_addr += count;
652
653 /* Wait for interrupt. */
654false_alarm:
655 ret = parport_wait_event(port, HZ);
656 if (ret < 0)
657 break;
658 ret = 0;
659 if (!time_before(jiffies, expire)) {
660 /* Timed out. */
661 printk(KERN_DEBUG "DMA write timed out\n");
662 break;
663 }
664 /* Is serviceIntr set? */
665 if (!(inb(ECONTROL(port)) & (1<<2))) {
666 cond_resched();
667
668 goto false_alarm;
669 }
670
671 dmaflag = claim_dma_lock();
672 disable_dma(port->dma);
673 clear_dma_ff(port->dma);
674 count = get_dma_residue(port->dma);
675 release_dma_lock(dmaflag);
676
677 cond_resched(); /* Can't yield the port. */
678
679 /* Anyone else waiting for the port? */
680 if (port->waithead) {
681 printk(KERN_DEBUG "Somebody wants the port\n");
682 break;
683 }
684
685 /* update for possible DMA residue ! */
686 buf -= count;
687 left += count;
688 if (dma_handle)
689 dma_addr -= count;
690 }
691
692 /* Maybe got here through break, so adjust for DMA residue! */
693 dmaflag = claim_dma_lock();
694 disable_dma(port->dma);
695 clear_dma_ff(port->dma);
696 left += get_dma_residue(port->dma);
697 release_dma_lock(dmaflag);
698
699 /* Turn off DMA mode */
700 frob_econtrol(port, 1<<3, 0);
701
702 if (dma_handle)
703 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
704
705 dump_parport_state("leave fifo_write_block_dma", port);
706 return length - left;
707}
708#endif
709
710static inline size_t parport_pc_fifo_write_block(struct parport *port,
711 const void *buf, size_t length)
712{
713#ifdef HAS_DMA
714 if (port->dma != PARPORT_DMA_NONE)
715 return parport_pc_fifo_write_block_dma(port, buf, length);
716#endif
717 return parport_pc_fifo_write_block_pio(port, buf, length);
718}
719
720/* Parallel Port FIFO mode (ECP chipsets) */
721static size_t parport_pc_compat_write_block_pio(struct parport *port,
722 const void *buf, size_t length,
723 int flags)
724{
725 size_t written;
726 int r;
727 unsigned long expire;
728 const struct parport_pc_private *priv = port->physport->private_data;
729
730 /* Special case: a timeout of zero means we cannot call schedule().
731 * Also if O_NONBLOCK is set then use the default implementation. */
732 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
733 return parport_ieee1284_write_compat(port, buf,
734 length, flags);
735
736 /* Set up parallel port FIFO mode.*/
737 parport_pc_data_forward(port); /* Must be in PS2 mode */
738 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
739 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
740 if (r)
741 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
742 port->name);
743
744 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
745
746 /* Write the data to the FIFO. */
747 written = parport_pc_fifo_write_block(port, buf, length);
748
749 /* Finish up. */
750 /* For some hardware we don't want to touch the mode until
751 * the FIFO is empty, so allow 4 seconds for each position
752 * in the fifo.
753 */
754 expire = jiffies + (priv->fifo_depth * HZ * 4);
755 do {
756 /* Wait for the FIFO to empty */
757 r = change_mode(port, ECR_PS2);
758 if (r != -EBUSY)
759 break;
760 } while (time_before(jiffies, expire));
761 if (r == -EBUSY) {
762
763 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
764
765 /* Prevent further data transfer. */
766 frob_set_mode(port, ECR_TST);
767
768 /* Adjust for the contents of the FIFO. */
769 for (written -= priv->fifo_depth; ; written++) {
770 if (inb(ECONTROL(port)) & 0x2) {
771 /* Full up. */
772 break;
773 }
774 outb(0, FIFO(port));
775 }
776
777 /* Reset the FIFO and return to PS2 mode. */
778 frob_set_mode(port, ECR_PS2);
779 }
780
781 r = parport_wait_peripheral(port,
782 PARPORT_STATUS_BUSY,
783 PARPORT_STATUS_BUSY);
784 if (r)
785 printk(KERN_DEBUG "%s: BUSY timeout (%d) in compat_write_block_pio\n",
786 port->name, r);
787
788 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
789
790 return written;
791}
792
793/* ECP */
794#ifdef CONFIG_PARPORT_1284
795static size_t parport_pc_ecp_write_block_pio(struct parport *port,
796 const void *buf, size_t length,
797 int flags)
798{
799 size_t written;
800 int r;
801 unsigned long expire;
802 const struct parport_pc_private *priv = port->physport->private_data;
803
804 /* Special case: a timeout of zero means we cannot call schedule().
805 * Also if O_NONBLOCK is set then use the default implementation. */
806 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
807 return parport_ieee1284_ecp_write_data(port, buf,
808 length, flags);
809
810 /* Switch to forward mode if necessary. */
811 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
812 /* Event 47: Set nInit high. */
813 parport_frob_control(port,
814 PARPORT_CONTROL_INIT
815 | PARPORT_CONTROL_AUTOFD,
816 PARPORT_CONTROL_INIT
817 | PARPORT_CONTROL_AUTOFD);
818
819 /* Event 49: PError goes high. */
820 r = parport_wait_peripheral(port,
821 PARPORT_STATUS_PAPEROUT,
822 PARPORT_STATUS_PAPEROUT);
823 if (r) {
824 printk(KERN_DEBUG "%s: PError timeout (%d) in ecp_write_block_pio\n",
825 port->name, r);
826 }
827 }
828
829 /* Set up ECP parallel port mode.*/
830 parport_pc_data_forward(port); /* Must be in PS2 mode */
831 parport_pc_frob_control(port,
832 PARPORT_CONTROL_STROBE |
833 PARPORT_CONTROL_AUTOFD,
834 0);
835 r = change_mode(port, ECR_ECP); /* ECP FIFO */
836 if (r)
837 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
838 port->name);
839 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
840
841 /* Write the data to the FIFO. */
842 written = parport_pc_fifo_write_block(port, buf, length);
843
844 /* Finish up. */
845 /* For some hardware we don't want to touch the mode until
846 * the FIFO is empty, so allow 4 seconds for each position
847 * in the fifo.
848 */
849 expire = jiffies + (priv->fifo_depth * (HZ * 4));
850 do {
851 /* Wait for the FIFO to empty */
852 r = change_mode(port, ECR_PS2);
853 if (r != -EBUSY)
854 break;
855 } while (time_before(jiffies, expire));
856 if (r == -EBUSY) {
857
858 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
859
860 /* Prevent further data transfer. */
861 frob_set_mode(port, ECR_TST);
862
863 /* Adjust for the contents of the FIFO. */
864 for (written -= priv->fifo_depth; ; written++) {
865 if (inb(ECONTROL(port)) & 0x2) {
866 /* Full up. */
867 break;
868 }
869 outb(0, FIFO(port));
870 }
871
872 /* Reset the FIFO and return to PS2 mode. */
873 frob_set_mode(port, ECR_PS2);
874
875 /* Host transfer recovery. */
876 parport_pc_data_reverse(port); /* Must be in PS2 mode */
877 udelay(5);
878 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
879 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
880 if (r)
881 printk(KERN_DEBUG "%s: PE,1 timeout (%d) in ecp_write_block_pio\n",
882 port->name, r);
883
884 parport_frob_control(port,
885 PARPORT_CONTROL_INIT,
886 PARPORT_CONTROL_INIT);
887 r = parport_wait_peripheral(port,
888 PARPORT_STATUS_PAPEROUT,
889 PARPORT_STATUS_PAPEROUT);
890 if (r)
891 printk(KERN_DEBUG "%s: PE,2 timeout (%d) in ecp_write_block_pio\n",
892 port->name, r);
893 }
894
895 r = parport_wait_peripheral(port,
896 PARPORT_STATUS_BUSY,
897 PARPORT_STATUS_BUSY);
898 if (r)
899 printk(KERN_DEBUG "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
900 port->name, r);
901
902 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
903
904 return written;
905}
906#endif /* IEEE 1284 support */
907#endif /* Allowed to use FIFO/DMA */
908
909
910/*
911 * ******************************************
912 * INITIALISATION AND MODULE STUFF BELOW HERE
913 * ******************************************
914 */
915
916/* GCC is not inlining extern inline function later overwritten to non-inline,
917 so we use outlined_ variants here. */
918static const struct parport_operations parport_pc_ops = {
919 .write_data = parport_pc_write_data,
920 .read_data = parport_pc_read_data,
921
922 .write_control = parport_pc_write_control,
923 .read_control = parport_pc_read_control,
924 .frob_control = parport_pc_frob_control,
925
926 .read_status = parport_pc_read_status,
927
928 .enable_irq = parport_pc_enable_irq,
929 .disable_irq = parport_pc_disable_irq,
930
931 .data_forward = parport_pc_data_forward,
932 .data_reverse = parport_pc_data_reverse,
933
934 .init_state = parport_pc_init_state,
935 .save_state = parport_pc_save_state,
936 .restore_state = parport_pc_restore_state,
937
938 .epp_write_data = parport_ieee1284_epp_write_data,
939 .epp_read_data = parport_ieee1284_epp_read_data,
940 .epp_write_addr = parport_ieee1284_epp_write_addr,
941 .epp_read_addr = parport_ieee1284_epp_read_addr,
942
943 .ecp_write_data = parport_ieee1284_ecp_write_data,
944 .ecp_read_data = parport_ieee1284_ecp_read_data,
945 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
946
947 .compat_write_data = parport_ieee1284_write_compat,
948 .nibble_read_data = parport_ieee1284_read_nibble,
949 .byte_read_data = parport_ieee1284_read_byte,
950
951 .owner = THIS_MODULE,
952};
953
954#ifdef CONFIG_PARPORT_PC_SUPERIO
955
956static struct superio_struct *find_free_superio(void)
957{
958 int i;
959 for (i = 0; i < NR_SUPERIOS; i++)
960 if (superios[i].io == 0)
961 return &superios[i];
962 return NULL;
963}
964
965
966/* Super-IO chipset detection, Winbond, SMSC */
967static void show_parconfig_smsc37c669(int io, int key)
968{
969 int cr1, cr4, cra, cr23, cr26, cr27;
970 struct superio_struct *s;
971
972 static const char *const modes[] = {
973 "SPP and Bidirectional (PS/2)",
974 "EPP and SPP",
975 "ECP",
976 "ECP and EPP" };
977
978 outb(key, io);
979 outb(key, io);
980 outb(1, io);
981 cr1 = inb(io + 1);
982 outb(4, io);
983 cr4 = inb(io + 1);
984 outb(0x0a, io);
985 cra = inb(io + 1);
986 outb(0x23, io);
987 cr23 = inb(io + 1);
988 outb(0x26, io);
989 cr26 = inb(io + 1);
990 outb(0x27, io);
991 cr27 = inb(io + 1);
992 outb(0xaa, io);
993
994 if (verbose_probing) {
995 pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
996 cr1, cr4, cra, cr23, cr26, cr27);
997
998 /* The documentation calls DMA and IRQ-Lines by letters, so
999 the board maker can/will wire them
1000 appropriately/randomly... G=reserved H=IDE-irq, */
1001 pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
1002 cr23 * 4,
1003 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
1004 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
1005 cra & 0x0f);
1006 pr_info("SMSC LPT Config: enabled=%s power=%s\n",
1007 (cr23 * 4 >= 0x100) ? "yes" : "no",
1008 (cr1 & 4) ? "yes" : "no");
1009 pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1010 (cr1 & 0x08) ? "Standard mode only (SPP)"
1011 : modes[cr4 & 0x03],
1012 (cr4 & 0x40) ? "1.7" : "1.9");
1013 }
1014
1015 /* Heuristics ! BIOS setup for this mainboard device limits
1016 the choices to standard settings, i.e. io-address and IRQ
1017 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1018 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1019 if (cr23 * 4 >= 0x100) { /* if active */
1020 s = find_free_superio();
1021 if (s == NULL)
1022 pr_info("Super-IO: too many chips!\n");
1023 else {
1024 int d;
1025 switch (cr23 * 4) {
1026 case 0x3bc:
1027 s->io = 0x3bc;
1028 s->irq = 7;
1029 break;
1030 case 0x378:
1031 s->io = 0x378;
1032 s->irq = 7;
1033 break;
1034 case 0x278:
1035 s->io = 0x278;
1036 s->irq = 5;
1037 }
1038 d = (cr26 & 0x0f);
1039 if (d == 1 || d == 3)
1040 s->dma = d;
1041 else
1042 s->dma = PARPORT_DMA_NONE;
1043 }
1044 }
1045}
1046
1047
1048static void show_parconfig_winbond(int io, int key)
1049{
1050 int cr30, cr60, cr61, cr70, cr74, crf0;
1051 struct superio_struct *s;
1052 static const char *const modes[] = {
1053 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1054 "EPP-1.9 and SPP",
1055 "ECP",
1056 "ECP and EPP-1.9",
1057 "Standard (SPP)",
1058 "EPP-1.7 and SPP", /* 5 */
1059 "undefined!",
1060 "ECP and EPP-1.7" };
1061 static char *const irqtypes[] = {
1062 "pulsed low, high-Z",
1063 "follows nACK" };
1064
1065 /* The registers are called compatible-PnP because the
1066 register layout is modelled after ISA-PnP, the access
1067 method is just another ... */
1068 outb(key, io);
1069 outb(key, io);
1070 outb(0x07, io); /* Register 7: Select Logical Device */
1071 outb(0x01, io + 1); /* LD1 is Parallel Port */
1072 outb(0x30, io);
1073 cr30 = inb(io + 1);
1074 outb(0x60, io);
1075 cr60 = inb(io + 1);
1076 outb(0x61, io);
1077 cr61 = inb(io + 1);
1078 outb(0x70, io);
1079 cr70 = inb(io + 1);
1080 outb(0x74, io);
1081 cr74 = inb(io + 1);
1082 outb(0xf0, io);
1083 crf0 = inb(io + 1);
1084 outb(0xaa, io);
1085
1086 if (verbose_probing) {
1087 pr_info("Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1088 cr30, cr60, cr61, cr70, cr74, crf0);
1089 pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1090 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1091 if ((cr74 & 0x07) > 3)
1092 pr_cont("dma=none\n");
1093 else
1094 pr_cont("dma=%d\n", cr74 & 0x07);
1095 pr_info("Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1096 irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f);
1097 pr_info("Winbond LPT Config: Port mode=%s\n",
1098 modes[crf0 & 0x07]);
1099 }
1100
1101 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1102 s = find_free_superio();
1103 if (s == NULL)
1104 pr_info("Super-IO: too many chips!\n");
1105 else {
1106 s->io = (cr60 << 8) | cr61;
1107 s->irq = cr70 & 0x0f;
1108 s->dma = (((cr74 & 0x07) > 3) ?
1109 PARPORT_DMA_NONE : (cr74 & 0x07));
1110 }
1111 }
1112}
1113
1114static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1115{
1116 const char *type = "unknown";
1117 int id, progif = 2;
1118
1119 if (devid == devrev)
1120 /* simple heuristics, we happened to read some
1121 non-winbond register */
1122 return;
1123
1124 id = (devid << 8) | devrev;
1125
1126 /* Values are from public data sheets pdf files, I can just
1127 confirm 83977TF is correct :-) */
1128 if (id == 0x9771)
1129 type = "83977F/AF";
1130 else if (id == 0x9773)
1131 type = "83977TF / SMSC 97w33x/97w34x";
1132 else if (id == 0x9774)
1133 type = "83977ATF";
1134 else if ((id & ~0x0f) == 0x5270)
1135 type = "83977CTF / SMSC 97w36x";
1136 else if ((id & ~0x0f) == 0x52f0)
1137 type = "83977EF / SMSC 97w35x";
1138 else if ((id & ~0x0f) == 0x5210)
1139 type = "83627";
1140 else if ((id & ~0x0f) == 0x6010)
1141 type = "83697HF";
1142 else if ((oldid & 0x0f) == 0x0a) {
1143 type = "83877F";
1144 progif = 1;
1145 } else if ((oldid & 0x0f) == 0x0b) {
1146 type = "83877AF";
1147 progif = 1;
1148 } else if ((oldid & 0x0f) == 0x0c) {
1149 type = "83877TF";
1150 progif = 1;
1151 } else if ((oldid & 0x0f) == 0x0d) {
1152 type = "83877ATF";
1153 progif = 1;
1154 } else
1155 progif = 0;
1156
1157 if (verbose_probing)
1158 pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n",
1159 efer, key, devid, devrev, oldid, type);
1160
1161 if (progif == 2)
1162 show_parconfig_winbond(efer, key);
1163}
1164
1165static void decode_smsc(int efer, int key, int devid, int devrev)
1166{
1167 const char *type = "unknown";
1168 void (*func)(int io, int key);
1169 int id;
1170
1171 if (devid == devrev)
1172 /* simple heuristics, we happened to read some
1173 non-smsc register */
1174 return;
1175
1176 func = NULL;
1177 id = (devid << 8) | devrev;
1178
1179 if (id == 0x0302) {
1180 type = "37c669";
1181 func = show_parconfig_smsc37c669;
1182 } else if (id == 0x6582)
1183 type = "37c665IR";
1184 else if (devid == 0x65)
1185 type = "37c665GT";
1186 else if (devid == 0x66)
1187 type = "37c666GT";
1188
1189 if (verbose_probing)
1190 pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n",
1191 efer, key, devid, devrev, type);
1192
1193 if (func)
1194 func(efer, key);
1195}
1196
1197
1198static void winbond_check(int io, int key)
1199{
1200 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1201
1202 if (!request_region(io, 3, __func__))
1203 return;
1204
1205 origval = inb(io); /* Save original value */
1206
1207 /* First probe without key */
1208 outb(0x20, io);
1209 x_devid = inb(io + 1);
1210 outb(0x21, io);
1211 x_devrev = inb(io + 1);
1212 outb(0x09, io);
1213 x_oldid = inb(io + 1);
1214
1215 outb(key, io);
1216 outb(key, io); /* Write Magic Sequence to EFER, extended
1217 function enable register */
1218 outb(0x20, io); /* Write EFIR, extended function index register */
1219 devid = inb(io + 1); /* Read EFDR, extended function data register */
1220 outb(0x21, io);
1221 devrev = inb(io + 1);
1222 outb(0x09, io);
1223 oldid = inb(io + 1);
1224 outb(0xaa, io); /* Magic Seal */
1225
1226 outb(origval, io); /* in case we poked some entirely different hardware */
1227
1228 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1229 goto out; /* protection against false positives */
1230
1231 decode_winbond(io, key, devid, devrev, oldid);
1232out:
1233 release_region(io, 3);
1234}
1235
1236static void winbond_check2(int io, int key)
1237{
1238 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1239
1240 if (!request_region(io, 3, __func__))
1241 return;
1242
1243 origval[0] = inb(io); /* Save original values */
1244 origval[1] = inb(io + 1);
1245 origval[2] = inb(io + 2);
1246
1247 /* First probe without the key */
1248 outb(0x20, io + 2);
1249 x_devid = inb(io + 2);
1250 outb(0x21, io + 1);
1251 x_devrev = inb(io + 2);
1252 outb(0x09, io + 1);
1253 x_oldid = inb(io + 2);
1254
1255 outb(key, io); /* Write Magic Byte to EFER, extended
1256 function enable register */
1257 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1258 devid = inb(io + 2); /* Read EFDR, extended function data register */
1259 outb(0x21, io + 1);
1260 devrev = inb(io + 2);
1261 outb(0x09, io + 1);
1262 oldid = inb(io + 2);
1263 outb(0xaa, io); /* Magic Seal */
1264
1265 outb(origval[0], io); /* in case we poked some entirely different hardware */
1266 outb(origval[1], io + 1);
1267 outb(origval[2], io + 2);
1268
1269 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1270 goto out; /* protection against false positives */
1271
1272 decode_winbond(io, key, devid, devrev, oldid);
1273out:
1274 release_region(io, 3);
1275}
1276
1277static void smsc_check(int io, int key)
1278{
1279 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1280
1281 if (!request_region(io, 3, __func__))
1282 return;
1283
1284 origval = inb(io); /* Save original value */
1285
1286 /* First probe without the key */
1287 outb(0x0d, io);
1288 x_oldid = inb(io + 1);
1289 outb(0x0e, io);
1290 x_oldrev = inb(io + 1);
1291 outb(0x20, io);
1292 x_id = inb(io + 1);
1293 outb(0x21, io);
1294 x_rev = inb(io + 1);
1295
1296 outb(key, io);
1297 outb(key, io); /* Write Magic Sequence to EFER, extended
1298 function enable register */
1299 outb(0x0d, io); /* Write EFIR, extended function index register */
1300 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1301 outb(0x0e, io);
1302 oldrev = inb(io + 1);
1303 outb(0x20, io);
1304 id = inb(io + 1);
1305 outb(0x21, io);
1306 rev = inb(io + 1);
1307 outb(0xaa, io); /* Magic Seal */
1308
1309 outb(origval, io); /* in case we poked some entirely different hardware */
1310
1311 if (x_id == id && x_oldrev == oldrev &&
1312 x_oldid == oldid && x_rev == rev)
1313 goto out; /* protection against false positives */
1314
1315 decode_smsc(io, key, oldid, oldrev);
1316out:
1317 release_region(io, 3);
1318}
1319
1320
1321static void detect_and_report_winbond(void)
1322{
1323 if (verbose_probing)
1324 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1325 winbond_check(0x3f0, 0x87);
1326 winbond_check(0x370, 0x87);
1327 winbond_check(0x2e , 0x87);
1328 winbond_check(0x4e , 0x87);
1329 winbond_check(0x3f0, 0x86);
1330 winbond_check2(0x250, 0x88);
1331 winbond_check2(0x250, 0x89);
1332}
1333
1334static void detect_and_report_smsc(void)
1335{
1336 if (verbose_probing)
1337 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1338 smsc_check(0x3f0, 0x55);
1339 smsc_check(0x370, 0x55);
1340 smsc_check(0x3f0, 0x44);
1341 smsc_check(0x370, 0x44);
1342}
1343
1344static void detect_and_report_it87(void)
1345{
1346 u16 dev;
1347 u8 origval, r;
1348 if (verbose_probing)
1349 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1350 if (!request_muxed_region(0x2e, 2, __func__))
1351 return;
1352 origval = inb(0x2e); /* Save original value */
1353 outb(0x87, 0x2e);
1354 outb(0x01, 0x2e);
1355 outb(0x55, 0x2e);
1356 outb(0x55, 0x2e);
1357 outb(0x20, 0x2e);
1358 dev = inb(0x2f) << 8;
1359 outb(0x21, 0x2e);
1360 dev |= inb(0x2f);
1361 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1362 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1363 pr_info("IT%04X SuperIO detected\n", dev);
1364 outb(0x07, 0x2E); /* Parallel Port */
1365 outb(0x03, 0x2F);
1366 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1367 r = inb(0x2f);
1368 outb(0xF0, 0x2E);
1369 outb(r | 8, 0x2F);
1370 outb(0x02, 0x2E); /* Lock */
1371 outb(0x02, 0x2F);
1372 } else {
1373 outb(origval, 0x2e); /* Oops, sorry to disturb */
1374 }
1375 release_region(0x2e, 2);
1376}
1377#endif /* CONFIG_PARPORT_PC_SUPERIO */
1378
1379static struct superio_struct *find_superio(struct parport *p)
1380{
1381 int i;
1382 for (i = 0; i < NR_SUPERIOS; i++)
1383 if (superios[i].io == p->base)
1384 return &superios[i];
1385 return NULL;
1386}
1387
1388static int get_superio_dma(struct parport *p)
1389{
1390 struct superio_struct *s = find_superio(p);
1391 if (s)
1392 return s->dma;
1393 return PARPORT_DMA_NONE;
1394}
1395
1396static int get_superio_irq(struct parport *p)
1397{
1398 struct superio_struct *s = find_superio(p);
1399 if (s)
1400 return s->irq;
1401 return PARPORT_IRQ_NONE;
1402}
1403
1404
1405/* --- Mode detection ------------------------------------- */
1406
1407/*
1408 * Checks for port existence, all ports support SPP MODE
1409 * Returns:
1410 * 0 : No parallel port at this address
1411 * PARPORT_MODE_PCSPP : SPP port detected
1412 * (if the user specified an ioport himself,
1413 * this shall always be the case!)
1414 *
1415 */
1416static int parport_SPP_supported(struct parport *pb)
1417{
1418 unsigned char r, w;
1419
1420 /*
1421 * first clear an eventually pending EPP timeout
1422 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1423 * that does not even respond to SPP cycles if an EPP
1424 * timeout is pending
1425 */
1426 clear_epp_timeout(pb);
1427
1428 /* Do a simple read-write test to make sure the port exists. */
1429 w = 0xc;
1430 outb(w, CONTROL(pb));
1431
1432 /* Is there a control register that we can read from? Some
1433 * ports don't allow reads, so read_control just returns a
1434 * software copy. Some ports _do_ allow reads, so bypass the
1435 * software copy here. In addition, some bits aren't
1436 * writable. */
1437 r = inb(CONTROL(pb));
1438 if ((r & 0xf) == w) {
1439 w = 0xe;
1440 outb(w, CONTROL(pb));
1441 r = inb(CONTROL(pb));
1442 outb(0xc, CONTROL(pb));
1443 if ((r & 0xf) == w)
1444 return PARPORT_MODE_PCSPP;
1445 }
1446
1447 if (user_specified)
1448 /* That didn't work, but the user thinks there's a
1449 * port here. */
1450 pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n",
1451 pb->base, w, r);
1452
1453 /* Try the data register. The data lines aren't tri-stated at
1454 * this stage, so we expect back what we wrote. */
1455 w = 0xaa;
1456 parport_pc_write_data(pb, w);
1457 r = parport_pc_read_data(pb);
1458 if (r == w) {
1459 w = 0x55;
1460 parport_pc_write_data(pb, w);
1461 r = parport_pc_read_data(pb);
1462 if (r == w)
1463 return PARPORT_MODE_PCSPP;
1464 }
1465
1466 if (user_specified) {
1467 /* Didn't work, but the user is convinced this is the
1468 * place. */
1469 pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n",
1470 pb->base, w, r);
1471 pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n",
1472 pb->base);
1473 }
1474
1475 /* It's possible that we can't read the control register or
1476 * the data register. In that case just believe the user. */
1477 if (user_specified)
1478 return PARPORT_MODE_PCSPP;
1479
1480 return 0;
1481}
1482
1483/* Check for ECR
1484 *
1485 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1486 * on these cards actually accesses the CTR.
1487 *
1488 * Modern cards don't do this but reading from ECR will return 0xff
1489 * regardless of what is written here if the card does NOT support
1490 * ECP.
1491 *
1492 * We first check to see if ECR is the same as CTR. If not, the low
1493 * two bits of ECR aren't writable, so we check by writing ECR and
1494 * reading it back to see if it's what we expect.
1495 */
1496static int parport_ECR_present(struct parport *pb)
1497{
1498 struct parport_pc_private *priv = pb->private_data;
1499 unsigned char r = 0xc;
1500
1501 if (!priv->ecr_writable) {
1502 outb(r, CONTROL(pb));
1503 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1504 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1505
1506 r = inb(CONTROL(pb));
1507 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1508 /* Sure that no ECR register exists */
1509 goto no_reg;
1510 }
1511
1512 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1513 goto no_reg;
1514
1515 ECR_WRITE(pb, 0x34);
1516 if (inb(ECONTROL(pb)) != 0x35)
1517 goto no_reg;
1518 }
1519
1520 priv->ecr = 1;
1521 outb(0xc, CONTROL(pb));
1522
1523 /* Go to mode 000 */
1524 frob_set_mode(pb, ECR_SPP);
1525
1526 return 1;
1527
1528 no_reg:
1529 outb(0xc, CONTROL(pb));
1530 return 0;
1531}
1532
1533#ifdef CONFIG_PARPORT_1284
1534/* Detect PS/2 support.
1535 *
1536 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1537 * allows us to read data from the data lines. In theory we would get back
1538 * 0xff but any peripheral attached to the port may drag some or all of the
1539 * lines down to zero. So if we get back anything that isn't the contents
1540 * of the data register we deem PS/2 support to be present.
1541 *
1542 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1543 * drivers, but an external peripheral with sufficiently beefy drivers of
1544 * its own can overpower them and assert its own levels onto the bus, from
1545 * where they can then be read back as normal. Ports with this property
1546 * and the right type of device attached are likely to fail the SPP test,
1547 * (as they will appear to have stuck bits) and so the fact that they might
1548 * be misdetected here is rather academic.
1549 */
1550
1551static int parport_PS2_supported(struct parport *pb)
1552{
1553 int ok = 0;
1554
1555 clear_epp_timeout(pb);
1556
1557 /* try to tri-state the buffer */
1558 parport_pc_data_reverse(pb);
1559
1560 parport_pc_write_data(pb, 0x55);
1561 if (parport_pc_read_data(pb) != 0x55)
1562 ok++;
1563
1564 parport_pc_write_data(pb, 0xaa);
1565 if (parport_pc_read_data(pb) != 0xaa)
1566 ok++;
1567
1568 /* cancel input mode */
1569 parport_pc_data_forward(pb);
1570
1571 if (ok) {
1572 pb->modes |= PARPORT_MODE_TRISTATE;
1573 } else {
1574 struct parport_pc_private *priv = pb->private_data;
1575 priv->ctr_writable &= ~0x20;
1576 }
1577
1578 return ok;
1579}
1580
1581#ifdef CONFIG_PARPORT_PC_FIFO
1582static int parport_ECP_supported(struct parport *pb)
1583{
1584 int i;
1585 int config, configb;
1586 int pword;
1587 struct parport_pc_private *priv = pb->private_data;
1588 /* Translate ECP intrLine to ISA irq value */
1589 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1590
1591 /* If there is no ECR, we have no hope of supporting ECP. */
1592 if (!priv->ecr)
1593 return 0;
1594
1595 /* Find out FIFO depth */
1596 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1597 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1598 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1599 outb(0xaa, FIFO(pb));
1600
1601 /*
1602 * Using LGS chipset it uses ECR register, but
1603 * it doesn't support ECP or FIFO MODE
1604 */
1605 if (i == 1024) {
1606 ECR_WRITE(pb, ECR_SPP << 5);
1607 return 0;
1608 }
1609
1610 priv->fifo_depth = i;
1611 if (verbose_probing)
1612 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1613
1614 /* Find out writeIntrThreshold */
1615 frob_econtrol(pb, 1<<2, 1<<2);
1616 frob_econtrol(pb, 1<<2, 0);
1617 for (i = 1; i <= priv->fifo_depth; i++) {
1618 inb(FIFO(pb));
1619 udelay(50);
1620 if (inb(ECONTROL(pb)) & (1<<2))
1621 break;
1622 }
1623
1624 if (i <= priv->fifo_depth) {
1625 if (verbose_probing)
1626 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1627 pb->base, i);
1628 } else
1629 /* Number of bytes we know we can write if we get an
1630 interrupt. */
1631 i = 0;
1632
1633 priv->writeIntrThreshold = i;
1634
1635 /* Find out readIntrThreshold */
1636 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1637 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1638 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1639 frob_econtrol(pb, 1<<2, 1<<2);
1640 frob_econtrol(pb, 1<<2, 0);
1641 for (i = 1; i <= priv->fifo_depth; i++) {
1642 outb(0xaa, FIFO(pb));
1643 if (inb(ECONTROL(pb)) & (1<<2))
1644 break;
1645 }
1646
1647 if (i <= priv->fifo_depth) {
1648 if (verbose_probing)
1649 pr_info("0x%lx: readIntrThreshold is %d\n",
1650 pb->base, i);
1651 } else
1652 /* Number of bytes we can read if we get an interrupt. */
1653 i = 0;
1654
1655 priv->readIntrThreshold = i;
1656
1657 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1658 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1659 config = inb(CONFIGA(pb));
1660 pword = (config >> 4) & 0x7;
1661 switch (pword) {
1662 case 0:
1663 pword = 2;
1664 pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
1665 break;
1666 case 2:
1667 pword = 4;
1668 pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
1669 break;
1670 default:
1671 pr_warn("0x%lx: Unknown implementation ID\n", pb->base);
1672 fallthrough; /* Assume 1 */
1673 case 1:
1674 pword = 1;
1675 }
1676 priv->pword = pword;
1677
1678 if (verbose_probing) {
1679 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1680 pb->base, 8 * pword);
1681
1682 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n",
1683 pb->base, config & 0x80 ? "Level" : "Pulses");
1684
1685 configb = inb(CONFIGB(pb));
1686 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1687 pb->base, config, configb);
1688 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1689 if ((configb >> 3) & 0x07)
1690 pr_cont("%d", intrline[(configb >> 3) & 0x07]);
1691 else
1692 pr_cont("<none or set by other means>");
1693 pr_cont(" dma=");
1694 if ((configb & 0x03) == 0x00)
1695 pr_cont("<none or set by other means>\n");
1696 else
1697 pr_cont("%d\n", configb & 0x07);
1698 }
1699
1700 /* Go back to mode 000 */
1701 frob_set_mode(pb, ECR_SPP);
1702
1703 return 1;
1704}
1705#endif
1706
1707#ifdef CONFIG_X86_32
1708static int intel_bug_present_check_epp(struct parport *pb)
1709{
1710 const struct parport_pc_private *priv = pb->private_data;
1711 int bug_present = 0;
1712
1713 if (priv->ecr) {
1714 /* store value of ECR */
1715 unsigned char ecr = inb(ECONTROL(pb));
1716 unsigned char i;
1717 for (i = 0x00; i < 0x80; i += 0x20) {
1718 ECR_WRITE(pb, i);
1719 if (clear_epp_timeout(pb)) {
1720 /* Phony EPP in ECP. */
1721 bug_present = 1;
1722 break;
1723 }
1724 }
1725 /* return ECR into the inital state */
1726 ECR_WRITE(pb, ecr);
1727 }
1728
1729 return bug_present;
1730}
1731static int intel_bug_present(struct parport *pb)
1732{
1733/* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */
1734 if (pb->dev != NULL) {
1735 return 0;
1736 }
1737
1738 return intel_bug_present_check_epp(pb);
1739}
1740#else
1741static int intel_bug_present(struct parport *pb)
1742{
1743 return 0;
1744}
1745#endif /* CONFIG_X86_32 */
1746
1747static int parport_ECPPS2_supported(struct parport *pb)
1748{
1749 const struct parport_pc_private *priv = pb->private_data;
1750 int result;
1751 unsigned char oecr;
1752
1753 if (!priv->ecr)
1754 return 0;
1755
1756 oecr = inb(ECONTROL(pb));
1757 ECR_WRITE(pb, ECR_PS2 << 5);
1758 result = parport_PS2_supported(pb);
1759 ECR_WRITE(pb, oecr);
1760 return result;
1761}
1762
1763/* EPP mode detection */
1764
1765static int parport_EPP_supported(struct parport *pb)
1766{
1767 /*
1768 * Theory:
1769 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1770 * when EPP is possible and is set high when an EPP timeout
1771 * occurs (EPP uses the HALT line to stop the CPU while it does
1772 * the byte transfer, an EPP timeout occurs if the attached
1773 * device fails to respond after 10 micro seconds).
1774 *
1775 * This bit is cleared by either reading it (National Semi)
1776 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1777 * This bit is always high in non EPP modes.
1778 */
1779
1780 /* If EPP timeout bit clear then EPP available */
1781 if (!clear_epp_timeout(pb))
1782 return 0; /* No way to clear timeout */
1783
1784 /* Check for Intel bug. */
1785 if (intel_bug_present(pb))
1786 return 0;
1787
1788 pb->modes |= PARPORT_MODE_EPP;
1789
1790 /* Set up access functions to use EPP hardware. */
1791 pb->ops->epp_read_data = parport_pc_epp_read_data;
1792 pb->ops->epp_write_data = parport_pc_epp_write_data;
1793 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1794 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1795
1796 return 1;
1797}
1798
1799static int parport_ECPEPP_supported(struct parport *pb)
1800{
1801 struct parport_pc_private *priv = pb->private_data;
1802 int result;
1803 unsigned char oecr;
1804
1805 if (!priv->ecr)
1806 return 0;
1807
1808 oecr = inb(ECONTROL(pb));
1809 /* Search for SMC style EPP+ECP mode */
1810 ECR_WRITE(pb, 0x80);
1811 outb(0x04, CONTROL(pb));
1812 result = parport_EPP_supported(pb);
1813
1814 ECR_WRITE(pb, oecr);
1815
1816 if (result) {
1817 /* Set up access functions to use ECP+EPP hardware. */
1818 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1819 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1820 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1821 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1822 }
1823
1824 return result;
1825}
1826
1827#else /* No IEEE 1284 support */
1828
1829/* Don't bother probing for modes we know we won't use. */
1830static int parport_PS2_supported(struct parport *pb) { return 0; }
1831#ifdef CONFIG_PARPORT_PC_FIFO
1832static int parport_ECP_supported(struct parport *pb)
1833{
1834 return 0;
1835}
1836#endif
1837static int parport_EPP_supported(struct parport *pb)
1838{
1839 return 0;
1840}
1841
1842static int parport_ECPEPP_supported(struct parport *pb)
1843{
1844 return 0;
1845}
1846
1847static int parport_ECPPS2_supported(struct parport *pb)
1848{
1849 return 0;
1850}
1851
1852#endif /* No IEEE 1284 support */
1853
1854/* --- IRQ detection -------------------------------------- */
1855
1856/* Only if supports ECP mode */
1857static int programmable_irq_support(struct parport *pb)
1858{
1859 int irq, intrLine;
1860 unsigned char oecr = inb(ECONTROL(pb));
1861 static const int lookup[8] = {
1862 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1863 };
1864
1865 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1866
1867 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1868 irq = lookup[intrLine];
1869
1870 ECR_WRITE(pb, oecr);
1871 return irq;
1872}
1873
1874static int irq_probe_ECP(struct parport *pb)
1875{
1876 int i;
1877 unsigned long irqs;
1878
1879 irqs = probe_irq_on();
1880
1881 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1882 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1883 ECR_WRITE(pb, ECR_TST << 5);
1884
1885 /* If Full FIFO sure that writeIntrThreshold is generated */
1886 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1887 outb(0xaa, FIFO(pb));
1888
1889 pb->irq = probe_irq_off(irqs);
1890 ECR_WRITE(pb, ECR_SPP << 5);
1891
1892 if (pb->irq <= 0)
1893 pb->irq = PARPORT_IRQ_NONE;
1894
1895 return pb->irq;
1896}
1897
1898/*
1899 * This detection seems that only works in National Semiconductors
1900 * This doesn't work in SMC, LGS, and Winbond
1901 */
1902static int irq_probe_EPP(struct parport *pb)
1903{
1904#ifndef ADVANCED_DETECT
1905 return PARPORT_IRQ_NONE;
1906#else
1907 int irqs;
1908 unsigned char oecr;
1909
1910 if (pb->modes & PARPORT_MODE_PCECR)
1911 oecr = inb(ECONTROL(pb));
1912
1913 irqs = probe_irq_on();
1914
1915 if (pb->modes & PARPORT_MODE_PCECR)
1916 frob_econtrol(pb, 0x10, 0x10);
1917
1918 clear_epp_timeout(pb);
1919 parport_pc_frob_control(pb, 0x20, 0x20);
1920 parport_pc_frob_control(pb, 0x10, 0x10);
1921 clear_epp_timeout(pb);
1922
1923 /* Device isn't expecting an EPP read
1924 * and generates an IRQ.
1925 */
1926 parport_pc_read_epp(pb);
1927 udelay(20);
1928
1929 pb->irq = probe_irq_off(irqs);
1930 if (pb->modes & PARPORT_MODE_PCECR)
1931 ECR_WRITE(pb, oecr);
1932 parport_pc_write_control(pb, 0xc);
1933
1934 if (pb->irq <= 0)
1935 pb->irq = PARPORT_IRQ_NONE;
1936
1937 return pb->irq;
1938#endif /* Advanced detection */
1939}
1940
1941static int irq_probe_SPP(struct parport *pb)
1942{
1943 /* Don't even try to do this. */
1944 return PARPORT_IRQ_NONE;
1945}
1946
1947/* We will attempt to share interrupt requests since other devices
1948 * such as sound cards and network cards seem to like using the
1949 * printer IRQs.
1950 *
1951 * When ECP is available we can autoprobe for IRQs.
1952 * NOTE: If we can autoprobe it, we can register the IRQ.
1953 */
1954static int parport_irq_probe(struct parport *pb)
1955{
1956 struct parport_pc_private *priv = pb->private_data;
1957
1958 if (priv->ecr) {
1959 pb->irq = programmable_irq_support(pb);
1960
1961 if (pb->irq == PARPORT_IRQ_NONE)
1962 pb->irq = irq_probe_ECP(pb);
1963 }
1964
1965 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1966 (pb->modes & PARPORT_MODE_EPP))
1967 pb->irq = irq_probe_EPP(pb);
1968
1969 clear_epp_timeout(pb);
1970
1971 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1972 pb->irq = irq_probe_EPP(pb);
1973
1974 clear_epp_timeout(pb);
1975
1976 if (pb->irq == PARPORT_IRQ_NONE)
1977 pb->irq = irq_probe_SPP(pb);
1978
1979 if (pb->irq == PARPORT_IRQ_NONE)
1980 pb->irq = get_superio_irq(pb);
1981
1982 return pb->irq;
1983}
1984
1985/* --- DMA detection -------------------------------------- */
1986
1987/* Only if chipset conforms to ECP ISA Interface Standard */
1988static int programmable_dma_support(struct parport *p)
1989{
1990 unsigned char oecr = inb(ECONTROL(p));
1991 int dma;
1992
1993 frob_set_mode(p, ECR_CNF);
1994
1995 dma = inb(CONFIGB(p)) & 0x07;
1996 /* 000: Indicates jumpered 8-bit DMA if read-only.
1997 100: Indicates jumpered 16-bit DMA if read-only. */
1998 if ((dma & 0x03) == 0)
1999 dma = PARPORT_DMA_NONE;
2000
2001 ECR_WRITE(p, oecr);
2002 return dma;
2003}
2004
2005static int parport_dma_probe(struct parport *p)
2006{
2007 const struct parport_pc_private *priv = p->private_data;
2008 if (priv->ecr) /* ask ECP chipset first */
2009 p->dma = programmable_dma_support(p);
2010 if (p->dma == PARPORT_DMA_NONE) {
2011 /* ask known Super-IO chips proper, although these
2012 claim ECP compatible, some don't report their DMA
2013 conforming to ECP standards */
2014 p->dma = get_superio_dma(p);
2015 }
2016
2017 return p->dma;
2018}
2019
2020/* --- Initialisation code -------------------------------- */
2021
2022static LIST_HEAD(ports_list);
2023static DEFINE_SPINLOCK(ports_lock);
2024
2025static struct parport *__parport_pc_probe_port(unsigned long int base,
2026 unsigned long int base_hi,
2027 int irq, int dma,
2028 struct device *dev,
2029 int irqflags,
2030 unsigned int mode_mask,
2031 unsigned char ecr_writable)
2032{
2033 struct parport_pc_private *priv;
2034 struct parport_operations *ops;
2035 struct parport *p;
2036 int probedirq = PARPORT_IRQ_NONE;
2037 struct resource *base_res;
2038 struct resource *ECR_res = NULL;
2039 struct resource *EPP_res = NULL;
2040 struct platform_device *pdev = NULL;
2041 int ret;
2042
2043 if (!dev) {
2044 /* We need a physical device to attach to, but none was
2045 * provided. Create our own. */
2046 pdev = platform_device_register_simple("parport_pc",
2047 base, NULL, 0);
2048 if (IS_ERR(pdev))
2049 return NULL;
2050 dev = &pdev->dev;
2051
2052 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24));
2053 if (ret) {
2054 dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n");
2055 dma = PARPORT_DMA_NONE;
2056 }
2057 }
2058
2059 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2060 if (!ops)
2061 goto out1;
2062
2063 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2064 if (!priv)
2065 goto out2;
2066
2067 /* a misnomer, actually - it's allocate and reserve parport number */
2068 p = parport_register_port(base, irq, dma, ops);
2069 if (!p)
2070 goto out3;
2071
2072 base_res = request_region(base, 3, p->name);
2073 if (!base_res)
2074 goto out4;
2075
2076 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2077 priv->ctr = 0xc;
2078 priv->ctr_writable = ~0x10;
2079 priv->ecr = 0;
2080 priv->ecr_writable = ecr_writable;
2081 priv->fifo_depth = 0;
2082 priv->dma_buf = NULL;
2083 priv->dma_handle = 0;
2084 INIT_LIST_HEAD(&priv->list);
2085 priv->port = p;
2086
2087 p->dev = dev;
2088 p->base_hi = base_hi;
2089 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2090 p->private_data = priv;
2091
2092 if (base_hi) {
2093 ECR_res = request_region(base_hi, 3, p->name);
2094 if (ECR_res)
2095 parport_ECR_present(p);
2096 }
2097
2098 if (base != 0x3bc) {
2099 EPP_res = request_region(base+0x3, 5, p->name);
2100 if (EPP_res)
2101 if (!parport_EPP_supported(p))
2102 parport_ECPEPP_supported(p);
2103 }
2104 if (!parport_SPP_supported(p))
2105 /* No port. */
2106 goto out5;
2107 if (priv->ecr)
2108 parport_ECPPS2_supported(p);
2109 else
2110 parport_PS2_supported(p);
2111
2112 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2113
2114 pr_info("%s: PC-style at 0x%lx", p->name, p->base);
2115 if (p->base_hi && priv->ecr)
2116 pr_cont(" (0x%lx)", p->base_hi);
2117 if (p->irq == PARPORT_IRQ_AUTO) {
2118 p->irq = PARPORT_IRQ_NONE;
2119 parport_irq_probe(p);
2120 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2121 p->irq = PARPORT_IRQ_NONE;
2122 parport_irq_probe(p);
2123 probedirq = p->irq;
2124 p->irq = PARPORT_IRQ_NONE;
2125 }
2126 if (p->irq != PARPORT_IRQ_NONE) {
2127 pr_cont(", irq %d", p->irq);
2128 priv->ctr_writable |= 0x10;
2129
2130 if (p->dma == PARPORT_DMA_AUTO) {
2131 p->dma = PARPORT_DMA_NONE;
2132 parport_dma_probe(p);
2133 }
2134 }
2135 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2136 is mandatory (see above) */
2137 p->dma = PARPORT_DMA_NONE;
2138
2139#ifdef CONFIG_PARPORT_PC_FIFO
2140 if (parport_ECP_supported(p) &&
2141 p->dma != PARPORT_DMA_NOFIFO &&
2142 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2143 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2144 if (p->dma != PARPORT_DMA_NONE)
2145 p->modes |= PARPORT_MODE_DMA;
2146 } else
2147 /* We can't use the DMA channel after all. */
2148 p->dma = PARPORT_DMA_NONE;
2149#endif /* Allowed to use FIFO/DMA */
2150
2151 p->modes &= ~mode_mask;
2152
2153#ifdef CONFIG_PARPORT_PC_FIFO
2154 if ((p->modes & PARPORT_MODE_COMPAT) != 0)
2155 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2156#ifdef CONFIG_PARPORT_1284
2157 if ((p->modes & PARPORT_MODE_ECP) != 0)
2158 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2159#endif
2160 if ((p->modes & (PARPORT_MODE_ECP | PARPORT_MODE_COMPAT)) != 0) {
2161 if ((p->modes & PARPORT_MODE_DMA) != 0)
2162 pr_cont(", dma %d", p->dma);
2163 else
2164 pr_cont(", using FIFO");
2165 }
2166#endif /* Allowed to use FIFO/DMA */
2167
2168 pr_cont(" [");
2169
2170#define printmode(x) \
2171do { \
2172 if (p->modes & PARPORT_MODE_##x) \
2173 pr_cont("%s%s", f++ ? "," : "", #x); \
2174} while (0)
2175
2176 {
2177 int f = 0;
2178 printmode(PCSPP);
2179 printmode(TRISTATE);
2180 printmode(COMPAT);
2181 printmode(EPP);
2182 printmode(ECP);
2183 printmode(DMA);
2184 }
2185#undef printmode
2186#ifndef CONFIG_PARPORT_1284
2187 pr_cont("(,...)");
2188#endif /* CONFIG_PARPORT_1284 */
2189 pr_cont("]\n");
2190 if (probedirq != PARPORT_IRQ_NONE)
2191 pr_info("%s: irq %d detected\n", p->name, probedirq);
2192
2193 /* If No ECP release the ports grabbed above. */
2194 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2195 release_region(base_hi, 3);
2196 ECR_res = NULL;
2197 }
2198 /* Likewise for EEP ports */
2199 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2200 release_region(base+3, 5);
2201 EPP_res = NULL;
2202 }
2203 if (p->irq != PARPORT_IRQ_NONE) {
2204 if (request_irq(p->irq, parport_irq_handler,
2205 irqflags, p->name, p)) {
2206 pr_warn("%s: irq %d in use, resorting to polled operation\n",
2207 p->name, p->irq);
2208 p->irq = PARPORT_IRQ_NONE;
2209 p->dma = PARPORT_DMA_NONE;
2210 }
2211
2212#ifdef CONFIG_PARPORT_PC_FIFO
2213#ifdef HAS_DMA
2214 if (p->dma != PARPORT_DMA_NONE) {
2215 if (request_dma(p->dma, p->name)) {
2216 pr_warn("%s: dma %d in use, resorting to PIO operation\n",
2217 p->name, p->dma);
2218 p->dma = PARPORT_DMA_NONE;
2219 } else {
2220 priv->dma_buf =
2221 dma_alloc_coherent(dev,
2222 PAGE_SIZE,
2223 &priv->dma_handle,
2224 GFP_KERNEL);
2225 if (!priv->dma_buf) {
2226 pr_warn("%s: cannot get buffer for DMA, resorting to PIO operation\n",
2227 p->name);
2228 free_dma(p->dma);
2229 p->dma = PARPORT_DMA_NONE;
2230 }
2231 }
2232 }
2233#endif
2234#endif
2235 }
2236
2237 /* Done probing. Now put the port into a sensible start-up state. */
2238 if (priv->ecr)
2239 /*
2240 * Put the ECP detected port in PS2 mode.
2241 * Do this also for ports that have ECR but don't do ECP.
2242 */
2243 ECR_WRITE(p, 0x34);
2244
2245 parport_pc_write_data(p, 0);
2246 parport_pc_data_forward(p);
2247
2248 /* Now that we've told the sharing engine about the port, and
2249 found out its characteristics, let the high-level drivers
2250 know about it. */
2251 spin_lock(&ports_lock);
2252 list_add(&priv->list, &ports_list);
2253 spin_unlock(&ports_lock);
2254 parport_announce_port(p);
2255
2256 return p;
2257
2258out5:
2259 if (ECR_res)
2260 release_region(base_hi, 3);
2261 if (EPP_res)
2262 release_region(base+0x3, 5);
2263 release_region(base, 3);
2264out4:
2265 parport_del_port(p);
2266out3:
2267 kfree(priv);
2268out2:
2269 kfree(ops);
2270out1:
2271 if (pdev)
2272 platform_device_unregister(pdev);
2273 return NULL;
2274}
2275
2276struct parport *parport_pc_probe_port(unsigned long int base,
2277 unsigned long int base_hi,
2278 int irq, int dma,
2279 struct device *dev,
2280 int irqflags)
2281{
2282 return __parport_pc_probe_port(base, base_hi, irq, dma,
2283 dev, irqflags, 0, 0);
2284}
2285EXPORT_SYMBOL(parport_pc_probe_port);
2286
2287void parport_pc_unregister_port(struct parport *p)
2288{
2289 struct parport_pc_private *priv = p->private_data;
2290 struct parport_operations *ops = p->ops;
2291
2292 parport_remove_port(p);
2293 spin_lock(&ports_lock);
2294 list_del_init(&priv->list);
2295 spin_unlock(&ports_lock);
2296#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2297 if (p->dma != PARPORT_DMA_NONE)
2298 free_dma(p->dma);
2299#endif
2300 if (p->irq != PARPORT_IRQ_NONE)
2301 free_irq(p->irq, p);
2302 release_region(p->base, 3);
2303 if (p->size > 3)
2304 release_region(p->base + 3, p->size - 3);
2305 if (p->modes & PARPORT_MODE_ECP)
2306 release_region(p->base_hi, 3);
2307#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2308 if (priv->dma_buf)
2309 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2310 priv->dma_buf,
2311 priv->dma_handle);
2312#endif
2313 kfree(p->private_data);
2314 parport_del_port(p);
2315 kfree(ops); /* hope no-one cached it */
2316}
2317EXPORT_SYMBOL(parport_pc_unregister_port);
2318
2319#ifdef CONFIG_PCI
2320
2321/* ITE support maintained by Rich Liu <richliu@poorman.org> */
2322static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
2323 const struct parport_pc_via_data *via)
2324{
2325 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2326 u32 ite8872set;
2327 u32 ite8872_lpt, ite8872_lpthi;
2328 u8 ite8872_irq, type;
2329 int irq;
2330 int i;
2331
2332 pr_debug("sio_ite_8872_probe()\n");
2333
2334 /* make sure which one chip */
2335 for (i = 0; i < 5; i++) {
2336 if (request_region(inta_addr[i], 32, "it887x")) {
2337 int test;
2338 pci_write_config_dword(pdev, 0x60,
2339 0xe5000000 | inta_addr[i]);
2340 pci_write_config_dword(pdev, 0x78,
2341 0x00000000 | inta_addr[i]);
2342 test = inb(inta_addr[i]);
2343 if (test != 0xff)
2344 break;
2345 release_region(inta_addr[i], 32);
2346 }
2347 }
2348 if (i >= 5) {
2349 pr_info("parport_pc: cannot find ITE8872 INTA\n");
2350 return 0;
2351 }
2352
2353 type = inb(inta_addr[i] + 0x18);
2354 type &= 0x0f;
2355
2356 switch (type) {
2357 case 0x2:
2358 pr_info("parport_pc: ITE8871 found (1P)\n");
2359 ite8872set = 0x64200000;
2360 break;
2361 case 0xa:
2362 pr_info("parport_pc: ITE8875 found (1P)\n");
2363 ite8872set = 0x64200000;
2364 break;
2365 case 0xe:
2366 pr_info("parport_pc: ITE8872 found (2S1P)\n");
2367 ite8872set = 0x64e00000;
2368 break;
2369 case 0x6:
2370 pr_info("parport_pc: ITE8873 found (1S)\n");
2371 release_region(inta_addr[i], 32);
2372 return 0;
2373 case 0x8:
2374 pr_info("parport_pc: ITE8874 found (2S)\n");
2375 release_region(inta_addr[i], 32);
2376 return 0;
2377 default:
2378 pr_info("parport_pc: unknown ITE887x\n");
2379 pr_info("parport_pc: please mail 'lspci -nvv' output to Rich.Liu@ite.com.tw\n");
2380 release_region(inta_addr[i], 32);
2381 return 0;
2382 }
2383
2384 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2385 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2386 ite8872_lpt &= 0x0000ff00;
2387 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2388 ite8872_lpthi &= 0x0000ff00;
2389 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2390 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2391 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2392 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2393 /* SET Parallel IRQ */
2394 pci_write_config_dword(pdev, 0x9c,
2395 ite8872set | (ite8872_irq * 0x11111));
2396
2397 pr_debug("ITE887x: The IRQ is %d\n", ite8872_irq);
2398 pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt);
2399 pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi);
2400
2401 /* Let the user (or defaults) steer us away from interrupts */
2402 irq = ite8872_irq;
2403 if (autoirq != PARPORT_IRQ_AUTO)
2404 irq = PARPORT_IRQ_NONE;
2405
2406 /*
2407 * Release the resource so that parport_pc_probe_port can get it.
2408 */
2409 release_region(inta_addr[i], 32);
2410 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2411 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2412 pr_info("parport_pc: ITE 8872 parallel port: io=0x%X",
2413 ite8872_lpt);
2414 if (irq != PARPORT_IRQ_NONE)
2415 pr_cont(", irq=%d", irq);
2416 pr_cont("\n");
2417 return 1;
2418 }
2419
2420 return 0;
2421}
2422
2423/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2424 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2425static int parport_init_mode;
2426
2427/* Data for two known VIA chips */
2428static struct parport_pc_via_data via_686a_data = {
2429 0x51,
2430 0x50,
2431 0x85,
2432 0x02,
2433 0xE2,
2434 0xF0,
2435 0xE6
2436};
2437static struct parport_pc_via_data via_8231_data = {
2438 0x45,
2439 0x44,
2440 0x50,
2441 0x04,
2442 0xF2,
2443 0xFA,
2444 0xF6
2445};
2446
2447static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
2448 const struct parport_pc_via_data *via)
2449{
2450 u8 tmp, tmp2, siofunc;
2451 u8 ppcontrol = 0;
2452 int dma, irq;
2453 unsigned port1, port2;
2454 unsigned have_epp = 0;
2455
2456 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2457
2458 switch (parport_init_mode) {
2459 case 1:
2460 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2461 siofunc = VIA_FUNCTION_PARPORT_SPP;
2462 break;
2463 case 2:
2464 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2465 siofunc = VIA_FUNCTION_PARPORT_SPP;
2466 ppcontrol = VIA_PARPORT_BIDIR;
2467 break;
2468 case 3:
2469 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2470 siofunc = VIA_FUNCTION_PARPORT_EPP;
2471 ppcontrol = VIA_PARPORT_BIDIR;
2472 have_epp = 1;
2473 break;
2474 case 4:
2475 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2476 siofunc = VIA_FUNCTION_PARPORT_ECP;
2477 ppcontrol = VIA_PARPORT_BIDIR;
2478 break;
2479 case 5:
2480 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2481 siofunc = VIA_FUNCTION_PARPORT_ECP;
2482 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2483 have_epp = 1;
2484 break;
2485 default:
2486 printk(KERN_DEBUG "parport_pc: probing current configuration\n");
2487 siofunc = VIA_FUNCTION_PROBE;
2488 break;
2489 }
2490 /*
2491 * unlock super i/o configuration
2492 */
2493 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2494 tmp |= via->via_pci_superio_config_data;
2495 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2496
2497 /* Bits 1-0: Parallel Port Mode / Enable */
2498 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2499 tmp = inb(VIA_CONFIG_DATA);
2500 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2501 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2502 tmp2 = inb(VIA_CONFIG_DATA);
2503 if (siofunc == VIA_FUNCTION_PROBE) {
2504 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2505 ppcontrol = tmp2;
2506 } else {
2507 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2508 tmp |= siofunc;
2509 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2510 outb(tmp, VIA_CONFIG_DATA);
2511 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2512 tmp2 |= ppcontrol;
2513 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2514 outb(tmp2, VIA_CONFIG_DATA);
2515 }
2516
2517 /* Parallel Port I/O Base Address, bits 9-2 */
2518 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2519 port1 = inb(VIA_CONFIG_DATA) << 2;
2520
2521 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2522 port1);
2523 if (port1 == 0x3BC && have_epp) {
2524 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2525 outb((0x378 >> 2), VIA_CONFIG_DATA);
2526 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2527 port1 = 0x378;
2528 }
2529
2530 /*
2531 * lock super i/o configuration
2532 */
2533 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2534 tmp &= ~via->via_pci_superio_config_data;
2535 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2536
2537 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2538 pr_info("parport_pc: VIA parallel port disabled in BIOS\n");
2539 return 0;
2540 }
2541
2542 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2543 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2544 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2545
2546 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2547 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2548 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2549 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2550 } else
2551 /* if ECP not enabled, DMA is not enabled, assumed
2552 bogus 'dma' value */
2553 dma = PARPORT_DMA_NONE;
2554
2555 /* Let the user (or defaults) steer us away from interrupts and DMA */
2556 if (autoirq == PARPORT_IRQ_NONE) {
2557 irq = PARPORT_IRQ_NONE;
2558 dma = PARPORT_DMA_NONE;
2559 }
2560 if (autodma == PARPORT_DMA_NONE)
2561 dma = PARPORT_DMA_NONE;
2562
2563 switch (port1) {
2564 case 0x3bc:
2565 port2 = 0x7bc; break;
2566 case 0x378:
2567 port2 = 0x778; break;
2568 case 0x278:
2569 port2 = 0x678; break;
2570 default:
2571 pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2572 port1);
2573 return 0;
2574 }
2575
2576 /* filter bogus IRQs */
2577 switch (irq) {
2578 case 0:
2579 case 2:
2580 case 8:
2581 case 13:
2582 irq = PARPORT_IRQ_NONE;
2583 break;
2584
2585 default: /* do nothing */
2586 break;
2587 }
2588
2589 /* finally, do the probe with values obtained */
2590 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2591 pr_info("parport_pc: VIA parallel port: io=0x%X", port1);
2592 if (irq != PARPORT_IRQ_NONE)
2593 pr_cont(", irq=%d", irq);
2594 if (dma != PARPORT_DMA_NONE)
2595 pr_cont(", dma=%d", dma);
2596 pr_cont("\n");
2597 return 1;
2598 }
2599
2600 pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2601 port1, irq, dma);
2602 return 0;
2603}
2604
2605
2606enum parport_pc_sio_types {
2607 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2608 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2609 sio_ite_8872,
2610 last_sio
2611};
2612
2613/* each element directly indexed from enum list, above */
2614static struct parport_pc_superio {
2615 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2616 const struct parport_pc_via_data *via);
2617 const struct parport_pc_via_data *via;
2618} parport_pc_superio_info[] = {
2619 { sio_via_probe, &via_686a_data, },
2620 { sio_via_probe, &via_8231_data, },
2621 { sio_ite_8872_probe, NULL, },
2622};
2623
2624enum parport_pc_pci_cards {
2625 siig_1p_10x = last_sio,
2626 siig_2p_10x,
2627 siig_1p_20x,
2628 siig_2p_20x,
2629 lava_parallel,
2630 lava_parallel_dual_a,
2631 lava_parallel_dual_b,
2632 boca_ioppar,
2633 plx_9050,
2634 timedia_4006a,
2635 timedia_4014,
2636 timedia_4008a,
2637 timedia_4018,
2638 timedia_9018a,
2639 syba_2p_epp,
2640 syba_1p_ecp,
2641 titan_010l,
2642 avlab_1p,
2643 avlab_2p,
2644 oxsemi_952,
2645 oxsemi_954,
2646 oxsemi_840,
2647 oxsemi_pcie_pport,
2648 aks_0100,
2649 mobility_pp,
2650 netmos_9900,
2651 netmos_9705,
2652 netmos_9715,
2653 netmos_9755,
2654 netmos_9805,
2655 netmos_9815,
2656 netmos_9901,
2657 netmos_9865,
2658 asix_ax99100,
2659 quatech_sppxp100,
2660 wch_ch382l,
2661 brainboxes_uc146,
2662 brainboxes_px203,
2663};
2664
2665
2666/* each element directly indexed from enum list, above
2667 * (but offset by last_sio) */
2668static struct parport_pc_pci {
2669 int numports;
2670 struct { /* BAR (base address registers) numbers in the config
2671 space header */
2672 int lo;
2673 int hi;
2674 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2675 } addr[2];
2676
2677 /* Bit field of parport modes to exclude. */
2678 unsigned int mode_mask;
2679
2680 /* If non-zero, sets the bitmask of writable ECR bits. In that
2681 * case additionally bit 0 will be forcibly set on writes. */
2682 unsigned char ecr_writable;
2683
2684 /* If set, this is called immediately after pci_enable_device.
2685 * If it returns non-zero, no probing will take place and the
2686 * ports will not be used. */
2687 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2688
2689 /* If set, this is called after probing for ports. If 'failed'
2690 * is non-zero we couldn't use any of the ports. */
2691 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2692} cards[] = {
2693 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2694 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2695 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2696 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2697 /* lava_parallel */ { 1, { { 0, -1 }, } },
2698 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2699 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2700 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2701 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2702 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2703 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2704 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2705 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2706 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2707 /* SYBA uses fixed offsets in
2708 a 1K io window */
2709 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2710 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2711 /* titan_010l */ { 1, { { 3, -1 }, } },
2712 /* avlab_1p */ { 1, { { 0, 1}, } },
2713 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2714 /* The Oxford Semi cards are unusual: older variants of 954 don't
2715 * support ECP, and 840 locks up if you write 1 to bit 2! None
2716 * implement nFault or service interrupts and all require 00001
2717 * bit pattern to be used for bits 4:0 with ECR writes. */
2718 /* oxsemi_952 */ { 1, { { 0, 1 }, },
2719 PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2720 /* oxsemi_954 */ { 1, { { 0, 1 }, },
2721 PARPORT_MODE_ECP |
2722 PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2723 /* oxsemi_840 */ { 1, { { 0, 1 }, },
2724 PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2725 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, },
2726 PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2727 /* aks_0100 */ { 1, { { 0, -1 }, } },
2728 /* mobility_pp */ { 1, { { 0, 1 }, } },
2729 /* netmos_9900 */ { 1, { { 0, -1 }, } },
2730
2731 /* The netmos entries below are untested */
2732 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2733 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2734 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2735 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2736 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2737 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2738 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2739 /* asix_ax99100 */ { 1, { { 0, 1 }, } },
2740 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2741 /* wch_ch382l */ { 1, { { 2, -1 }, } },
2742 /* brainboxes_uc146 */ { 1, { { 3, -1 }, } },
2743 /* brainboxes_px203 */ { 1, { { 0, -1 }, } },
2744};
2745
2746static const struct pci_device_id parport_pc_pci_tbl[] = {
2747 /* Super-IO onboard chips */
2748 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2749 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2750 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2752
2753 /* PCI cards */
2754 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2756 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2758 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2759 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2760 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2762 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2764 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2766 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2768 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2770 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2771 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2772 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2773 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2774 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2775 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2776 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2777 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2778 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2780 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2782 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2784 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2785 /* AFAVLAB_TK9902 */
2786 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2787 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2788 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2790 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2792 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2794 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2796 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2798 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2800 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2802 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2804 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2806 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2808 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2810 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2812 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2813 /* NetMos communication controllers */
2814 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
2815 0xA000, 0x2000, 0, 0, netmos_9900 },
2816 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2818 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2819 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2820 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2822 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2824 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2825 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2826 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2827 0xA000, 0x2000, 0, 0, netmos_9901 },
2828 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2829 0xA000, 0x1000, 0, 0, netmos_9865 },
2830 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2831 0xA000, 0x2000, 0, 0, netmos_9865 },
2832 /* ASIX AX99100 PCIe to Multi I/O Controller */
2833 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
2834 0xA000, 0x2000, 0, 0, asix_ax99100 },
2835 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2836 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2838 /* WCH CH382L PCI-E single parallel port card */
2839 { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l },
2840 /* Brainboxes IX-500/550 */
2841 { PCI_VENDOR_ID_INTASHIELD, 0x402a,
2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2843 /* Brainboxes UC-146/UC-157 */
2844 { PCI_VENDOR_ID_INTASHIELD, 0x0be1,
2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 },
2846 { PCI_VENDOR_ID_INTASHIELD, 0x0be2,
2847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 },
2848 /* Brainboxes PX-146/PX-257 */
2849 { PCI_VENDOR_ID_INTASHIELD, 0x401c,
2850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2851 /* Brainboxes PX-203 */
2852 { PCI_VENDOR_ID_INTASHIELD, 0x4007,
2853 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_px203 },
2854 /* Brainboxes PX-475 */
2855 { PCI_VENDOR_ID_INTASHIELD, 0x401f,
2856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2857 { 0, } /* terminate list */
2858};
2859MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
2860
2861struct pci_parport_data {
2862 int num;
2863 struct parport *ports[2];
2864};
2865
2866static int parport_pc_pci_probe(struct pci_dev *dev,
2867 const struct pci_device_id *id)
2868{
2869 int err, count, n, i = id->driver_data;
2870 struct pci_parport_data *data;
2871
2872 if (i < last_sio)
2873 /* This is an onboard Super-IO and has already been probed */
2874 return 0;
2875
2876 /* This is a PCI card */
2877 i -= last_sio;
2878 count = 0;
2879 err = pci_enable_device(dev);
2880 if (err)
2881 return err;
2882
2883 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2884 if (!data)
2885 return -ENOMEM;
2886
2887 if (cards[i].preinit_hook &&
2888 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2889 kfree(data);
2890 return -ENODEV;
2891 }
2892
2893 for (n = 0; n < cards[i].numports; n++) {
2894 int lo = cards[i].addr[n].lo;
2895 int hi = cards[i].addr[n].hi;
2896 int irq;
2897 unsigned long io_lo, io_hi;
2898 io_lo = pci_resource_start(dev, lo);
2899 io_hi = 0;
2900 if ((hi >= 0) && (hi <= 6))
2901 io_hi = pci_resource_start(dev, hi);
2902 else if (hi > 6)
2903 io_lo += hi; /* Reinterpret the meaning of
2904 "hi" as an offset (see SYBA
2905 def.) */
2906 /* TODO: test if sharing interrupts works */
2907 irq = dev->irq;
2908 if (irq == IRQ_NONE) {
2909 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2910 id->vendor, id->device, io_lo, io_hi);
2911 irq = PARPORT_IRQ_NONE;
2912 } else {
2913 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2914 id->vendor, id->device, io_lo, io_hi, irq);
2915 }
2916 data->ports[count] =
2917 __parport_pc_probe_port(io_lo, io_hi, irq,
2918 PARPORT_DMA_NONE, &dev->dev,
2919 IRQF_SHARED,
2920 cards[i].mode_mask,
2921 cards[i].ecr_writable);
2922 if (data->ports[count])
2923 count++;
2924 }
2925
2926 data->num = count;
2927
2928 if (cards[i].postinit_hook)
2929 cards[i].postinit_hook(dev, count == 0);
2930
2931 if (count) {
2932 pci_set_drvdata(dev, data);
2933 return 0;
2934 }
2935
2936 kfree(data);
2937
2938 return -ENODEV;
2939}
2940
2941static void parport_pc_pci_remove(struct pci_dev *dev)
2942{
2943 struct pci_parport_data *data = pci_get_drvdata(dev);
2944 int i;
2945
2946 if (data) {
2947 for (i = data->num - 1; i >= 0; i--)
2948 parport_pc_unregister_port(data->ports[i]);
2949
2950 kfree(data);
2951 }
2952}
2953
2954static struct pci_driver parport_pc_pci_driver = {
2955 .name = "parport_pc",
2956 .id_table = parport_pc_pci_tbl,
2957 .probe = parport_pc_pci_probe,
2958 .remove = parport_pc_pci_remove,
2959};
2960
2961static int __init parport_pc_init_superio(int autoirq, int autodma)
2962{
2963 const struct pci_device_id *id;
2964 struct pci_dev *pdev = NULL;
2965 int ret = 0;
2966
2967 for_each_pci_dev(pdev) {
2968 id = pci_match_id(parport_pc_pci_tbl, pdev);
2969 if (id == NULL || id->driver_data >= last_sio)
2970 continue;
2971
2972 if (parport_pc_superio_info[id->driver_data].probe(
2973 pdev, autoirq, autodma,
2974 parport_pc_superio_info[id->driver_data].via)) {
2975 ret++;
2976 }
2977 }
2978
2979 return ret; /* number of devices found */
2980}
2981#else
2982static struct pci_driver parport_pc_pci_driver;
2983static int __init parport_pc_init_superio(int autoirq, int autodma)
2984{
2985 return 0;
2986}
2987#endif /* CONFIG_PCI */
2988
2989#ifdef CONFIG_PNP
2990
2991static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2992 /* Standard LPT Printer Port */
2993 {.id = "PNP0400", .driver_data = 0},
2994 /* ECP Printer Port */
2995 {.id = "PNP0401", .driver_data = 0},
2996 { }
2997};
2998
2999MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
3000
3001static int parport_pc_pnp_probe(struct pnp_dev *dev,
3002 const struct pnp_device_id *id)
3003{
3004 struct parport *pdata;
3005 unsigned long io_lo, io_hi;
3006 int dma, irq;
3007
3008 if (pnp_port_valid(dev, 0) &&
3009 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
3010 io_lo = pnp_port_start(dev, 0);
3011 } else
3012 return -EINVAL;
3013
3014 if (pnp_port_valid(dev, 1) &&
3015 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
3016 io_hi = pnp_port_start(dev, 1);
3017 } else
3018 io_hi = 0;
3019
3020 if (pnp_irq_valid(dev, 0) &&
3021 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
3022 irq = pnp_irq(dev, 0);
3023 } else
3024 irq = PARPORT_IRQ_NONE;
3025
3026 if (pnp_dma_valid(dev, 0) &&
3027 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
3028 dma = pnp_dma(dev, 0);
3029 } else
3030 dma = PARPORT_DMA_NONE;
3031
3032 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
3033 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
3034 if (pdata == NULL)
3035 return -ENODEV;
3036
3037 pnp_set_drvdata(dev, pdata);
3038 return 0;
3039}
3040
3041static void parport_pc_pnp_remove(struct pnp_dev *dev)
3042{
3043 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3044 if (!pdata)
3045 return;
3046
3047 parport_pc_unregister_port(pdata);
3048}
3049
3050/* we only need the pnp layer to activate the device, at least for now */
3051static struct pnp_driver parport_pc_pnp_driver = {
3052 .name = "parport_pc",
3053 .id_table = parport_pc_pnp_tbl,
3054 .probe = parport_pc_pnp_probe,
3055 .remove = parport_pc_pnp_remove,
3056};
3057
3058#else
3059static struct pnp_driver parport_pc_pnp_driver;
3060#endif /* CONFIG_PNP */
3061
3062static int parport_pc_platform_probe(struct platform_device *pdev)
3063{
3064 /* Always succeed, the actual probing is done in
3065 * parport_pc_probe_port(). */
3066 return 0;
3067}
3068
3069static struct platform_driver parport_pc_platform_driver = {
3070 .driver = {
3071 .name = "parport_pc",
3072 },
3073 .probe = parport_pc_platform_probe,
3074};
3075
3076/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3077static int __attribute__((unused))
3078parport_pc_find_isa_ports(int autoirq, int autodma)
3079{
3080 int count = 0;
3081
3082 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3083 count++;
3084 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3085 count++;
3086 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3087 count++;
3088
3089 return count;
3090}
3091
3092/* This function is called by parport_pc_init if the user didn't
3093 * specify any ports to probe. Its job is to find some ports. Order
3094 * is important here -- we want ISA ports to be registered first,
3095 * followed by PCI cards (for least surprise), but before that we want
3096 * to do chipset-specific tests for some onboard ports that we know
3097 * about.
3098 *
3099 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3100 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3101 */
3102static void __init parport_pc_find_ports(int autoirq, int autodma)
3103{
3104 int count = 0, err;
3105
3106#ifdef CONFIG_PARPORT_PC_SUPERIO
3107 detect_and_report_it87();
3108 detect_and_report_winbond();
3109 detect_and_report_smsc();
3110#endif
3111
3112 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3113 count += parport_pc_init_superio(autoirq, autodma);
3114
3115 /* PnP ports, skip detection if SuperIO already found them */
3116 if (!count) {
3117 err = pnp_register_driver(&parport_pc_pnp_driver);
3118 if (!err)
3119 pnp_registered_parport = 1;
3120 }
3121
3122 /* ISA ports and whatever (see asm/parport.h). */
3123 parport_pc_find_nonpci_ports(autoirq, autodma);
3124
3125 err = pci_register_driver(&parport_pc_pci_driver);
3126 if (!err)
3127 pci_registered_parport = 1;
3128}
3129
3130/*
3131 * Piles of crap below pretend to be a parser for module and kernel
3132 * parameters. Say "thank you" to whoever had come up with that
3133 * syntax and keep in mind that code below is a cleaned up version.
3134 */
3135
3136static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3137 [0 ... PARPORT_PC_MAX_PORTS] = 0
3138};
3139static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3140 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3141};
3142static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3143 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3144};
3145static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3146 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3147};
3148
3149static int __init parport_parse_param(const char *s, int *val,
3150 int automatic, int none, int nofifo)
3151{
3152 if (!s)
3153 return 0;
3154 if (!strncmp(s, "auto", 4))
3155 *val = automatic;
3156 else if (!strncmp(s, "none", 4))
3157 *val = none;
3158 else if (nofifo && !strncmp(s, "nofifo", 6))
3159 *val = nofifo;
3160 else {
3161 char *ep;
3162 unsigned long r = simple_strtoul(s, &ep, 0);
3163 if (ep != s)
3164 *val = r;
3165 else {
3166 pr_err("parport: bad specifier `%s'\n", s);
3167 return -1;
3168 }
3169 }
3170 return 0;
3171}
3172
3173static int __init parport_parse_irq(const char *irqstr, int *val)
3174{
3175 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3176 PARPORT_IRQ_NONE, 0);
3177}
3178
3179static int __init parport_parse_dma(const char *dmastr, int *val)
3180{
3181 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3182 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3183}
3184
3185#ifdef CONFIG_PCI
3186static int __init parport_init_mode_setup(char *str)
3187{
3188 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n",
3189 str);
3190
3191 if (!strcmp(str, "spp"))
3192 parport_init_mode = 1;
3193 if (!strcmp(str, "ps2"))
3194 parport_init_mode = 2;
3195 if (!strcmp(str, "epp"))
3196 parport_init_mode = 3;
3197 if (!strcmp(str, "ecp"))
3198 parport_init_mode = 4;
3199 if (!strcmp(str, "ecpepp"))
3200 parport_init_mode = 5;
3201 return 1;
3202}
3203#endif
3204
3205#ifdef MODULE
3206static char *irq[PARPORT_PC_MAX_PORTS];
3207static char *dma[PARPORT_PC_MAX_PORTS];
3208
3209MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3210module_param_hw_array(io, int, ioport, NULL, 0);
3211MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3212module_param_hw_array(io_hi, int, ioport, NULL, 0);
3213MODULE_PARM_DESC(irq, "IRQ line");
3214module_param_hw_array(irq, charp, irq, NULL, 0);
3215MODULE_PARM_DESC(dma, "DMA channel");
3216module_param_hw_array(dma, charp, dma, NULL, 0);
3217#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3218 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3219MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3220module_param(verbose_probing, int, 0644);
3221#endif
3222#ifdef CONFIG_PCI
3223static char *init_mode;
3224MODULE_PARM_DESC(init_mode,
3225 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3226module_param(init_mode, charp, 0);
3227#endif
3228
3229static int __init parse_parport_params(void)
3230{
3231 unsigned int i;
3232 int val;
3233
3234#ifdef CONFIG_PCI
3235 if (init_mode)
3236 parport_init_mode_setup(init_mode);
3237#endif
3238
3239 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3240 if (parport_parse_irq(irq[i], &val))
3241 return 1;
3242 irqval[i] = val;
3243 if (parport_parse_dma(dma[i], &val))
3244 return 1;
3245 dmaval[i] = val;
3246 }
3247 if (!io[0]) {
3248 /* The user can make us use any IRQs or DMAs we find. */
3249 if (irq[0] && !parport_parse_irq(irq[0], &val))
3250 switch (val) {
3251 case PARPORT_IRQ_NONE:
3252 case PARPORT_IRQ_AUTO:
3253 irqval[0] = val;
3254 break;
3255 default:
3256 pr_warn("parport_pc: irq specified without base address. Use 'io=' to specify one\n");
3257 }
3258
3259 if (dma[0] && !parport_parse_dma(dma[0], &val))
3260 switch (val) {
3261 case PARPORT_DMA_NONE:
3262 case PARPORT_DMA_AUTO:
3263 dmaval[0] = val;
3264 break;
3265 default:
3266 pr_warn("parport_pc: dma specified without base address. Use 'io=' to specify one\n");
3267 }
3268 }
3269 return 0;
3270}
3271
3272#else
3273
3274static int parport_setup_ptr __initdata;
3275
3276/*
3277 * Acceptable parameters:
3278 *
3279 * parport=0
3280 * parport=auto
3281 * parport=0xBASE[,IRQ[,DMA]]
3282 *
3283 * IRQ/DMA may be numeric or 'auto' or 'none'
3284 */
3285static int __init parport_setup(char *str)
3286{
3287 char *endptr;
3288 char *sep;
3289 int val;
3290
3291 if (!str || !*str || (*str == '0' && !*(str+1))) {
3292 /* Disable parport if "parport=0" in cmdline */
3293 io[0] = PARPORT_DISABLE;
3294 return 1;
3295 }
3296
3297 if (!strncmp(str, "auto", 4)) {
3298 irqval[0] = PARPORT_IRQ_AUTO;
3299 dmaval[0] = PARPORT_DMA_AUTO;
3300 return 1;
3301 }
3302
3303 val = simple_strtoul(str, &endptr, 0);
3304 if (endptr == str) {
3305 pr_warn("parport=%s not understood\n", str);
3306 return 1;
3307 }
3308
3309 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3310 pr_err("parport=%s ignored, too many ports\n", str);
3311 return 1;
3312 }
3313
3314 io[parport_setup_ptr] = val;
3315 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3316 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3317
3318 sep = strchr(str, ',');
3319 if (sep++) {
3320 if (parport_parse_irq(sep, &val))
3321 return 1;
3322 irqval[parport_setup_ptr] = val;
3323 sep = strchr(sep, ',');
3324 if (sep++) {
3325 if (parport_parse_dma(sep, &val))
3326 return 1;
3327 dmaval[parport_setup_ptr] = val;
3328 }
3329 }
3330 parport_setup_ptr++;
3331 return 1;
3332}
3333
3334static int __init parse_parport_params(void)
3335{
3336 return io[0] == PARPORT_DISABLE;
3337}
3338
3339__setup("parport=", parport_setup);
3340
3341/*
3342 * Acceptable parameters:
3343 *
3344 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3345 */
3346#ifdef CONFIG_PCI
3347__setup("parport_init_mode=", parport_init_mode_setup);
3348#endif
3349#endif
3350
3351/* "Parser" ends here */
3352
3353static int __init parport_pc_init(void)
3354{
3355 int err;
3356
3357 if (parse_parport_params())
3358 return -EINVAL;
3359
3360 err = platform_driver_register(&parport_pc_platform_driver);
3361 if (err)
3362 return err;
3363
3364 if (io[0]) {
3365 int i;
3366 /* Only probe the ports we were given. */
3367 user_specified = 1;
3368 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3369 if (!io[i])
3370 break;
3371 if (io_hi[i] == PARPORT_IOHI_AUTO)
3372 io_hi[i] = 0x400 + io[i];
3373 parport_pc_probe_port(io[i], io_hi[i],
3374 irqval[i], dmaval[i], NULL, 0);
3375 }
3376 } else
3377 parport_pc_find_ports(irqval[0], dmaval[0]);
3378
3379 return 0;
3380}
3381
3382static void __exit parport_pc_exit(void)
3383{
3384 if (pci_registered_parport)
3385 pci_unregister_driver(&parport_pc_pci_driver);
3386 if (pnp_registered_parport)
3387 pnp_unregister_driver(&parport_pc_pnp_driver);
3388 platform_driver_unregister(&parport_pc_platform_driver);
3389
3390 while (!list_empty(&ports_list)) {
3391 struct parport_pc_private *priv;
3392 struct parport *port;
3393 struct device *dev;
3394 priv = list_entry(ports_list.next,
3395 struct parport_pc_private, list);
3396 port = priv->port;
3397 dev = port->dev;
3398 parport_pc_unregister_port(port);
3399 if (dev && dev->bus == &platform_bus_type)
3400 platform_device_unregister(to_platform_device(dev));
3401 }
3402}
3403
3404MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3405MODULE_DESCRIPTION("PC-style parallel port driver");
3406MODULE_LICENSE("GPL");
3407module_init(parport_pc_init)
3408module_exit(parport_pc_exit)
1/* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19/* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45#include <linux/module.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/delay.h>
49#include <linux/errno.h>
50#include <linux/interrupt.h>
51#include <linux/ioport.h>
52#include <linux/kernel.h>
53#include <linux/slab.h>
54#include <linux/dma-mapping.h>
55#include <linux/pci.h>
56#include <linux/pnp.h>
57#include <linux/platform_device.h>
58#include <linux/sysctl.h>
59#include <linux/io.h>
60#include <linux/uaccess.h>
61
62#include <asm/dma.h>
63
64#include <linux/parport.h>
65#include <linux/parport_pc.h>
66#include <linux/via.h>
67#include <asm/parport.h>
68
69#define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
71#ifdef CONFIG_ISA_DMA_API
72#define HAS_DMA
73#endif
74
75/* ECR modes */
76#define ECR_SPP 00
77#define ECR_PS2 01
78#define ECR_PPF 02
79#define ECR_ECP 03
80#define ECR_EPP 04
81#define ECR_VND 05
82#define ECR_TST 06
83#define ECR_CNF 07
84#define ECR_MODE_MASK 0xe0
85#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
86
87#undef DEBUG
88
89#ifdef DEBUG
90#define DPRINTK printk
91#else
92#define DPRINTK(stuff...)
93#endif
94
95
96#define NR_SUPERIOS 3
97static struct superio_struct { /* For Super-IO chips autodetection */
98 int io;
99 int irq;
100 int dma;
101} superios[NR_SUPERIOS] = { {0,},};
102
103static int user_specified;
104#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106static int verbose_probing;
107#endif
108static int pci_registered_parport;
109static int pnp_registered_parport;
110
111/* frob_control, but for ECR */
112static void frob_econtrol(struct parport *pb, unsigned char m,
113 unsigned char v)
114{
115 unsigned char ectr = 0;
116
117 if (m != 0xff)
118 ectr = inb(ECONTROL(pb));
119
120 DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
121 m, v, ectr, (ectr & ~m) ^ v);
122
123 outb((ectr & ~m) ^ v, ECONTROL(pb));
124}
125
126static inline void frob_set_mode(struct parport *p, int mode)
127{
128 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
129}
130
131#ifdef CONFIG_PARPORT_PC_FIFO
132/* Safely change the mode bits in the ECR
133 Returns:
134 0 : Success
135 -EBUSY: Could not drain FIFO in some finite amount of time,
136 mode not changed!
137 */
138static int change_mode(struct parport *p, int m)
139{
140 const struct parport_pc_private *priv = p->physport->private_data;
141 unsigned char oecr;
142 int mode;
143
144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
145
146 if (!priv->ecr) {
147 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
148 return 0;
149 }
150
151 /* Bits <7:5> contain the mode. */
152 oecr = inb(ECONTROL(p));
153 mode = (oecr >> 5) & 0x7;
154 if (mode == m)
155 return 0;
156
157 if (mode >= 2 && !(priv->ctr & 0x20)) {
158 /* This mode resets the FIFO, so we may
159 * have to wait for it to drain first. */
160 unsigned long expire = jiffies + p->physport->cad->timeout;
161 int counter;
162 switch (mode) {
163 case ECR_PPF: /* Parallel Port FIFO mode */
164 case ECR_ECP: /* ECP Parallel Port mode */
165 /* Busy wait for 200us */
166 for (counter = 0; counter < 40; counter++) {
167 if (inb(ECONTROL(p)) & 0x01)
168 break;
169 if (signal_pending(current))
170 break;
171 udelay(5);
172 }
173
174 /* Poll slowly. */
175 while (!(inb(ECONTROL(p)) & 0x01)) {
176 if (time_after_eq(jiffies, expire))
177 /* The FIFO is stuck. */
178 return -EBUSY;
179 schedule_timeout_interruptible(
180 msecs_to_jiffies(10));
181 if (signal_pending(current))
182 break;
183 }
184 }
185 }
186
187 if (mode >= 2 && m >= 2) {
188 /* We have to go through mode 001 */
189 oecr &= ~(7 << 5);
190 oecr |= ECR_PS2 << 5;
191 ECR_WRITE(p, oecr);
192 }
193
194 /* Set the mode. */
195 oecr &= ~(7 << 5);
196 oecr |= m << 5;
197 ECR_WRITE(p, oecr);
198 return 0;
199}
200#endif /* FIFO support */
201
202/*
203 * Clear TIMEOUT BIT in EPP MODE
204 *
205 * This is also used in SPP detection.
206 */
207static int clear_epp_timeout(struct parport *pb)
208{
209 unsigned char r;
210
211 if (!(parport_pc_read_status(pb) & 0x01))
212 return 1;
213
214 /* To clear timeout some chips require double read */
215 parport_pc_read_status(pb);
216 r = parport_pc_read_status(pb);
217 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
218 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
219 r = parport_pc_read_status(pb);
220
221 return !(r & 0x01);
222}
223
224/*
225 * Access functions.
226 *
227 * Most of these aren't static because they may be used by the
228 * parport_xxx_yyy macros. extern __inline__ versions of several
229 * of these are in parport_pc.h.
230 */
231
232static void parport_pc_init_state(struct pardevice *dev,
233 struct parport_state *s)
234{
235 s->u.pc.ctr = 0xc;
236 if (dev->irq_func &&
237 dev->port->irq != PARPORT_IRQ_NONE)
238 /* Set ackIntEn */
239 s->u.pc.ctr |= 0x10;
240
241 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
242 * D.Gruszka VScom */
243}
244
245static void parport_pc_save_state(struct parport *p, struct parport_state *s)
246{
247 const struct parport_pc_private *priv = p->physport->private_data;
248 s->u.pc.ctr = priv->ctr;
249 if (priv->ecr)
250 s->u.pc.ecr = inb(ECONTROL(p));
251}
252
253static void parport_pc_restore_state(struct parport *p,
254 struct parport_state *s)
255{
256 struct parport_pc_private *priv = p->physport->private_data;
257 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
258 outb(c, CONTROL(p));
259 priv->ctr = c;
260 if (priv->ecr)
261 ECR_WRITE(p, s->u.pc.ecr);
262}
263
264#ifdef CONFIG_PARPORT_1284
265static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
266 size_t length, int flags)
267{
268 size_t got = 0;
269
270 if (flags & PARPORT_W91284PIC) {
271 unsigned char status;
272 size_t left = length;
273
274 /* use knowledge about data lines..:
275 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
276 * pError is 1 if there are 16 bytes in the Warp's FIFO
277 */
278 status = inb(STATUS(port));
279
280 while (!(status & 0x08) && got < length) {
281 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
282 /* can grab 16 bytes from warp fifo */
283 if (!((long)buf & 0x03))
284 insl(EPPDATA(port), buf, 4);
285 else
286 insb(EPPDATA(port), buf, 16);
287 buf += 16;
288 got += 16;
289 left -= 16;
290 } else {
291 /* grab single byte from the warp fifo */
292 *((char *)buf) = inb(EPPDATA(port));
293 buf++;
294 got++;
295 left--;
296 }
297 status = inb(STATUS(port));
298 if (status & 0x01) {
299 /* EPP timeout should never occur... */
300 printk(KERN_DEBUG
301"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
302 clear_epp_timeout(port);
303 }
304 }
305 return got;
306 }
307 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
308 if (!(((long)buf | length) & 0x03))
309 insl(EPPDATA(port), buf, (length >> 2));
310 else
311 insb(EPPDATA(port), buf, length);
312 if (inb(STATUS(port)) & 0x01) {
313 clear_epp_timeout(port);
314 return -EIO;
315 }
316 return length;
317 }
318 for (; got < length; got++) {
319 *((char *)buf) = inb(EPPDATA(port));
320 buf++;
321 if (inb(STATUS(port)) & 0x01) {
322 /* EPP timeout */
323 clear_epp_timeout(port);
324 break;
325 }
326 }
327
328 return got;
329}
330
331static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
332 size_t length, int flags)
333{
334 size_t written = 0;
335
336 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
337 if (!(((long)buf | length) & 0x03))
338 outsl(EPPDATA(port), buf, (length >> 2));
339 else
340 outsb(EPPDATA(port), buf, length);
341 if (inb(STATUS(port)) & 0x01) {
342 clear_epp_timeout(port);
343 return -EIO;
344 }
345 return length;
346 }
347 for (; written < length; written++) {
348 outb(*((char *)buf), EPPDATA(port));
349 buf++;
350 if (inb(STATUS(port)) & 0x01) {
351 clear_epp_timeout(port);
352 break;
353 }
354 }
355
356 return written;
357}
358
359static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
360 size_t length, int flags)
361{
362 size_t got = 0;
363
364 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
365 insb(EPPADDR(port), buf, length);
366 if (inb(STATUS(port)) & 0x01) {
367 clear_epp_timeout(port);
368 return -EIO;
369 }
370 return length;
371 }
372 for (; got < length; got++) {
373 *((char *)buf) = inb(EPPADDR(port));
374 buf++;
375 if (inb(STATUS(port)) & 0x01) {
376 clear_epp_timeout(port);
377 break;
378 }
379 }
380
381 return got;
382}
383
384static size_t parport_pc_epp_write_addr(struct parport *port,
385 const void *buf, size_t length,
386 int flags)
387{
388 size_t written = 0;
389
390 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
391 outsb(EPPADDR(port), buf, length);
392 if (inb(STATUS(port)) & 0x01) {
393 clear_epp_timeout(port);
394 return -EIO;
395 }
396 return length;
397 }
398 for (; written < length; written++) {
399 outb(*((char *)buf), EPPADDR(port));
400 buf++;
401 if (inb(STATUS(port)) & 0x01) {
402 clear_epp_timeout(port);
403 break;
404 }
405 }
406
407 return written;
408}
409
410static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
411 size_t length, int flags)
412{
413 size_t got;
414
415 frob_set_mode(port, ECR_EPP);
416 parport_pc_data_reverse(port);
417 parport_pc_write_control(port, 0x4);
418 got = parport_pc_epp_read_data(port, buf, length, flags);
419 frob_set_mode(port, ECR_PS2);
420
421 return got;
422}
423
424static size_t parport_pc_ecpepp_write_data(struct parport *port,
425 const void *buf, size_t length,
426 int flags)
427{
428 size_t written;
429
430 frob_set_mode(port, ECR_EPP);
431 parport_pc_write_control(port, 0x4);
432 parport_pc_data_forward(port);
433 written = parport_pc_epp_write_data(port, buf, length, flags);
434 frob_set_mode(port, ECR_PS2);
435
436 return written;
437}
438
439static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
440 size_t length, int flags)
441{
442 size_t got;
443
444 frob_set_mode(port, ECR_EPP);
445 parport_pc_data_reverse(port);
446 parport_pc_write_control(port, 0x4);
447 got = parport_pc_epp_read_addr(port, buf, length, flags);
448 frob_set_mode(port, ECR_PS2);
449
450 return got;
451}
452
453static size_t parport_pc_ecpepp_write_addr(struct parport *port,
454 const void *buf, size_t length,
455 int flags)
456{
457 size_t written;
458
459 frob_set_mode(port, ECR_EPP);
460 parport_pc_write_control(port, 0x4);
461 parport_pc_data_forward(port);
462 written = parport_pc_epp_write_addr(port, buf, length, flags);
463 frob_set_mode(port, ECR_PS2);
464
465 return written;
466}
467#endif /* IEEE 1284 support */
468
469#ifdef CONFIG_PARPORT_PC_FIFO
470static size_t parport_pc_fifo_write_block_pio(struct parport *port,
471 const void *buf, size_t length)
472{
473 int ret = 0;
474 const unsigned char *bufp = buf;
475 size_t left = length;
476 unsigned long expire = jiffies + port->physport->cad->timeout;
477 const int fifo = FIFO(port);
478 int poll_for = 8; /* 80 usecs */
479 const struct parport_pc_private *priv = port->physport->private_data;
480 const int fifo_depth = priv->fifo_depth;
481
482 port = port->physport;
483
484 /* We don't want to be interrupted every character. */
485 parport_pc_disable_irq(port);
486 /* set nErrIntrEn and serviceIntr */
487 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
488
489 /* Forward mode. */
490 parport_pc_data_forward(port); /* Must be in PS2 mode */
491
492 while (left) {
493 unsigned char byte;
494 unsigned char ecrval = inb(ECONTROL(port));
495 int i = 0;
496
497 if (need_resched() && time_before(jiffies, expire))
498 /* Can't yield the port. */
499 schedule();
500
501 /* Anyone else waiting for the port? */
502 if (port->waithead) {
503 printk(KERN_DEBUG "Somebody wants the port\n");
504 break;
505 }
506
507 if (ecrval & 0x02) {
508 /* FIFO is full. Wait for interrupt. */
509
510 /* Clear serviceIntr */
511 ECR_WRITE(port, ecrval & ~(1<<2));
512false_alarm:
513 ret = parport_wait_event(port, HZ);
514 if (ret < 0)
515 break;
516 ret = 0;
517 if (!time_before(jiffies, expire)) {
518 /* Timed out. */
519 printk(KERN_DEBUG "FIFO write timed out\n");
520 break;
521 }
522 ecrval = inb(ECONTROL(port));
523 if (!(ecrval & (1<<2))) {
524 if (need_resched() &&
525 time_before(jiffies, expire))
526 schedule();
527
528 goto false_alarm;
529 }
530
531 continue;
532 }
533
534 /* Can't fail now. */
535 expire = jiffies + port->cad->timeout;
536
537poll:
538 if (signal_pending(current))
539 break;
540
541 if (ecrval & 0x01) {
542 /* FIFO is empty. Blast it full. */
543 const int n = left < fifo_depth ? left : fifo_depth;
544 outsb(fifo, bufp, n);
545 bufp += n;
546 left -= n;
547
548 /* Adjust the poll time. */
549 if (i < (poll_for - 2))
550 poll_for--;
551 continue;
552 } else if (i++ < poll_for) {
553 udelay(10);
554 ecrval = inb(ECONTROL(port));
555 goto poll;
556 }
557
558 /* Half-full(call me an optimist) */
559 byte = *bufp++;
560 outb(byte, fifo);
561 left--;
562 }
563 dump_parport_state("leave fifo_write_block_pio", port);
564 return length - left;
565}
566
567#ifdef HAS_DMA
568static size_t parport_pc_fifo_write_block_dma(struct parport *port,
569 const void *buf, size_t length)
570{
571 int ret = 0;
572 unsigned long dmaflag;
573 size_t left = length;
574 const struct parport_pc_private *priv = port->physport->private_data;
575 struct device *dev = port->physport->dev;
576 dma_addr_t dma_addr, dma_handle;
577 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
578 unsigned long start = (unsigned long) buf;
579 unsigned long end = (unsigned long) buf + length - 1;
580
581 dump_parport_state("enter fifo_write_block_dma", port);
582 if (end < MAX_DMA_ADDRESS) {
583 /* If it would cross a 64k boundary, cap it at the end. */
584 if ((start ^ end) & ~0xffffUL)
585 maxlen = 0x10000 - (start & 0xffff);
586
587 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
588 DMA_TO_DEVICE);
589 } else {
590 /* above 16 MB we use a bounce buffer as ISA-DMA
591 is not possible */
592 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
593 dma_addr = priv->dma_handle;
594 dma_handle = 0;
595 }
596
597 port = port->physport;
598
599 /* We don't want to be interrupted every character. */
600 parport_pc_disable_irq(port);
601 /* set nErrIntrEn and serviceIntr */
602 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
603
604 /* Forward mode. */
605 parport_pc_data_forward(port); /* Must be in PS2 mode */
606
607 while (left) {
608 unsigned long expire = jiffies + port->physport->cad->timeout;
609
610 size_t count = left;
611
612 if (count > maxlen)
613 count = maxlen;
614
615 if (!dma_handle) /* bounce buffer ! */
616 memcpy(priv->dma_buf, buf, count);
617
618 dmaflag = claim_dma_lock();
619 disable_dma(port->dma);
620 clear_dma_ff(port->dma);
621 set_dma_mode(port->dma, DMA_MODE_WRITE);
622 set_dma_addr(port->dma, dma_addr);
623 set_dma_count(port->dma, count);
624
625 /* Set DMA mode */
626 frob_econtrol(port, 1<<3, 1<<3);
627
628 /* Clear serviceIntr */
629 frob_econtrol(port, 1<<2, 0);
630
631 enable_dma(port->dma);
632 release_dma_lock(dmaflag);
633
634 /* assume DMA will be successful */
635 left -= count;
636 buf += count;
637 if (dma_handle)
638 dma_addr += count;
639
640 /* Wait for interrupt. */
641false_alarm:
642 ret = parport_wait_event(port, HZ);
643 if (ret < 0)
644 break;
645 ret = 0;
646 if (!time_before(jiffies, expire)) {
647 /* Timed out. */
648 printk(KERN_DEBUG "DMA write timed out\n");
649 break;
650 }
651 /* Is serviceIntr set? */
652 if (!(inb(ECONTROL(port)) & (1<<2))) {
653 cond_resched();
654
655 goto false_alarm;
656 }
657
658 dmaflag = claim_dma_lock();
659 disable_dma(port->dma);
660 clear_dma_ff(port->dma);
661 count = get_dma_residue(port->dma);
662 release_dma_lock(dmaflag);
663
664 cond_resched(); /* Can't yield the port. */
665
666 /* Anyone else waiting for the port? */
667 if (port->waithead) {
668 printk(KERN_DEBUG "Somebody wants the port\n");
669 break;
670 }
671
672 /* update for possible DMA residue ! */
673 buf -= count;
674 left += count;
675 if (dma_handle)
676 dma_addr -= count;
677 }
678
679 /* Maybe got here through break, so adjust for DMA residue! */
680 dmaflag = claim_dma_lock();
681 disable_dma(port->dma);
682 clear_dma_ff(port->dma);
683 left += get_dma_residue(port->dma);
684 release_dma_lock(dmaflag);
685
686 /* Turn off DMA mode */
687 frob_econtrol(port, 1<<3, 0);
688
689 if (dma_handle)
690 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
691
692 dump_parport_state("leave fifo_write_block_dma", port);
693 return length - left;
694}
695#endif
696
697static inline size_t parport_pc_fifo_write_block(struct parport *port,
698 const void *buf, size_t length)
699{
700#ifdef HAS_DMA
701 if (port->dma != PARPORT_DMA_NONE)
702 return parport_pc_fifo_write_block_dma(port, buf, length);
703#endif
704 return parport_pc_fifo_write_block_pio(port, buf, length);
705}
706
707/* Parallel Port FIFO mode (ECP chipsets) */
708static size_t parport_pc_compat_write_block_pio(struct parport *port,
709 const void *buf, size_t length,
710 int flags)
711{
712 size_t written;
713 int r;
714 unsigned long expire;
715 const struct parport_pc_private *priv = port->physport->private_data;
716
717 /* Special case: a timeout of zero means we cannot call schedule().
718 * Also if O_NONBLOCK is set then use the default implementation. */
719 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
720 return parport_ieee1284_write_compat(port, buf,
721 length, flags);
722
723 /* Set up parallel port FIFO mode.*/
724 parport_pc_data_forward(port); /* Must be in PS2 mode */
725 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
726 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
727 if (r)
728 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
729 port->name);
730
731 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
732
733 /* Write the data to the FIFO. */
734 written = parport_pc_fifo_write_block(port, buf, length);
735
736 /* Finish up. */
737 /* For some hardware we don't want to touch the mode until
738 * the FIFO is empty, so allow 4 seconds for each position
739 * in the fifo.
740 */
741 expire = jiffies + (priv->fifo_depth * HZ * 4);
742 do {
743 /* Wait for the FIFO to empty */
744 r = change_mode(port, ECR_PS2);
745 if (r != -EBUSY)
746 break;
747 } while (time_before(jiffies, expire));
748 if (r == -EBUSY) {
749
750 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
751
752 /* Prevent further data transfer. */
753 frob_set_mode(port, ECR_TST);
754
755 /* Adjust for the contents of the FIFO. */
756 for (written -= priv->fifo_depth; ; written++) {
757 if (inb(ECONTROL(port)) & 0x2) {
758 /* Full up. */
759 break;
760 }
761 outb(0, FIFO(port));
762 }
763
764 /* Reset the FIFO and return to PS2 mode. */
765 frob_set_mode(port, ECR_PS2);
766 }
767
768 r = parport_wait_peripheral(port,
769 PARPORT_STATUS_BUSY,
770 PARPORT_STATUS_BUSY);
771 if (r)
772 printk(KERN_DEBUG
773 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
774 port->name, r);
775
776 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
777
778 return written;
779}
780
781/* ECP */
782#ifdef CONFIG_PARPORT_1284
783static size_t parport_pc_ecp_write_block_pio(struct parport *port,
784 const void *buf, size_t length,
785 int flags)
786{
787 size_t written;
788 int r;
789 unsigned long expire;
790 const struct parport_pc_private *priv = port->physport->private_data;
791
792 /* Special case: a timeout of zero means we cannot call schedule().
793 * Also if O_NONBLOCK is set then use the default implementation. */
794 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
795 return parport_ieee1284_ecp_write_data(port, buf,
796 length, flags);
797
798 /* Switch to forward mode if necessary. */
799 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
800 /* Event 47: Set nInit high. */
801 parport_frob_control(port,
802 PARPORT_CONTROL_INIT
803 | PARPORT_CONTROL_AUTOFD,
804 PARPORT_CONTROL_INIT
805 | PARPORT_CONTROL_AUTOFD);
806
807 /* Event 49: PError goes high. */
808 r = parport_wait_peripheral(port,
809 PARPORT_STATUS_PAPEROUT,
810 PARPORT_STATUS_PAPEROUT);
811 if (r) {
812 printk(KERN_DEBUG "%s: PError timeout (%d) "
813 "in ecp_write_block_pio\n", port->name, r);
814 }
815 }
816
817 /* Set up ECP parallel port mode.*/
818 parport_pc_data_forward(port); /* Must be in PS2 mode */
819 parport_pc_frob_control(port,
820 PARPORT_CONTROL_STROBE |
821 PARPORT_CONTROL_AUTOFD,
822 0);
823 r = change_mode(port, ECR_ECP); /* ECP FIFO */
824 if (r)
825 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
826 port->name);
827 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
828
829 /* Write the data to the FIFO. */
830 written = parport_pc_fifo_write_block(port, buf, length);
831
832 /* Finish up. */
833 /* For some hardware we don't want to touch the mode until
834 * the FIFO is empty, so allow 4 seconds for each position
835 * in the fifo.
836 */
837 expire = jiffies + (priv->fifo_depth * (HZ * 4));
838 do {
839 /* Wait for the FIFO to empty */
840 r = change_mode(port, ECR_PS2);
841 if (r != -EBUSY)
842 break;
843 } while (time_before(jiffies, expire));
844 if (r == -EBUSY) {
845
846 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
847
848 /* Prevent further data transfer. */
849 frob_set_mode(port, ECR_TST);
850
851 /* Adjust for the contents of the FIFO. */
852 for (written -= priv->fifo_depth; ; written++) {
853 if (inb(ECONTROL(port)) & 0x2) {
854 /* Full up. */
855 break;
856 }
857 outb(0, FIFO(port));
858 }
859
860 /* Reset the FIFO and return to PS2 mode. */
861 frob_set_mode(port, ECR_PS2);
862
863 /* Host transfer recovery. */
864 parport_pc_data_reverse(port); /* Must be in PS2 mode */
865 udelay(5);
866 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
867 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
868 if (r)
869 printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
870 "in ecp_write_block_pio\n", port->name, r);
871
872 parport_frob_control(port,
873 PARPORT_CONTROL_INIT,
874 PARPORT_CONTROL_INIT);
875 r = parport_wait_peripheral(port,
876 PARPORT_STATUS_PAPEROUT,
877 PARPORT_STATUS_PAPEROUT);
878 if (r)
879 printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
880 "in ecp_write_block_pio\n", port->name, r);
881 }
882
883 r = parport_wait_peripheral(port,
884 PARPORT_STATUS_BUSY,
885 PARPORT_STATUS_BUSY);
886 if (r)
887 printk(KERN_DEBUG
888 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
889 port->name, r);
890
891 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
892
893 return written;
894}
895#endif /* IEEE 1284 support */
896#endif /* Allowed to use FIFO/DMA */
897
898
899/*
900 * ******************************************
901 * INITIALISATION AND MODULE STUFF BELOW HERE
902 * ******************************************
903 */
904
905/* GCC is not inlining extern inline function later overwriten to non-inline,
906 so we use outlined_ variants here. */
907static const struct parport_operations parport_pc_ops = {
908 .write_data = parport_pc_write_data,
909 .read_data = parport_pc_read_data,
910
911 .write_control = parport_pc_write_control,
912 .read_control = parport_pc_read_control,
913 .frob_control = parport_pc_frob_control,
914
915 .read_status = parport_pc_read_status,
916
917 .enable_irq = parport_pc_enable_irq,
918 .disable_irq = parport_pc_disable_irq,
919
920 .data_forward = parport_pc_data_forward,
921 .data_reverse = parport_pc_data_reverse,
922
923 .init_state = parport_pc_init_state,
924 .save_state = parport_pc_save_state,
925 .restore_state = parport_pc_restore_state,
926
927 .epp_write_data = parport_ieee1284_epp_write_data,
928 .epp_read_data = parport_ieee1284_epp_read_data,
929 .epp_write_addr = parport_ieee1284_epp_write_addr,
930 .epp_read_addr = parport_ieee1284_epp_read_addr,
931
932 .ecp_write_data = parport_ieee1284_ecp_write_data,
933 .ecp_read_data = parport_ieee1284_ecp_read_data,
934 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
935
936 .compat_write_data = parport_ieee1284_write_compat,
937 .nibble_read_data = parport_ieee1284_read_nibble,
938 .byte_read_data = parport_ieee1284_read_byte,
939
940 .owner = THIS_MODULE,
941};
942
943#ifdef CONFIG_PARPORT_PC_SUPERIO
944
945static struct superio_struct *find_free_superio(void)
946{
947 int i;
948 for (i = 0; i < NR_SUPERIOS; i++)
949 if (superios[i].io == 0)
950 return &superios[i];
951 return NULL;
952}
953
954
955/* Super-IO chipset detection, Winbond, SMSC */
956static void show_parconfig_smsc37c669(int io, int key)
957{
958 int cr1, cr4, cra, cr23, cr26, cr27;
959 struct superio_struct *s;
960
961 static const char *const modes[] = {
962 "SPP and Bidirectional (PS/2)",
963 "EPP and SPP",
964 "ECP",
965 "ECP and EPP" };
966
967 outb(key, io);
968 outb(key, io);
969 outb(1, io);
970 cr1 = inb(io + 1);
971 outb(4, io);
972 cr4 = inb(io + 1);
973 outb(0x0a, io);
974 cra = inb(io + 1);
975 outb(0x23, io);
976 cr23 = inb(io + 1);
977 outb(0x26, io);
978 cr26 = inb(io + 1);
979 outb(0x27, io);
980 cr27 = inb(io + 1);
981 outb(0xaa, io);
982
983 if (verbose_probing) {
984 printk(KERN_INFO
985 "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
986 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
987 cr1, cr4, cra, cr23, cr26, cr27);
988
989 /* The documentation calls DMA and IRQ-Lines by letters, so
990 the board maker can/will wire them
991 appropriately/randomly... G=reserved H=IDE-irq, */
992 printk(KERN_INFO
993 "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
994 cr23 * 4,
995 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
996 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
997 cra & 0x0f);
998 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
999 (cr23 * 4 >= 0x100) ? "yes" : "no",
1000 (cr1 & 4) ? "yes" : "no");
1001 printk(KERN_INFO
1002 "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1003 (cr1 & 0x08) ? "Standard mode only (SPP)"
1004 : modes[cr4 & 0x03],
1005 (cr4 & 0x40) ? "1.7" : "1.9");
1006 }
1007
1008 /* Heuristics ! BIOS setup for this mainboard device limits
1009 the choices to standard settings, i.e. io-address and IRQ
1010 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1011 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1012 if (cr23 * 4 >= 0x100) { /* if active */
1013 s = find_free_superio();
1014 if (s == NULL)
1015 printk(KERN_INFO "Super-IO: too many chips!\n");
1016 else {
1017 int d;
1018 switch (cr23 * 4) {
1019 case 0x3bc:
1020 s->io = 0x3bc;
1021 s->irq = 7;
1022 break;
1023 case 0x378:
1024 s->io = 0x378;
1025 s->irq = 7;
1026 break;
1027 case 0x278:
1028 s->io = 0x278;
1029 s->irq = 5;
1030 }
1031 d = (cr26 & 0x0f);
1032 if (d == 1 || d == 3)
1033 s->dma = d;
1034 else
1035 s->dma = PARPORT_DMA_NONE;
1036 }
1037 }
1038}
1039
1040
1041static void show_parconfig_winbond(int io, int key)
1042{
1043 int cr30, cr60, cr61, cr70, cr74, crf0;
1044 struct superio_struct *s;
1045 static const char *const modes[] = {
1046 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1047 "EPP-1.9 and SPP",
1048 "ECP",
1049 "ECP and EPP-1.9",
1050 "Standard (SPP)",
1051 "EPP-1.7 and SPP", /* 5 */
1052 "undefined!",
1053 "ECP and EPP-1.7" };
1054 static char *const irqtypes[] = {
1055 "pulsed low, high-Z",
1056 "follows nACK" };
1057
1058 /* The registers are called compatible-PnP because the
1059 register layout is modelled after ISA-PnP, the access
1060 method is just another ... */
1061 outb(key, io);
1062 outb(key, io);
1063 outb(0x07, io); /* Register 7: Select Logical Device */
1064 outb(0x01, io + 1); /* LD1 is Parallel Port */
1065 outb(0x30, io);
1066 cr30 = inb(io + 1);
1067 outb(0x60, io);
1068 cr60 = inb(io + 1);
1069 outb(0x61, io);
1070 cr61 = inb(io + 1);
1071 outb(0x70, io);
1072 cr70 = inb(io + 1);
1073 outb(0x74, io);
1074 cr74 = inb(io + 1);
1075 outb(0xf0, io);
1076 crf0 = inb(io + 1);
1077 outb(0xaa, io);
1078
1079 if (verbose_probing) {
1080 printk(KERN_INFO
1081 "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1082 cr30, cr60, cr61, cr70, cr74, crf0);
1083 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1084 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1085 if ((cr74 & 0x07) > 3)
1086 printk("dma=none\n");
1087 else
1088 printk("dma=%d\n", cr74 & 0x07);
1089 printk(KERN_INFO
1090 "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1091 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1092 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1093 modes[crf0 & 0x07]);
1094 }
1095
1096 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1097 s = find_free_superio();
1098 if (s == NULL)
1099 printk(KERN_INFO "Super-IO: too many chips!\n");
1100 else {
1101 s->io = (cr60 << 8) | cr61;
1102 s->irq = cr70 & 0x0f;
1103 s->dma = (((cr74 & 0x07) > 3) ?
1104 PARPORT_DMA_NONE : (cr74 & 0x07));
1105 }
1106 }
1107}
1108
1109static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1110{
1111 const char *type = "unknown";
1112 int id, progif = 2;
1113
1114 if (devid == devrev)
1115 /* simple heuristics, we happened to read some
1116 non-winbond register */
1117 return;
1118
1119 id = (devid << 8) | devrev;
1120
1121 /* Values are from public data sheets pdf files, I can just
1122 confirm 83977TF is correct :-) */
1123 if (id == 0x9771)
1124 type = "83977F/AF";
1125 else if (id == 0x9773)
1126 type = "83977TF / SMSC 97w33x/97w34x";
1127 else if (id == 0x9774)
1128 type = "83977ATF";
1129 else if ((id & ~0x0f) == 0x5270)
1130 type = "83977CTF / SMSC 97w36x";
1131 else if ((id & ~0x0f) == 0x52f0)
1132 type = "83977EF / SMSC 97w35x";
1133 else if ((id & ~0x0f) == 0x5210)
1134 type = "83627";
1135 else if ((id & ~0x0f) == 0x6010)
1136 type = "83697HF";
1137 else if ((oldid & 0x0f) == 0x0a) {
1138 type = "83877F";
1139 progif = 1;
1140 } else if ((oldid & 0x0f) == 0x0b) {
1141 type = "83877AF";
1142 progif = 1;
1143 } else if ((oldid & 0x0f) == 0x0c) {
1144 type = "83877TF";
1145 progif = 1;
1146 } else if ((oldid & 0x0f) == 0x0d) {
1147 type = "83877ATF";
1148 progif = 1;
1149 } else
1150 progif = 0;
1151
1152 if (verbose_probing)
1153 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1154 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1155 efer, key, devid, devrev, oldid, type);
1156
1157 if (progif == 2)
1158 show_parconfig_winbond(efer, key);
1159}
1160
1161static void decode_smsc(int efer, int key, int devid, int devrev)
1162{
1163 const char *type = "unknown";
1164 void (*func)(int io, int key);
1165 int id;
1166
1167 if (devid == devrev)
1168 /* simple heuristics, we happened to read some
1169 non-smsc register */
1170 return;
1171
1172 func = NULL;
1173 id = (devid << 8) | devrev;
1174
1175 if (id == 0x0302) {
1176 type = "37c669";
1177 func = show_parconfig_smsc37c669;
1178 } else if (id == 0x6582)
1179 type = "37c665IR";
1180 else if (devid == 0x65)
1181 type = "37c665GT";
1182 else if (devid == 0x66)
1183 type = "37c666GT";
1184
1185 if (verbose_probing)
1186 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1187 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1188 efer, key, devid, devrev, type);
1189
1190 if (func)
1191 func(efer, key);
1192}
1193
1194
1195static void winbond_check(int io, int key)
1196{
1197 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1198
1199 if (!request_region(io, 3, __func__))
1200 return;
1201
1202 origval = inb(io); /* Save original value */
1203
1204 /* First probe without key */
1205 outb(0x20, io);
1206 x_devid = inb(io + 1);
1207 outb(0x21, io);
1208 x_devrev = inb(io + 1);
1209 outb(0x09, io);
1210 x_oldid = inb(io + 1);
1211
1212 outb(key, io);
1213 outb(key, io); /* Write Magic Sequence to EFER, extended
1214 function enable register */
1215 outb(0x20, io); /* Write EFIR, extended function index register */
1216 devid = inb(io + 1); /* Read EFDR, extended function data register */
1217 outb(0x21, io);
1218 devrev = inb(io + 1);
1219 outb(0x09, io);
1220 oldid = inb(io + 1);
1221 outb(0xaa, io); /* Magic Seal */
1222
1223 outb(origval, io); /* in case we poked some entirely different hardware */
1224
1225 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1226 goto out; /* protection against false positives */
1227
1228 decode_winbond(io, key, devid, devrev, oldid);
1229out:
1230 release_region(io, 3);
1231}
1232
1233static void winbond_check2(int io, int key)
1234{
1235 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1236
1237 if (!request_region(io, 3, __func__))
1238 return;
1239
1240 origval[0] = inb(io); /* Save original values */
1241 origval[1] = inb(io + 1);
1242 origval[2] = inb(io + 2);
1243
1244 /* First probe without the key */
1245 outb(0x20, io + 2);
1246 x_devid = inb(io + 2);
1247 outb(0x21, io + 1);
1248 x_devrev = inb(io + 2);
1249 outb(0x09, io + 1);
1250 x_oldid = inb(io + 2);
1251
1252 outb(key, io); /* Write Magic Byte to EFER, extended
1253 function enable register */
1254 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1255 devid = inb(io + 2); /* Read EFDR, extended function data register */
1256 outb(0x21, io + 1);
1257 devrev = inb(io + 2);
1258 outb(0x09, io + 1);
1259 oldid = inb(io + 2);
1260 outb(0xaa, io); /* Magic Seal */
1261
1262 outb(origval[0], io); /* in case we poked some entirely different hardware */
1263 outb(origval[1], io + 1);
1264 outb(origval[2], io + 2);
1265
1266 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1267 goto out; /* protection against false positives */
1268
1269 decode_winbond(io, key, devid, devrev, oldid);
1270out:
1271 release_region(io, 3);
1272}
1273
1274static void smsc_check(int io, int key)
1275{
1276 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1277
1278 if (!request_region(io, 3, __func__))
1279 return;
1280
1281 origval = inb(io); /* Save original value */
1282
1283 /* First probe without the key */
1284 outb(0x0d, io);
1285 x_oldid = inb(io + 1);
1286 outb(0x0e, io);
1287 x_oldrev = inb(io + 1);
1288 outb(0x20, io);
1289 x_id = inb(io + 1);
1290 outb(0x21, io);
1291 x_rev = inb(io + 1);
1292
1293 outb(key, io);
1294 outb(key, io); /* Write Magic Sequence to EFER, extended
1295 function enable register */
1296 outb(0x0d, io); /* Write EFIR, extended function index register */
1297 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1298 outb(0x0e, io);
1299 oldrev = inb(io + 1);
1300 outb(0x20, io);
1301 id = inb(io + 1);
1302 outb(0x21, io);
1303 rev = inb(io + 1);
1304 outb(0xaa, io); /* Magic Seal */
1305
1306 outb(origval, io); /* in case we poked some entirely different hardware */
1307
1308 if (x_id == id && x_oldrev == oldrev &&
1309 x_oldid == oldid && x_rev == rev)
1310 goto out; /* protection against false positives */
1311
1312 decode_smsc(io, key, oldid, oldrev);
1313out:
1314 release_region(io, 3);
1315}
1316
1317
1318static void detect_and_report_winbond(void)
1319{
1320 if (verbose_probing)
1321 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1322 winbond_check(0x3f0, 0x87);
1323 winbond_check(0x370, 0x87);
1324 winbond_check(0x2e , 0x87);
1325 winbond_check(0x4e , 0x87);
1326 winbond_check(0x3f0, 0x86);
1327 winbond_check2(0x250, 0x88);
1328 winbond_check2(0x250, 0x89);
1329}
1330
1331static void detect_and_report_smsc(void)
1332{
1333 if (verbose_probing)
1334 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1335 smsc_check(0x3f0, 0x55);
1336 smsc_check(0x370, 0x55);
1337 smsc_check(0x3f0, 0x44);
1338 smsc_check(0x370, 0x44);
1339}
1340
1341static void detect_and_report_it87(void)
1342{
1343 u16 dev;
1344 u8 origval, r;
1345 if (verbose_probing)
1346 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1347 if (!request_muxed_region(0x2e, 2, __func__))
1348 return;
1349 origval = inb(0x2e); /* Save original value */
1350 outb(0x87, 0x2e);
1351 outb(0x01, 0x2e);
1352 outb(0x55, 0x2e);
1353 outb(0x55, 0x2e);
1354 outb(0x20, 0x2e);
1355 dev = inb(0x2f) << 8;
1356 outb(0x21, 0x2e);
1357 dev |= inb(0x2f);
1358 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1359 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1360 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1361 outb(0x07, 0x2E); /* Parallel Port */
1362 outb(0x03, 0x2F);
1363 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1364 r = inb(0x2f);
1365 outb(0xF0, 0x2E);
1366 outb(r | 8, 0x2F);
1367 outb(0x02, 0x2E); /* Lock */
1368 outb(0x02, 0x2F);
1369 } else {
1370 outb(origval, 0x2e); /* Oops, sorry to disturb */
1371 }
1372 release_region(0x2e, 2);
1373}
1374#endif /* CONFIG_PARPORT_PC_SUPERIO */
1375
1376static struct superio_struct *find_superio(struct parport *p)
1377{
1378 int i;
1379 for (i = 0; i < NR_SUPERIOS; i++)
1380 if (superios[i].io != p->base)
1381 return &superios[i];
1382 return NULL;
1383}
1384
1385static int get_superio_dma(struct parport *p)
1386{
1387 struct superio_struct *s = find_superio(p);
1388 if (s)
1389 return s->dma;
1390 return PARPORT_DMA_NONE;
1391}
1392
1393static int get_superio_irq(struct parport *p)
1394{
1395 struct superio_struct *s = find_superio(p);
1396 if (s)
1397 return s->irq;
1398 return PARPORT_IRQ_NONE;
1399}
1400
1401
1402/* --- Mode detection ------------------------------------- */
1403
1404/*
1405 * Checks for port existence, all ports support SPP MODE
1406 * Returns:
1407 * 0 : No parallel port at this address
1408 * PARPORT_MODE_PCSPP : SPP port detected
1409 * (if the user specified an ioport himself,
1410 * this shall always be the case!)
1411 *
1412 */
1413static int parport_SPP_supported(struct parport *pb)
1414{
1415 unsigned char r, w;
1416
1417 /*
1418 * first clear an eventually pending EPP timeout
1419 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1420 * that does not even respond to SPP cycles if an EPP
1421 * timeout is pending
1422 */
1423 clear_epp_timeout(pb);
1424
1425 /* Do a simple read-write test to make sure the port exists. */
1426 w = 0xc;
1427 outb(w, CONTROL(pb));
1428
1429 /* Is there a control register that we can read from? Some
1430 * ports don't allow reads, so read_control just returns a
1431 * software copy. Some ports _do_ allow reads, so bypass the
1432 * software copy here. In addition, some bits aren't
1433 * writable. */
1434 r = inb(CONTROL(pb));
1435 if ((r & 0xf) == w) {
1436 w = 0xe;
1437 outb(w, CONTROL(pb));
1438 r = inb(CONTROL(pb));
1439 outb(0xc, CONTROL(pb));
1440 if ((r & 0xf) == w)
1441 return PARPORT_MODE_PCSPP;
1442 }
1443
1444 if (user_specified)
1445 /* That didn't work, but the user thinks there's a
1446 * port here. */
1447 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1448 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1449
1450 /* Try the data register. The data lines aren't tri-stated at
1451 * this stage, so we expect back what we wrote. */
1452 w = 0xaa;
1453 parport_pc_write_data(pb, w);
1454 r = parport_pc_read_data(pb);
1455 if (r == w) {
1456 w = 0x55;
1457 parport_pc_write_data(pb, w);
1458 r = parport_pc_read_data(pb);
1459 if (r == w)
1460 return PARPORT_MODE_PCSPP;
1461 }
1462
1463 if (user_specified) {
1464 /* Didn't work, but the user is convinced this is the
1465 * place. */
1466 printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1467 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1468 printk(KERN_INFO "parport 0x%lx: You gave this address, "
1469 "but there is probably no parallel port there!\n",
1470 pb->base);
1471 }
1472
1473 /* It's possible that we can't read the control register or
1474 * the data register. In that case just believe the user. */
1475 if (user_specified)
1476 return PARPORT_MODE_PCSPP;
1477
1478 return 0;
1479}
1480
1481/* Check for ECR
1482 *
1483 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1484 * on these cards actually accesses the CTR.
1485 *
1486 * Modern cards don't do this but reading from ECR will return 0xff
1487 * regardless of what is written here if the card does NOT support
1488 * ECP.
1489 *
1490 * We first check to see if ECR is the same as CTR. If not, the low
1491 * two bits of ECR aren't writable, so we check by writing ECR and
1492 * reading it back to see if it's what we expect.
1493 */
1494static int parport_ECR_present(struct parport *pb)
1495{
1496 struct parport_pc_private *priv = pb->private_data;
1497 unsigned char r = 0xc;
1498
1499 outb(r, CONTROL(pb));
1500 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1501 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1502
1503 r = inb(CONTROL(pb));
1504 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1505 goto no_reg; /* Sure that no ECR register exists */
1506 }
1507
1508 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1509 goto no_reg;
1510
1511 ECR_WRITE(pb, 0x34);
1512 if (inb(ECONTROL(pb)) != 0x35)
1513 goto no_reg;
1514
1515 priv->ecr = 1;
1516 outb(0xc, CONTROL(pb));
1517
1518 /* Go to mode 000 */
1519 frob_set_mode(pb, ECR_SPP);
1520
1521 return 1;
1522
1523 no_reg:
1524 outb(0xc, CONTROL(pb));
1525 return 0;
1526}
1527
1528#ifdef CONFIG_PARPORT_1284
1529/* Detect PS/2 support.
1530 *
1531 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1532 * allows us to read data from the data lines. In theory we would get back
1533 * 0xff but any peripheral attached to the port may drag some or all of the
1534 * lines down to zero. So if we get back anything that isn't the contents
1535 * of the data register we deem PS/2 support to be present.
1536 *
1537 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1538 * drivers, but an external peripheral with sufficiently beefy drivers of
1539 * its own can overpower them and assert its own levels onto the bus, from
1540 * where they can then be read back as normal. Ports with this property
1541 * and the right type of device attached are likely to fail the SPP test,
1542 * (as they will appear to have stuck bits) and so the fact that they might
1543 * be misdetected here is rather academic.
1544 */
1545
1546static int parport_PS2_supported(struct parport *pb)
1547{
1548 int ok = 0;
1549
1550 clear_epp_timeout(pb);
1551
1552 /* try to tri-state the buffer */
1553 parport_pc_data_reverse(pb);
1554
1555 parport_pc_write_data(pb, 0x55);
1556 if (parport_pc_read_data(pb) != 0x55)
1557 ok++;
1558
1559 parport_pc_write_data(pb, 0xaa);
1560 if (parport_pc_read_data(pb) != 0xaa)
1561 ok++;
1562
1563 /* cancel input mode */
1564 parport_pc_data_forward(pb);
1565
1566 if (ok) {
1567 pb->modes |= PARPORT_MODE_TRISTATE;
1568 } else {
1569 struct parport_pc_private *priv = pb->private_data;
1570 priv->ctr_writable &= ~0x20;
1571 }
1572
1573 return ok;
1574}
1575
1576#ifdef CONFIG_PARPORT_PC_FIFO
1577static int parport_ECP_supported(struct parport *pb)
1578{
1579 int i;
1580 int config, configb;
1581 int pword;
1582 struct parport_pc_private *priv = pb->private_data;
1583 /* Translate ECP intrLine to ISA irq value */
1584 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1585
1586 /* If there is no ECR, we have no hope of supporting ECP. */
1587 if (!priv->ecr)
1588 return 0;
1589
1590 /* Find out FIFO depth */
1591 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1592 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1593 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1594 outb(0xaa, FIFO(pb));
1595
1596 /*
1597 * Using LGS chipset it uses ECR register, but
1598 * it doesn't support ECP or FIFO MODE
1599 */
1600 if (i == 1024) {
1601 ECR_WRITE(pb, ECR_SPP << 5);
1602 return 0;
1603 }
1604
1605 priv->fifo_depth = i;
1606 if (verbose_probing)
1607 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1608
1609 /* Find out writeIntrThreshold */
1610 frob_econtrol(pb, 1<<2, 1<<2);
1611 frob_econtrol(pb, 1<<2, 0);
1612 for (i = 1; i <= priv->fifo_depth; i++) {
1613 inb(FIFO(pb));
1614 udelay(50);
1615 if (inb(ECONTROL(pb)) & (1<<2))
1616 break;
1617 }
1618
1619 if (i <= priv->fifo_depth) {
1620 if (verbose_probing)
1621 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1622 pb->base, i);
1623 } else
1624 /* Number of bytes we know we can write if we get an
1625 interrupt. */
1626 i = 0;
1627
1628 priv->writeIntrThreshold = i;
1629
1630 /* Find out readIntrThreshold */
1631 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1632 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1633 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1634 frob_econtrol(pb, 1<<2, 1<<2);
1635 frob_econtrol(pb, 1<<2, 0);
1636 for (i = 1; i <= priv->fifo_depth; i++) {
1637 outb(0xaa, FIFO(pb));
1638 if (inb(ECONTROL(pb)) & (1<<2))
1639 break;
1640 }
1641
1642 if (i <= priv->fifo_depth) {
1643 if (verbose_probing)
1644 printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1645 pb->base, i);
1646 } else
1647 /* Number of bytes we can read if we get an interrupt. */
1648 i = 0;
1649
1650 priv->readIntrThreshold = i;
1651
1652 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1653 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1654 config = inb(CONFIGA(pb));
1655 pword = (config >> 4) & 0x7;
1656 switch (pword) {
1657 case 0:
1658 pword = 2;
1659 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1660 pb->base);
1661 break;
1662 case 2:
1663 pword = 4;
1664 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1665 pb->base);
1666 break;
1667 default:
1668 printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1669 pb->base);
1670 /* Assume 1 */
1671 case 1:
1672 pword = 1;
1673 }
1674 priv->pword = pword;
1675
1676 if (verbose_probing) {
1677 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1678 pb->base, 8 * pword);
1679
1680 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1681 config & 0x80 ? "Level" : "Pulses");
1682
1683 configb = inb(CONFIGB(pb));
1684 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1685 pb->base, config, configb);
1686 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1687 if ((configb >> 3) & 0x07)
1688 printk("%d", intrline[(configb >> 3) & 0x07]);
1689 else
1690 printk("<none or set by other means>");
1691 printk(" dma=");
1692 if ((configb & 0x03) == 0x00)
1693 printk("<none or set by other means>\n");
1694 else
1695 printk("%d\n", configb & 0x07);
1696 }
1697
1698 /* Go back to mode 000 */
1699 frob_set_mode(pb, ECR_SPP);
1700
1701 return 1;
1702}
1703#endif
1704
1705#ifdef CONFIG_X86_32
1706static int intel_bug_present_check_epp(struct parport *pb)
1707{
1708 const struct parport_pc_private *priv = pb->private_data;
1709 int bug_present = 0;
1710
1711 if (priv->ecr) {
1712 /* store value of ECR */
1713 unsigned char ecr = inb(ECONTROL(pb));
1714 unsigned char i;
1715 for (i = 0x00; i < 0x80; i += 0x20) {
1716 ECR_WRITE(pb, i);
1717 if (clear_epp_timeout(pb)) {
1718 /* Phony EPP in ECP. */
1719 bug_present = 1;
1720 break;
1721 }
1722 }
1723 /* return ECR into the inital state */
1724 ECR_WRITE(pb, ecr);
1725 }
1726
1727 return bug_present;
1728}
1729static int intel_bug_present(struct parport *pb)
1730{
1731/* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */
1732 if (pb->dev != NULL) {
1733 return 0;
1734 }
1735
1736 return intel_bug_present_check_epp(pb);
1737}
1738#else
1739static int intel_bug_present(struct parport *pb)
1740{
1741 return 0;
1742}
1743#endif /* CONFIG_X86_32 */
1744
1745static int parport_ECPPS2_supported(struct parport *pb)
1746{
1747 const struct parport_pc_private *priv = pb->private_data;
1748 int result;
1749 unsigned char oecr;
1750
1751 if (!priv->ecr)
1752 return 0;
1753
1754 oecr = inb(ECONTROL(pb));
1755 ECR_WRITE(pb, ECR_PS2 << 5);
1756 result = parport_PS2_supported(pb);
1757 ECR_WRITE(pb, oecr);
1758 return result;
1759}
1760
1761/* EPP mode detection */
1762
1763static int parport_EPP_supported(struct parport *pb)
1764{
1765 /*
1766 * Theory:
1767 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1768 * when EPP is possible and is set high when an EPP timeout
1769 * occurs (EPP uses the HALT line to stop the CPU while it does
1770 * the byte transfer, an EPP timeout occurs if the attached
1771 * device fails to respond after 10 micro seconds).
1772 *
1773 * This bit is cleared by either reading it (National Semi)
1774 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1775 * This bit is always high in non EPP modes.
1776 */
1777
1778 /* If EPP timeout bit clear then EPP available */
1779 if (!clear_epp_timeout(pb))
1780 return 0; /* No way to clear timeout */
1781
1782 /* Check for Intel bug. */
1783 if (intel_bug_present(pb))
1784 return 0;
1785
1786 pb->modes |= PARPORT_MODE_EPP;
1787
1788 /* Set up access functions to use EPP hardware. */
1789 pb->ops->epp_read_data = parport_pc_epp_read_data;
1790 pb->ops->epp_write_data = parport_pc_epp_write_data;
1791 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1792 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1793
1794 return 1;
1795}
1796
1797static int parport_ECPEPP_supported(struct parport *pb)
1798{
1799 struct parport_pc_private *priv = pb->private_data;
1800 int result;
1801 unsigned char oecr;
1802
1803 if (!priv->ecr)
1804 return 0;
1805
1806 oecr = inb(ECONTROL(pb));
1807 /* Search for SMC style EPP+ECP mode */
1808 ECR_WRITE(pb, 0x80);
1809 outb(0x04, CONTROL(pb));
1810 result = parport_EPP_supported(pb);
1811
1812 ECR_WRITE(pb, oecr);
1813
1814 if (result) {
1815 /* Set up access functions to use ECP+EPP hardware. */
1816 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1817 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1818 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1819 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1820 }
1821
1822 return result;
1823}
1824
1825#else /* No IEEE 1284 support */
1826
1827/* Don't bother probing for modes we know we won't use. */
1828static int parport_PS2_supported(struct parport *pb) { return 0; }
1829#ifdef CONFIG_PARPORT_PC_FIFO
1830static int parport_ECP_supported(struct parport *pb)
1831{
1832 return 0;
1833}
1834#endif
1835static int parport_EPP_supported(struct parport *pb)
1836{
1837 return 0;
1838}
1839
1840static int parport_ECPEPP_supported(struct parport *pb)
1841{
1842 return 0;
1843}
1844
1845static int parport_ECPPS2_supported(struct parport *pb)
1846{
1847 return 0;
1848}
1849
1850#endif /* No IEEE 1284 support */
1851
1852/* --- IRQ detection -------------------------------------- */
1853
1854/* Only if supports ECP mode */
1855static int programmable_irq_support(struct parport *pb)
1856{
1857 int irq, intrLine;
1858 unsigned char oecr = inb(ECONTROL(pb));
1859 static const int lookup[8] = {
1860 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1861 };
1862
1863 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1864
1865 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1866 irq = lookup[intrLine];
1867
1868 ECR_WRITE(pb, oecr);
1869 return irq;
1870}
1871
1872static int irq_probe_ECP(struct parport *pb)
1873{
1874 int i;
1875 unsigned long irqs;
1876
1877 irqs = probe_irq_on();
1878
1879 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1880 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1881 ECR_WRITE(pb, ECR_TST << 5);
1882
1883 /* If Full FIFO sure that writeIntrThreshold is generated */
1884 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1885 outb(0xaa, FIFO(pb));
1886
1887 pb->irq = probe_irq_off(irqs);
1888 ECR_WRITE(pb, ECR_SPP << 5);
1889
1890 if (pb->irq <= 0)
1891 pb->irq = PARPORT_IRQ_NONE;
1892
1893 return pb->irq;
1894}
1895
1896/*
1897 * This detection seems that only works in National Semiconductors
1898 * This doesn't work in SMC, LGS, and Winbond
1899 */
1900static int irq_probe_EPP(struct parport *pb)
1901{
1902#ifndef ADVANCED_DETECT
1903 return PARPORT_IRQ_NONE;
1904#else
1905 int irqs;
1906 unsigned char oecr;
1907
1908 if (pb->modes & PARPORT_MODE_PCECR)
1909 oecr = inb(ECONTROL(pb));
1910
1911 irqs = probe_irq_on();
1912
1913 if (pb->modes & PARPORT_MODE_PCECR)
1914 frob_econtrol(pb, 0x10, 0x10);
1915
1916 clear_epp_timeout(pb);
1917 parport_pc_frob_control(pb, 0x20, 0x20);
1918 parport_pc_frob_control(pb, 0x10, 0x10);
1919 clear_epp_timeout(pb);
1920
1921 /* Device isn't expecting an EPP read
1922 * and generates an IRQ.
1923 */
1924 parport_pc_read_epp(pb);
1925 udelay(20);
1926
1927 pb->irq = probe_irq_off(irqs);
1928 if (pb->modes & PARPORT_MODE_PCECR)
1929 ECR_WRITE(pb, oecr);
1930 parport_pc_write_control(pb, 0xc);
1931
1932 if (pb->irq <= 0)
1933 pb->irq = PARPORT_IRQ_NONE;
1934
1935 return pb->irq;
1936#endif /* Advanced detection */
1937}
1938
1939static int irq_probe_SPP(struct parport *pb)
1940{
1941 /* Don't even try to do this. */
1942 return PARPORT_IRQ_NONE;
1943}
1944
1945/* We will attempt to share interrupt requests since other devices
1946 * such as sound cards and network cards seem to like using the
1947 * printer IRQs.
1948 *
1949 * When ECP is available we can autoprobe for IRQs.
1950 * NOTE: If we can autoprobe it, we can register the IRQ.
1951 */
1952static int parport_irq_probe(struct parport *pb)
1953{
1954 struct parport_pc_private *priv = pb->private_data;
1955
1956 if (priv->ecr) {
1957 pb->irq = programmable_irq_support(pb);
1958
1959 if (pb->irq == PARPORT_IRQ_NONE)
1960 pb->irq = irq_probe_ECP(pb);
1961 }
1962
1963 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1964 (pb->modes & PARPORT_MODE_EPP))
1965 pb->irq = irq_probe_EPP(pb);
1966
1967 clear_epp_timeout(pb);
1968
1969 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1970 pb->irq = irq_probe_EPP(pb);
1971
1972 clear_epp_timeout(pb);
1973
1974 if (pb->irq == PARPORT_IRQ_NONE)
1975 pb->irq = irq_probe_SPP(pb);
1976
1977 if (pb->irq == PARPORT_IRQ_NONE)
1978 pb->irq = get_superio_irq(pb);
1979
1980 return pb->irq;
1981}
1982
1983/* --- DMA detection -------------------------------------- */
1984
1985/* Only if chipset conforms to ECP ISA Interface Standard */
1986static int programmable_dma_support(struct parport *p)
1987{
1988 unsigned char oecr = inb(ECONTROL(p));
1989 int dma;
1990
1991 frob_set_mode(p, ECR_CNF);
1992
1993 dma = inb(CONFIGB(p)) & 0x07;
1994 /* 000: Indicates jumpered 8-bit DMA if read-only.
1995 100: Indicates jumpered 16-bit DMA if read-only. */
1996 if ((dma & 0x03) == 0)
1997 dma = PARPORT_DMA_NONE;
1998
1999 ECR_WRITE(p, oecr);
2000 return dma;
2001}
2002
2003static int parport_dma_probe(struct parport *p)
2004{
2005 const struct parport_pc_private *priv = p->private_data;
2006 if (priv->ecr) /* ask ECP chipset first */
2007 p->dma = programmable_dma_support(p);
2008 if (p->dma == PARPORT_DMA_NONE) {
2009 /* ask known Super-IO chips proper, although these
2010 claim ECP compatible, some don't report their DMA
2011 conforming to ECP standards */
2012 p->dma = get_superio_dma(p);
2013 }
2014
2015 return p->dma;
2016}
2017
2018/* --- Initialisation code -------------------------------- */
2019
2020static LIST_HEAD(ports_list);
2021static DEFINE_SPINLOCK(ports_lock);
2022
2023struct parport *parport_pc_probe_port(unsigned long int base,
2024 unsigned long int base_hi,
2025 int irq, int dma,
2026 struct device *dev,
2027 int irqflags)
2028{
2029 struct parport_pc_private *priv;
2030 struct parport_operations *ops;
2031 struct parport *p;
2032 int probedirq = PARPORT_IRQ_NONE;
2033 struct resource *base_res;
2034 struct resource *ECR_res = NULL;
2035 struct resource *EPP_res = NULL;
2036 struct platform_device *pdev = NULL;
2037 int ret;
2038
2039 if (!dev) {
2040 /* We need a physical device to attach to, but none was
2041 * provided. Create our own. */
2042 pdev = platform_device_register_simple("parport_pc",
2043 base, NULL, 0);
2044 if (IS_ERR(pdev))
2045 return NULL;
2046 dev = &pdev->dev;
2047
2048 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24));
2049 if (ret) {
2050 dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n");
2051 dma = PARPORT_DMA_NONE;
2052 }
2053 }
2054
2055 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2056 if (!ops)
2057 goto out1;
2058
2059 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2060 if (!priv)
2061 goto out2;
2062
2063 /* a misnomer, actually - it's allocate and reserve parport number */
2064 p = parport_register_port(base, irq, dma, ops);
2065 if (!p)
2066 goto out3;
2067
2068 base_res = request_region(base, 3, p->name);
2069 if (!base_res)
2070 goto out4;
2071
2072 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2073 priv->ctr = 0xc;
2074 priv->ctr_writable = ~0x10;
2075 priv->ecr = 0;
2076 priv->fifo_depth = 0;
2077 priv->dma_buf = NULL;
2078 priv->dma_handle = 0;
2079 INIT_LIST_HEAD(&priv->list);
2080 priv->port = p;
2081
2082 p->dev = dev;
2083 p->base_hi = base_hi;
2084 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2085 p->private_data = priv;
2086
2087 if (base_hi) {
2088 ECR_res = request_region(base_hi, 3, p->name);
2089 if (ECR_res)
2090 parport_ECR_present(p);
2091 }
2092
2093 if (base != 0x3bc) {
2094 EPP_res = request_region(base+0x3, 5, p->name);
2095 if (EPP_res)
2096 if (!parport_EPP_supported(p))
2097 parport_ECPEPP_supported(p);
2098 }
2099 if (!parport_SPP_supported(p))
2100 /* No port. */
2101 goto out5;
2102 if (priv->ecr)
2103 parport_ECPPS2_supported(p);
2104 else
2105 parport_PS2_supported(p);
2106
2107 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2108
2109 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2110 if (p->base_hi && priv->ecr)
2111 printk(KERN_CONT " (0x%lx)", p->base_hi);
2112 if (p->irq == PARPORT_IRQ_AUTO) {
2113 p->irq = PARPORT_IRQ_NONE;
2114 parport_irq_probe(p);
2115 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2116 p->irq = PARPORT_IRQ_NONE;
2117 parport_irq_probe(p);
2118 probedirq = p->irq;
2119 p->irq = PARPORT_IRQ_NONE;
2120 }
2121 if (p->irq != PARPORT_IRQ_NONE) {
2122 printk(KERN_CONT ", irq %d", p->irq);
2123 priv->ctr_writable |= 0x10;
2124
2125 if (p->dma == PARPORT_DMA_AUTO) {
2126 p->dma = PARPORT_DMA_NONE;
2127 parport_dma_probe(p);
2128 }
2129 }
2130 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2131 is mandatory (see above) */
2132 p->dma = PARPORT_DMA_NONE;
2133
2134#ifdef CONFIG_PARPORT_PC_FIFO
2135 if (parport_ECP_supported(p) &&
2136 p->dma != PARPORT_DMA_NOFIFO &&
2137 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2138 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2139 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2140#ifdef CONFIG_PARPORT_1284
2141 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2142 /* currently broken, but working on it.. (FB) */
2143 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2144#endif /* IEEE 1284 support */
2145 if (p->dma != PARPORT_DMA_NONE) {
2146 printk(KERN_CONT ", dma %d", p->dma);
2147 p->modes |= PARPORT_MODE_DMA;
2148 } else
2149 printk(KERN_CONT ", using FIFO");
2150 } else
2151 /* We can't use the DMA channel after all. */
2152 p->dma = PARPORT_DMA_NONE;
2153#endif /* Allowed to use FIFO/DMA */
2154
2155 printk(KERN_CONT " [");
2156
2157#define printmode(x) \
2158 {\
2159 if (p->modes & PARPORT_MODE_##x) {\
2160 printk(KERN_CONT "%s%s", f ? "," : "", #x);\
2161 f++;\
2162 } \
2163 }
2164
2165 {
2166 int f = 0;
2167 printmode(PCSPP);
2168 printmode(TRISTATE);
2169 printmode(COMPAT)
2170 printmode(EPP);
2171 printmode(ECP);
2172 printmode(DMA);
2173 }
2174#undef printmode
2175#ifndef CONFIG_PARPORT_1284
2176 printk(KERN_CONT "(,...)");
2177#endif /* CONFIG_PARPORT_1284 */
2178 printk(KERN_CONT "]\n");
2179 if (probedirq != PARPORT_IRQ_NONE)
2180 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2181
2182 /* If No ECP release the ports grabbed above. */
2183 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2184 release_region(base_hi, 3);
2185 ECR_res = NULL;
2186 }
2187 /* Likewise for EEP ports */
2188 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2189 release_region(base+3, 5);
2190 EPP_res = NULL;
2191 }
2192 if (p->irq != PARPORT_IRQ_NONE) {
2193 if (request_irq(p->irq, parport_irq_handler,
2194 irqflags, p->name, p)) {
2195 printk(KERN_WARNING "%s: irq %d in use, "
2196 "resorting to polled operation\n",
2197 p->name, p->irq);
2198 p->irq = PARPORT_IRQ_NONE;
2199 p->dma = PARPORT_DMA_NONE;
2200 }
2201
2202#ifdef CONFIG_PARPORT_PC_FIFO
2203#ifdef HAS_DMA
2204 if (p->dma != PARPORT_DMA_NONE) {
2205 if (request_dma(p->dma, p->name)) {
2206 printk(KERN_WARNING "%s: dma %d in use, "
2207 "resorting to PIO operation\n",
2208 p->name, p->dma);
2209 p->dma = PARPORT_DMA_NONE;
2210 } else {
2211 priv->dma_buf =
2212 dma_alloc_coherent(dev,
2213 PAGE_SIZE,
2214 &priv->dma_handle,
2215 GFP_KERNEL);
2216 if (!priv->dma_buf) {
2217 printk(KERN_WARNING "%s: "
2218 "cannot get buffer for DMA, "
2219 "resorting to PIO operation\n",
2220 p->name);
2221 free_dma(p->dma);
2222 p->dma = PARPORT_DMA_NONE;
2223 }
2224 }
2225 }
2226#endif
2227#endif
2228 }
2229
2230 /* Done probing. Now put the port into a sensible start-up state. */
2231 if (priv->ecr)
2232 /*
2233 * Put the ECP detected port in PS2 mode.
2234 * Do this also for ports that have ECR but don't do ECP.
2235 */
2236 ECR_WRITE(p, 0x34);
2237
2238 parport_pc_write_data(p, 0);
2239 parport_pc_data_forward(p);
2240
2241 /* Now that we've told the sharing engine about the port, and
2242 found out its characteristics, let the high-level drivers
2243 know about it. */
2244 spin_lock(&ports_lock);
2245 list_add(&priv->list, &ports_list);
2246 spin_unlock(&ports_lock);
2247 parport_announce_port(p);
2248
2249 return p;
2250
2251out5:
2252 if (ECR_res)
2253 release_region(base_hi, 3);
2254 if (EPP_res)
2255 release_region(base+0x3, 5);
2256 release_region(base, 3);
2257out4:
2258 parport_del_port(p);
2259out3:
2260 kfree(priv);
2261out2:
2262 kfree(ops);
2263out1:
2264 if (pdev)
2265 platform_device_unregister(pdev);
2266 return NULL;
2267}
2268EXPORT_SYMBOL(parport_pc_probe_port);
2269
2270void parport_pc_unregister_port(struct parport *p)
2271{
2272 struct parport_pc_private *priv = p->private_data;
2273 struct parport_operations *ops = p->ops;
2274
2275 parport_remove_port(p);
2276 spin_lock(&ports_lock);
2277 list_del_init(&priv->list);
2278 spin_unlock(&ports_lock);
2279#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2280 if (p->dma != PARPORT_DMA_NONE)
2281 free_dma(p->dma);
2282#endif
2283 if (p->irq != PARPORT_IRQ_NONE)
2284 free_irq(p->irq, p);
2285 release_region(p->base, 3);
2286 if (p->size > 3)
2287 release_region(p->base + 3, p->size - 3);
2288 if (p->modes & PARPORT_MODE_ECP)
2289 release_region(p->base_hi, 3);
2290#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2291 if (priv->dma_buf)
2292 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2293 priv->dma_buf,
2294 priv->dma_handle);
2295#endif
2296 kfree(p->private_data);
2297 parport_del_port(p);
2298 kfree(ops); /* hope no-one cached it */
2299}
2300EXPORT_SYMBOL(parport_pc_unregister_port);
2301
2302#ifdef CONFIG_PCI
2303
2304/* ITE support maintained by Rich Liu <richliu@poorman.org> */
2305static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
2306 const struct parport_pc_via_data *via)
2307{
2308 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2309 u32 ite8872set;
2310 u32 ite8872_lpt, ite8872_lpthi;
2311 u8 ite8872_irq, type;
2312 int irq;
2313 int i;
2314
2315 DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2316
2317 /* make sure which one chip */
2318 for (i = 0; i < 5; i++) {
2319 if (request_region(inta_addr[i], 32, "it887x")) {
2320 int test;
2321 pci_write_config_dword(pdev, 0x60,
2322 0xe5000000 | inta_addr[i]);
2323 pci_write_config_dword(pdev, 0x78,
2324 0x00000000 | inta_addr[i]);
2325 test = inb(inta_addr[i]);
2326 if (test != 0xff)
2327 break;
2328 release_region(inta_addr[i], 32);
2329 }
2330 }
2331 if (i >= 5) {
2332 printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2333 return 0;
2334 }
2335
2336 type = inb(inta_addr[i] + 0x18);
2337 type &= 0x0f;
2338
2339 switch (type) {
2340 case 0x2:
2341 printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2342 ite8872set = 0x64200000;
2343 break;
2344 case 0xa:
2345 printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2346 ite8872set = 0x64200000;
2347 break;
2348 case 0xe:
2349 printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2350 ite8872set = 0x64e00000;
2351 break;
2352 case 0x6:
2353 printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2354 release_region(inta_addr[i], 32);
2355 return 0;
2356 case 0x8:
2357 printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n");
2358 release_region(inta_addr[i], 32);
2359 return 0;
2360 default:
2361 printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2362 printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2363 "output to Rich.Liu@ite.com.tw\n");
2364 release_region(inta_addr[i], 32);
2365 return 0;
2366 }
2367
2368 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2369 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2370 ite8872_lpt &= 0x0000ff00;
2371 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2372 ite8872_lpthi &= 0x0000ff00;
2373 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2374 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2375 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2376 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2377 /* SET Parallel IRQ */
2378 pci_write_config_dword(pdev, 0x9c,
2379 ite8872set | (ite8872_irq * 0x11111));
2380
2381 DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2382 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2383 ite8872_lpt);
2384 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2385 ite8872_lpthi);
2386
2387 /* Let the user (or defaults) steer us away from interrupts */
2388 irq = ite8872_irq;
2389 if (autoirq != PARPORT_IRQ_AUTO)
2390 irq = PARPORT_IRQ_NONE;
2391
2392 /*
2393 * Release the resource so that parport_pc_probe_port can get it.
2394 */
2395 release_region(inta_addr[i], 32);
2396 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2397 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2398 printk(KERN_INFO
2399 "parport_pc: ITE 8872 parallel port: io=0x%X",
2400 ite8872_lpt);
2401 if (irq != PARPORT_IRQ_NONE)
2402 printk(", irq=%d", irq);
2403 printk("\n");
2404 return 1;
2405 }
2406
2407 return 0;
2408}
2409
2410/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2411 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2412static int parport_init_mode;
2413
2414/* Data for two known VIA chips */
2415static struct parport_pc_via_data via_686a_data = {
2416 0x51,
2417 0x50,
2418 0x85,
2419 0x02,
2420 0xE2,
2421 0xF0,
2422 0xE6
2423};
2424static struct parport_pc_via_data via_8231_data = {
2425 0x45,
2426 0x44,
2427 0x50,
2428 0x04,
2429 0xF2,
2430 0xFA,
2431 0xF6
2432};
2433
2434static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
2435 const struct parport_pc_via_data *via)
2436{
2437 u8 tmp, tmp2, siofunc;
2438 u8 ppcontrol = 0;
2439 int dma, irq;
2440 unsigned port1, port2;
2441 unsigned have_epp = 0;
2442
2443 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2444
2445 switch (parport_init_mode) {
2446 case 1:
2447 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2448 siofunc = VIA_FUNCTION_PARPORT_SPP;
2449 break;
2450 case 2:
2451 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2452 siofunc = VIA_FUNCTION_PARPORT_SPP;
2453 ppcontrol = VIA_PARPORT_BIDIR;
2454 break;
2455 case 3:
2456 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2457 siofunc = VIA_FUNCTION_PARPORT_EPP;
2458 ppcontrol = VIA_PARPORT_BIDIR;
2459 have_epp = 1;
2460 break;
2461 case 4:
2462 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2463 siofunc = VIA_FUNCTION_PARPORT_ECP;
2464 ppcontrol = VIA_PARPORT_BIDIR;
2465 break;
2466 case 5:
2467 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2468 siofunc = VIA_FUNCTION_PARPORT_ECP;
2469 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2470 have_epp = 1;
2471 break;
2472 default:
2473 printk(KERN_DEBUG
2474 "parport_pc: probing current configuration\n");
2475 siofunc = VIA_FUNCTION_PROBE;
2476 break;
2477 }
2478 /*
2479 * unlock super i/o configuration
2480 */
2481 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2482 tmp |= via->via_pci_superio_config_data;
2483 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2484
2485 /* Bits 1-0: Parallel Port Mode / Enable */
2486 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2487 tmp = inb(VIA_CONFIG_DATA);
2488 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2489 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2490 tmp2 = inb(VIA_CONFIG_DATA);
2491 if (siofunc == VIA_FUNCTION_PROBE) {
2492 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2493 ppcontrol = tmp2;
2494 } else {
2495 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2496 tmp |= siofunc;
2497 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2498 outb(tmp, VIA_CONFIG_DATA);
2499 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2500 tmp2 |= ppcontrol;
2501 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2502 outb(tmp2, VIA_CONFIG_DATA);
2503 }
2504
2505 /* Parallel Port I/O Base Address, bits 9-2 */
2506 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2507 port1 = inb(VIA_CONFIG_DATA) << 2;
2508
2509 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2510 port1);
2511 if (port1 == 0x3BC && have_epp) {
2512 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2513 outb((0x378 >> 2), VIA_CONFIG_DATA);
2514 printk(KERN_DEBUG
2515 "parport_pc: Parallel port base changed to 0x378\n");
2516 port1 = 0x378;
2517 }
2518
2519 /*
2520 * lock super i/o configuration
2521 */
2522 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2523 tmp &= ~via->via_pci_superio_config_data;
2524 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2525
2526 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2527 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2528 return 0;
2529 }
2530
2531 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2532 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2533 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2534
2535 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2536 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2537 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2538 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2539 } else
2540 /* if ECP not enabled, DMA is not enabled, assumed
2541 bogus 'dma' value */
2542 dma = PARPORT_DMA_NONE;
2543
2544 /* Let the user (or defaults) steer us away from interrupts and DMA */
2545 if (autoirq == PARPORT_IRQ_NONE) {
2546 irq = PARPORT_IRQ_NONE;
2547 dma = PARPORT_DMA_NONE;
2548 }
2549 if (autodma == PARPORT_DMA_NONE)
2550 dma = PARPORT_DMA_NONE;
2551
2552 switch (port1) {
2553 case 0x3bc:
2554 port2 = 0x7bc; break;
2555 case 0x378:
2556 port2 = 0x778; break;
2557 case 0x278:
2558 port2 = 0x678; break;
2559 default:
2560 printk(KERN_INFO
2561 "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2562 port1);
2563 return 0;
2564 }
2565
2566 /* filter bogus IRQs */
2567 switch (irq) {
2568 case 0:
2569 case 2:
2570 case 8:
2571 case 13:
2572 irq = PARPORT_IRQ_NONE;
2573 break;
2574
2575 default: /* do nothing */
2576 break;
2577 }
2578
2579 /* finally, do the probe with values obtained */
2580 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2581 printk(KERN_INFO
2582 "parport_pc: VIA parallel port: io=0x%X", port1);
2583 if (irq != PARPORT_IRQ_NONE)
2584 printk(", irq=%d", irq);
2585 if (dma != PARPORT_DMA_NONE)
2586 printk(", dma=%d", dma);
2587 printk("\n");
2588 return 1;
2589 }
2590
2591 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2592 port1, irq, dma);
2593 return 0;
2594}
2595
2596
2597enum parport_pc_sio_types {
2598 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2599 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2600 sio_ite_8872,
2601 last_sio
2602};
2603
2604/* each element directly indexed from enum list, above */
2605static struct parport_pc_superio {
2606 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2607 const struct parport_pc_via_data *via);
2608 const struct parport_pc_via_data *via;
2609} parport_pc_superio_info[] = {
2610 { sio_via_probe, &via_686a_data, },
2611 { sio_via_probe, &via_8231_data, },
2612 { sio_ite_8872_probe, NULL, },
2613};
2614
2615enum parport_pc_pci_cards {
2616 siig_1p_10x = last_sio,
2617 siig_2p_10x,
2618 siig_1p_20x,
2619 siig_2p_20x,
2620 lava_parallel,
2621 lava_parallel_dual_a,
2622 lava_parallel_dual_b,
2623 boca_ioppar,
2624 plx_9050,
2625 timedia_4006a,
2626 timedia_4014,
2627 timedia_4008a,
2628 timedia_4018,
2629 timedia_9018a,
2630 syba_2p_epp,
2631 syba_1p_ecp,
2632 titan_010l,
2633 avlab_1p,
2634 avlab_2p,
2635 oxsemi_952,
2636 oxsemi_954,
2637 oxsemi_840,
2638 oxsemi_pcie_pport,
2639 aks_0100,
2640 mobility_pp,
2641 netmos_9705,
2642 netmos_9715,
2643 netmos_9755,
2644 netmos_9805,
2645 netmos_9815,
2646 netmos_9901,
2647 netmos_9865,
2648 quatech_sppxp100,
2649};
2650
2651
2652/* each element directly indexed from enum list, above
2653 * (but offset by last_sio) */
2654static struct parport_pc_pci {
2655 int numports;
2656 struct { /* BAR (base address registers) numbers in the config
2657 space header */
2658 int lo;
2659 int hi;
2660 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2661 } addr[4];
2662
2663 /* If set, this is called immediately after pci_enable_device.
2664 * If it returns non-zero, no probing will take place and the
2665 * ports will not be used. */
2666 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2667
2668 /* If set, this is called after probing for ports. If 'failed'
2669 * is non-zero we couldn't use any of the ports. */
2670 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2671} cards[] = {
2672 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2673 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2674 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2675 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2676 /* lava_parallel */ { 1, { { 0, -1 }, } },
2677 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2678 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2679 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2680 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2681 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2682 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2683 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2684 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2685 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2686 /* SYBA uses fixed offsets in
2687 a 1K io window */
2688 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2689 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2690 /* titan_010l */ { 1, { { 3, -1 }, } },
2691 /* avlab_1p */ { 1, { { 0, 1}, } },
2692 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2693 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2694 * and 840 locks up if you write 1 to bit 2! */
2695 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2696 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2697 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2698 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2699 /* aks_0100 */ { 1, { { 0, -1 }, } },
2700 /* mobility_pp */ { 1, { { 0, 1 }, } },
2701
2702 /* The netmos entries below are untested */
2703 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2704 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2705 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2706 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2707 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2708 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2709 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2710 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2711};
2712
2713static const struct pci_device_id parport_pc_pci_tbl[] = {
2714 /* Super-IO onboard chips */
2715 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2716 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2717 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2719
2720 /* PCI cards */
2721 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2723 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2725 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2727 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2729 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2731 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2733 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2735 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2737 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2738 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2739 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2740 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2741 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2742 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2743 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2744 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2745 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2747 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2749 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2751 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2752 /* AFAVLAB_TK9902 */
2753 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2754 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2755 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2757 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2759 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2761 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2762 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2763 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2765 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2767 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2768 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2769 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2771 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2773 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2775 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2777 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2779 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2780 /* NetMos communication controllers */
2781 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2783 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2785 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2786 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2787 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2789 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2791 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2792 0xA000, 0x2000, 0, 0, netmos_9901 },
2793 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2794 0xA000, 0x1000, 0, 0, netmos_9865 },
2795 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2796 0xA000, 0x2000, 0, 0, netmos_9865 },
2797 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2798 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2800 { 0, } /* terminate list */
2801};
2802MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
2803
2804struct pci_parport_data {
2805 int num;
2806 struct parport *ports[2];
2807};
2808
2809static int parport_pc_pci_probe(struct pci_dev *dev,
2810 const struct pci_device_id *id)
2811{
2812 int err, count, n, i = id->driver_data;
2813 struct pci_parport_data *data;
2814
2815 if (i < last_sio)
2816 /* This is an onboard Super-IO and has already been probed */
2817 return 0;
2818
2819 /* This is a PCI card */
2820 i -= last_sio;
2821 count = 0;
2822 err = pci_enable_device(dev);
2823 if (err)
2824 return err;
2825
2826 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2827 if (!data)
2828 return -ENOMEM;
2829
2830 if (cards[i].preinit_hook &&
2831 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2832 kfree(data);
2833 return -ENODEV;
2834 }
2835
2836 for (n = 0; n < cards[i].numports; n++) {
2837 int lo = cards[i].addr[n].lo;
2838 int hi = cards[i].addr[n].hi;
2839 int irq;
2840 unsigned long io_lo, io_hi;
2841 io_lo = pci_resource_start(dev, lo);
2842 io_hi = 0;
2843 if ((hi >= 0) && (hi <= 6))
2844 io_hi = pci_resource_start(dev, hi);
2845 else if (hi > 6)
2846 io_lo += hi; /* Reinterpret the meaning of
2847 "hi" as an offset (see SYBA
2848 def.) */
2849 /* TODO: test if sharing interrupts works */
2850 irq = dev->irq;
2851 if (irq == IRQ_NONE) {
2852 printk(KERN_DEBUG
2853 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2854 id->vendor, id->device, io_lo, io_hi);
2855 irq = PARPORT_IRQ_NONE;
2856 } else {
2857 printk(KERN_DEBUG
2858 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2859 id->vendor, id->device, io_lo, io_hi, irq);
2860 }
2861 data->ports[count] =
2862 parport_pc_probe_port(io_lo, io_hi, irq,
2863 PARPORT_DMA_NONE, &dev->dev,
2864 IRQF_SHARED);
2865 if (data->ports[count])
2866 count++;
2867 }
2868
2869 data->num = count;
2870
2871 if (cards[i].postinit_hook)
2872 cards[i].postinit_hook(dev, count == 0);
2873
2874 if (count) {
2875 pci_set_drvdata(dev, data);
2876 return 0;
2877 }
2878
2879 kfree(data);
2880
2881 return -ENODEV;
2882}
2883
2884static void parport_pc_pci_remove(struct pci_dev *dev)
2885{
2886 struct pci_parport_data *data = pci_get_drvdata(dev);
2887 int i;
2888
2889 if (data) {
2890 for (i = data->num - 1; i >= 0; i--)
2891 parport_pc_unregister_port(data->ports[i]);
2892
2893 kfree(data);
2894 }
2895}
2896
2897static struct pci_driver parport_pc_pci_driver = {
2898 .name = "parport_pc",
2899 .id_table = parport_pc_pci_tbl,
2900 .probe = parport_pc_pci_probe,
2901 .remove = parport_pc_pci_remove,
2902};
2903
2904static int __init parport_pc_init_superio(int autoirq, int autodma)
2905{
2906 const struct pci_device_id *id;
2907 struct pci_dev *pdev = NULL;
2908 int ret = 0;
2909
2910 for_each_pci_dev(pdev) {
2911 id = pci_match_id(parport_pc_pci_tbl, pdev);
2912 if (id == NULL || id->driver_data >= last_sio)
2913 continue;
2914
2915 if (parport_pc_superio_info[id->driver_data].probe(
2916 pdev, autoirq, autodma,
2917 parport_pc_superio_info[id->driver_data].via)) {
2918 ret++;
2919 }
2920 }
2921
2922 return ret; /* number of devices found */
2923}
2924#else
2925static struct pci_driver parport_pc_pci_driver;
2926static int __init parport_pc_init_superio(int autoirq, int autodma)
2927{
2928 return 0;
2929}
2930#endif /* CONFIG_PCI */
2931
2932#ifdef CONFIG_PNP
2933
2934static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2935 /* Standard LPT Printer Port */
2936 {.id = "PNP0400", .driver_data = 0},
2937 /* ECP Printer Port */
2938 {.id = "PNP0401", .driver_data = 0},
2939 { }
2940};
2941
2942MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
2943
2944static int parport_pc_pnp_probe(struct pnp_dev *dev,
2945 const struct pnp_device_id *id)
2946{
2947 struct parport *pdata;
2948 unsigned long io_lo, io_hi;
2949 int dma, irq;
2950
2951 if (pnp_port_valid(dev, 0) &&
2952 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2953 io_lo = pnp_port_start(dev, 0);
2954 } else
2955 return -EINVAL;
2956
2957 if (pnp_port_valid(dev, 1) &&
2958 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2959 io_hi = pnp_port_start(dev, 1);
2960 } else
2961 io_hi = 0;
2962
2963 if (pnp_irq_valid(dev, 0) &&
2964 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
2965 irq = pnp_irq(dev, 0);
2966 } else
2967 irq = PARPORT_IRQ_NONE;
2968
2969 if (pnp_dma_valid(dev, 0) &&
2970 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
2971 dma = pnp_dma(dev, 0);
2972 } else
2973 dma = PARPORT_DMA_NONE;
2974
2975 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
2976 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
2977 if (pdata == NULL)
2978 return -ENODEV;
2979
2980 pnp_set_drvdata(dev, pdata);
2981 return 0;
2982}
2983
2984static void parport_pc_pnp_remove(struct pnp_dev *dev)
2985{
2986 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
2987 if (!pdata)
2988 return;
2989
2990 parport_pc_unregister_port(pdata);
2991}
2992
2993/* we only need the pnp layer to activate the device, at least for now */
2994static struct pnp_driver parport_pc_pnp_driver = {
2995 .name = "parport_pc",
2996 .id_table = parport_pc_pnp_tbl,
2997 .probe = parport_pc_pnp_probe,
2998 .remove = parport_pc_pnp_remove,
2999};
3000
3001#else
3002static struct pnp_driver parport_pc_pnp_driver;
3003#endif /* CONFIG_PNP */
3004
3005static int parport_pc_platform_probe(struct platform_device *pdev)
3006{
3007 /* Always succeed, the actual probing is done in
3008 * parport_pc_probe_port(). */
3009 return 0;
3010}
3011
3012static struct platform_driver parport_pc_platform_driver = {
3013 .driver = {
3014 .name = "parport_pc",
3015 },
3016 .probe = parport_pc_platform_probe,
3017};
3018
3019/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3020static int __attribute__((unused))
3021parport_pc_find_isa_ports(int autoirq, int autodma)
3022{
3023 int count = 0;
3024
3025 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3026 count++;
3027 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3028 count++;
3029 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3030 count++;
3031
3032 return count;
3033}
3034
3035/* This function is called by parport_pc_init if the user didn't
3036 * specify any ports to probe. Its job is to find some ports. Order
3037 * is important here -- we want ISA ports to be registered first,
3038 * followed by PCI cards (for least surprise), but before that we want
3039 * to do chipset-specific tests for some onboard ports that we know
3040 * about.
3041 *
3042 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3043 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3044 */
3045static void __init parport_pc_find_ports(int autoirq, int autodma)
3046{
3047 int count = 0, err;
3048
3049#ifdef CONFIG_PARPORT_PC_SUPERIO
3050 detect_and_report_it87();
3051 detect_and_report_winbond();
3052 detect_and_report_smsc();
3053#endif
3054
3055 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3056 count += parport_pc_init_superio(autoirq, autodma);
3057
3058 /* PnP ports, skip detection if SuperIO already found them */
3059 if (!count) {
3060 err = pnp_register_driver(&parport_pc_pnp_driver);
3061 if (!err)
3062 pnp_registered_parport = 1;
3063 }
3064
3065 /* ISA ports and whatever (see asm/parport.h). */
3066 parport_pc_find_nonpci_ports(autoirq, autodma);
3067
3068 err = pci_register_driver(&parport_pc_pci_driver);
3069 if (!err)
3070 pci_registered_parport = 1;
3071}
3072
3073/*
3074 * Piles of crap below pretend to be a parser for module and kernel
3075 * parameters. Say "thank you" to whoever had come up with that
3076 * syntax and keep in mind that code below is a cleaned up version.
3077 */
3078
3079static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3080 [0 ... PARPORT_PC_MAX_PORTS] = 0
3081};
3082static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3083 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3084};
3085static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3086 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3087};
3088static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3089 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3090};
3091
3092static int __init parport_parse_param(const char *s, int *val,
3093 int automatic, int none, int nofifo)
3094{
3095 if (!s)
3096 return 0;
3097 if (!strncmp(s, "auto", 4))
3098 *val = automatic;
3099 else if (!strncmp(s, "none", 4))
3100 *val = none;
3101 else if (nofifo && !strncmp(s, "nofifo", 6))
3102 *val = nofifo;
3103 else {
3104 char *ep;
3105 unsigned long r = simple_strtoul(s, &ep, 0);
3106 if (ep != s)
3107 *val = r;
3108 else {
3109 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3110 return -1;
3111 }
3112 }
3113 return 0;
3114}
3115
3116static int __init parport_parse_irq(const char *irqstr, int *val)
3117{
3118 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3119 PARPORT_IRQ_NONE, 0);
3120}
3121
3122static int __init parport_parse_dma(const char *dmastr, int *val)
3123{
3124 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3125 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3126}
3127
3128#ifdef CONFIG_PCI
3129static int __init parport_init_mode_setup(char *str)
3130{
3131 printk(KERN_DEBUG
3132 "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3133
3134 if (!strcmp(str, "spp"))
3135 parport_init_mode = 1;
3136 if (!strcmp(str, "ps2"))
3137 parport_init_mode = 2;
3138 if (!strcmp(str, "epp"))
3139 parport_init_mode = 3;
3140 if (!strcmp(str, "ecp"))
3141 parport_init_mode = 4;
3142 if (!strcmp(str, "ecpepp"))
3143 parport_init_mode = 5;
3144 return 1;
3145}
3146#endif
3147
3148#ifdef MODULE
3149static char *irq[PARPORT_PC_MAX_PORTS];
3150static char *dma[PARPORT_PC_MAX_PORTS];
3151
3152MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3153module_param_array(io, int, NULL, 0);
3154MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3155module_param_array(io_hi, int, NULL, 0);
3156MODULE_PARM_DESC(irq, "IRQ line");
3157module_param_array(irq, charp, NULL, 0);
3158MODULE_PARM_DESC(dma, "DMA channel");
3159module_param_array(dma, charp, NULL, 0);
3160#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3161 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3162MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3163module_param(verbose_probing, int, 0644);
3164#endif
3165#ifdef CONFIG_PCI
3166static char *init_mode;
3167MODULE_PARM_DESC(init_mode,
3168 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3169module_param(init_mode, charp, 0);
3170#endif
3171
3172static int __init parse_parport_params(void)
3173{
3174 unsigned int i;
3175 int val;
3176
3177#ifdef CONFIG_PCI
3178 if (init_mode)
3179 parport_init_mode_setup(init_mode);
3180#endif
3181
3182 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3183 if (parport_parse_irq(irq[i], &val))
3184 return 1;
3185 irqval[i] = val;
3186 if (parport_parse_dma(dma[i], &val))
3187 return 1;
3188 dmaval[i] = val;
3189 }
3190 if (!io[0]) {
3191 /* The user can make us use any IRQs or DMAs we find. */
3192 if (irq[0] && !parport_parse_irq(irq[0], &val))
3193 switch (val) {
3194 case PARPORT_IRQ_NONE:
3195 case PARPORT_IRQ_AUTO:
3196 irqval[0] = val;
3197 break;
3198 default:
3199 printk(KERN_WARNING
3200 "parport_pc: irq specified "
3201 "without base address. Use 'io=' "
3202 "to specify one\n");
3203 }
3204
3205 if (dma[0] && !parport_parse_dma(dma[0], &val))
3206 switch (val) {
3207 case PARPORT_DMA_NONE:
3208 case PARPORT_DMA_AUTO:
3209 dmaval[0] = val;
3210 break;
3211 default:
3212 printk(KERN_WARNING
3213 "parport_pc: dma specified "
3214 "without base address. Use 'io=' "
3215 "to specify one\n");
3216 }
3217 }
3218 return 0;
3219}
3220
3221#else
3222
3223static int parport_setup_ptr __initdata;
3224
3225/*
3226 * Acceptable parameters:
3227 *
3228 * parport=0
3229 * parport=auto
3230 * parport=0xBASE[,IRQ[,DMA]]
3231 *
3232 * IRQ/DMA may be numeric or 'auto' or 'none'
3233 */
3234static int __init parport_setup(char *str)
3235{
3236 char *endptr;
3237 char *sep;
3238 int val;
3239
3240 if (!str || !*str || (*str == '0' && !*(str+1))) {
3241 /* Disable parport if "parport=0" in cmdline */
3242 io[0] = PARPORT_DISABLE;
3243 return 1;
3244 }
3245
3246 if (!strncmp(str, "auto", 4)) {
3247 irqval[0] = PARPORT_IRQ_AUTO;
3248 dmaval[0] = PARPORT_DMA_AUTO;
3249 return 1;
3250 }
3251
3252 val = simple_strtoul(str, &endptr, 0);
3253 if (endptr == str) {
3254 printk(KERN_WARNING "parport=%s not understood\n", str);
3255 return 1;
3256 }
3257
3258 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3259 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3260 return 1;
3261 }
3262
3263 io[parport_setup_ptr] = val;
3264 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3265 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3266
3267 sep = strchr(str, ',');
3268 if (sep++) {
3269 if (parport_parse_irq(sep, &val))
3270 return 1;
3271 irqval[parport_setup_ptr] = val;
3272 sep = strchr(sep, ',');
3273 if (sep++) {
3274 if (parport_parse_dma(sep, &val))
3275 return 1;
3276 dmaval[parport_setup_ptr] = val;
3277 }
3278 }
3279 parport_setup_ptr++;
3280 return 1;
3281}
3282
3283static int __init parse_parport_params(void)
3284{
3285 return io[0] == PARPORT_DISABLE;
3286}
3287
3288__setup("parport=", parport_setup);
3289
3290/*
3291 * Acceptable parameters:
3292 *
3293 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3294 */
3295#ifdef CONFIG_PCI
3296__setup("parport_init_mode=", parport_init_mode_setup);
3297#endif
3298#endif
3299
3300/* "Parser" ends here */
3301
3302static int __init parport_pc_init(void)
3303{
3304 int err;
3305
3306 if (parse_parport_params())
3307 return -EINVAL;
3308
3309 err = platform_driver_register(&parport_pc_platform_driver);
3310 if (err)
3311 return err;
3312
3313 if (io[0]) {
3314 int i;
3315 /* Only probe the ports we were given. */
3316 user_specified = 1;
3317 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3318 if (!io[i])
3319 break;
3320 if (io_hi[i] == PARPORT_IOHI_AUTO)
3321 io_hi[i] = 0x400 + io[i];
3322 parport_pc_probe_port(io[i], io_hi[i],
3323 irqval[i], dmaval[i], NULL, 0);
3324 }
3325 } else
3326 parport_pc_find_ports(irqval[0], dmaval[0]);
3327
3328 return 0;
3329}
3330
3331static void __exit parport_pc_exit(void)
3332{
3333 if (pci_registered_parport)
3334 pci_unregister_driver(&parport_pc_pci_driver);
3335 if (pnp_registered_parport)
3336 pnp_unregister_driver(&parport_pc_pnp_driver);
3337 platform_driver_unregister(&parport_pc_platform_driver);
3338
3339 while (!list_empty(&ports_list)) {
3340 struct parport_pc_private *priv;
3341 struct parport *port;
3342 struct device *dev;
3343 priv = list_entry(ports_list.next,
3344 struct parport_pc_private, list);
3345 port = priv->port;
3346 dev = port->dev;
3347 parport_pc_unregister_port(port);
3348 if (dev && dev->bus == &platform_bus_type)
3349 platform_device_unregister(to_platform_device(dev));
3350 }
3351}
3352
3353MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3354MODULE_DESCRIPTION("PC-style parallel port driver");
3355MODULE_LICENSE("GPL");
3356module_init(parport_pc_init)
3357module_exit(parport_pc_exit)