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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/dma-mapping.h>
18#include "ath9k.h"
19#include "ar9003_mac.h"
20
21#define BITS_PER_BYTE 8
22#define OFDM_PLCP_BITS 22
23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24#define L_STF 8
25#define L_LTF 8
26#define L_SIG 4
27#define HT_SIG 8
28#define HT_STF 4
29#define HT_LTF(_ns) (4 * (_ns))
30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32#define TIME_SYMBOLS(t) ((t) >> 2)
33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37/* Shifts in ar5008_phy.c and ar9003_phy.c are equal for all revisions */
38#define ATH9K_PWRTBL_11NA_OFDM_SHIFT 0
39#define ATH9K_PWRTBL_11NG_OFDM_SHIFT 4
40#define ATH9K_PWRTBL_11NA_HT_SHIFT 8
41#define ATH9K_PWRTBL_11NG_HT_SHIFT 12
42
43
44static u16 bits_per_symbol[][2] = {
45 /* 20MHz 40MHz */
46 { 26, 54 }, /* 0: BPSK */
47 { 52, 108 }, /* 1: QPSK 1/2 */
48 { 78, 162 }, /* 2: QPSK 3/4 */
49 { 104, 216 }, /* 3: 16-QAM 1/2 */
50 { 156, 324 }, /* 4: 16-QAM 3/4 */
51 { 208, 432 }, /* 5: 64-QAM 2/3 */
52 { 234, 486 }, /* 6: 64-QAM 3/4 */
53 { 260, 540 }, /* 7: 64-QAM 5/6 */
54};
55
56static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
57 struct ath_atx_tid *tid, struct sk_buff *skb);
58static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
59 int tx_flags, struct ath_txq *txq,
60 struct ieee80211_sta *sta);
61static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_txq *txq, struct list_head *bf_q,
63 struct ieee80211_sta *sta,
64 struct ath_tx_status *ts, int txok);
65static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
66 struct list_head *head, bool internal);
67static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
68 struct ath_tx_status *ts, int nframes, int nbad,
69 int txok);
70static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
71 struct ath_buf *bf);
72static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
73 struct ath_txq *txq,
74 struct ath_atx_tid *tid,
75 struct sk_buff *skb);
76static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
77 struct ath_tx_control *txctl);
78
79enum {
80 MCS_HT20,
81 MCS_HT20_SGI,
82 MCS_HT40,
83 MCS_HT40_SGI,
84};
85
86/*********************/
87/* Aggregation logic */
88/*********************/
89
90static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
91{
92 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
93 struct ieee80211_sta *sta = info->status.status_driver_data[0];
94
95 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
96 IEEE80211_TX_STATUS_EOSP)) {
97 ieee80211_tx_status_skb(hw, skb);
98 return;
99 }
100
101 if (sta)
102 ieee80211_tx_status_noskb(hw, sta, info);
103
104 dev_kfree_skb(skb);
105}
106
107void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
108 __releases(&txq->axq_lock)
109{
110 struct ieee80211_hw *hw = sc->hw;
111 struct sk_buff_head q;
112 struct sk_buff *skb;
113
114 __skb_queue_head_init(&q);
115 skb_queue_splice_init(&txq->complete_q, &q);
116 spin_unlock_bh(&txq->axq_lock);
117
118 while ((skb = __skb_dequeue(&q)))
119 ath_tx_status(hw, skb);
120}
121
122void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
123{
124 struct ieee80211_txq *queue =
125 container_of((void *)tid, struct ieee80211_txq, drv_priv);
126
127 ieee80211_schedule_txq(sc->hw, queue);
128}
129
130void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
131{
132 struct ath_softc *sc = hw->priv;
133 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
134 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
135 struct ath_txq *txq = tid->txq;
136
137 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
138 queue->sta ? queue->sta->addr : queue->vif->addr,
139 tid->tidno);
140
141 ath_txq_lock(sc, txq);
142 ath_txq_schedule(sc, txq);
143 ath_txq_unlock(sc, txq);
144}
145
146static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
147{
148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
150 sizeof(tx_info->status.status_driver_data));
151 return (struct ath_frame_info *) &tx_info->status.status_driver_data[0];
152}
153
154static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
155{
156 if (!tid->an->sta)
157 return;
158
159 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
160 seqno << IEEE80211_SEQ_SEQ_SHIFT);
161}
162
163static bool ath_merge_ratetbl(struct ieee80211_sta *sta, struct ath_buf *bf,
164 struct ieee80211_tx_info *tx_info)
165{
166 struct ieee80211_sta_rates *ratetbl;
167 u8 i;
168
169 if (!sta)
170 return false;
171
172 ratetbl = rcu_dereference(sta->rates);
173 if (!ratetbl)
174 return false;
175
176 if (tx_info->control.rates[0].idx < 0 ||
177 tx_info->control.rates[0].count == 0)
178 {
179 i = 0;
180 } else {
181 bf->rates[0] = tx_info->control.rates[0];
182 i = 1;
183 }
184
185 for ( ; i < IEEE80211_TX_MAX_RATES; i++) {
186 bf->rates[i].idx = ratetbl->rate[i].idx;
187 bf->rates[i].flags = ratetbl->rate[i].flags;
188 if (tx_info->control.use_rts)
189 bf->rates[i].count = ratetbl->rate[i].count_rts;
190 else if (tx_info->control.use_cts_prot)
191 bf->rates[i].count = ratetbl->rate[i].count_cts;
192 else
193 bf->rates[i].count = ratetbl->rate[i].count;
194 }
195
196 return true;
197}
198
199static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
200 struct ath_buf *bf)
201{
202 struct ieee80211_tx_info *tx_info;
203
204 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
205
206 if (!ath_merge_ratetbl(sta, bf, tx_info))
207 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
208 ARRAY_SIZE(bf->rates));
209}
210
211static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
212 struct sk_buff *skb)
213{
214 struct ath_frame_info *fi = get_frame_info(skb);
215 int q = fi->txq;
216
217 if (q < 0)
218 return;
219
220 txq = sc->tx.txq_map[q];
221 if (WARN_ON(--txq->pending_frames < 0))
222 txq->pending_frames = 0;
223
224}
225
226static struct ath_atx_tid *
227ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
228{
229 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
230 return ATH_AN_2_TID(an, tidno);
231}
232
233static int
234ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf)
235{
236 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
237 struct ath_softc *sc = tid->an->sc;
238 struct ieee80211_hw *hw = sc->hw;
239 struct ath_tx_control txctl = {
240 .txq = tid->txq,
241 .sta = tid->an->sta,
242 };
243 struct sk_buff *skb;
244 struct ath_frame_info *fi;
245 int q, ret;
246
247 skb = ieee80211_tx_dequeue(hw, txq);
248 if (!skb)
249 return -ENOENT;
250
251 ret = ath_tx_prepare(hw, skb, &txctl);
252 if (ret) {
253 ieee80211_free_txskb(hw, skb);
254 return ret;
255 }
256
257 q = skb_get_queue_mapping(skb);
258 if (tid->txq == sc->tx.txq_map[q]) {
259 fi = get_frame_info(skb);
260 fi->txq = q;
261 ++tid->txq->pending_frames;
262 }
263
264 *skbuf = skb;
265 return 0;
266}
267
268static int ath_tid_dequeue(struct ath_atx_tid *tid,
269 struct sk_buff **skb)
270{
271 int ret = 0;
272 *skb = __skb_dequeue(&tid->retry_q);
273 if (!*skb)
274 ret = ath_tid_pull(tid, skb);
275
276 return ret;
277}
278
279static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
280{
281 struct ath_txq *txq = tid->txq;
282 struct sk_buff *skb;
283 struct ath_buf *bf;
284 struct list_head bf_head;
285 struct ath_tx_status ts;
286 struct ath_frame_info *fi;
287 bool sendbar = false;
288
289 INIT_LIST_HEAD(&bf_head);
290
291 memset(&ts, 0, sizeof(ts));
292
293 while ((skb = __skb_dequeue(&tid->retry_q))) {
294 fi = get_frame_info(skb);
295 bf = fi->bf;
296 if (!bf) {
297 ath_txq_skb_done(sc, txq, skb);
298 ieee80211_free_txskb(sc->hw, skb);
299 continue;
300 }
301
302 if (fi->baw_tracked) {
303 ath_tx_update_baw(sc, tid, bf);
304 sendbar = true;
305 }
306
307 list_add_tail(&bf->list, &bf_head);
308 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
309 }
310
311 if (sendbar) {
312 ath_txq_unlock(sc, txq);
313 ath_send_bar(tid, tid->seq_start);
314 ath_txq_lock(sc, txq);
315 }
316}
317
318static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
319 struct ath_buf *bf)
320{
321 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
322 u16 seqno = bf->bf_state.seqno;
323 int index, cindex;
324
325 if (!fi->baw_tracked)
326 return;
327
328 index = ATH_BA_INDEX(tid->seq_start, seqno);
329 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
330
331 __clear_bit(cindex, tid->tx_buf);
332
333 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
334 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
335 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
336 if (tid->bar_index >= 0)
337 tid->bar_index--;
338 }
339}
340
341static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
342 struct ath_buf *bf)
343{
344 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
345 u16 seqno = bf->bf_state.seqno;
346 int index, cindex;
347
348 if (fi->baw_tracked)
349 return;
350
351 index = ATH_BA_INDEX(tid->seq_start, seqno);
352 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
353 __set_bit(cindex, tid->tx_buf);
354 fi->baw_tracked = 1;
355
356 if (index >= ((tid->baw_tail - tid->baw_head) &
357 (ATH_TID_MAX_BUFS - 1))) {
358 tid->baw_tail = cindex;
359 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
360 }
361}
362
363static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
364 struct ath_atx_tid *tid)
365
366{
367 struct sk_buff *skb;
368 struct ath_buf *bf;
369 struct list_head bf_head;
370 struct ath_tx_status ts;
371 struct ath_frame_info *fi;
372 int ret;
373
374 memset(&ts, 0, sizeof(ts));
375 INIT_LIST_HEAD(&bf_head);
376
377 while ((ret = ath_tid_dequeue(tid, &skb)) == 0) {
378 fi = get_frame_info(skb);
379 bf = fi->bf;
380
381 if (!bf) {
382 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
383 continue;
384 }
385
386 list_add_tail(&bf->list, &bf_head);
387 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
388 }
389}
390
391static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
392 struct sk_buff *skb, int count)
393{
394 struct ath_frame_info *fi = get_frame_info(skb);
395 struct ath_buf *bf = fi->bf;
396 struct ieee80211_hdr *hdr;
397 int prev = fi->retries;
398
399 TX_STAT_INC(sc, txq->axq_qnum, a_retries);
400 fi->retries += count;
401
402 if (prev > 0)
403 return;
404
405 hdr = (struct ieee80211_hdr *)skb->data;
406 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
407 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
408 sizeof(*hdr), DMA_TO_DEVICE);
409}
410
411static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
412{
413 struct ath_buf *bf = NULL;
414
415 spin_lock_bh(&sc->tx.txbuflock);
416
417 if (unlikely(list_empty(&sc->tx.txbuf))) {
418 spin_unlock_bh(&sc->tx.txbuflock);
419 return NULL;
420 }
421
422 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
423 list_del(&bf->list);
424
425 spin_unlock_bh(&sc->tx.txbuflock);
426
427 return bf;
428}
429
430static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
431{
432 spin_lock_bh(&sc->tx.txbuflock);
433 list_add_tail(&bf->list, &sc->tx.txbuf);
434 spin_unlock_bh(&sc->tx.txbuflock);
435}
436
437static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
438{
439 struct ath_buf *tbf;
440
441 tbf = ath_tx_get_buffer(sc);
442 if (WARN_ON(!tbf))
443 return NULL;
444
445 ATH_TXBUF_RESET(tbf);
446
447 tbf->bf_mpdu = bf->bf_mpdu;
448 tbf->bf_buf_addr = bf->bf_buf_addr;
449 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
450 tbf->bf_state = bf->bf_state;
451 tbf->bf_state.stale = false;
452
453 return tbf;
454}
455
456static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
457 struct ath_tx_status *ts, int txok,
458 int *nframes, int *nbad)
459{
460 u16 seq_st = 0;
461 u32 ba[WME_BA_BMP_SIZE >> 5];
462 int ba_index;
463 int isaggr = 0;
464
465 *nbad = 0;
466 *nframes = 0;
467
468 isaggr = bf_isaggr(bf);
469 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
470
471 if (isaggr) {
472 seq_st = ts->ts_seqnum;
473 memcpy(ba, &ts->ba, WME_BA_BMP_SIZE >> 3);
474 }
475
476 while (bf) {
477 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
478
479 (*nframes)++;
480 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
481 (*nbad)++;
482
483 bf = bf->bf_next;
484 }
485}
486
487
488static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
489 struct ath_buf *bf, struct list_head *bf_q,
490 struct ieee80211_sta *sta,
491 struct ath_atx_tid *tid,
492 struct ath_tx_status *ts, int txok)
493{
494 struct ath_node *an = NULL;
495 struct sk_buff *skb;
496 struct ieee80211_tx_info *tx_info;
497 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
498 struct list_head bf_head;
499 struct sk_buff_head bf_pending;
500 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
501 u32 ba[WME_BA_BMP_SIZE >> 5];
502 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
503 bool rc_update = true, isba;
504 struct ieee80211_tx_rate rates[4];
505 struct ath_frame_info *fi;
506 int nframes;
507 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
508 int i, retries;
509 int bar_index = -1;
510
511 skb = bf->bf_mpdu;
512 tx_info = IEEE80211_SKB_CB(skb);
513
514 memcpy(rates, bf->rates, sizeof(rates));
515
516 retries = ts->ts_longretry + 1;
517 for (i = 0; i < ts->ts_rateindex; i++)
518 retries += rates[i].count;
519
520 if (!sta) {
521 INIT_LIST_HEAD(&bf_head);
522 while (bf) {
523 bf_next = bf->bf_next;
524
525 if (!bf->bf_state.stale || bf_next != NULL)
526 list_move_tail(&bf->list, &bf_head);
527
528 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
529
530 bf = bf_next;
531 }
532 return;
533 }
534
535 an = (struct ath_node *)sta->drv_priv;
536 seq_first = tid->seq_start;
537 isba = ts->ts_flags & ATH9K_TX_BA;
538
539 /*
540 * The hardware occasionally sends a tx status for the wrong TID.
541 * In this case, the BA status cannot be considered valid and all
542 * subframes need to be retransmitted
543 *
544 * Only BlockAcks have a TID and therefore normal Acks cannot be
545 * checked
546 */
547 if (isba && tid->tidno != ts->tid)
548 txok = false;
549
550 isaggr = bf_isaggr(bf);
551 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
552
553 if (isaggr && txok) {
554 if (ts->ts_flags & ATH9K_TX_BA) {
555 seq_st = ts->ts_seqnum;
556 memcpy(ba, &ts->ba, WME_BA_BMP_SIZE >> 3);
557 } else {
558 /*
559 * AR5416 can become deaf/mute when BA
560 * issue happens. Chip needs to be reset.
561 * But AP code may have sychronization issues
562 * when perform internal reset in this routine.
563 * Only enable reset in STA mode for now.
564 */
565 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
566 needreset = 1;
567 }
568 }
569
570 __skb_queue_head_init(&bf_pending);
571
572 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
573 while (bf) {
574 u16 seqno = bf->bf_state.seqno;
575
576 txfail = txpending = sendbar = 0;
577 bf_next = bf->bf_next;
578
579 skb = bf->bf_mpdu;
580 tx_info = IEEE80211_SKB_CB(skb);
581 fi = get_frame_info(skb);
582
583 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
584 !tid->active) {
585 /*
586 * Outside of the current BlockAck window,
587 * maybe part of a previous session
588 */
589 txfail = 1;
590 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
591 /* transmit completion, subframe is
592 * acked by block ack */
593 acked_cnt++;
594 } else if (!isaggr && txok) {
595 /* transmit completion */
596 acked_cnt++;
597 } else if (flush) {
598 txpending = 1;
599 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
600 if (txok || !an->sleeping)
601 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
602 retries);
603
604 txpending = 1;
605 } else {
606 txfail = 1;
607 txfail_cnt++;
608 bar_index = max_t(int, bar_index,
609 ATH_BA_INDEX(seq_first, seqno));
610 }
611
612 /*
613 * Make sure the last desc is reclaimed if it
614 * not a holding desc.
615 */
616 INIT_LIST_HEAD(&bf_head);
617 if (bf_next != NULL || !bf_last->bf_state.stale)
618 list_move_tail(&bf->list, &bf_head);
619
620 if (!txpending) {
621 /*
622 * complete the acked-ones/xretried ones; update
623 * block-ack window
624 */
625 ath_tx_update_baw(sc, tid, bf);
626
627 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
628 memcpy(tx_info->control.rates, rates, sizeof(rates));
629 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
630 rc_update = false;
631 if (bf == bf->bf_lastbf)
632 ath_dynack_sample_tx_ts(sc->sc_ah,
633 bf->bf_mpdu,
634 ts, sta);
635 }
636
637 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
638 !txfail);
639 } else {
640 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
641 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
642 ieee80211_sta_eosp(sta);
643 }
644 /* retry the un-acked ones */
645 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
646 struct ath_buf *tbf;
647
648 tbf = ath_clone_txbuf(sc, bf_last);
649 /*
650 * Update tx baw and complete the
651 * frame with failed status if we
652 * run out of tx buf.
653 */
654 if (!tbf) {
655 ath_tx_update_baw(sc, tid, bf);
656
657 ath_tx_complete_buf(sc, bf, txq,
658 &bf_head, NULL, ts,
659 0);
660 bar_index = max_t(int, bar_index,
661 ATH_BA_INDEX(seq_first, seqno));
662 break;
663 }
664
665 fi->bf = tbf;
666 }
667
668 /*
669 * Put this buffer to the temporary pending
670 * queue to retain ordering
671 */
672 __skb_queue_tail(&bf_pending, skb);
673 }
674
675 bf = bf_next;
676 }
677
678 /* prepend un-acked frames to the beginning of the pending frame queue */
679 if (!skb_queue_empty(&bf_pending)) {
680 if (an->sleeping)
681 ieee80211_sta_set_buffered(sta, tid->tidno, true);
682
683 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
684 if (!an->sleeping) {
685 ath_tx_queue_tid(sc, tid);
686 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
687 tid->clear_ps_filter = true;
688 }
689 }
690
691 if (bar_index >= 0) {
692 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
693
694 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
695 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
696
697 ath_txq_unlock(sc, txq);
698 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
699 ath_txq_lock(sc, txq);
700 }
701
702 if (needreset)
703 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
704}
705
706static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
707{
708 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
709 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
710}
711
712static void ath_tx_count_airtime(struct ath_softc *sc,
713 struct ieee80211_sta *sta,
714 struct ath_buf *bf,
715 struct ath_tx_status *ts,
716 u8 tid)
717{
718 u32 airtime = 0;
719 int i;
720
721 airtime += ts->duration * (ts->ts_longretry + 1);
722 for(i = 0; i < ts->ts_rateindex; i++) {
723 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
724 airtime += rate_dur * bf->rates[i].count;
725 }
726
727 ieee80211_sta_register_airtime(sta, tid, airtime, 0);
728}
729
730static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
731 struct ath_tx_status *ts, struct ath_buf *bf,
732 struct list_head *bf_head)
733{
734 struct ieee80211_hw *hw = sc->hw;
735 struct ieee80211_tx_info *info;
736 struct ieee80211_sta *sta;
737 struct ieee80211_hdr *hdr;
738 struct ath_atx_tid *tid = NULL;
739 bool txok, flush;
740
741 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
742 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
743 txq->axq_tx_inprogress = false;
744
745 txq->axq_depth--;
746 if (bf_is_ampdu_not_probing(bf))
747 txq->axq_ampdu_depth--;
748
749 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
750 ts->ts_rateindex);
751
752 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
753 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
754 if (sta) {
755 struct ath_node *an = (struct ath_node *)sta->drv_priv;
756 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
757 ath_tx_count_airtime(sc, sta, bf, ts, tid->tidno);
758 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
759 tid->clear_ps_filter = true;
760 }
761
762 if (!bf_isampdu(bf)) {
763 if (!flush) {
764 info = IEEE80211_SKB_CB(bf->bf_mpdu);
765 memcpy(info->control.rates, bf->rates,
766 sizeof(info->control.rates));
767 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
768 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
769 sta);
770 }
771 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
772 } else
773 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
774
775 if (!flush)
776 ath_txq_schedule(sc, txq);
777}
778
779static bool ath_lookup_legacy(struct ath_buf *bf)
780{
781 struct sk_buff *skb;
782 struct ieee80211_tx_info *tx_info;
783 struct ieee80211_tx_rate *rates;
784 int i;
785
786 skb = bf->bf_mpdu;
787 tx_info = IEEE80211_SKB_CB(skb);
788 rates = tx_info->control.rates;
789
790 for (i = 0; i < 4; i++) {
791 if (!rates[i].count || rates[i].idx < 0)
792 break;
793
794 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
795 return true;
796 }
797
798 return false;
799}
800
801static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
802 struct ath_atx_tid *tid)
803{
804 struct sk_buff *skb;
805 struct ieee80211_tx_info *tx_info;
806 struct ieee80211_tx_rate *rates;
807 u32 max_4ms_framelen, frmlen;
808 u16 aggr_limit, bt_aggr_limit, legacy = 0;
809 int q = tid->txq->mac80211_qnum;
810 int i;
811
812 skb = bf->bf_mpdu;
813 tx_info = IEEE80211_SKB_CB(skb);
814 rates = bf->rates;
815
816 /*
817 * Find the lowest frame length among the rate series that will have a
818 * 4ms (or TXOP limited) transmit duration.
819 */
820 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
821
822 for (i = 0; i < 4; i++) {
823 int modeidx;
824
825 if (!rates[i].count)
826 continue;
827
828 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
829 legacy = 1;
830 break;
831 }
832
833 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
834 modeidx = MCS_HT40;
835 else
836 modeidx = MCS_HT20;
837
838 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
839 modeidx++;
840
841 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
842 max_4ms_framelen = min(max_4ms_framelen, frmlen);
843 }
844
845 /*
846 * limit aggregate size by the minimum rate if rate selected is
847 * not a probe rate, if rate selected is a probe rate then
848 * avoid aggregation of this packet.
849 */
850 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
851 return 0;
852
853 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
854
855 /*
856 * Override the default aggregation limit for BTCOEX.
857 */
858 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
859 if (bt_aggr_limit)
860 aggr_limit = bt_aggr_limit;
861
862 if (tid->an->maxampdu)
863 aggr_limit = min(aggr_limit, tid->an->maxampdu);
864
865 return aggr_limit;
866}
867
868/*
869 * Returns the number of delimiters to be added to
870 * meet the minimum required mpdudensity.
871 */
872static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
873 struct ath_buf *bf, u16 frmlen,
874 bool first_subfrm)
875{
876#define FIRST_DESC_NDELIMS 60
877 u32 nsymbits, nsymbols;
878 u16 minlen;
879 u8 flags, rix;
880 int width, streams, half_gi, ndelim, mindelim;
881 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
882
883 /* Select standard number of delimiters based on frame length alone */
884 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
885
886 /*
887 * If encryption enabled, hardware requires some more padding between
888 * subframes.
889 * TODO - this could be improved to be dependent on the rate.
890 * The hardware can keep up at lower rates, but not higher rates
891 */
892 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
893 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
894 ndelim += ATH_AGGR_ENCRYPTDELIM;
895
896 /*
897 * Add delimiter when using RTS/CTS with aggregation
898 * and non enterprise AR9003 card
899 */
900 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
901 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
902 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
903
904 /*
905 * Convert desired mpdu density from microeconds to bytes based
906 * on highest rate in rate series (i.e. first rate) to determine
907 * required minimum length for subframe. Take into account
908 * whether high rate is 20 or 40Mhz and half or full GI.
909 *
910 * If there is no mpdu density restriction, no further calculation
911 * is needed.
912 */
913
914 if (tid->an->mpdudensity == 0)
915 return ndelim;
916
917 rix = bf->rates[0].idx;
918 flags = bf->rates[0].flags;
919 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
920 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
921
922 if (half_gi)
923 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
924 else
925 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
926
927 if (nsymbols == 0)
928 nsymbols = 1;
929
930 streams = HT_RC_2_STREAMS(rix);
931 nsymbits = bits_per_symbol[rix % 8][width] * streams;
932 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
933
934 if (frmlen < minlen) {
935 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
936 ndelim = max(mindelim, ndelim);
937 }
938
939 return ndelim;
940}
941
942static int
943ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
944 struct ath_atx_tid *tid, struct ath_buf **buf)
945{
946 struct ieee80211_tx_info *tx_info;
947 struct ath_frame_info *fi;
948 struct ath_buf *bf;
949 struct sk_buff *skb, *first_skb = NULL;
950 u16 seqno;
951 int ret;
952
953 while (1) {
954 ret = ath_tid_dequeue(tid, &skb);
955 if (ret < 0)
956 return ret;
957
958 fi = get_frame_info(skb);
959 bf = fi->bf;
960 if (!fi->bf)
961 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
962 else
963 bf->bf_state.stale = false;
964
965 if (!bf) {
966 ath_txq_skb_done(sc, txq, skb);
967 ieee80211_free_txskb(sc->hw, skb);
968 continue;
969 }
970
971 bf->bf_next = NULL;
972 bf->bf_lastbf = bf;
973
974 tx_info = IEEE80211_SKB_CB(skb);
975 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT |
976 IEEE80211_TX_STATUS_EOSP);
977
978 /*
979 * No aggregation session is running, but there may be frames
980 * from a previous session or a failed attempt in the queue.
981 * Send them out as normal data frames
982 */
983 if (!tid->active)
984 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
985
986 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
987 bf->bf_state.bf_type = 0;
988 break;
989 }
990
991 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
992 seqno = bf->bf_state.seqno;
993
994 /* do not step over block-ack window */
995 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
996 __skb_queue_tail(&tid->retry_q, skb);
997
998 /* If there are other skbs in the retry q, they are
999 * probably within the BAW, so loop immediately to get
1000 * one of them. Otherwise the queue can get stuck. */
1001 if (!skb_queue_is_first(&tid->retry_q, skb) &&
1002 !WARN_ON(skb == first_skb)) {
1003 if(!first_skb) /* infinite loop prevention */
1004 first_skb = skb;
1005 continue;
1006 }
1007 return -EINPROGRESS;
1008 }
1009
1010 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
1011 struct ath_tx_status ts = {};
1012 struct list_head bf_head;
1013
1014 INIT_LIST_HEAD(&bf_head);
1015 list_add(&bf->list, &bf_head);
1016 ath_tx_update_baw(sc, tid, bf);
1017 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
1018 continue;
1019 }
1020
1021 if (bf_isampdu(bf))
1022 ath_tx_addto_baw(sc, tid, bf);
1023
1024 break;
1025 }
1026
1027 *buf = bf;
1028 return 0;
1029}
1030
1031static int
1032ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
1033 struct ath_atx_tid *tid, struct list_head *bf_q,
1034 struct ath_buf *bf_first)
1035{
1036#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1037 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1038 int nframes = 0, ndelim, ret;
1039 u16 aggr_limit = 0, al = 0, bpad = 0,
1040 al_delta, h_baw = tid->baw_size / 2;
1041 struct ieee80211_tx_info *tx_info;
1042 struct ath_frame_info *fi;
1043 struct sk_buff *skb;
1044
1045
1046 bf = bf_first;
1047 aggr_limit = ath_lookup_rate(sc, bf, tid);
1048
1049 while (bf)
1050 {
1051 skb = bf->bf_mpdu;
1052 fi = get_frame_info(skb);
1053
1054 /* do not exceed aggregation limit */
1055 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1056 if (nframes) {
1057 if (aggr_limit < al + bpad + al_delta ||
1058 ath_lookup_legacy(bf) || nframes >= h_baw)
1059 goto stop;
1060
1061 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1062 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1063 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1064 goto stop;
1065 }
1066
1067 /* add padding for previous frame to aggregation length */
1068 al += bpad + al_delta;
1069
1070 /*
1071 * Get the delimiters needed to meet the MPDU
1072 * density for this node.
1073 */
1074 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1075 !nframes);
1076 bpad = PADBYTES(al_delta) + (ndelim << 2);
1077
1078 nframes++;
1079 bf->bf_next = NULL;
1080
1081 /* link buffers of this frame to the aggregate */
1082 bf->bf_state.ndelim = ndelim;
1083
1084 list_add_tail(&bf->list, bf_q);
1085 if (bf_prev)
1086 bf_prev->bf_next = bf;
1087
1088 bf_prev = bf;
1089
1090 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1091 if (ret < 0)
1092 break;
1093 }
1094 goto finish;
1095stop:
1096 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1097finish:
1098 bf = bf_first;
1099 bf->bf_lastbf = bf_prev;
1100
1101 if (bf == bf_prev) {
1102 al = get_frame_info(bf->bf_mpdu)->framelen;
1103 bf->bf_state.bf_type = BUF_AMPDU;
1104 } else {
1105 TX_STAT_INC(sc, txq->axq_qnum, a_aggr);
1106 }
1107
1108 return al;
1109#undef PADBYTES
1110}
1111
1112/*
1113 * rix - rate index
1114 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1115 * width - 0 for 20 MHz, 1 for 40 MHz
1116 * half_gi - to use 4us v/s 3.6 us for symbol time
1117 */
1118u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1119 int width, int half_gi, bool shortPreamble)
1120{
1121 u32 nbits, nsymbits, duration, nsymbols;
1122 int streams;
1123
1124 /* find number of symbols: PLCP + data */
1125 streams = HT_RC_2_STREAMS(rix);
1126 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1127 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1128 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1129
1130 if (!half_gi)
1131 duration = SYMBOL_TIME(nsymbols);
1132 else
1133 duration = SYMBOL_TIME_HALFGI(nsymbols);
1134
1135 /* addup duration for legacy/ht training and signal fields */
1136 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1137
1138 return duration;
1139}
1140
1141static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1142{
1143 int streams = HT_RC_2_STREAMS(mcs);
1144 int symbols, bits;
1145 int bytes = 0;
1146
1147 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1148 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1149 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1150 bits -= OFDM_PLCP_BITS;
1151 bytes = bits / 8;
1152 if (bytes > 65532)
1153 bytes = 65532;
1154
1155 return bytes;
1156}
1157
1158void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1159{
1160 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1161 int mcs;
1162
1163 /* 4ms is the default (and maximum) duration */
1164 if (!txop || txop > 4096)
1165 txop = 4096;
1166
1167 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1168 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1169 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1170 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1171 for (mcs = 0; mcs < 32; mcs++) {
1172 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1173 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1174 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1175 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1176 }
1177}
1178
1179static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1180 u8 rateidx, bool is_40, bool is_cck, bool is_mcs)
1181{
1182 u8 max_power;
1183 struct sk_buff *skb;
1184 struct ath_frame_info *fi;
1185 struct ieee80211_tx_info *info;
1186 struct ath_hw *ah = sc->sc_ah;
1187 bool is_2ghz, is_5ghz, use_stbc;
1188
1189 if (sc->tx99_state || !ah->tpc_enabled)
1190 return MAX_RATE_POWER;
1191
1192 skb = bf->bf_mpdu;
1193 fi = get_frame_info(skb);
1194 info = IEEE80211_SKB_CB(skb);
1195
1196 is_2ghz = info->band == NL80211_BAND_2GHZ;
1197 is_5ghz = info->band == NL80211_BAND_5GHZ;
1198 use_stbc = is_mcs && rateidx < 8 && (info->flags &
1199 IEEE80211_TX_CTL_STBC);
1200
1201 if (is_mcs)
1202 rateidx += is_5ghz ? ATH9K_PWRTBL_11NA_HT_SHIFT
1203 : ATH9K_PWRTBL_11NG_HT_SHIFT;
1204 else if (is_2ghz && !is_cck)
1205 rateidx += ATH9K_PWRTBL_11NG_OFDM_SHIFT;
1206 else
1207 rateidx += ATH9K_PWRTBL_11NA_OFDM_SHIFT;
1208
1209 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1210 int txpower = fi->tx_power;
1211
1212 if (is_40) {
1213 u8 power_ht40delta;
1214 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1215 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1216
1217 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1218 struct modal_eep_header *pmodal;
1219
1220 pmodal = &eep->modalHeader[is_2ghz];
1221 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1222 } else {
1223 power_ht40delta = 2;
1224 }
1225 txpower += power_ht40delta;
1226 }
1227
1228 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1229 AR_SREV_9271(ah)) {
1230 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1231 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1232 s8 power_offset;
1233
1234 power_offset = ah->eep_ops->get_eeprom(ah,
1235 EEP_PWR_TABLE_OFFSET);
1236 txpower -= 2 * power_offset;
1237 }
1238
1239 if (OLC_FOR_AR9280_20_LATER(ah) && is_cck)
1240 txpower -= 2;
1241
1242 txpower = max(txpower, 0);
1243 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1244
1245 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1246 * max_power is set to 0, frames are transmitted at max
1247 * TX power
1248 */
1249 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1250 max_power = 1;
1251 } else if (!bf->bf_state.bfs_paprd) {
1252 if (use_stbc)
1253 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1254 fi->tx_power);
1255 else
1256 max_power = min_t(u8, ah->tx_power[rateidx],
1257 fi->tx_power);
1258 } else {
1259 max_power = ah->paprd_training_power;
1260 }
1261
1262 return max_power;
1263}
1264
1265static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1266 struct ath_tx_info *info, int len, bool rts)
1267{
1268 struct ath_hw *ah = sc->sc_ah;
1269 struct ath_common *common = ath9k_hw_common(ah);
1270 struct sk_buff *skb;
1271 struct ieee80211_tx_info *tx_info;
1272 struct ieee80211_tx_rate *rates;
1273 const struct ieee80211_rate *rate;
1274 struct ieee80211_hdr *hdr;
1275 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1276 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1277 int i;
1278 u8 rix = 0;
1279
1280 skb = bf->bf_mpdu;
1281 tx_info = IEEE80211_SKB_CB(skb);
1282 rates = bf->rates;
1283 hdr = (struct ieee80211_hdr *)skb->data;
1284
1285 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1286 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1287 info->rtscts_rate = fi->rtscts_rate;
1288
1289 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1290 bool is_40, is_sgi, is_sp, is_cck;
1291 int phy;
1292
1293 if (!rates[i].count || (rates[i].idx < 0))
1294 break;
1295
1296 rix = rates[i].idx;
1297 info->rates[i].Tries = rates[i].count;
1298
1299 /*
1300 * Handle RTS threshold for unaggregated HT frames.
1301 */
1302 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1303 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1304 unlikely(rts_thresh != (u32) -1)) {
1305 if (!rts_thresh || (len > rts_thresh))
1306 rts = true;
1307 }
1308
1309 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1310 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1311 info->flags |= ATH9K_TXDESC_RTSENA;
1312 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1313 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1314 info->flags |= ATH9K_TXDESC_CTSENA;
1315 }
1316
1317 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1318 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1319 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1320 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1321
1322 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1323 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1324 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1325
1326 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1327 /* MCS rates */
1328 info->rates[i].Rate = rix | 0x80;
1329 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1330 ah->txchainmask, info->rates[i].Rate);
1331 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1332 is_40, is_sgi, is_sp);
1333 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1334 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1335 if (rix >= 8 && fi->dyn_smps) {
1336 info->rates[i].RateFlags |=
1337 ATH9K_RATESERIES_RTS_CTS;
1338 info->flags |= ATH9K_TXDESC_CTSENA;
1339 }
1340
1341 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1342 is_40, false, true);
1343 continue;
1344 }
1345
1346 /* legacy rates */
1347 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1348 if ((tx_info->band == NL80211_BAND_2GHZ) &&
1349 !(rate->flags & IEEE80211_RATE_ERP_G))
1350 phy = WLAN_RC_PHY_CCK;
1351 else
1352 phy = WLAN_RC_PHY_OFDM;
1353
1354 info->rates[i].Rate = rate->hw_value;
1355 if (rate->hw_value_short) {
1356 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1357 info->rates[i].Rate |= rate->hw_value_short;
1358 } else {
1359 is_sp = false;
1360 }
1361
1362 if (bf->bf_state.bfs_paprd)
1363 info->rates[i].ChSel = ah->txchainmask;
1364 else
1365 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1366 ah->txchainmask, info->rates[i].Rate);
1367
1368 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1369 phy, rate->bitrate * 100, len, rix, is_sp);
1370
1371 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1372 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1373 is_cck, false);
1374 }
1375
1376 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1377 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1378 info->flags &= ~ATH9K_TXDESC_RTSENA;
1379
1380 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1381 if (info->flags & ATH9K_TXDESC_RTSENA)
1382 info->flags &= ~ATH9K_TXDESC_CTSENA;
1383}
1384
1385static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1386{
1387 struct ieee80211_hdr *hdr;
1388 enum ath9k_pkt_type htype;
1389 __le16 fc;
1390
1391 hdr = (struct ieee80211_hdr *)skb->data;
1392 fc = hdr->frame_control;
1393
1394 if (ieee80211_is_beacon(fc))
1395 htype = ATH9K_PKT_TYPE_BEACON;
1396 else if (ieee80211_is_probe_resp(fc))
1397 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1398 else if (ieee80211_is_atim(fc))
1399 htype = ATH9K_PKT_TYPE_ATIM;
1400 else if (ieee80211_is_pspoll(fc))
1401 htype = ATH9K_PKT_TYPE_PSPOLL;
1402 else
1403 htype = ATH9K_PKT_TYPE_NORMAL;
1404
1405 return htype;
1406}
1407
1408static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1409 struct ath_txq *txq, int len)
1410{
1411 struct ath_hw *ah = sc->sc_ah;
1412 struct ath_buf *bf_first = NULL;
1413 struct ath_tx_info info;
1414 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1415 bool rts = false;
1416
1417 memset(&info, 0, sizeof(info));
1418 info.is_first = true;
1419 info.is_last = true;
1420 info.qcu = txq->axq_qnum;
1421
1422 while (bf) {
1423 struct sk_buff *skb = bf->bf_mpdu;
1424 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1425 struct ath_frame_info *fi = get_frame_info(skb);
1426 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1427
1428 info.type = get_hw_packet_type(skb);
1429 if (bf->bf_next)
1430 info.link = bf->bf_next->bf_daddr;
1431 else
1432 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1433
1434 if (!bf_first) {
1435 bf_first = bf;
1436
1437 if (!sc->tx99_state)
1438 info.flags = ATH9K_TXDESC_INTREQ;
1439 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1440 txq == sc->tx.uapsdq)
1441 info.flags |= ATH9K_TXDESC_CLRDMASK;
1442
1443 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1444 info.flags |= ATH9K_TXDESC_NOACK;
1445 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1446 info.flags |= ATH9K_TXDESC_LDPC;
1447
1448 if (bf->bf_state.bfs_paprd)
1449 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1450 ATH9K_TXDESC_PAPRD_S;
1451
1452 /*
1453 * mac80211 doesn't handle RTS threshold for HT because
1454 * the decision has to be taken based on AMPDU length
1455 * and aggregation is done entirely inside ath9k.
1456 * Set the RTS/CTS flag for the first subframe based
1457 * on the threshold.
1458 */
1459 if (aggr && (bf == bf_first) &&
1460 unlikely(rts_thresh != (u32) -1)) {
1461 /*
1462 * "len" is the size of the entire AMPDU.
1463 */
1464 if (!rts_thresh || (len > rts_thresh))
1465 rts = true;
1466 }
1467
1468 if (!aggr)
1469 len = fi->framelen;
1470
1471 ath_buf_set_rate(sc, bf, &info, len, rts);
1472 }
1473
1474 info.buf_addr[0] = bf->bf_buf_addr;
1475 info.buf_len[0] = skb->len;
1476 info.pkt_len = fi->framelen;
1477 info.keyix = fi->keyix;
1478 info.keytype = fi->keytype;
1479
1480 if (aggr) {
1481 if (bf == bf_first)
1482 info.aggr = AGGR_BUF_FIRST;
1483 else if (bf == bf_first->bf_lastbf)
1484 info.aggr = AGGR_BUF_LAST;
1485 else
1486 info.aggr = AGGR_BUF_MIDDLE;
1487
1488 info.ndelim = bf->bf_state.ndelim;
1489 info.aggr_len = len;
1490 }
1491
1492 if (bf == bf_first->bf_lastbf)
1493 bf_first = NULL;
1494
1495 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1496 bf = bf->bf_next;
1497 }
1498}
1499
1500static void
1501ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1502 struct ath_atx_tid *tid, struct list_head *bf_q,
1503 struct ath_buf *bf_first)
1504{
1505 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1506 int nframes = 0, ret;
1507
1508 do {
1509 struct ieee80211_tx_info *tx_info;
1510
1511 nframes++;
1512 list_add_tail(&bf->list, bf_q);
1513 if (bf_prev)
1514 bf_prev->bf_next = bf;
1515 bf_prev = bf;
1516
1517 if (nframes >= 2)
1518 break;
1519
1520 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1521 if (ret < 0)
1522 break;
1523
1524 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1525 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1526 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1527 break;
1528 }
1529
1530 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1531 } while (1);
1532}
1533
1534static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1535 struct ath_atx_tid *tid)
1536{
1537 struct ath_buf *bf = NULL;
1538 struct ieee80211_tx_info *tx_info;
1539 struct list_head bf_q;
1540 int aggr_len = 0, ret;
1541 bool aggr;
1542
1543 INIT_LIST_HEAD(&bf_q);
1544
1545 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1546 if (ret < 0)
1547 return ret;
1548
1549 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1550 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1551 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1552 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1553 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1554 return -EBUSY;
1555 }
1556
1557 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1558 if (aggr)
1559 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1560 else
1561 ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1562
1563 if (list_empty(&bf_q))
1564 return -EAGAIN;
1565
1566 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1567 tid->clear_ps_filter = false;
1568 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1569 }
1570
1571 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1572 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1573 return 0;
1574}
1575
1576int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1577 u16 tid, u16 *ssn)
1578{
1579 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1580 struct ath_atx_tid *txtid;
1581 struct ath_txq *txq;
1582 struct ath_node *an;
1583 u8 density;
1584
1585 ath_dbg(common, XMIT, "%s called\n", __func__);
1586
1587 an = (struct ath_node *)sta->drv_priv;
1588 txtid = ATH_AN_2_TID(an, tid);
1589 txq = txtid->txq;
1590
1591 ath_txq_lock(sc, txq);
1592
1593 /* update ampdu factor/density, they may have changed. This may happen
1594 * in HT IBSS when a beacon with HT-info is received after the station
1595 * has already been added.
1596 */
1597 if (sta->deflink.ht_cap.ht_supported) {
1598 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1599 sta->deflink.ht_cap.ampdu_factor)) - 1;
1600 density = ath9k_parse_mpdudensity(sta->deflink.ht_cap.ampdu_density);
1601 an->mpdudensity = density;
1602 }
1603
1604 txtid->active = true;
1605 *ssn = txtid->seq_start = txtid->seq_next;
1606 txtid->bar_index = -1;
1607
1608 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1609 txtid->baw_head = txtid->baw_tail = 0;
1610
1611 ath_txq_unlock_complete(sc, txq);
1612
1613 return 0;
1614}
1615
1616void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1617{
1618 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1619 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1620 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1621 struct ath_txq *txq = txtid->txq;
1622
1623 ath_dbg(common, XMIT, "%s called\n", __func__);
1624
1625 ath_txq_lock(sc, txq);
1626 txtid->active = false;
1627 ath_tx_flush_tid(sc, txtid);
1628 ath_txq_unlock_complete(sc, txq);
1629}
1630
1631void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1632 struct ath_node *an)
1633{
1634 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1635 struct ath_atx_tid *tid;
1636 int tidno;
1637
1638 ath_dbg(common, XMIT, "%s called\n", __func__);
1639
1640 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1641 tid = ath_node_to_tid(an, tidno);
1642
1643 if (!skb_queue_empty(&tid->retry_q))
1644 ieee80211_sta_set_buffered(sta, tid->tidno, true);
1645
1646 }
1647}
1648
1649void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1650{
1651 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1652 struct ath_atx_tid *tid;
1653 struct ath_txq *txq;
1654 int tidno;
1655
1656 ath_dbg(common, XMIT, "%s called\n", __func__);
1657
1658 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1659 tid = ath_node_to_tid(an, tidno);
1660 txq = tid->txq;
1661
1662 ath_txq_lock(sc, txq);
1663 tid->clear_ps_filter = true;
1664 if (!skb_queue_empty(&tid->retry_q)) {
1665 ath_tx_queue_tid(sc, tid);
1666 ath_txq_schedule(sc, txq);
1667 }
1668 ath_txq_unlock_complete(sc, txq);
1669
1670 }
1671}
1672
1673
1674static void
1675ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val)
1676{
1677 struct ieee80211_hdr *hdr;
1678 u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1679 u16 mask_val = mask * val;
1680
1681 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
1682 if ((hdr->frame_control & mask) != mask_val) {
1683 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val;
1684 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1685 sizeof(*hdr), DMA_TO_DEVICE);
1686 }
1687}
1688
1689void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1690 struct ieee80211_sta *sta,
1691 u16 tids, int nframes,
1692 enum ieee80211_frame_release_type reason,
1693 bool more_data)
1694{
1695 struct ath_softc *sc = hw->priv;
1696 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1697 struct ath_txq *txq = sc->tx.uapsdq;
1698 struct ieee80211_tx_info *info;
1699 struct list_head bf_q;
1700 struct ath_buf *bf_tail = NULL, *bf = NULL;
1701 int i, ret;
1702
1703 INIT_LIST_HEAD(&bf_q);
1704 for (i = 0; tids && nframes; i++, tids >>= 1) {
1705 struct ath_atx_tid *tid;
1706
1707 if (!(tids & 1))
1708 continue;
1709
1710 tid = ATH_AN_2_TID(an, i);
1711
1712 ath_txq_lock(sc, tid->txq);
1713 while (nframes > 0) {
1714 ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq,
1715 tid, &bf);
1716 if (ret < 0)
1717 break;
1718
1719 ath9k_set_moredata(sc, bf, true);
1720 list_add_tail(&bf->list, &bf_q);
1721 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1722 if (bf_isampdu(bf))
1723 bf->bf_state.bf_type &= ~BUF_AGGR;
1724 if (bf_tail)
1725 bf_tail->bf_next = bf;
1726
1727 bf_tail = bf;
1728 nframes--;
1729 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw);
1730
1731 if (an->sta && skb_queue_empty(&tid->retry_q))
1732 ieee80211_sta_set_buffered(an->sta, i, false);
1733 }
1734 ath_txq_unlock_complete(sc, tid->txq);
1735 }
1736
1737 if (list_empty(&bf_q))
1738 return;
1739
1740 if (!more_data)
1741 ath9k_set_moredata(sc, bf_tail, false);
1742
1743 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1744 info->flags |= IEEE80211_TX_STATUS_EOSP;
1745
1746 bf = list_first_entry(&bf_q, struct ath_buf, list);
1747 ath_txq_lock(sc, txq);
1748 ath_tx_fill_desc(sc, bf, txq, 0);
1749 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1750 ath_txq_unlock(sc, txq);
1751}
1752
1753/********************/
1754/* Queue Management */
1755/********************/
1756
1757struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1758{
1759 struct ath_hw *ah = sc->sc_ah;
1760 struct ath9k_tx_queue_info qi;
1761 static const int subtype_txq_to_hwq[] = {
1762 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1763 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1764 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1765 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1766 };
1767 int axq_qnum, i;
1768
1769 memset(&qi, 0, sizeof(qi));
1770 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1771 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1772 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1773 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1774 qi.tqi_physCompBuf = 0;
1775
1776 /*
1777 * Enable interrupts only for EOL and DESC conditions.
1778 * We mark tx descriptors to receive a DESC interrupt
1779 * when a tx queue gets deep; otherwise waiting for the
1780 * EOL to reap descriptors. Note that this is done to
1781 * reduce interrupt load and this only defers reaping
1782 * descriptors, never transmitting frames. Aside from
1783 * reducing interrupts this also permits more concurrency.
1784 * The only potential downside is if the tx queue backs
1785 * up in which case the top half of the kernel may backup
1786 * due to a lack of tx descriptors.
1787 *
1788 * The UAPSD queue is an exception, since we take a desc-
1789 * based intr on the EOSP frames.
1790 */
1791 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1792 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1793 } else {
1794 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1795 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1796 else
1797 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1798 TXQ_FLAG_TXDESCINT_ENABLE;
1799 }
1800 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1801 if (axq_qnum == -1) {
1802 /*
1803 * NB: don't print a message, this happens
1804 * normally on parts with too few tx queues
1805 */
1806 return NULL;
1807 }
1808 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1809 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1810
1811 txq->axq_qnum = axq_qnum;
1812 txq->mac80211_qnum = -1;
1813 txq->axq_link = NULL;
1814 __skb_queue_head_init(&txq->complete_q);
1815 INIT_LIST_HEAD(&txq->axq_q);
1816 spin_lock_init(&txq->axq_lock);
1817 txq->axq_depth = 0;
1818 txq->axq_ampdu_depth = 0;
1819 txq->axq_tx_inprogress = false;
1820 sc->tx.txqsetup |= 1<<axq_qnum;
1821
1822 txq->txq_headidx = txq->txq_tailidx = 0;
1823 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1824 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1825 }
1826 return &sc->tx.txq[axq_qnum];
1827}
1828
1829int ath_txq_update(struct ath_softc *sc, int qnum,
1830 struct ath9k_tx_queue_info *qinfo)
1831{
1832 struct ath_hw *ah = sc->sc_ah;
1833 int error = 0;
1834 struct ath9k_tx_queue_info qi;
1835
1836 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1837
1838 ath9k_hw_get_txq_props(ah, qnum, &qi);
1839 qi.tqi_aifs = qinfo->tqi_aifs;
1840 qi.tqi_cwmin = qinfo->tqi_cwmin;
1841 qi.tqi_cwmax = qinfo->tqi_cwmax;
1842 qi.tqi_burstTime = qinfo->tqi_burstTime;
1843 qi.tqi_readyTime = qinfo->tqi_readyTime;
1844
1845 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1846 ath_err(ath9k_hw_common(sc->sc_ah),
1847 "Unable to update hardware queue %u!\n", qnum);
1848 error = -EIO;
1849 } else {
1850 ath9k_hw_resettxqueue(ah, qnum);
1851 }
1852
1853 return error;
1854}
1855
1856int ath_cabq_update(struct ath_softc *sc)
1857{
1858 struct ath9k_tx_queue_info qi;
1859 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1860 int qnum = sc->beacon.cabq->axq_qnum;
1861
1862 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1863
1864 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1865 ATH_CABQ_READY_TIME) / 100;
1866 ath_txq_update(sc, qnum, &qi);
1867
1868 return 0;
1869}
1870
1871static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1872 struct list_head *list)
1873{
1874 struct ath_buf *bf, *lastbf;
1875 struct list_head bf_head;
1876 struct ath_tx_status ts;
1877
1878 memset(&ts, 0, sizeof(ts));
1879 ts.ts_status = ATH9K_TX_FLUSH;
1880 INIT_LIST_HEAD(&bf_head);
1881
1882 while (!list_empty(list)) {
1883 bf = list_first_entry(list, struct ath_buf, list);
1884
1885 if (bf->bf_state.stale) {
1886 list_del(&bf->list);
1887
1888 ath_tx_return_buffer(sc, bf);
1889 continue;
1890 }
1891
1892 lastbf = bf->bf_lastbf;
1893 list_cut_position(&bf_head, list, &lastbf->list);
1894 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1895 }
1896}
1897
1898/*
1899 * Drain a given TX queue (could be Beacon or Data)
1900 *
1901 * This assumes output has been stopped and
1902 * we do not need to block ath_tx_tasklet.
1903 */
1904void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1905{
1906 rcu_read_lock();
1907 ath_txq_lock(sc, txq);
1908
1909 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1910 int idx = txq->txq_tailidx;
1911
1912 while (!list_empty(&txq->txq_fifo[idx])) {
1913 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1914
1915 INCR(idx, ATH_TXFIFO_DEPTH);
1916 }
1917 txq->txq_tailidx = idx;
1918 }
1919
1920 txq->axq_link = NULL;
1921 txq->axq_tx_inprogress = false;
1922 ath_drain_txq_list(sc, txq, &txq->axq_q);
1923
1924 ath_txq_unlock_complete(sc, txq);
1925 rcu_read_unlock();
1926}
1927
1928bool ath_drain_all_txq(struct ath_softc *sc)
1929{
1930 struct ath_hw *ah = sc->sc_ah;
1931 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1932 struct ath_txq *txq;
1933 int i;
1934 u32 npend = 0;
1935
1936 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1937 return true;
1938
1939 ath9k_hw_abort_tx_dma(ah);
1940
1941 /* Check if any queue remains active */
1942 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1943 if (!ATH_TXQ_SETUP(sc, i))
1944 continue;
1945
1946 if (!sc->tx.txq[i].axq_depth)
1947 continue;
1948
1949 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1950 npend |= BIT(i);
1951 }
1952
1953 if (npend) {
1954 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1955 ath_dbg(common, RESET,
1956 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1957 }
1958
1959 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1960 if (!ATH_TXQ_SETUP(sc, i))
1961 continue;
1962
1963 txq = &sc->tx.txq[i];
1964 ath_draintxq(sc, txq);
1965 }
1966
1967 return !npend;
1968}
1969
1970void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1971{
1972 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1973 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1974}
1975
1976/* For each acq entry, for each tid, try to schedule packets
1977 * for transmit until ampdu_depth has reached min Q depth.
1978 */
1979void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1980{
1981 struct ieee80211_hw *hw = sc->hw;
1982 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1983 struct ieee80211_txq *queue;
1984 struct ath_atx_tid *tid;
1985 int ret;
1986
1987 if (txq->mac80211_qnum < 0)
1988 return;
1989
1990 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1991 return;
1992
1993 ieee80211_txq_schedule_start(hw, txq->mac80211_qnum);
1994 spin_lock_bh(&sc->chan_lock);
1995 rcu_read_lock();
1996
1997 if (sc->cur_chan->stopped)
1998 goto out;
1999
2000 while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) {
2001 bool force;
2002
2003 tid = (struct ath_atx_tid *)queue->drv_priv;
2004
2005 ret = ath_tx_sched_aggr(sc, txq, tid);
2006 ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret);
2007
2008 force = !skb_queue_empty(&tid->retry_q);
2009 ieee80211_return_txq(hw, queue, force);
2010 }
2011
2012out:
2013 rcu_read_unlock();
2014 spin_unlock_bh(&sc->chan_lock);
2015 ieee80211_txq_schedule_end(hw, txq->mac80211_qnum);
2016}
2017
2018void ath_txq_schedule_all(struct ath_softc *sc)
2019{
2020 struct ath_txq *txq;
2021 int i;
2022
2023 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2024 txq = sc->tx.txq_map[i];
2025
2026 spin_lock_bh(&txq->axq_lock);
2027 ath_txq_schedule(sc, txq);
2028 spin_unlock_bh(&txq->axq_lock);
2029 }
2030}
2031
2032/***********/
2033/* TX, DMA */
2034/***********/
2035
2036/*
2037 * Insert a chain of ath_buf (descriptors) on a txq and
2038 * assume the descriptors are already chained together by caller.
2039 */
2040static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2041 struct list_head *head, bool internal)
2042{
2043 struct ath_hw *ah = sc->sc_ah;
2044 struct ath_common *common = ath9k_hw_common(ah);
2045 struct ath_buf *bf, *bf_last;
2046 bool puttxbuf = false;
2047 bool edma;
2048
2049 /*
2050 * Insert the frame on the outbound list and
2051 * pass it on to the hardware.
2052 */
2053
2054 if (list_empty(head))
2055 return;
2056
2057 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2058 bf = list_first_entry(head, struct ath_buf, list);
2059 bf_last = list_entry(head->prev, struct ath_buf, list);
2060
2061 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2062 txq->axq_qnum, txq->axq_depth);
2063
2064 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2065 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2066 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2067 puttxbuf = true;
2068 } else {
2069 list_splice_tail_init(head, &txq->axq_q);
2070
2071 if (txq->axq_link) {
2072 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2073 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2074 txq->axq_qnum, txq->axq_link,
2075 ito64(bf->bf_daddr), bf->bf_desc);
2076 } else if (!edma)
2077 puttxbuf = true;
2078
2079 txq->axq_link = bf_last->bf_desc;
2080 }
2081
2082 if (puttxbuf) {
2083 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf);
2084 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2085 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2086 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2087 }
2088
2089 if (!edma || sc->tx99_state) {
2090 TX_STAT_INC(sc, txq->axq_qnum, txstart);
2091 ath9k_hw_txstart(ah, txq->axq_qnum);
2092 }
2093
2094 if (!internal) {
2095 while (bf) {
2096 txq->axq_depth++;
2097 if (bf_is_ampdu_not_probing(bf))
2098 txq->axq_ampdu_depth++;
2099
2100 bf_last = bf->bf_lastbf;
2101 bf = bf_last->bf_next;
2102 bf_last->bf_next = NULL;
2103 }
2104 }
2105}
2106
2107static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2108 struct ath_atx_tid *tid, struct sk_buff *skb)
2109{
2110 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2111 struct ath_frame_info *fi = get_frame_info(skb);
2112 struct list_head bf_head;
2113 struct ath_buf *bf = fi->bf;
2114
2115 INIT_LIST_HEAD(&bf_head);
2116 list_add_tail(&bf->list, &bf_head);
2117 bf->bf_state.bf_type = 0;
2118 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2119 bf->bf_state.bf_type = BUF_AMPDU;
2120 ath_tx_addto_baw(sc, tid, bf);
2121 }
2122
2123 bf->bf_next = NULL;
2124 bf->bf_lastbf = bf;
2125 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2126 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2127 TX_STAT_INC(sc, txq->axq_qnum, queued);
2128}
2129
2130static void setup_frame_info(struct ieee80211_hw *hw,
2131 struct ieee80211_sta *sta,
2132 struct sk_buff *skb,
2133 int framelen)
2134{
2135 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2136 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2137 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2138 const struct ieee80211_rate *rate;
2139 struct ath_frame_info *fi = get_frame_info(skb);
2140 struct ath_node *an = NULL;
2141 enum ath9k_key_type keytype;
2142 bool short_preamble = false;
2143 u8 txpower;
2144
2145 /*
2146 * We check if Short Preamble is needed for the CTS rate by
2147 * checking the BSS's global flag.
2148 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2149 */
2150 if (tx_info->control.vif &&
2151 tx_info->control.vif->bss_conf.use_short_preamble)
2152 short_preamble = true;
2153
2154 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2155 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2156
2157 if (sta)
2158 an = (struct ath_node *) sta->drv_priv;
2159
2160 if (tx_info->control.vif) {
2161 struct ieee80211_vif *vif = tx_info->control.vif;
2162 if (vif->bss_conf.txpower == INT_MIN)
2163 goto nonvifpower;
2164 txpower = 2 * vif->bss_conf.txpower;
2165 } else {
2166 struct ath_softc *sc;
2167 nonvifpower:
2168 sc = hw->priv;
2169
2170 txpower = sc->cur_chan->cur_txpower;
2171 }
2172
2173 memset(fi, 0, sizeof(*fi));
2174 fi->txq = -1;
2175 if (hw_key)
2176 fi->keyix = hw_key->hw_key_idx;
2177 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2178 fi->keyix = an->ps_key;
2179 else
2180 fi->keyix = ATH9K_TXKEYIX_INVALID;
2181 fi->dyn_smps = sta && sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC;
2182 fi->keytype = keytype;
2183 fi->framelen = framelen;
2184 fi->tx_power = txpower;
2185
2186 if (!rate)
2187 return;
2188 fi->rtscts_rate = rate->hw_value;
2189 if (short_preamble)
2190 fi->rtscts_rate |= rate->hw_value_short;
2191}
2192
2193u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2194{
2195 struct ath_hw *ah = sc->sc_ah;
2196 struct ath9k_channel *curchan = ah->curchan;
2197
2198 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2199 (chainmask == 0x7) && (rate < 0x90))
2200 return 0x3;
2201 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2202 IS_CCK_RATE(rate))
2203 return 0x2;
2204 else
2205 return chainmask;
2206}
2207
2208/*
2209 * Assign a descriptor (and sequence number if necessary,
2210 * and map buffer for DMA. Frees skb on error
2211 */
2212static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2213 struct ath_txq *txq,
2214 struct ath_atx_tid *tid,
2215 struct sk_buff *skb)
2216{
2217 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2218 struct ath_frame_info *fi = get_frame_info(skb);
2219 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2220 struct ath_buf *bf;
2221 int fragno;
2222 u16 seqno;
2223
2224 bf = ath_tx_get_buffer(sc);
2225 if (!bf) {
2226 ath_dbg(common, XMIT, "TX buffers are full\n");
2227 return NULL;
2228 }
2229
2230 ATH_TXBUF_RESET(bf);
2231
2232 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2233 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2234 seqno = tid->seq_next;
2235 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2236
2237 if (fragno)
2238 hdr->seq_ctrl |= cpu_to_le16(fragno);
2239
2240 if (!ieee80211_has_morefrags(hdr->frame_control))
2241 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2242
2243 bf->bf_state.seqno = seqno;
2244 }
2245
2246 bf->bf_mpdu = skb;
2247
2248 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2249 skb->len, DMA_TO_DEVICE);
2250 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2251 bf->bf_mpdu = NULL;
2252 bf->bf_buf_addr = 0;
2253 ath_err(ath9k_hw_common(sc->sc_ah),
2254 "dma_mapping_error() on TX\n");
2255 ath_tx_return_buffer(sc, bf);
2256 return NULL;
2257 }
2258
2259 fi->bf = bf;
2260
2261 return bf;
2262}
2263
2264void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2265{
2266 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2267 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2268 struct ieee80211_vif *vif = info->control.vif;
2269 struct ath_vif *avp;
2270
2271 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2272 return;
2273
2274 if (!vif)
2275 return;
2276
2277 avp = (struct ath_vif *)vif->drv_priv;
2278
2279 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2280 avp->seq_no += 0x10;
2281
2282 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2283 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2284}
2285
2286static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2287 struct ath_tx_control *txctl)
2288{
2289 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2290 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2291 struct ieee80211_sta *sta = txctl->sta;
2292 struct ieee80211_vif *vif = info->control.vif;
2293 struct ath_vif *avp;
2294 struct ath_softc *sc = hw->priv;
2295 int frmlen = skb->len + FCS_LEN;
2296 int padpos, padsize;
2297
2298 /* NOTE: sta can be NULL according to net/mac80211.h */
2299 if (sta)
2300 txctl->an = (struct ath_node *)sta->drv_priv;
2301 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2302 avp = (void *)vif->drv_priv;
2303 txctl->an = &avp->mcast_node;
2304 }
2305
2306 if (info->control.hw_key)
2307 frmlen += info->control.hw_key->icv_len;
2308
2309 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2310
2311 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2312 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2313 !ieee80211_is_data(hdr->frame_control))
2314 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2315
2316 /* Add the padding after the header if this is not already done */
2317 padpos = ieee80211_hdrlen(hdr->frame_control);
2318 padsize = padpos & 3;
2319 if (padsize && skb->len > padpos) {
2320 if (skb_headroom(skb) < padsize)
2321 return -ENOMEM;
2322
2323 skb_push(skb, padsize);
2324 memmove(skb->data, skb->data + padsize, padpos);
2325 }
2326
2327 setup_frame_info(hw, sta, skb, frmlen);
2328 return 0;
2329}
2330
2331
2332/* Upon failure caller should free skb */
2333int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2334 struct ath_tx_control *txctl)
2335{
2336 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2337 struct ieee80211_sta *sta = txctl->sta;
2338 struct ieee80211_vif *vif = info->control.vif;
2339 struct ath_frame_info *fi = get_frame_info(skb);
2340 struct ath_softc *sc = hw->priv;
2341 struct ath_txq *txq = txctl->txq;
2342 struct ath_atx_tid *tid = NULL;
2343 struct ath_node *an = NULL;
2344 struct ath_buf *bf;
2345 bool ps_resp;
2346 int q, ret;
2347
2348 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2349
2350 ret = ath_tx_prepare(hw, skb, txctl);
2351 if (ret)
2352 return ret;
2353
2354 /*
2355 * At this point, the vif, hw_key and sta pointers in the tx control
2356 * info are no longer valid (overwritten by the ath_frame_info data.
2357 */
2358
2359 q = skb_get_queue_mapping(skb);
2360
2361 if (ps_resp)
2362 txq = sc->tx.uapsdq;
2363
2364 if (txctl->sta) {
2365 an = (struct ath_node *) sta->drv_priv;
2366 tid = ath_get_skb_tid(sc, an, skb);
2367 }
2368
2369 ath_txq_lock(sc, txq);
2370 if (txq == sc->tx.txq_map[q]) {
2371 fi->txq = q;
2372 ++txq->pending_frames;
2373 }
2374
2375 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2376 if (!bf) {
2377 ath_txq_skb_done(sc, txq, skb);
2378 if (txctl->paprd)
2379 dev_kfree_skb_any(skb);
2380 else
2381 ieee80211_free_txskb(sc->hw, skb);
2382 goto out;
2383 }
2384
2385 bf->bf_state.bfs_paprd = txctl->paprd;
2386
2387 if (txctl->paprd)
2388 bf->bf_state.bfs_paprd_timestamp = jiffies;
2389
2390 ath_set_rates(vif, sta, bf);
2391 ath_tx_send_normal(sc, txq, tid, skb);
2392
2393out:
2394 ath_txq_unlock(sc, txq);
2395
2396 return 0;
2397}
2398
2399void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2400 struct sk_buff *skb)
2401{
2402 struct ath_softc *sc = hw->priv;
2403 struct ath_tx_control txctl = {
2404 .txq = sc->beacon.cabq
2405 };
2406 struct ath_tx_info info = {};
2407 struct ath_buf *bf_tail = NULL;
2408 struct ath_buf *bf;
2409 LIST_HEAD(bf_q);
2410 int duration = 0;
2411 int max_duration;
2412
2413 max_duration =
2414 sc->cur_chan->beacon.beacon_interval * 1000 *
2415 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2416
2417 do {
2418 struct ath_frame_info *fi = get_frame_info(skb);
2419
2420 if (ath_tx_prepare(hw, skb, &txctl))
2421 break;
2422
2423 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2424 if (!bf)
2425 break;
2426
2427 bf->bf_lastbf = bf;
2428 ath_set_rates(vif, NULL, bf);
2429 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2430 duration += info.rates[0].PktDuration;
2431 if (bf_tail)
2432 bf_tail->bf_next = bf;
2433
2434 list_add_tail(&bf->list, &bf_q);
2435 bf_tail = bf;
2436 skb = NULL;
2437
2438 if (duration > max_duration)
2439 break;
2440
2441 skb = ieee80211_get_buffered_bc(hw, vif);
2442 } while(skb);
2443
2444 if (skb)
2445 ieee80211_free_txskb(hw, skb);
2446
2447 if (list_empty(&bf_q))
2448 return;
2449
2450 bf = list_last_entry(&bf_q, struct ath_buf, list);
2451 ath9k_set_moredata(sc, bf, false);
2452
2453 bf = list_first_entry(&bf_q, struct ath_buf, list);
2454 ath_txq_lock(sc, txctl.txq);
2455 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2456 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2457 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued);
2458 ath_txq_unlock(sc, txctl.txq);
2459}
2460
2461/*****************/
2462/* TX Completion */
2463/*****************/
2464
2465static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2466 int tx_flags, struct ath_txq *txq,
2467 struct ieee80211_sta *sta)
2468{
2469 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2470 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2471 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2472 int padpos, padsize;
2473 unsigned long flags;
2474
2475 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2476
2477 if (sc->sc_ah->caldata)
2478 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2479
2480 if (!(tx_flags & ATH_TX_ERROR)) {
2481 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2482 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2483 else
2484 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2485 }
2486
2487 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2488 padpos = ieee80211_hdrlen(hdr->frame_control);
2489 padsize = padpos & 3;
2490 if (padsize && skb->len>padpos+padsize) {
2491 /*
2492 * Remove MAC header padding before giving the frame back to
2493 * mac80211.
2494 */
2495 memmove(skb->data + padsize, skb->data, padpos);
2496 skb_pull(skb, padsize);
2497 }
2498 }
2499
2500 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2501 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2502 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2503 ath_dbg(common, PS,
2504 "Going back to sleep after having received TX status (0x%lx)\n",
2505 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2506 PS_WAIT_FOR_CAB |
2507 PS_WAIT_FOR_PSPOLL_DATA |
2508 PS_WAIT_FOR_TX_ACK));
2509 }
2510 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2511
2512 ath_txq_skb_done(sc, txq, skb);
2513 tx_info->status.status_driver_data[0] = sta;
2514 __skb_queue_tail(&txq->complete_q, skb);
2515}
2516
2517static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2518 struct ath_txq *txq, struct list_head *bf_q,
2519 struct ieee80211_sta *sta,
2520 struct ath_tx_status *ts, int txok)
2521{
2522 struct sk_buff *skb = bf->bf_mpdu;
2523 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2524 unsigned long flags;
2525 int tx_flags = 0;
2526
2527 if (!txok)
2528 tx_flags |= ATH_TX_ERROR;
2529
2530 if (ts->ts_status & ATH9K_TXERR_FILT)
2531 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2532
2533 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2534 bf->bf_buf_addr = 0;
2535 if (sc->tx99_state)
2536 goto skip_tx_complete;
2537
2538 if (bf->bf_state.bfs_paprd) {
2539 if (time_after(jiffies,
2540 bf->bf_state.bfs_paprd_timestamp +
2541 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2542 dev_kfree_skb_any(skb);
2543 else
2544 complete(&sc->paprd_complete);
2545 } else {
2546 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2547 ath_tx_complete(sc, skb, tx_flags, txq, sta);
2548 }
2549skip_tx_complete:
2550 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2551 * accidentally reference it later.
2552 */
2553 bf->bf_mpdu = NULL;
2554
2555 /*
2556 * Return the list of ath_buf of this mpdu to free queue
2557 */
2558 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2559 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2560 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2561}
2562
2563static void ath_clear_tx_status(struct ieee80211_tx_info *tx_info)
2564{
2565 void *ptr = &tx_info->status;
2566
2567 memset(ptr + sizeof(tx_info->status.rates), 0,
2568 sizeof(tx_info->status) -
2569 sizeof(tx_info->status.rates) -
2570 sizeof(tx_info->status.status_driver_data));
2571}
2572
2573static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2574 struct ath_tx_status *ts, int nframes, int nbad,
2575 int txok)
2576{
2577 struct sk_buff *skb = bf->bf_mpdu;
2578 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2579 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2580 struct ieee80211_hw *hw = sc->hw;
2581 struct ath_hw *ah = sc->sc_ah;
2582 u8 i, tx_rateindex;
2583
2584 ath_clear_tx_status(tx_info);
2585
2586 if (txok)
2587 tx_info->status.ack_signal = ts->ts_rssi;
2588
2589 tx_rateindex = ts->ts_rateindex;
2590 WARN_ON(tx_rateindex >= hw->max_rates);
2591
2592 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2593 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2594
2595 BUG_ON(nbad > nframes);
2596 }
2597 tx_info->status.ampdu_len = nframes;
2598 tx_info->status.ampdu_ack_len = nframes - nbad;
2599
2600 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2601
2602 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2603 tx_info->status.rates[i].count = 0;
2604 tx_info->status.rates[i].idx = -1;
2605 }
2606
2607 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2608 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2609 /*
2610 * If an underrun error is seen assume it as an excessive
2611 * retry only if max frame trigger level has been reached
2612 * (2 KB for single stream, and 4 KB for dual stream).
2613 * Adjust the long retry as if the frame was tried
2614 * hw->max_rate_tries times to affect how rate control updates
2615 * PER for the failed rate.
2616 * In case of congestion on the bus penalizing this type of
2617 * underruns should help hardware actually transmit new frames
2618 * successfully by eventually preferring slower rates.
2619 * This itself should also alleviate congestion on the bus.
2620 */
2621 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2622 ATH9K_TX_DELIM_UNDERRUN)) &&
2623 ieee80211_is_data(hdr->frame_control) &&
2624 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2625 tx_info->status.rates[tx_rateindex].count =
2626 hw->max_rate_tries;
2627 }
2628}
2629
2630static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2631{
2632 struct ath_hw *ah = sc->sc_ah;
2633 struct ath_common *common = ath9k_hw_common(ah);
2634 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2635 struct list_head bf_head;
2636 struct ath_desc *ds;
2637 struct ath_tx_status ts;
2638 int status;
2639
2640 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2641 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2642 txq->axq_link);
2643
2644 ath_txq_lock(sc, txq);
2645 for (;;) {
2646 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2647 break;
2648
2649 if (list_empty(&txq->axq_q)) {
2650 txq->axq_link = NULL;
2651 ath_txq_schedule(sc, txq);
2652 break;
2653 }
2654 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2655
2656 /*
2657 * There is a race condition that a BH gets scheduled
2658 * after sw writes TxE and before hw re-load the last
2659 * descriptor to get the newly chained one.
2660 * Software must keep the last DONE descriptor as a
2661 * holding descriptor - software does so by marking
2662 * it with the STALE flag.
2663 */
2664 bf_held = NULL;
2665 if (bf->bf_state.stale) {
2666 bf_held = bf;
2667 if (list_is_last(&bf_held->list, &txq->axq_q))
2668 break;
2669
2670 bf = list_entry(bf_held->list.next, struct ath_buf,
2671 list);
2672 }
2673
2674 lastbf = bf->bf_lastbf;
2675 ds = lastbf->bf_desc;
2676
2677 memset(&ts, 0, sizeof(ts));
2678 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2679 if (status == -EINPROGRESS)
2680 break;
2681
2682 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2683
2684 /*
2685 * Remove ath_buf's of the same transmit unit from txq,
2686 * however leave the last descriptor back as the holding
2687 * descriptor for hw.
2688 */
2689 lastbf->bf_state.stale = true;
2690 INIT_LIST_HEAD(&bf_head);
2691 if (!list_is_singular(&lastbf->list))
2692 list_cut_position(&bf_head,
2693 &txq->axq_q, lastbf->list.prev);
2694
2695 if (bf_held) {
2696 list_del(&bf_held->list);
2697 ath_tx_return_buffer(sc, bf_held);
2698 }
2699
2700 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2701 }
2702 ath_txq_unlock_complete(sc, txq);
2703}
2704
2705void ath_tx_tasklet(struct ath_softc *sc)
2706{
2707 struct ath_hw *ah = sc->sc_ah;
2708 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2709 int i;
2710
2711 rcu_read_lock();
2712 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2713 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2714 ath_tx_processq(sc, &sc->tx.txq[i]);
2715 }
2716 rcu_read_unlock();
2717}
2718
2719void ath_tx_edma_tasklet(struct ath_softc *sc)
2720{
2721 struct ath_tx_status ts;
2722 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2723 struct ath_hw *ah = sc->sc_ah;
2724 struct ath_txq *txq;
2725 struct ath_buf *bf, *lastbf;
2726 struct list_head bf_head;
2727 struct list_head *fifo_list;
2728 int status;
2729
2730 rcu_read_lock();
2731 for (;;) {
2732 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2733 break;
2734
2735 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2736 if (status == -EINPROGRESS)
2737 break;
2738 if (status == -EIO) {
2739 ath_dbg(common, XMIT, "Error processing tx status\n");
2740 break;
2741 }
2742
2743 /* Process beacon completions separately */
2744 if (ts.qid == sc->beacon.beaconq) {
2745 sc->beacon.tx_processed = true;
2746 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2747
2748 if (ath9k_is_chanctx_enabled()) {
2749 ath_chanctx_event(sc, NULL,
2750 ATH_CHANCTX_EVENT_BEACON_SENT);
2751 }
2752
2753 ath9k_csa_update(sc);
2754 continue;
2755 }
2756
2757 txq = &sc->tx.txq[ts.qid];
2758
2759 ath_txq_lock(sc, txq);
2760
2761 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2762
2763 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2764 if (list_empty(fifo_list)) {
2765 ath_txq_unlock(sc, txq);
2766 break;
2767 }
2768
2769 bf = list_first_entry(fifo_list, struct ath_buf, list);
2770 if (bf->bf_state.stale) {
2771 list_del(&bf->list);
2772 ath_tx_return_buffer(sc, bf);
2773 bf = list_first_entry(fifo_list, struct ath_buf, list);
2774 }
2775
2776 lastbf = bf->bf_lastbf;
2777
2778 INIT_LIST_HEAD(&bf_head);
2779 if (list_is_last(&lastbf->list, fifo_list)) {
2780 list_splice_tail_init(fifo_list, &bf_head);
2781 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2782
2783 if (!list_empty(&txq->axq_q)) {
2784 struct list_head bf_q;
2785
2786 INIT_LIST_HEAD(&bf_q);
2787 txq->axq_link = NULL;
2788 list_splice_tail_init(&txq->axq_q, &bf_q);
2789 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2790 }
2791 } else {
2792 lastbf->bf_state.stale = true;
2793 if (bf != lastbf)
2794 list_cut_position(&bf_head, fifo_list,
2795 lastbf->list.prev);
2796 }
2797
2798 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2799 ath_txq_unlock_complete(sc, txq);
2800 }
2801 rcu_read_unlock();
2802}
2803
2804/*****************/
2805/* Init, Cleanup */
2806/*****************/
2807
2808static int ath_txstatus_setup(struct ath_softc *sc, int size)
2809{
2810 struct ath_descdma *dd = &sc->txsdma;
2811 u8 txs_len = sc->sc_ah->caps.txs_len;
2812
2813 dd->dd_desc_len = size * txs_len;
2814 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2815 &dd->dd_desc_paddr, GFP_KERNEL);
2816 if (!dd->dd_desc)
2817 return -ENOMEM;
2818
2819 return 0;
2820}
2821
2822static int ath_tx_edma_init(struct ath_softc *sc)
2823{
2824 int err;
2825
2826 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2827 if (!err)
2828 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2829 sc->txsdma.dd_desc_paddr,
2830 ATH_TXSTATUS_RING_SIZE);
2831
2832 return err;
2833}
2834
2835int ath_tx_init(struct ath_softc *sc, int nbufs)
2836{
2837 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2838 int error = 0;
2839
2840 spin_lock_init(&sc->tx.txbuflock);
2841
2842 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2843 "tx", nbufs, 1, 1);
2844 if (error != 0) {
2845 ath_err(common,
2846 "Failed to allocate tx descriptors: %d\n", error);
2847 return error;
2848 }
2849
2850 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2851 "beacon", ATH_BCBUF, 1, 1);
2852 if (error != 0) {
2853 ath_err(common,
2854 "Failed to allocate beacon descriptors: %d\n", error);
2855 return error;
2856 }
2857
2858 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2859 error = ath_tx_edma_init(sc);
2860
2861 return error;
2862}
2863
2864void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2865{
2866 struct ath_atx_tid *tid;
2867 int tidno, acno;
2868
2869 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2870 tid = ath_node_to_tid(an, tidno);
2871 tid->an = an;
2872 tid->tidno = tidno;
2873 tid->seq_start = tid->seq_next = 0;
2874 tid->baw_size = WME_MAX_BA;
2875 tid->baw_head = tid->baw_tail = 0;
2876 tid->active = false;
2877 tid->clear_ps_filter = true;
2878 __skb_queue_head_init(&tid->retry_q);
2879 INIT_LIST_HEAD(&tid->list);
2880 acno = TID_TO_WME_AC(tidno);
2881 tid->txq = sc->tx.txq_map[acno];
2882
2883 if (!an->sta)
2884 break; /* just one multicast ath_atx_tid */
2885 }
2886}
2887
2888void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2889{
2890 struct ath_atx_tid *tid;
2891 struct ath_txq *txq;
2892 int tidno;
2893
2894 rcu_read_lock();
2895
2896 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2897 tid = ath_node_to_tid(an, tidno);
2898 txq = tid->txq;
2899
2900 ath_txq_lock(sc, txq);
2901
2902 if (!list_empty(&tid->list))
2903 list_del_init(&tid->list);
2904
2905 ath_tid_drain(sc, txq, tid);
2906 tid->active = false;
2907
2908 ath_txq_unlock(sc, txq);
2909
2910 if (!an->sta)
2911 break; /* just one multicast ath_atx_tid */
2912 }
2913
2914 rcu_read_unlock();
2915}
2916
2917#ifdef CONFIG_ATH9K_TX99
2918
2919int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2920 struct ath_tx_control *txctl)
2921{
2922 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2923 struct ath_frame_info *fi = get_frame_info(skb);
2924 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2925 struct ath_buf *bf;
2926 int padpos, padsize;
2927
2928 padpos = ieee80211_hdrlen(hdr->frame_control);
2929 padsize = padpos & 3;
2930
2931 if (padsize && skb->len > padpos) {
2932 if (skb_headroom(skb) < padsize) {
2933 ath_dbg(common, XMIT,
2934 "tx99 padding failed\n");
2935 return -EINVAL;
2936 }
2937
2938 skb_push(skb, padsize);
2939 memmove(skb->data, skb->data + padsize, padpos);
2940 }
2941
2942 fi->keyix = ATH9K_TXKEYIX_INVALID;
2943 fi->framelen = skb->len + FCS_LEN;
2944 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2945
2946 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2947 if (!bf) {
2948 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2949 return -EINVAL;
2950 }
2951
2952 ath_set_rates(sc->tx99_vif, NULL, bf);
2953
2954 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2955 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2956
2957 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2958
2959 return 0;
2960}
2961
2962#endif /* CONFIG_ATH9K_TX99 */
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/dma-mapping.h>
18#include "ath9k.h"
19#include "ar9003_mac.h"
20
21#define BITS_PER_BYTE 8
22#define OFDM_PLCP_BITS 22
23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24#define L_STF 8
25#define L_LTF 8
26#define L_SIG 4
27#define HT_SIG 8
28#define HT_STF 4
29#define HT_LTF(_ns) (4 * (_ns))
30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32#define TIME_SYMBOLS(t) ((t) >> 2)
33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38static u16 bits_per_symbol[][2] = {
39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
48};
49
50static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok);
62static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
65 struct ath_txq *txq,
66 struct ath_atx_tid *tid,
67 struct sk_buff *skb);
68
69enum {
70 MCS_HT20,
71 MCS_HT20_SGI,
72 MCS_HT40,
73 MCS_HT40_SGI,
74};
75
76/*********************/
77/* Aggregation logic */
78/*********************/
79
80void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
81 __acquires(&txq->axq_lock)
82{
83 spin_lock_bh(&txq->axq_lock);
84}
85
86void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
87 __releases(&txq->axq_lock)
88{
89 spin_unlock_bh(&txq->axq_lock);
90}
91
92void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
93 __releases(&txq->axq_lock)
94{
95 struct sk_buff_head q;
96 struct sk_buff *skb;
97
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
101
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
104}
105
106static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq,
107 struct ath_atx_tid *tid)
108{
109 struct list_head *list;
110 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
111 struct ath_chanctx *ctx = avp->chanctx;
112
113 if (!ctx)
114 return;
115
116 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
117 if (list_empty(&tid->list))
118 list_add_tail(&tid->list, list);
119}
120
121static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
122{
123 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
124 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
125 sizeof(tx_info->rate_driver_data));
126 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
127}
128
129static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
130{
131 if (!tid->an->sta)
132 return;
133
134 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
135 seqno << IEEE80211_SEQ_SEQ_SHIFT);
136}
137
138static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
139 struct ath_buf *bf)
140{
141 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
142 ARRAY_SIZE(bf->rates));
143}
144
145static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
146 struct sk_buff *skb)
147{
148 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
149 struct ath_frame_info *fi = get_frame_info(skb);
150 int q = fi->txq;
151
152 if (q < 0)
153 return;
154
155 txq = sc->tx.txq_map[q];
156 if (WARN_ON(--txq->pending_frames < 0))
157 txq->pending_frames = 0;
158
159 if (txq->stopped &&
160 txq->pending_frames < sc->tx.txq_max_pending[q]) {
161 if (ath9k_is_chanctx_enabled())
162 ieee80211_wake_queue(sc->hw, info->hw_queue);
163 else
164 ieee80211_wake_queue(sc->hw, q);
165 txq->stopped = false;
166 }
167}
168
169static struct ath_atx_tid *
170ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
171{
172 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
173 return ATH_AN_2_TID(an, tidno);
174}
175
176static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
177{
178 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
179}
180
181static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
182{
183 struct sk_buff *skb;
184
185 skb = __skb_dequeue(&tid->retry_q);
186 if (!skb)
187 skb = __skb_dequeue(&tid->buf_q);
188
189 return skb;
190}
191
192/*
193 * ath_tx_tid_change_state:
194 * - clears a-mpdu flag of previous session
195 * - force sequence number allocation to fix next BlockAck Window
196 */
197static void
198ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
199{
200 struct ath_txq *txq = tid->txq;
201 struct ieee80211_tx_info *tx_info;
202 struct sk_buff *skb, *tskb;
203 struct ath_buf *bf;
204 struct ath_frame_info *fi;
205
206 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
207 fi = get_frame_info(skb);
208 bf = fi->bf;
209
210 tx_info = IEEE80211_SKB_CB(skb);
211 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
212
213 if (bf)
214 continue;
215
216 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
217 if (!bf) {
218 __skb_unlink(skb, &tid->buf_q);
219 ath_txq_skb_done(sc, txq, skb);
220 ieee80211_free_txskb(sc->hw, skb);
221 continue;
222 }
223 }
224
225}
226
227static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
228{
229 struct ath_txq *txq = tid->txq;
230 struct sk_buff *skb;
231 struct ath_buf *bf;
232 struct list_head bf_head;
233 struct ath_tx_status ts;
234 struct ath_frame_info *fi;
235 bool sendbar = false;
236
237 INIT_LIST_HEAD(&bf_head);
238
239 memset(&ts, 0, sizeof(ts));
240
241 while ((skb = __skb_dequeue(&tid->retry_q))) {
242 fi = get_frame_info(skb);
243 bf = fi->bf;
244 if (!bf) {
245 ath_txq_skb_done(sc, txq, skb);
246 ieee80211_free_txskb(sc->hw, skb);
247 continue;
248 }
249
250 if (fi->baw_tracked) {
251 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
252 sendbar = true;
253 }
254
255 list_add_tail(&bf->list, &bf_head);
256 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
257 }
258
259 if (sendbar) {
260 ath_txq_unlock(sc, txq);
261 ath_send_bar(tid, tid->seq_start);
262 ath_txq_lock(sc, txq);
263 }
264}
265
266static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
267 int seqno)
268{
269 int index, cindex;
270
271 index = ATH_BA_INDEX(tid->seq_start, seqno);
272 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
273
274 __clear_bit(cindex, tid->tx_buf);
275
276 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
277 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
278 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
279 if (tid->bar_index >= 0)
280 tid->bar_index--;
281 }
282}
283
284static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
285 struct ath_buf *bf)
286{
287 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
288 u16 seqno = bf->bf_state.seqno;
289 int index, cindex;
290
291 index = ATH_BA_INDEX(tid->seq_start, seqno);
292 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
293 __set_bit(cindex, tid->tx_buf);
294 fi->baw_tracked = 1;
295
296 if (index >= ((tid->baw_tail - tid->baw_head) &
297 (ATH_TID_MAX_BUFS - 1))) {
298 tid->baw_tail = cindex;
299 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
300 }
301}
302
303static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
304 struct ath_atx_tid *tid)
305
306{
307 struct sk_buff *skb;
308 struct ath_buf *bf;
309 struct list_head bf_head;
310 struct ath_tx_status ts;
311 struct ath_frame_info *fi;
312
313 memset(&ts, 0, sizeof(ts));
314 INIT_LIST_HEAD(&bf_head);
315
316 while ((skb = ath_tid_dequeue(tid))) {
317 fi = get_frame_info(skb);
318 bf = fi->bf;
319
320 if (!bf) {
321 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
322 continue;
323 }
324
325 list_add_tail(&bf->list, &bf_head);
326 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
327 }
328}
329
330static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
331 struct sk_buff *skb, int count)
332{
333 struct ath_frame_info *fi = get_frame_info(skb);
334 struct ath_buf *bf = fi->bf;
335 struct ieee80211_hdr *hdr;
336 int prev = fi->retries;
337
338 TX_STAT_INC(txq->axq_qnum, a_retries);
339 fi->retries += count;
340
341 if (prev > 0)
342 return;
343
344 hdr = (struct ieee80211_hdr *)skb->data;
345 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
346 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
347 sizeof(*hdr), DMA_TO_DEVICE);
348}
349
350static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
351{
352 struct ath_buf *bf = NULL;
353
354 spin_lock_bh(&sc->tx.txbuflock);
355
356 if (unlikely(list_empty(&sc->tx.txbuf))) {
357 spin_unlock_bh(&sc->tx.txbuflock);
358 return NULL;
359 }
360
361 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
362 list_del(&bf->list);
363
364 spin_unlock_bh(&sc->tx.txbuflock);
365
366 return bf;
367}
368
369static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
370{
371 spin_lock_bh(&sc->tx.txbuflock);
372 list_add_tail(&bf->list, &sc->tx.txbuf);
373 spin_unlock_bh(&sc->tx.txbuflock);
374}
375
376static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
377{
378 struct ath_buf *tbf;
379
380 tbf = ath_tx_get_buffer(sc);
381 if (WARN_ON(!tbf))
382 return NULL;
383
384 ATH_TXBUF_RESET(tbf);
385
386 tbf->bf_mpdu = bf->bf_mpdu;
387 tbf->bf_buf_addr = bf->bf_buf_addr;
388 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
389 tbf->bf_state = bf->bf_state;
390 tbf->bf_state.stale = false;
391
392 return tbf;
393}
394
395static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
396 struct ath_tx_status *ts, int txok,
397 int *nframes, int *nbad)
398{
399 struct ath_frame_info *fi;
400 u16 seq_st = 0;
401 u32 ba[WME_BA_BMP_SIZE >> 5];
402 int ba_index;
403 int isaggr = 0;
404
405 *nbad = 0;
406 *nframes = 0;
407
408 isaggr = bf_isaggr(bf);
409 if (isaggr) {
410 seq_st = ts->ts_seqnum;
411 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
412 }
413
414 while (bf) {
415 fi = get_frame_info(bf->bf_mpdu);
416 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
417
418 (*nframes)++;
419 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
420 (*nbad)++;
421
422 bf = bf->bf_next;
423 }
424}
425
426
427static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
428 struct ath_buf *bf, struct list_head *bf_q,
429 struct ath_tx_status *ts, int txok)
430{
431 struct ath_node *an = NULL;
432 struct sk_buff *skb;
433 struct ieee80211_sta *sta;
434 struct ieee80211_hw *hw = sc->hw;
435 struct ieee80211_hdr *hdr;
436 struct ieee80211_tx_info *tx_info;
437 struct ath_atx_tid *tid = NULL;
438 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
439 struct list_head bf_head;
440 struct sk_buff_head bf_pending;
441 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
442 u32 ba[WME_BA_BMP_SIZE >> 5];
443 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
444 bool rc_update = true, isba;
445 struct ieee80211_tx_rate rates[4];
446 struct ath_frame_info *fi;
447 int nframes;
448 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
449 int i, retries;
450 int bar_index = -1;
451
452 skb = bf->bf_mpdu;
453 hdr = (struct ieee80211_hdr *)skb->data;
454
455 tx_info = IEEE80211_SKB_CB(skb);
456
457 memcpy(rates, bf->rates, sizeof(rates));
458
459 retries = ts->ts_longretry + 1;
460 for (i = 0; i < ts->ts_rateindex; i++)
461 retries += rates[i].count;
462
463 rcu_read_lock();
464
465 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
466 if (!sta) {
467 rcu_read_unlock();
468
469 INIT_LIST_HEAD(&bf_head);
470 while (bf) {
471 bf_next = bf->bf_next;
472
473 if (!bf->bf_state.stale || bf_next != NULL)
474 list_move_tail(&bf->list, &bf_head);
475
476 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
477
478 bf = bf_next;
479 }
480 return;
481 }
482
483 an = (struct ath_node *)sta->drv_priv;
484 tid = ath_get_skb_tid(sc, an, skb);
485 seq_first = tid->seq_start;
486 isba = ts->ts_flags & ATH9K_TX_BA;
487
488 /*
489 * The hardware occasionally sends a tx status for the wrong TID.
490 * In this case, the BA status cannot be considered valid and all
491 * subframes need to be retransmitted
492 *
493 * Only BlockAcks have a TID and therefore normal Acks cannot be
494 * checked
495 */
496 if (isba && tid->tidno != ts->tid)
497 txok = false;
498
499 isaggr = bf_isaggr(bf);
500 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
501
502 if (isaggr && txok) {
503 if (ts->ts_flags & ATH9K_TX_BA) {
504 seq_st = ts->ts_seqnum;
505 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
506 } else {
507 /*
508 * AR5416 can become deaf/mute when BA
509 * issue happens. Chip needs to be reset.
510 * But AP code may have sychronization issues
511 * when perform internal reset in this routine.
512 * Only enable reset in STA mode for now.
513 */
514 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
515 needreset = 1;
516 }
517 }
518
519 __skb_queue_head_init(&bf_pending);
520
521 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
522 while (bf) {
523 u16 seqno = bf->bf_state.seqno;
524
525 txfail = txpending = sendbar = 0;
526 bf_next = bf->bf_next;
527
528 skb = bf->bf_mpdu;
529 tx_info = IEEE80211_SKB_CB(skb);
530 fi = get_frame_info(skb);
531
532 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
533 !tid->active) {
534 /*
535 * Outside of the current BlockAck window,
536 * maybe part of a previous session
537 */
538 txfail = 1;
539 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
540 /* transmit completion, subframe is
541 * acked by block ack */
542 acked_cnt++;
543 } else if (!isaggr && txok) {
544 /* transmit completion */
545 acked_cnt++;
546 } else if (flush) {
547 txpending = 1;
548 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
549 if (txok || !an->sleeping)
550 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
551 retries);
552
553 txpending = 1;
554 } else {
555 txfail = 1;
556 txfail_cnt++;
557 bar_index = max_t(int, bar_index,
558 ATH_BA_INDEX(seq_first, seqno));
559 }
560
561 /*
562 * Make sure the last desc is reclaimed if it
563 * not a holding desc.
564 */
565 INIT_LIST_HEAD(&bf_head);
566 if (bf_next != NULL || !bf_last->bf_state.stale)
567 list_move_tail(&bf->list, &bf_head);
568
569 if (!txpending) {
570 /*
571 * complete the acked-ones/xretried ones; update
572 * block-ack window
573 */
574 ath_tx_update_baw(sc, tid, seqno);
575
576 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
577 memcpy(tx_info->control.rates, rates, sizeof(rates));
578 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
579 rc_update = false;
580 if (bf == bf->bf_lastbf)
581 ath_dynack_sample_tx_ts(sc->sc_ah,
582 bf->bf_mpdu,
583 ts);
584 }
585
586 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
587 !txfail);
588 } else {
589 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
590 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
591 ieee80211_sta_eosp(sta);
592 }
593 /* retry the un-acked ones */
594 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
595 struct ath_buf *tbf;
596
597 tbf = ath_clone_txbuf(sc, bf_last);
598 /*
599 * Update tx baw and complete the
600 * frame with failed status if we
601 * run out of tx buf.
602 */
603 if (!tbf) {
604 ath_tx_update_baw(sc, tid, seqno);
605
606 ath_tx_complete_buf(sc, bf, txq,
607 &bf_head, ts, 0);
608 bar_index = max_t(int, bar_index,
609 ATH_BA_INDEX(seq_first, seqno));
610 break;
611 }
612
613 fi->bf = tbf;
614 }
615
616 /*
617 * Put this buffer to the temporary pending
618 * queue to retain ordering
619 */
620 __skb_queue_tail(&bf_pending, skb);
621 }
622
623 bf = bf_next;
624 }
625
626 /* prepend un-acked frames to the beginning of the pending frame queue */
627 if (!skb_queue_empty(&bf_pending)) {
628 if (an->sleeping)
629 ieee80211_sta_set_buffered(sta, tid->tidno, true);
630
631 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
632 if (!an->sleeping) {
633 ath_tx_queue_tid(sc, txq, tid);
634
635 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
636 tid->clear_ps_filter = true;
637 }
638 }
639
640 if (bar_index >= 0) {
641 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
642
643 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
644 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
645
646 ath_txq_unlock(sc, txq);
647 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
648 ath_txq_lock(sc, txq);
649 }
650
651 rcu_read_unlock();
652
653 if (needreset)
654 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
655}
656
657static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
658{
659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
660 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
661}
662
663static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
664 struct ath_tx_status *ts, struct ath_buf *bf,
665 struct list_head *bf_head)
666{
667 struct ieee80211_tx_info *info;
668 bool txok, flush;
669
670 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
671 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
672 txq->axq_tx_inprogress = false;
673
674 txq->axq_depth--;
675 if (bf_is_ampdu_not_probing(bf))
676 txq->axq_ampdu_depth--;
677
678 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
679 ts->ts_rateindex);
680 if (!bf_isampdu(bf)) {
681 if (!flush) {
682 info = IEEE80211_SKB_CB(bf->bf_mpdu);
683 memcpy(info->control.rates, bf->rates,
684 sizeof(info->control.rates));
685 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
686 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts);
687 }
688 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
689 } else
690 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
691
692 if (!flush)
693 ath_txq_schedule(sc, txq);
694}
695
696static bool ath_lookup_legacy(struct ath_buf *bf)
697{
698 struct sk_buff *skb;
699 struct ieee80211_tx_info *tx_info;
700 struct ieee80211_tx_rate *rates;
701 int i;
702
703 skb = bf->bf_mpdu;
704 tx_info = IEEE80211_SKB_CB(skb);
705 rates = tx_info->control.rates;
706
707 for (i = 0; i < 4; i++) {
708 if (!rates[i].count || rates[i].idx < 0)
709 break;
710
711 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
712 return true;
713 }
714
715 return false;
716}
717
718static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
719 struct ath_atx_tid *tid)
720{
721 struct sk_buff *skb;
722 struct ieee80211_tx_info *tx_info;
723 struct ieee80211_tx_rate *rates;
724 u32 max_4ms_framelen, frmlen;
725 u16 aggr_limit, bt_aggr_limit, legacy = 0;
726 int q = tid->txq->mac80211_qnum;
727 int i;
728
729 skb = bf->bf_mpdu;
730 tx_info = IEEE80211_SKB_CB(skb);
731 rates = bf->rates;
732
733 /*
734 * Find the lowest frame length among the rate series that will have a
735 * 4ms (or TXOP limited) transmit duration.
736 */
737 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
738
739 for (i = 0; i < 4; i++) {
740 int modeidx;
741
742 if (!rates[i].count)
743 continue;
744
745 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
746 legacy = 1;
747 break;
748 }
749
750 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
751 modeidx = MCS_HT40;
752 else
753 modeidx = MCS_HT20;
754
755 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
756 modeidx++;
757
758 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
759 max_4ms_framelen = min(max_4ms_framelen, frmlen);
760 }
761
762 /*
763 * limit aggregate size by the minimum rate if rate selected is
764 * not a probe rate, if rate selected is a probe rate then
765 * avoid aggregation of this packet.
766 */
767 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
768 return 0;
769
770 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
771
772 /*
773 * Override the default aggregation limit for BTCOEX.
774 */
775 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
776 if (bt_aggr_limit)
777 aggr_limit = bt_aggr_limit;
778
779 if (tid->an->maxampdu)
780 aggr_limit = min(aggr_limit, tid->an->maxampdu);
781
782 return aggr_limit;
783}
784
785/*
786 * Returns the number of delimiters to be added to
787 * meet the minimum required mpdudensity.
788 */
789static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
790 struct ath_buf *bf, u16 frmlen,
791 bool first_subfrm)
792{
793#define FIRST_DESC_NDELIMS 60
794 u32 nsymbits, nsymbols;
795 u16 minlen;
796 u8 flags, rix;
797 int width, streams, half_gi, ndelim, mindelim;
798 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
799
800 /* Select standard number of delimiters based on frame length alone */
801 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
802
803 /*
804 * If encryption enabled, hardware requires some more padding between
805 * subframes.
806 * TODO - this could be improved to be dependent on the rate.
807 * The hardware can keep up at lower rates, but not higher rates
808 */
809 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
810 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
811 ndelim += ATH_AGGR_ENCRYPTDELIM;
812
813 /*
814 * Add delimiter when using RTS/CTS with aggregation
815 * and non enterprise AR9003 card
816 */
817 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
818 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
819 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
820
821 /*
822 * Convert desired mpdu density from microeconds to bytes based
823 * on highest rate in rate series (i.e. first rate) to determine
824 * required minimum length for subframe. Take into account
825 * whether high rate is 20 or 40Mhz and half or full GI.
826 *
827 * If there is no mpdu density restriction, no further calculation
828 * is needed.
829 */
830
831 if (tid->an->mpdudensity == 0)
832 return ndelim;
833
834 rix = bf->rates[0].idx;
835 flags = bf->rates[0].flags;
836 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
837 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
838
839 if (half_gi)
840 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
841 else
842 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
843
844 if (nsymbols == 0)
845 nsymbols = 1;
846
847 streams = HT_RC_2_STREAMS(rix);
848 nsymbits = bits_per_symbol[rix % 8][width] * streams;
849 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
850
851 if (frmlen < minlen) {
852 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
853 ndelim = max(mindelim, ndelim);
854 }
855
856 return ndelim;
857}
858
859static struct ath_buf *
860ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
861 struct ath_atx_tid *tid, struct sk_buff_head **q)
862{
863 struct ieee80211_tx_info *tx_info;
864 struct ath_frame_info *fi;
865 struct sk_buff *skb;
866 struct ath_buf *bf;
867 u16 seqno;
868
869 while (1) {
870 *q = &tid->retry_q;
871 if (skb_queue_empty(*q))
872 *q = &tid->buf_q;
873
874 skb = skb_peek(*q);
875 if (!skb)
876 break;
877
878 fi = get_frame_info(skb);
879 bf = fi->bf;
880 if (!fi->bf)
881 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
882 else
883 bf->bf_state.stale = false;
884
885 if (!bf) {
886 __skb_unlink(skb, *q);
887 ath_txq_skb_done(sc, txq, skb);
888 ieee80211_free_txskb(sc->hw, skb);
889 continue;
890 }
891
892 bf->bf_next = NULL;
893 bf->bf_lastbf = bf;
894
895 tx_info = IEEE80211_SKB_CB(skb);
896 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
897
898 /*
899 * No aggregation session is running, but there may be frames
900 * from a previous session or a failed attempt in the queue.
901 * Send them out as normal data frames
902 */
903 if (!tid->active)
904 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
905
906 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
907 bf->bf_state.bf_type = 0;
908 return bf;
909 }
910
911 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
912 seqno = bf->bf_state.seqno;
913
914 /* do not step over block-ack window */
915 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
916 break;
917
918 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
919 struct ath_tx_status ts = {};
920 struct list_head bf_head;
921
922 INIT_LIST_HEAD(&bf_head);
923 list_add(&bf->list, &bf_head);
924 __skb_unlink(skb, *q);
925 ath_tx_update_baw(sc, tid, seqno);
926 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
927 continue;
928 }
929
930 return bf;
931 }
932
933 return NULL;
934}
935
936static bool
937ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
938 struct ath_atx_tid *tid, struct list_head *bf_q,
939 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
940 int *aggr_len)
941{
942#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
943 struct ath_buf *bf = bf_first, *bf_prev = NULL;
944 int nframes = 0, ndelim;
945 u16 aggr_limit = 0, al = 0, bpad = 0,
946 al_delta, h_baw = tid->baw_size / 2;
947 struct ieee80211_tx_info *tx_info;
948 struct ath_frame_info *fi;
949 struct sk_buff *skb;
950 bool closed = false;
951
952 bf = bf_first;
953 aggr_limit = ath_lookup_rate(sc, bf, tid);
954
955 do {
956 skb = bf->bf_mpdu;
957 fi = get_frame_info(skb);
958
959 /* do not exceed aggregation limit */
960 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
961 if (nframes) {
962 if (aggr_limit < al + bpad + al_delta ||
963 ath_lookup_legacy(bf) || nframes >= h_baw)
964 break;
965
966 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
967 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
968 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
969 break;
970 }
971
972 /* add padding for previous frame to aggregation length */
973 al += bpad + al_delta;
974
975 /*
976 * Get the delimiters needed to meet the MPDU
977 * density for this node.
978 */
979 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
980 !nframes);
981 bpad = PADBYTES(al_delta) + (ndelim << 2);
982
983 nframes++;
984 bf->bf_next = NULL;
985
986 /* link buffers of this frame to the aggregate */
987 if (!fi->baw_tracked)
988 ath_tx_addto_baw(sc, tid, bf);
989 bf->bf_state.ndelim = ndelim;
990
991 __skb_unlink(skb, tid_q);
992 list_add_tail(&bf->list, bf_q);
993 if (bf_prev)
994 bf_prev->bf_next = bf;
995
996 bf_prev = bf;
997
998 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
999 if (!bf) {
1000 closed = true;
1001 break;
1002 }
1003 } while (ath_tid_has_buffered(tid));
1004
1005 bf = bf_first;
1006 bf->bf_lastbf = bf_prev;
1007
1008 if (bf == bf_prev) {
1009 al = get_frame_info(bf->bf_mpdu)->framelen;
1010 bf->bf_state.bf_type = BUF_AMPDU;
1011 } else {
1012 TX_STAT_INC(txq->axq_qnum, a_aggr);
1013 }
1014
1015 *aggr_len = al;
1016
1017 return closed;
1018#undef PADBYTES
1019}
1020
1021/*
1022 * rix - rate index
1023 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1024 * width - 0 for 20 MHz, 1 for 40 MHz
1025 * half_gi - to use 4us v/s 3.6 us for symbol time
1026 */
1027static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1028 int width, int half_gi, bool shortPreamble)
1029{
1030 u32 nbits, nsymbits, duration, nsymbols;
1031 int streams;
1032
1033 /* find number of symbols: PLCP + data */
1034 streams = HT_RC_2_STREAMS(rix);
1035 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1036 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1037 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1038
1039 if (!half_gi)
1040 duration = SYMBOL_TIME(nsymbols);
1041 else
1042 duration = SYMBOL_TIME_HALFGI(nsymbols);
1043
1044 /* addup duration for legacy/ht training and signal fields */
1045 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1046
1047 return duration;
1048}
1049
1050static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1051{
1052 int streams = HT_RC_2_STREAMS(mcs);
1053 int symbols, bits;
1054 int bytes = 0;
1055
1056 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1057 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1058 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1059 bits -= OFDM_PLCP_BITS;
1060 bytes = bits / 8;
1061 if (bytes > 65532)
1062 bytes = 65532;
1063
1064 return bytes;
1065}
1066
1067void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1068{
1069 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1070 int mcs;
1071
1072 /* 4ms is the default (and maximum) duration */
1073 if (!txop || txop > 4096)
1074 txop = 4096;
1075
1076 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1077 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1078 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1079 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1080 for (mcs = 0; mcs < 32; mcs++) {
1081 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1082 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1083 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1084 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1085 }
1086}
1087
1088static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1089 u8 rateidx, bool is_40, bool is_cck)
1090{
1091 u8 max_power;
1092 struct sk_buff *skb;
1093 struct ath_frame_info *fi;
1094 struct ieee80211_tx_info *info;
1095 struct ath_hw *ah = sc->sc_ah;
1096
1097 if (sc->tx99_state || !ah->tpc_enabled)
1098 return MAX_RATE_POWER;
1099
1100 skb = bf->bf_mpdu;
1101 fi = get_frame_info(skb);
1102 info = IEEE80211_SKB_CB(skb);
1103
1104 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1105 int txpower = fi->tx_power;
1106
1107 if (is_40) {
1108 u8 power_ht40delta;
1109 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1110
1111 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
1112 bool is_2ghz;
1113 struct modal_eep_header *pmodal;
1114
1115 is_2ghz = info->band == IEEE80211_BAND_2GHZ;
1116 pmodal = &eep->modalHeader[is_2ghz];
1117 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1118 } else {
1119 power_ht40delta = 2;
1120 }
1121 txpower += power_ht40delta;
1122 }
1123
1124 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1125 AR_SREV_9271(ah)) {
1126 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1127 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1128 s8 power_offset;
1129
1130 power_offset = ah->eep_ops->get_eeprom(ah,
1131 EEP_PWR_TABLE_OFFSET);
1132 txpower -= 2 * power_offset;
1133 }
1134
1135 if (OLC_FOR_AR9280_20_LATER && is_cck)
1136 txpower -= 2;
1137
1138 txpower = max(txpower, 0);
1139 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1140
1141 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1142 * max_power is set to 0, frames are transmitted at max
1143 * TX power
1144 */
1145 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1146 max_power = 1;
1147 } else if (!bf->bf_state.bfs_paprd) {
1148 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1149 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1150 fi->tx_power);
1151 else
1152 max_power = min_t(u8, ah->tx_power[rateidx],
1153 fi->tx_power);
1154 } else {
1155 max_power = ah->paprd_training_power;
1156 }
1157
1158 return max_power;
1159}
1160
1161static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1162 struct ath_tx_info *info, int len, bool rts)
1163{
1164 struct ath_hw *ah = sc->sc_ah;
1165 struct ath_common *common = ath9k_hw_common(ah);
1166 struct sk_buff *skb;
1167 struct ieee80211_tx_info *tx_info;
1168 struct ieee80211_tx_rate *rates;
1169 const struct ieee80211_rate *rate;
1170 struct ieee80211_hdr *hdr;
1171 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1172 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1173 int i;
1174 u8 rix = 0;
1175
1176 skb = bf->bf_mpdu;
1177 tx_info = IEEE80211_SKB_CB(skb);
1178 rates = bf->rates;
1179 hdr = (struct ieee80211_hdr *)skb->data;
1180
1181 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1182 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1183 info->rtscts_rate = fi->rtscts_rate;
1184
1185 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1186 bool is_40, is_sgi, is_sp, is_cck;
1187 int phy;
1188
1189 if (!rates[i].count || (rates[i].idx < 0))
1190 continue;
1191
1192 rix = rates[i].idx;
1193 info->rates[i].Tries = rates[i].count;
1194
1195 /*
1196 * Handle RTS threshold for unaggregated HT frames.
1197 */
1198 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1199 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1200 unlikely(rts_thresh != (u32) -1)) {
1201 if (!rts_thresh || (len > rts_thresh))
1202 rts = true;
1203 }
1204
1205 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1206 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1207 info->flags |= ATH9K_TXDESC_RTSENA;
1208 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1209 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1210 info->flags |= ATH9K_TXDESC_CTSENA;
1211 }
1212
1213 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1214 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1215 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1216 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1217
1218 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1219 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1220 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1221
1222 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1223 /* MCS rates */
1224 info->rates[i].Rate = rix | 0x80;
1225 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1226 ah->txchainmask, info->rates[i].Rate);
1227 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1228 is_40, is_sgi, is_sp);
1229 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1230 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1231
1232 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1233 is_40, false);
1234 continue;
1235 }
1236
1237 /* legacy rates */
1238 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1239 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1240 !(rate->flags & IEEE80211_RATE_ERP_G))
1241 phy = WLAN_RC_PHY_CCK;
1242 else
1243 phy = WLAN_RC_PHY_OFDM;
1244
1245 info->rates[i].Rate = rate->hw_value;
1246 if (rate->hw_value_short) {
1247 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1248 info->rates[i].Rate |= rate->hw_value_short;
1249 } else {
1250 is_sp = false;
1251 }
1252
1253 if (bf->bf_state.bfs_paprd)
1254 info->rates[i].ChSel = ah->txchainmask;
1255 else
1256 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1257 ah->txchainmask, info->rates[i].Rate);
1258
1259 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1260 phy, rate->bitrate * 100, len, rix, is_sp);
1261
1262 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1263 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1264 is_cck);
1265 }
1266
1267 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1268 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1269 info->flags &= ~ATH9K_TXDESC_RTSENA;
1270
1271 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1272 if (info->flags & ATH9K_TXDESC_RTSENA)
1273 info->flags &= ~ATH9K_TXDESC_CTSENA;
1274}
1275
1276static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1277{
1278 struct ieee80211_hdr *hdr;
1279 enum ath9k_pkt_type htype;
1280 __le16 fc;
1281
1282 hdr = (struct ieee80211_hdr *)skb->data;
1283 fc = hdr->frame_control;
1284
1285 if (ieee80211_is_beacon(fc))
1286 htype = ATH9K_PKT_TYPE_BEACON;
1287 else if (ieee80211_is_probe_resp(fc))
1288 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1289 else if (ieee80211_is_atim(fc))
1290 htype = ATH9K_PKT_TYPE_ATIM;
1291 else if (ieee80211_is_pspoll(fc))
1292 htype = ATH9K_PKT_TYPE_PSPOLL;
1293 else
1294 htype = ATH9K_PKT_TYPE_NORMAL;
1295
1296 return htype;
1297}
1298
1299static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1300 struct ath_txq *txq, int len)
1301{
1302 struct ath_hw *ah = sc->sc_ah;
1303 struct ath_buf *bf_first = NULL;
1304 struct ath_tx_info info;
1305 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1306 bool rts = false;
1307
1308 memset(&info, 0, sizeof(info));
1309 info.is_first = true;
1310 info.is_last = true;
1311 info.qcu = txq->axq_qnum;
1312
1313 while (bf) {
1314 struct sk_buff *skb = bf->bf_mpdu;
1315 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1316 struct ath_frame_info *fi = get_frame_info(skb);
1317 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1318
1319 info.type = get_hw_packet_type(skb);
1320 if (bf->bf_next)
1321 info.link = bf->bf_next->bf_daddr;
1322 else
1323 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1324
1325 if (!bf_first) {
1326 bf_first = bf;
1327
1328 if (!sc->tx99_state)
1329 info.flags = ATH9K_TXDESC_INTREQ;
1330 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1331 txq == sc->tx.uapsdq)
1332 info.flags |= ATH9K_TXDESC_CLRDMASK;
1333
1334 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1335 info.flags |= ATH9K_TXDESC_NOACK;
1336 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1337 info.flags |= ATH9K_TXDESC_LDPC;
1338
1339 if (bf->bf_state.bfs_paprd)
1340 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1341 ATH9K_TXDESC_PAPRD_S;
1342
1343 /*
1344 * mac80211 doesn't handle RTS threshold for HT because
1345 * the decision has to be taken based on AMPDU length
1346 * and aggregation is done entirely inside ath9k.
1347 * Set the RTS/CTS flag for the first subframe based
1348 * on the threshold.
1349 */
1350 if (aggr && (bf == bf_first) &&
1351 unlikely(rts_thresh != (u32) -1)) {
1352 /*
1353 * "len" is the size of the entire AMPDU.
1354 */
1355 if (!rts_thresh || (len > rts_thresh))
1356 rts = true;
1357 }
1358
1359 if (!aggr)
1360 len = fi->framelen;
1361
1362 ath_buf_set_rate(sc, bf, &info, len, rts);
1363 }
1364
1365 info.buf_addr[0] = bf->bf_buf_addr;
1366 info.buf_len[0] = skb->len;
1367 info.pkt_len = fi->framelen;
1368 info.keyix = fi->keyix;
1369 info.keytype = fi->keytype;
1370
1371 if (aggr) {
1372 if (bf == bf_first)
1373 info.aggr = AGGR_BUF_FIRST;
1374 else if (bf == bf_first->bf_lastbf)
1375 info.aggr = AGGR_BUF_LAST;
1376 else
1377 info.aggr = AGGR_BUF_MIDDLE;
1378
1379 info.ndelim = bf->bf_state.ndelim;
1380 info.aggr_len = len;
1381 }
1382
1383 if (bf == bf_first->bf_lastbf)
1384 bf_first = NULL;
1385
1386 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1387 bf = bf->bf_next;
1388 }
1389}
1390
1391static void
1392ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1393 struct ath_atx_tid *tid, struct list_head *bf_q,
1394 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1395{
1396 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1397 struct sk_buff *skb;
1398 int nframes = 0;
1399
1400 do {
1401 struct ieee80211_tx_info *tx_info;
1402 skb = bf->bf_mpdu;
1403
1404 nframes++;
1405 __skb_unlink(skb, tid_q);
1406 list_add_tail(&bf->list, bf_q);
1407 if (bf_prev)
1408 bf_prev->bf_next = bf;
1409 bf_prev = bf;
1410
1411 if (nframes >= 2)
1412 break;
1413
1414 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1415 if (!bf)
1416 break;
1417
1418 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1419 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1420 break;
1421
1422 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1423 } while (1);
1424}
1425
1426static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1427 struct ath_atx_tid *tid, bool *stop)
1428{
1429 struct ath_buf *bf;
1430 struct ieee80211_tx_info *tx_info;
1431 struct sk_buff_head *tid_q;
1432 struct list_head bf_q;
1433 int aggr_len = 0;
1434 bool aggr, last = true;
1435
1436 if (!ath_tid_has_buffered(tid))
1437 return false;
1438
1439 INIT_LIST_HEAD(&bf_q);
1440
1441 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1442 if (!bf)
1443 return false;
1444
1445 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1446 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1447 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1448 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1449 *stop = true;
1450 return false;
1451 }
1452
1453 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1454 if (aggr)
1455 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1456 tid_q, &aggr_len);
1457 else
1458 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1459
1460 if (list_empty(&bf_q))
1461 return false;
1462
1463 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1464 tid->clear_ps_filter = false;
1465 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1466 }
1467
1468 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1469 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1470 return true;
1471}
1472
1473int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1474 u16 tid, u16 *ssn)
1475{
1476 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1477 struct ath_atx_tid *txtid;
1478 struct ath_txq *txq;
1479 struct ath_node *an;
1480 u8 density;
1481
1482 ath_dbg(common, XMIT, "%s called\n", __func__);
1483
1484 an = (struct ath_node *)sta->drv_priv;
1485 txtid = ATH_AN_2_TID(an, tid);
1486 txq = txtid->txq;
1487
1488 ath_txq_lock(sc, txq);
1489
1490 /* update ampdu factor/density, they may have changed. This may happen
1491 * in HT IBSS when a beacon with HT-info is received after the station
1492 * has already been added.
1493 */
1494 if (sta->ht_cap.ht_supported) {
1495 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1496 sta->ht_cap.ampdu_factor)) - 1;
1497 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1498 an->mpdudensity = density;
1499 }
1500
1501 /* force sequence number allocation for pending frames */
1502 ath_tx_tid_change_state(sc, txtid);
1503
1504 txtid->active = true;
1505 *ssn = txtid->seq_start = txtid->seq_next;
1506 txtid->bar_index = -1;
1507
1508 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1509 txtid->baw_head = txtid->baw_tail = 0;
1510
1511 ath_txq_unlock_complete(sc, txq);
1512
1513 return 0;
1514}
1515
1516void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1517{
1518 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1519 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1520 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1521 struct ath_txq *txq = txtid->txq;
1522
1523 ath_dbg(common, XMIT, "%s called\n", __func__);
1524
1525 ath_txq_lock(sc, txq);
1526 txtid->active = false;
1527 ath_tx_flush_tid(sc, txtid);
1528 ath_tx_tid_change_state(sc, txtid);
1529 ath_txq_unlock_complete(sc, txq);
1530}
1531
1532void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1533 struct ath_node *an)
1534{
1535 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1536 struct ath_atx_tid *tid;
1537 struct ath_txq *txq;
1538 bool buffered;
1539 int tidno;
1540
1541 ath_dbg(common, XMIT, "%s called\n", __func__);
1542
1543 for (tidno = 0, tid = &an->tid[tidno];
1544 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1545
1546 txq = tid->txq;
1547
1548 ath_txq_lock(sc, txq);
1549
1550 if (list_empty(&tid->list)) {
1551 ath_txq_unlock(sc, txq);
1552 continue;
1553 }
1554
1555 buffered = ath_tid_has_buffered(tid);
1556
1557 list_del_init(&tid->list);
1558
1559 ath_txq_unlock(sc, txq);
1560
1561 ieee80211_sta_set_buffered(sta, tidno, buffered);
1562 }
1563}
1564
1565void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1566{
1567 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1568 struct ath_atx_tid *tid;
1569 struct ath_txq *txq;
1570 int tidno;
1571
1572 ath_dbg(common, XMIT, "%s called\n", __func__);
1573
1574 for (tidno = 0, tid = &an->tid[tidno];
1575 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1576
1577 txq = tid->txq;
1578
1579 ath_txq_lock(sc, txq);
1580 tid->clear_ps_filter = true;
1581
1582 if (ath_tid_has_buffered(tid)) {
1583 ath_tx_queue_tid(sc, txq, tid);
1584 ath_txq_schedule(sc, txq);
1585 }
1586
1587 ath_txq_unlock_complete(sc, txq);
1588 }
1589}
1590
1591void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1592 u16 tidno)
1593{
1594 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1595 struct ath_atx_tid *tid;
1596 struct ath_node *an;
1597 struct ath_txq *txq;
1598
1599 ath_dbg(common, XMIT, "%s called\n", __func__);
1600
1601 an = (struct ath_node *)sta->drv_priv;
1602 tid = ATH_AN_2_TID(an, tidno);
1603 txq = tid->txq;
1604
1605 ath_txq_lock(sc, txq);
1606
1607 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1608
1609 if (ath_tid_has_buffered(tid)) {
1610 ath_tx_queue_tid(sc, txq, tid);
1611 ath_txq_schedule(sc, txq);
1612 }
1613
1614 ath_txq_unlock_complete(sc, txq);
1615}
1616
1617void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1618 struct ieee80211_sta *sta,
1619 u16 tids, int nframes,
1620 enum ieee80211_frame_release_type reason,
1621 bool more_data)
1622{
1623 struct ath_softc *sc = hw->priv;
1624 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1625 struct ath_txq *txq = sc->tx.uapsdq;
1626 struct ieee80211_tx_info *info;
1627 struct list_head bf_q;
1628 struct ath_buf *bf_tail = NULL, *bf;
1629 struct sk_buff_head *tid_q;
1630 int sent = 0;
1631 int i;
1632
1633 INIT_LIST_HEAD(&bf_q);
1634 for (i = 0; tids && nframes; i++, tids >>= 1) {
1635 struct ath_atx_tid *tid;
1636
1637 if (!(tids & 1))
1638 continue;
1639
1640 tid = ATH_AN_2_TID(an, i);
1641
1642 ath_txq_lock(sc, tid->txq);
1643 while (nframes > 0) {
1644 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1645 if (!bf)
1646 break;
1647
1648 __skb_unlink(bf->bf_mpdu, tid_q);
1649 list_add_tail(&bf->list, &bf_q);
1650 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1651 if (bf_isampdu(bf)) {
1652 ath_tx_addto_baw(sc, tid, bf);
1653 bf->bf_state.bf_type &= ~BUF_AGGR;
1654 }
1655 if (bf_tail)
1656 bf_tail->bf_next = bf;
1657
1658 bf_tail = bf;
1659 nframes--;
1660 sent++;
1661 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1662
1663 if (an->sta && !ath_tid_has_buffered(tid))
1664 ieee80211_sta_set_buffered(an->sta, i, false);
1665 }
1666 ath_txq_unlock_complete(sc, tid->txq);
1667 }
1668
1669 if (list_empty(&bf_q))
1670 return;
1671
1672 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1673 info->flags |= IEEE80211_TX_STATUS_EOSP;
1674
1675 bf = list_first_entry(&bf_q, struct ath_buf, list);
1676 ath_txq_lock(sc, txq);
1677 ath_tx_fill_desc(sc, bf, txq, 0);
1678 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1679 ath_txq_unlock(sc, txq);
1680}
1681
1682/********************/
1683/* Queue Management */
1684/********************/
1685
1686struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1687{
1688 struct ath_hw *ah = sc->sc_ah;
1689 struct ath9k_tx_queue_info qi;
1690 static const int subtype_txq_to_hwq[] = {
1691 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1692 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1693 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1694 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1695 };
1696 int axq_qnum, i;
1697
1698 memset(&qi, 0, sizeof(qi));
1699 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1700 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1701 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1702 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1703 qi.tqi_physCompBuf = 0;
1704
1705 /*
1706 * Enable interrupts only for EOL and DESC conditions.
1707 * We mark tx descriptors to receive a DESC interrupt
1708 * when a tx queue gets deep; otherwise waiting for the
1709 * EOL to reap descriptors. Note that this is done to
1710 * reduce interrupt load and this only defers reaping
1711 * descriptors, never transmitting frames. Aside from
1712 * reducing interrupts this also permits more concurrency.
1713 * The only potential downside is if the tx queue backs
1714 * up in which case the top half of the kernel may backup
1715 * due to a lack of tx descriptors.
1716 *
1717 * The UAPSD queue is an exception, since we take a desc-
1718 * based intr on the EOSP frames.
1719 */
1720 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1721 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1722 } else {
1723 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1724 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1725 else
1726 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1727 TXQ_FLAG_TXDESCINT_ENABLE;
1728 }
1729 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1730 if (axq_qnum == -1) {
1731 /*
1732 * NB: don't print a message, this happens
1733 * normally on parts with too few tx queues
1734 */
1735 return NULL;
1736 }
1737 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1738 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1739
1740 txq->axq_qnum = axq_qnum;
1741 txq->mac80211_qnum = -1;
1742 txq->axq_link = NULL;
1743 __skb_queue_head_init(&txq->complete_q);
1744 INIT_LIST_HEAD(&txq->axq_q);
1745 spin_lock_init(&txq->axq_lock);
1746 txq->axq_depth = 0;
1747 txq->axq_ampdu_depth = 0;
1748 txq->axq_tx_inprogress = false;
1749 sc->tx.txqsetup |= 1<<axq_qnum;
1750
1751 txq->txq_headidx = txq->txq_tailidx = 0;
1752 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1753 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1754 }
1755 return &sc->tx.txq[axq_qnum];
1756}
1757
1758int ath_txq_update(struct ath_softc *sc, int qnum,
1759 struct ath9k_tx_queue_info *qinfo)
1760{
1761 struct ath_hw *ah = sc->sc_ah;
1762 int error = 0;
1763 struct ath9k_tx_queue_info qi;
1764
1765 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1766
1767 ath9k_hw_get_txq_props(ah, qnum, &qi);
1768 qi.tqi_aifs = qinfo->tqi_aifs;
1769 qi.tqi_cwmin = qinfo->tqi_cwmin;
1770 qi.tqi_cwmax = qinfo->tqi_cwmax;
1771 qi.tqi_burstTime = qinfo->tqi_burstTime;
1772 qi.tqi_readyTime = qinfo->tqi_readyTime;
1773
1774 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1775 ath_err(ath9k_hw_common(sc->sc_ah),
1776 "Unable to update hardware queue %u!\n", qnum);
1777 error = -EIO;
1778 } else {
1779 ath9k_hw_resettxqueue(ah, qnum);
1780 }
1781
1782 return error;
1783}
1784
1785int ath_cabq_update(struct ath_softc *sc)
1786{
1787 struct ath9k_tx_queue_info qi;
1788 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1789 int qnum = sc->beacon.cabq->axq_qnum;
1790
1791 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1792
1793 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1794 ATH_CABQ_READY_TIME) / 100;
1795 ath_txq_update(sc, qnum, &qi);
1796
1797 return 0;
1798}
1799
1800static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1801 struct list_head *list)
1802{
1803 struct ath_buf *bf, *lastbf;
1804 struct list_head bf_head;
1805 struct ath_tx_status ts;
1806
1807 memset(&ts, 0, sizeof(ts));
1808 ts.ts_status = ATH9K_TX_FLUSH;
1809 INIT_LIST_HEAD(&bf_head);
1810
1811 while (!list_empty(list)) {
1812 bf = list_first_entry(list, struct ath_buf, list);
1813
1814 if (bf->bf_state.stale) {
1815 list_del(&bf->list);
1816
1817 ath_tx_return_buffer(sc, bf);
1818 continue;
1819 }
1820
1821 lastbf = bf->bf_lastbf;
1822 list_cut_position(&bf_head, list, &lastbf->list);
1823 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1824 }
1825}
1826
1827/*
1828 * Drain a given TX queue (could be Beacon or Data)
1829 *
1830 * This assumes output has been stopped and
1831 * we do not need to block ath_tx_tasklet.
1832 */
1833void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1834{
1835 ath_txq_lock(sc, txq);
1836
1837 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1838 int idx = txq->txq_tailidx;
1839
1840 while (!list_empty(&txq->txq_fifo[idx])) {
1841 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1842
1843 INCR(idx, ATH_TXFIFO_DEPTH);
1844 }
1845 txq->txq_tailidx = idx;
1846 }
1847
1848 txq->axq_link = NULL;
1849 txq->axq_tx_inprogress = false;
1850 ath_drain_txq_list(sc, txq, &txq->axq_q);
1851
1852 ath_txq_unlock_complete(sc, txq);
1853}
1854
1855bool ath_drain_all_txq(struct ath_softc *sc)
1856{
1857 struct ath_hw *ah = sc->sc_ah;
1858 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1859 struct ath_txq *txq;
1860 int i;
1861 u32 npend = 0;
1862
1863 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1864 return true;
1865
1866 ath9k_hw_abort_tx_dma(ah);
1867
1868 /* Check if any queue remains active */
1869 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1870 if (!ATH_TXQ_SETUP(sc, i))
1871 continue;
1872
1873 if (!sc->tx.txq[i].axq_depth)
1874 continue;
1875
1876 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1877 npend |= BIT(i);
1878 }
1879
1880 if (npend) {
1881 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1882 ath_dbg(common, RESET,
1883 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1884 }
1885
1886 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1887 if (!ATH_TXQ_SETUP(sc, i))
1888 continue;
1889
1890 /*
1891 * The caller will resume queues with ieee80211_wake_queues.
1892 * Mark the queue as not stopped to prevent ath_tx_complete
1893 * from waking the queue too early.
1894 */
1895 txq = &sc->tx.txq[i];
1896 txq->stopped = false;
1897 ath_draintxq(sc, txq);
1898 }
1899
1900 return !npend;
1901}
1902
1903void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1904{
1905 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1906 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1907}
1908
1909/* For each acq entry, for each tid, try to schedule packets
1910 * for transmit until ampdu_depth has reached min Q depth.
1911 */
1912void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1913{
1914 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1915 struct ath_atx_tid *tid, *last_tid;
1916 struct list_head *tid_list;
1917 bool sent = false;
1918
1919 if (txq->mac80211_qnum < 0)
1920 return;
1921
1922 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1923 return;
1924
1925 spin_lock_bh(&sc->chan_lock);
1926 tid_list = &sc->cur_chan->acq[txq->mac80211_qnum];
1927
1928 if (list_empty(tid_list)) {
1929 spin_unlock_bh(&sc->chan_lock);
1930 return;
1931 }
1932
1933 rcu_read_lock();
1934
1935 last_tid = list_entry(tid_list->prev, struct ath_atx_tid, list);
1936 while (!list_empty(tid_list)) {
1937 bool stop = false;
1938
1939 if (sc->cur_chan->stopped)
1940 break;
1941
1942 tid = list_first_entry(tid_list, struct ath_atx_tid, list);
1943 list_del_init(&tid->list);
1944
1945 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1946 sent = true;
1947
1948 /*
1949 * add tid to round-robin queue if more frames
1950 * are pending for the tid
1951 */
1952 if (ath_tid_has_buffered(tid))
1953 ath_tx_queue_tid(sc, txq, tid);
1954
1955 if (stop)
1956 break;
1957
1958 if (tid == last_tid) {
1959 if (!sent)
1960 break;
1961
1962 sent = false;
1963 last_tid = list_entry(tid_list->prev,
1964 struct ath_atx_tid, list);
1965 }
1966 }
1967
1968 rcu_read_unlock();
1969 spin_unlock_bh(&sc->chan_lock);
1970}
1971
1972void ath_txq_schedule_all(struct ath_softc *sc)
1973{
1974 struct ath_txq *txq;
1975 int i;
1976
1977 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1978 txq = sc->tx.txq_map[i];
1979
1980 spin_lock_bh(&txq->axq_lock);
1981 ath_txq_schedule(sc, txq);
1982 spin_unlock_bh(&txq->axq_lock);
1983 }
1984}
1985
1986/***********/
1987/* TX, DMA */
1988/***********/
1989
1990/*
1991 * Insert a chain of ath_buf (descriptors) on a txq and
1992 * assume the descriptors are already chained together by caller.
1993 */
1994static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1995 struct list_head *head, bool internal)
1996{
1997 struct ath_hw *ah = sc->sc_ah;
1998 struct ath_common *common = ath9k_hw_common(ah);
1999 struct ath_buf *bf, *bf_last;
2000 bool puttxbuf = false;
2001 bool edma;
2002
2003 /*
2004 * Insert the frame on the outbound list and
2005 * pass it on to the hardware.
2006 */
2007
2008 if (list_empty(head))
2009 return;
2010
2011 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2012 bf = list_first_entry(head, struct ath_buf, list);
2013 bf_last = list_entry(head->prev, struct ath_buf, list);
2014
2015 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2016 txq->axq_qnum, txq->axq_depth);
2017
2018 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2019 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2020 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2021 puttxbuf = true;
2022 } else {
2023 list_splice_tail_init(head, &txq->axq_q);
2024
2025 if (txq->axq_link) {
2026 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2027 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2028 txq->axq_qnum, txq->axq_link,
2029 ito64(bf->bf_daddr), bf->bf_desc);
2030 } else if (!edma)
2031 puttxbuf = true;
2032
2033 txq->axq_link = bf_last->bf_desc;
2034 }
2035
2036 if (puttxbuf) {
2037 TX_STAT_INC(txq->axq_qnum, puttxbuf);
2038 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2039 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2040 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2041 }
2042
2043 if (!edma || sc->tx99_state) {
2044 TX_STAT_INC(txq->axq_qnum, txstart);
2045 ath9k_hw_txstart(ah, txq->axq_qnum);
2046 }
2047
2048 if (!internal) {
2049 while (bf) {
2050 txq->axq_depth++;
2051 if (bf_is_ampdu_not_probing(bf))
2052 txq->axq_ampdu_depth++;
2053
2054 bf_last = bf->bf_lastbf;
2055 bf = bf_last->bf_next;
2056 bf_last->bf_next = NULL;
2057 }
2058 }
2059}
2060
2061static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2062 struct ath_atx_tid *tid, struct sk_buff *skb)
2063{
2064 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2065 struct ath_frame_info *fi = get_frame_info(skb);
2066 struct list_head bf_head;
2067 struct ath_buf *bf = fi->bf;
2068
2069 INIT_LIST_HEAD(&bf_head);
2070 list_add_tail(&bf->list, &bf_head);
2071 bf->bf_state.bf_type = 0;
2072 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2073 bf->bf_state.bf_type = BUF_AMPDU;
2074 ath_tx_addto_baw(sc, tid, bf);
2075 }
2076
2077 bf->bf_next = NULL;
2078 bf->bf_lastbf = bf;
2079 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2080 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2081 TX_STAT_INC(txq->axq_qnum, queued);
2082}
2083
2084static void setup_frame_info(struct ieee80211_hw *hw,
2085 struct ieee80211_sta *sta,
2086 struct sk_buff *skb,
2087 int framelen)
2088{
2089 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2090 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2091 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2092 const struct ieee80211_rate *rate;
2093 struct ath_frame_info *fi = get_frame_info(skb);
2094 struct ath_node *an = NULL;
2095 enum ath9k_key_type keytype;
2096 bool short_preamble = false;
2097 u8 txpower;
2098
2099 /*
2100 * We check if Short Preamble is needed for the CTS rate by
2101 * checking the BSS's global flag.
2102 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2103 */
2104 if (tx_info->control.vif &&
2105 tx_info->control.vif->bss_conf.use_short_preamble)
2106 short_preamble = true;
2107
2108 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2109 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2110
2111 if (sta)
2112 an = (struct ath_node *) sta->drv_priv;
2113
2114 if (tx_info->control.vif) {
2115 struct ieee80211_vif *vif = tx_info->control.vif;
2116
2117 txpower = 2 * vif->bss_conf.txpower;
2118 } else {
2119 struct ath_softc *sc = hw->priv;
2120
2121 txpower = sc->cur_chan->cur_txpower;
2122 }
2123
2124 memset(fi, 0, sizeof(*fi));
2125 fi->txq = -1;
2126 if (hw_key)
2127 fi->keyix = hw_key->hw_key_idx;
2128 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2129 fi->keyix = an->ps_key;
2130 else
2131 fi->keyix = ATH9K_TXKEYIX_INVALID;
2132 fi->keytype = keytype;
2133 fi->framelen = framelen;
2134 fi->tx_power = txpower;
2135
2136 if (!rate)
2137 return;
2138 fi->rtscts_rate = rate->hw_value;
2139 if (short_preamble)
2140 fi->rtscts_rate |= rate->hw_value_short;
2141}
2142
2143u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2144{
2145 struct ath_hw *ah = sc->sc_ah;
2146 struct ath9k_channel *curchan = ah->curchan;
2147
2148 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2149 (chainmask == 0x7) && (rate < 0x90))
2150 return 0x3;
2151 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2152 IS_CCK_RATE(rate))
2153 return 0x2;
2154 else
2155 return chainmask;
2156}
2157
2158/*
2159 * Assign a descriptor (and sequence number if necessary,
2160 * and map buffer for DMA. Frees skb on error
2161 */
2162static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2163 struct ath_txq *txq,
2164 struct ath_atx_tid *tid,
2165 struct sk_buff *skb)
2166{
2167 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2168 struct ath_frame_info *fi = get_frame_info(skb);
2169 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2170 struct ath_buf *bf;
2171 int fragno;
2172 u16 seqno;
2173
2174 bf = ath_tx_get_buffer(sc);
2175 if (!bf) {
2176 ath_dbg(common, XMIT, "TX buffers are full\n");
2177 return NULL;
2178 }
2179
2180 ATH_TXBUF_RESET(bf);
2181
2182 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2183 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2184 seqno = tid->seq_next;
2185 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2186
2187 if (fragno)
2188 hdr->seq_ctrl |= cpu_to_le16(fragno);
2189
2190 if (!ieee80211_has_morefrags(hdr->frame_control))
2191 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2192
2193 bf->bf_state.seqno = seqno;
2194 }
2195
2196 bf->bf_mpdu = skb;
2197
2198 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2199 skb->len, DMA_TO_DEVICE);
2200 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2201 bf->bf_mpdu = NULL;
2202 bf->bf_buf_addr = 0;
2203 ath_err(ath9k_hw_common(sc->sc_ah),
2204 "dma_mapping_error() on TX\n");
2205 ath_tx_return_buffer(sc, bf);
2206 return NULL;
2207 }
2208
2209 fi->bf = bf;
2210
2211 return bf;
2212}
2213
2214void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2215{
2216 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2217 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2218 struct ieee80211_vif *vif = info->control.vif;
2219 struct ath_vif *avp;
2220
2221 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2222 return;
2223
2224 if (!vif)
2225 return;
2226
2227 avp = (struct ath_vif *)vif->drv_priv;
2228
2229 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2230 avp->seq_no += 0x10;
2231
2232 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2233 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2234}
2235
2236static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2237 struct ath_tx_control *txctl)
2238{
2239 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2240 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2241 struct ieee80211_sta *sta = txctl->sta;
2242 struct ieee80211_vif *vif = info->control.vif;
2243 struct ath_vif *avp;
2244 struct ath_softc *sc = hw->priv;
2245 int frmlen = skb->len + FCS_LEN;
2246 int padpos, padsize;
2247
2248 /* NOTE: sta can be NULL according to net/mac80211.h */
2249 if (sta)
2250 txctl->an = (struct ath_node *)sta->drv_priv;
2251 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2252 avp = (void *)vif->drv_priv;
2253 txctl->an = &avp->mcast_node;
2254 }
2255
2256 if (info->control.hw_key)
2257 frmlen += info->control.hw_key->icv_len;
2258
2259 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2260
2261 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2262 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2263 !ieee80211_is_data(hdr->frame_control))
2264 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2265
2266 /* Add the padding after the header if this is not already done */
2267 padpos = ieee80211_hdrlen(hdr->frame_control);
2268 padsize = padpos & 3;
2269 if (padsize && skb->len > padpos) {
2270 if (skb_headroom(skb) < padsize)
2271 return -ENOMEM;
2272
2273 skb_push(skb, padsize);
2274 memmove(skb->data, skb->data + padsize, padpos);
2275 }
2276
2277 setup_frame_info(hw, sta, skb, frmlen);
2278 return 0;
2279}
2280
2281
2282/* Upon failure caller should free skb */
2283int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2284 struct ath_tx_control *txctl)
2285{
2286 struct ieee80211_hdr *hdr;
2287 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2288 struct ieee80211_sta *sta = txctl->sta;
2289 struct ieee80211_vif *vif = info->control.vif;
2290 struct ath_frame_info *fi = get_frame_info(skb);
2291 struct ath_vif *avp = NULL;
2292 struct ath_softc *sc = hw->priv;
2293 struct ath_txq *txq = txctl->txq;
2294 struct ath_atx_tid *tid = NULL;
2295 struct ath_buf *bf;
2296 bool queue, skip_uapsd = false, ps_resp;
2297 int q, ret;
2298
2299 if (vif)
2300 avp = (void *)vif->drv_priv;
2301
2302 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
2303 txctl->force_channel = true;
2304
2305 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2306
2307 ret = ath_tx_prepare(hw, skb, txctl);
2308 if (ret)
2309 return ret;
2310
2311 hdr = (struct ieee80211_hdr *) skb->data;
2312 /*
2313 * At this point, the vif, hw_key and sta pointers in the tx control
2314 * info are no longer valid (overwritten by the ath_frame_info data.
2315 */
2316
2317 q = skb_get_queue_mapping(skb);
2318
2319 ath_txq_lock(sc, txq);
2320 if (txq == sc->tx.txq_map[q]) {
2321 fi->txq = q;
2322 if (++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2323 !txq->stopped) {
2324 if (ath9k_is_chanctx_enabled())
2325 ieee80211_stop_queue(sc->hw, info->hw_queue);
2326 else
2327 ieee80211_stop_queue(sc->hw, q);
2328 txq->stopped = true;
2329 }
2330 }
2331
2332 queue = ieee80211_is_data_present(hdr->frame_control);
2333
2334 /* If chanctx, queue all null frames while NOA could be there */
2335 if (ath9k_is_chanctx_enabled() &&
2336 ieee80211_is_nullfunc(hdr->frame_control) &&
2337 !txctl->force_channel)
2338 queue = true;
2339
2340 /* Force queueing of all frames that belong to a virtual interface on
2341 * a different channel context, to ensure that they are sent on the
2342 * correct channel.
2343 */
2344 if (((avp && avp->chanctx != sc->cur_chan) ||
2345 sc->cur_chan->stopped) && !txctl->force_channel) {
2346 if (!txctl->an)
2347 txctl->an = &avp->mcast_node;
2348 queue = true;
2349 skip_uapsd = true;
2350 }
2351
2352 if (txctl->an && queue)
2353 tid = ath_get_skb_tid(sc, txctl->an, skb);
2354
2355 if (!skip_uapsd && ps_resp) {
2356 ath_txq_unlock(sc, txq);
2357 txq = sc->tx.uapsdq;
2358 ath_txq_lock(sc, txq);
2359 } else if (txctl->an && queue) {
2360 WARN_ON(tid->txq != txctl->txq);
2361
2362 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2363 tid->clear_ps_filter = true;
2364
2365 /*
2366 * Add this frame to software queue for scheduling later
2367 * for aggregation.
2368 */
2369 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2370 __skb_queue_tail(&tid->buf_q, skb);
2371 if (!txctl->an->sleeping)
2372 ath_tx_queue_tid(sc, txq, tid);
2373
2374 ath_txq_schedule(sc, txq);
2375 goto out;
2376 }
2377
2378 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2379 if (!bf) {
2380 ath_txq_skb_done(sc, txq, skb);
2381 if (txctl->paprd)
2382 dev_kfree_skb_any(skb);
2383 else
2384 ieee80211_free_txskb(sc->hw, skb);
2385 goto out;
2386 }
2387
2388 bf->bf_state.bfs_paprd = txctl->paprd;
2389
2390 if (txctl->paprd)
2391 bf->bf_state.bfs_paprd_timestamp = jiffies;
2392
2393 ath_set_rates(vif, sta, bf);
2394 ath_tx_send_normal(sc, txq, tid, skb);
2395
2396out:
2397 ath_txq_unlock(sc, txq);
2398
2399 return 0;
2400}
2401
2402void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2403 struct sk_buff *skb)
2404{
2405 struct ath_softc *sc = hw->priv;
2406 struct ath_tx_control txctl = {
2407 .txq = sc->beacon.cabq
2408 };
2409 struct ath_tx_info info = {};
2410 struct ieee80211_hdr *hdr;
2411 struct ath_buf *bf_tail = NULL;
2412 struct ath_buf *bf;
2413 LIST_HEAD(bf_q);
2414 int duration = 0;
2415 int max_duration;
2416
2417 max_duration =
2418 sc->cur_chan->beacon.beacon_interval * 1000 *
2419 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2420
2421 do {
2422 struct ath_frame_info *fi = get_frame_info(skb);
2423
2424 if (ath_tx_prepare(hw, skb, &txctl))
2425 break;
2426
2427 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2428 if (!bf)
2429 break;
2430
2431 bf->bf_lastbf = bf;
2432 ath_set_rates(vif, NULL, bf);
2433 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2434 duration += info.rates[0].PktDuration;
2435 if (bf_tail)
2436 bf_tail->bf_next = bf;
2437
2438 list_add_tail(&bf->list, &bf_q);
2439 bf_tail = bf;
2440 skb = NULL;
2441
2442 if (duration > max_duration)
2443 break;
2444
2445 skb = ieee80211_get_buffered_bc(hw, vif);
2446 } while(skb);
2447
2448 if (skb)
2449 ieee80211_free_txskb(hw, skb);
2450
2451 if (list_empty(&bf_q))
2452 return;
2453
2454 bf = list_first_entry(&bf_q, struct ath_buf, list);
2455 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2456
2457 if (hdr->frame_control & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) {
2458 hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA);
2459 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2460 sizeof(*hdr), DMA_TO_DEVICE);
2461 }
2462
2463 ath_txq_lock(sc, txctl.txq);
2464 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2465 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2466 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2467 ath_txq_unlock(sc, txctl.txq);
2468}
2469
2470/*****************/
2471/* TX Completion */
2472/*****************/
2473
2474static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2475 int tx_flags, struct ath_txq *txq)
2476{
2477 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2478 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2479 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2480 int padpos, padsize;
2481 unsigned long flags;
2482
2483 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2484
2485 if (sc->sc_ah->caldata)
2486 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2487
2488 if (!(tx_flags & ATH_TX_ERROR)) {
2489 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2490 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2491 else
2492 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2493 }
2494
2495 padpos = ieee80211_hdrlen(hdr->frame_control);
2496 padsize = padpos & 3;
2497 if (padsize && skb->len>padpos+padsize) {
2498 /*
2499 * Remove MAC header padding before giving the frame back to
2500 * mac80211.
2501 */
2502 memmove(skb->data + padsize, skb->data, padpos);
2503 skb_pull(skb, padsize);
2504 }
2505
2506 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2507 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2508 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2509 ath_dbg(common, PS,
2510 "Going back to sleep after having received TX status (0x%lx)\n",
2511 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2512 PS_WAIT_FOR_CAB |
2513 PS_WAIT_FOR_PSPOLL_DATA |
2514 PS_WAIT_FOR_TX_ACK));
2515 }
2516 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2517
2518 __skb_queue_tail(&txq->complete_q, skb);
2519 ath_txq_skb_done(sc, txq, skb);
2520}
2521
2522static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2523 struct ath_txq *txq, struct list_head *bf_q,
2524 struct ath_tx_status *ts, int txok)
2525{
2526 struct sk_buff *skb = bf->bf_mpdu;
2527 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2528 unsigned long flags;
2529 int tx_flags = 0;
2530
2531 if (!txok)
2532 tx_flags |= ATH_TX_ERROR;
2533
2534 if (ts->ts_status & ATH9K_TXERR_FILT)
2535 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2536
2537 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2538 bf->bf_buf_addr = 0;
2539 if (sc->tx99_state)
2540 goto skip_tx_complete;
2541
2542 if (bf->bf_state.bfs_paprd) {
2543 if (time_after(jiffies,
2544 bf->bf_state.bfs_paprd_timestamp +
2545 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2546 dev_kfree_skb_any(skb);
2547 else
2548 complete(&sc->paprd_complete);
2549 } else {
2550 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2551 ath_tx_complete(sc, skb, tx_flags, txq);
2552 }
2553skip_tx_complete:
2554 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2555 * accidentally reference it later.
2556 */
2557 bf->bf_mpdu = NULL;
2558
2559 /*
2560 * Return the list of ath_buf of this mpdu to free queue
2561 */
2562 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2563 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2564 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2565}
2566
2567static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2568 struct ath_tx_status *ts, int nframes, int nbad,
2569 int txok)
2570{
2571 struct sk_buff *skb = bf->bf_mpdu;
2572 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2573 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2574 struct ieee80211_hw *hw = sc->hw;
2575 struct ath_hw *ah = sc->sc_ah;
2576 u8 i, tx_rateindex;
2577
2578 if (txok)
2579 tx_info->status.ack_signal = ts->ts_rssi;
2580
2581 tx_rateindex = ts->ts_rateindex;
2582 WARN_ON(tx_rateindex >= hw->max_rates);
2583
2584 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2585 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2586
2587 BUG_ON(nbad > nframes);
2588 }
2589 tx_info->status.ampdu_len = nframes;
2590 tx_info->status.ampdu_ack_len = nframes - nbad;
2591
2592 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2593 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2594 /*
2595 * If an underrun error is seen assume it as an excessive
2596 * retry only if max frame trigger level has been reached
2597 * (2 KB for single stream, and 4 KB for dual stream).
2598 * Adjust the long retry as if the frame was tried
2599 * hw->max_rate_tries times to affect how rate control updates
2600 * PER for the failed rate.
2601 * In case of congestion on the bus penalizing this type of
2602 * underruns should help hardware actually transmit new frames
2603 * successfully by eventually preferring slower rates.
2604 * This itself should also alleviate congestion on the bus.
2605 */
2606 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2607 ATH9K_TX_DELIM_UNDERRUN)) &&
2608 ieee80211_is_data(hdr->frame_control) &&
2609 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2610 tx_info->status.rates[tx_rateindex].count =
2611 hw->max_rate_tries;
2612 }
2613
2614 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2615 tx_info->status.rates[i].count = 0;
2616 tx_info->status.rates[i].idx = -1;
2617 }
2618
2619 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2620}
2621
2622static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2623{
2624 struct ath_hw *ah = sc->sc_ah;
2625 struct ath_common *common = ath9k_hw_common(ah);
2626 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2627 struct list_head bf_head;
2628 struct ath_desc *ds;
2629 struct ath_tx_status ts;
2630 int status;
2631
2632 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2633 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2634 txq->axq_link);
2635
2636 ath_txq_lock(sc, txq);
2637 for (;;) {
2638 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2639 break;
2640
2641 if (list_empty(&txq->axq_q)) {
2642 txq->axq_link = NULL;
2643 ath_txq_schedule(sc, txq);
2644 break;
2645 }
2646 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2647
2648 /*
2649 * There is a race condition that a BH gets scheduled
2650 * after sw writes TxE and before hw re-load the last
2651 * descriptor to get the newly chained one.
2652 * Software must keep the last DONE descriptor as a
2653 * holding descriptor - software does so by marking
2654 * it with the STALE flag.
2655 */
2656 bf_held = NULL;
2657 if (bf->bf_state.stale) {
2658 bf_held = bf;
2659 if (list_is_last(&bf_held->list, &txq->axq_q))
2660 break;
2661
2662 bf = list_entry(bf_held->list.next, struct ath_buf,
2663 list);
2664 }
2665
2666 lastbf = bf->bf_lastbf;
2667 ds = lastbf->bf_desc;
2668
2669 memset(&ts, 0, sizeof(ts));
2670 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2671 if (status == -EINPROGRESS)
2672 break;
2673
2674 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2675
2676 /*
2677 * Remove ath_buf's of the same transmit unit from txq,
2678 * however leave the last descriptor back as the holding
2679 * descriptor for hw.
2680 */
2681 lastbf->bf_state.stale = true;
2682 INIT_LIST_HEAD(&bf_head);
2683 if (!list_is_singular(&lastbf->list))
2684 list_cut_position(&bf_head,
2685 &txq->axq_q, lastbf->list.prev);
2686
2687 if (bf_held) {
2688 list_del(&bf_held->list);
2689 ath_tx_return_buffer(sc, bf_held);
2690 }
2691
2692 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2693 }
2694 ath_txq_unlock_complete(sc, txq);
2695}
2696
2697void ath_tx_tasklet(struct ath_softc *sc)
2698{
2699 struct ath_hw *ah = sc->sc_ah;
2700 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2701 int i;
2702
2703 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2704 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2705 ath_tx_processq(sc, &sc->tx.txq[i]);
2706 }
2707}
2708
2709void ath_tx_edma_tasklet(struct ath_softc *sc)
2710{
2711 struct ath_tx_status ts;
2712 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2713 struct ath_hw *ah = sc->sc_ah;
2714 struct ath_txq *txq;
2715 struct ath_buf *bf, *lastbf;
2716 struct list_head bf_head;
2717 struct list_head *fifo_list;
2718 int status;
2719
2720 for (;;) {
2721 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2722 break;
2723
2724 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2725 if (status == -EINPROGRESS)
2726 break;
2727 if (status == -EIO) {
2728 ath_dbg(common, XMIT, "Error processing tx status\n");
2729 break;
2730 }
2731
2732 /* Process beacon completions separately */
2733 if (ts.qid == sc->beacon.beaconq) {
2734 sc->beacon.tx_processed = true;
2735 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2736
2737 if (ath9k_is_chanctx_enabled()) {
2738 ath_chanctx_event(sc, NULL,
2739 ATH_CHANCTX_EVENT_BEACON_SENT);
2740 }
2741
2742 ath9k_csa_update(sc);
2743 continue;
2744 }
2745
2746 txq = &sc->tx.txq[ts.qid];
2747
2748 ath_txq_lock(sc, txq);
2749
2750 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2751
2752 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2753 if (list_empty(fifo_list)) {
2754 ath_txq_unlock(sc, txq);
2755 return;
2756 }
2757
2758 bf = list_first_entry(fifo_list, struct ath_buf, list);
2759 if (bf->bf_state.stale) {
2760 list_del(&bf->list);
2761 ath_tx_return_buffer(sc, bf);
2762 bf = list_first_entry(fifo_list, struct ath_buf, list);
2763 }
2764
2765 lastbf = bf->bf_lastbf;
2766
2767 INIT_LIST_HEAD(&bf_head);
2768 if (list_is_last(&lastbf->list, fifo_list)) {
2769 list_splice_tail_init(fifo_list, &bf_head);
2770 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2771
2772 if (!list_empty(&txq->axq_q)) {
2773 struct list_head bf_q;
2774
2775 INIT_LIST_HEAD(&bf_q);
2776 txq->axq_link = NULL;
2777 list_splice_tail_init(&txq->axq_q, &bf_q);
2778 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2779 }
2780 } else {
2781 lastbf->bf_state.stale = true;
2782 if (bf != lastbf)
2783 list_cut_position(&bf_head, fifo_list,
2784 lastbf->list.prev);
2785 }
2786
2787 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2788 ath_txq_unlock_complete(sc, txq);
2789 }
2790}
2791
2792/*****************/
2793/* Init, Cleanup */
2794/*****************/
2795
2796static int ath_txstatus_setup(struct ath_softc *sc, int size)
2797{
2798 struct ath_descdma *dd = &sc->txsdma;
2799 u8 txs_len = sc->sc_ah->caps.txs_len;
2800
2801 dd->dd_desc_len = size * txs_len;
2802 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2803 &dd->dd_desc_paddr, GFP_KERNEL);
2804 if (!dd->dd_desc)
2805 return -ENOMEM;
2806
2807 return 0;
2808}
2809
2810static int ath_tx_edma_init(struct ath_softc *sc)
2811{
2812 int err;
2813
2814 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2815 if (!err)
2816 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2817 sc->txsdma.dd_desc_paddr,
2818 ATH_TXSTATUS_RING_SIZE);
2819
2820 return err;
2821}
2822
2823int ath_tx_init(struct ath_softc *sc, int nbufs)
2824{
2825 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2826 int error = 0;
2827
2828 spin_lock_init(&sc->tx.txbuflock);
2829
2830 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2831 "tx", nbufs, 1, 1);
2832 if (error != 0) {
2833 ath_err(common,
2834 "Failed to allocate tx descriptors: %d\n", error);
2835 return error;
2836 }
2837
2838 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2839 "beacon", ATH_BCBUF, 1, 1);
2840 if (error != 0) {
2841 ath_err(common,
2842 "Failed to allocate beacon descriptors: %d\n", error);
2843 return error;
2844 }
2845
2846 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2847
2848 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2849 error = ath_tx_edma_init(sc);
2850
2851 return error;
2852}
2853
2854void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2855{
2856 struct ath_atx_tid *tid;
2857 int tidno, acno;
2858
2859 for (tidno = 0, tid = &an->tid[tidno];
2860 tidno < IEEE80211_NUM_TIDS;
2861 tidno++, tid++) {
2862 tid->an = an;
2863 tid->tidno = tidno;
2864 tid->seq_start = tid->seq_next = 0;
2865 tid->baw_size = WME_MAX_BA;
2866 tid->baw_head = tid->baw_tail = 0;
2867 tid->active = false;
2868 tid->clear_ps_filter = true;
2869 __skb_queue_head_init(&tid->buf_q);
2870 __skb_queue_head_init(&tid->retry_q);
2871 INIT_LIST_HEAD(&tid->list);
2872 acno = TID_TO_WME_AC(tidno);
2873 tid->txq = sc->tx.txq_map[acno];
2874 }
2875}
2876
2877void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2878{
2879 struct ath_atx_tid *tid;
2880 struct ath_txq *txq;
2881 int tidno;
2882
2883 for (tidno = 0, tid = &an->tid[tidno];
2884 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2885
2886 txq = tid->txq;
2887
2888 ath_txq_lock(sc, txq);
2889
2890 if (!list_empty(&tid->list))
2891 list_del_init(&tid->list);
2892
2893 ath_tid_drain(sc, txq, tid);
2894 tid->active = false;
2895
2896 ath_txq_unlock(sc, txq);
2897 }
2898}
2899
2900#ifdef CONFIG_ATH9K_TX99
2901
2902int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2903 struct ath_tx_control *txctl)
2904{
2905 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2906 struct ath_frame_info *fi = get_frame_info(skb);
2907 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2908 struct ath_buf *bf;
2909 int padpos, padsize;
2910
2911 padpos = ieee80211_hdrlen(hdr->frame_control);
2912 padsize = padpos & 3;
2913
2914 if (padsize && skb->len > padpos) {
2915 if (skb_headroom(skb) < padsize) {
2916 ath_dbg(common, XMIT,
2917 "tx99 padding failed\n");
2918 return -EINVAL;
2919 }
2920
2921 skb_push(skb, padsize);
2922 memmove(skb->data, skb->data + padsize, padpos);
2923 }
2924
2925 fi->keyix = ATH9K_TXKEYIX_INVALID;
2926 fi->framelen = skb->len + FCS_LEN;
2927 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2928
2929 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2930 if (!bf) {
2931 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2932 return -EINVAL;
2933 }
2934
2935 ath_set_rates(sc->tx99_vif, NULL, bf);
2936
2937 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2938 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2939
2940 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2941
2942 return 0;
2943}
2944
2945#endif /* CONFIG_ATH9K_TX99 */