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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/nl80211.h>
18#include <linux/delay.h>
19#include "ath9k.h"
20#include "btcoex.h"
21
22static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
23 u32 queues, bool drop);
24
25u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26{
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58}
59
60static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
61 bool sw_pending)
62{
63 bool pending = false;
64
65 spin_lock_bh(&txq->axq_lock);
66
67 if (txq->axq_depth) {
68 pending = true;
69 goto out;
70 }
71
72 if (!sw_pending)
73 goto out;
74
75 if (txq->mac80211_qnum >= 0) {
76 struct ath_acq *acq;
77
78 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
80 pending = true;
81 }
82out:
83 spin_unlock_bh(&txq->axq_lock);
84 return pending;
85}
86
87static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
88{
89 unsigned long flags;
90 bool ret;
91
92 spin_lock_irqsave(&sc->sc_pm_lock, flags);
93 ret = ath9k_hw_setpower(sc->sc_ah, mode);
94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
95
96 return ret;
97}
98
99void ath_ps_full_sleep(struct timer_list *t)
100{
101 struct ath_softc *sc = from_timer(sc, t, sleep_timer);
102 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
103 unsigned long flags;
104 bool reset;
105
106 spin_lock_irqsave(&common->cc_lock, flags);
107 ath_hw_cycle_counters_update(common);
108 spin_unlock_irqrestore(&common->cc_lock, flags);
109
110 ath9k_hw_setrxabort(sc->sc_ah, 1);
111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
112
113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
114}
115
116void ath9k_ps_wakeup(struct ath_softc *sc)
117{
118 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
119 unsigned long flags;
120 enum ath9k_power_mode power_mode;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (++sc->ps_usecount != 1)
124 goto unlock;
125
126 del_timer_sync(&sc->sleep_timer);
127 power_mode = sc->sc_ah->power_mode;
128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
129
130 /*
131 * While the hardware is asleep, the cycle counters contain no
132 * useful data. Better clear them now so that they don't mess up
133 * survey data results.
134 */
135 if (power_mode != ATH9K_PM_AWAKE) {
136 spin_lock(&common->cc_lock);
137 ath_hw_cycle_counters_update(common);
138 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
139 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
140 spin_unlock(&common->cc_lock);
141 }
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145}
146
147void ath9k_ps_restore(struct ath_softc *sc)
148{
149 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
150 enum ath9k_power_mode mode;
151 unsigned long flags;
152
153 spin_lock_irqsave(&sc->sc_pm_lock, flags);
154 if (--sc->ps_usecount != 0)
155 goto unlock;
156
157 if (sc->ps_idle) {
158 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
159 goto unlock;
160 }
161
162 if (sc->ps_enabled &&
163 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
164 PS_WAIT_FOR_CAB |
165 PS_WAIT_FOR_PSPOLL_DATA |
166 PS_WAIT_FOR_TX_ACK |
167 PS_WAIT_FOR_ANI))) {
168 mode = ATH9K_PM_NETWORK_SLEEP;
169 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
170 ath9k_btcoex_stop_gen_timer(sc);
171 } else {
172 goto unlock;
173 }
174
175 spin_lock(&common->cc_lock);
176 ath_hw_cycle_counters_update(common);
177 spin_unlock(&common->cc_lock);
178
179 ath9k_hw_setpower(sc->sc_ah, mode);
180
181 unlock:
182 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
183}
184
185static void __ath_cancel_work(struct ath_softc *sc)
186{
187 cancel_work_sync(&sc->paprd_work);
188 cancel_delayed_work_sync(&sc->hw_check_work);
189 cancel_delayed_work_sync(&sc->hw_pll_work);
190
191#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
192 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
193 cancel_work_sync(&sc->mci_work);
194#endif
195}
196
197void ath_cancel_work(struct ath_softc *sc)
198{
199 __ath_cancel_work(sc);
200 cancel_work_sync(&sc->hw_reset_work);
201}
202
203void ath_restart_work(struct ath_softc *sc)
204{
205 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
206 msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
207
208 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
209 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
210 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
211
212 ath_start_ani(sc);
213}
214
215static bool ath_prepare_reset(struct ath_softc *sc)
216{
217 struct ath_hw *ah = sc->sc_ah;
218 bool ret = true;
219
220 ieee80211_stop_queues(sc->hw);
221 ath_stop_ani(sc);
222 ath9k_hw_disable_interrupts(ah);
223
224 if (AR_SREV_9300_20_OR_LATER(ah)) {
225 ret &= ath_stoprecv(sc);
226 ret &= ath_drain_all_txq(sc);
227 } else {
228 ret &= ath_drain_all_txq(sc);
229 ret &= ath_stoprecv(sc);
230 }
231
232 return ret;
233}
234
235static bool ath_complete_reset(struct ath_softc *sc, bool start)
236{
237 struct ath_hw *ah = sc->sc_ah;
238 struct ath_common *common = ath9k_hw_common(ah);
239 unsigned long flags;
240
241 ath9k_calculate_summary_state(sc, sc->cur_chan);
242 ath_startrecv(sc);
243 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
244 sc->cur_chan->txpower,
245 &sc->cur_chan->cur_txpower);
246 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
247
248 if (!sc->cur_chan->offchannel && start) {
249 /* restore per chanctx TSF timer */
250 if (sc->cur_chan->tsf_val) {
251 u32 offset;
252
253 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
254 NULL);
255 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
256 }
257
258
259 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
260 goto work;
261
262 if (ah->opmode == NL80211_IFTYPE_STATION &&
263 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
264 spin_lock_irqsave(&sc->sc_pm_lock, flags);
265 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267 } else {
268 ath9k_set_beacon(sc);
269 }
270 work:
271 ath_restart_work(sc);
272 ath_txq_schedule_all(sc);
273 }
274
275 sc->gtt_cnt = 0;
276
277 ath9k_hw_set_interrupts(ah);
278 ath9k_hw_enable_interrupts(ah);
279 ieee80211_wake_queues(sc->hw);
280 ath9k_p2p_ps_timer(sc);
281
282 return true;
283}
284
285static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
286{
287 struct ath_hw *ah = sc->sc_ah;
288 struct ath_common *common = ath9k_hw_common(ah);
289 struct ath9k_hw_cal_data *caldata = NULL;
290 bool fastcc = true;
291 int r;
292
293 __ath_cancel_work(sc);
294
295 disable_irq(sc->irq);
296 tasklet_disable(&sc->intr_tq);
297 tasklet_disable(&sc->bcon_tasklet);
298 spin_lock_bh(&sc->sc_pcu_lock);
299
300 if (!sc->cur_chan->offchannel) {
301 fastcc = false;
302 caldata = &sc->cur_chan->caldata;
303 }
304
305 if (!hchan) {
306 fastcc = false;
307 hchan = ah->curchan;
308 }
309
310 if (!hchan) {
311 fastcc = false;
312 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
313 }
314
315 if (!ath_prepare_reset(sc))
316 fastcc = false;
317
318 if (ath9k_is_chanctx_enabled())
319 fastcc = false;
320
321 spin_lock_bh(&sc->chan_lock);
322 sc->cur_chandef = sc->cur_chan->chandef;
323 spin_unlock_bh(&sc->chan_lock);
324
325 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
326 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
327
328 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
329 if (r) {
330 ath_err(common,
331 "Unable to reset channel, reset status %d\n", r);
332
333 ath9k_hw_enable_interrupts(ah);
334 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
335
336 goto out;
337 }
338
339 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
340 sc->cur_chan->offchannel)
341 ath9k_mci_set_txpower(sc, true, false);
342
343 if (!ath_complete_reset(sc, true))
344 r = -EIO;
345
346out:
347 enable_irq(sc->irq);
348 spin_unlock_bh(&sc->sc_pcu_lock);
349 tasklet_enable(&sc->bcon_tasklet);
350 tasklet_enable(&sc->intr_tq);
351
352 return r;
353}
354
355static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
356 struct ieee80211_vif *vif)
357{
358 struct ath_node *an;
359 an = (struct ath_node *)sta->drv_priv;
360
361 an->sc = sc;
362 an->sta = sta;
363 an->vif = vif;
364 memset(&an->key_idx, 0, sizeof(an->key_idx));
365
366 ath_tx_node_init(sc, an);
367
368 ath_dynack_node_init(sc->sc_ah, an);
369}
370
371static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
372{
373 struct ath_node *an = (struct ath_node *)sta->drv_priv;
374 ath_tx_node_cleanup(sc, an);
375
376 ath_dynack_node_deinit(sc->sc_ah, an);
377}
378
379void ath9k_tasklet(struct tasklet_struct *t)
380{
381 struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
382 struct ath_hw *ah = sc->sc_ah;
383 struct ath_common *common = ath9k_hw_common(ah);
384 enum ath_reset_type type;
385 unsigned long flags;
386 u32 status;
387 u32 rxmask;
388
389 spin_lock_irqsave(&sc->intr_lock, flags);
390 status = sc->intrstatus;
391 sc->intrstatus = 0;
392 spin_unlock_irqrestore(&sc->intr_lock, flags);
393
394 ath9k_ps_wakeup(sc);
395 spin_lock(&sc->sc_pcu_lock);
396
397 if (status & ATH9K_INT_FATAL) {
398 type = RESET_TYPE_FATAL_INT;
399 ath9k_queue_reset(sc, type);
400 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
401 goto out;
402 }
403
404 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
405 (status & ATH9K_INT_BB_WATCHDOG)) {
406 spin_lock_irqsave(&common->cc_lock, flags);
407 ath_hw_cycle_counters_update(common);
408 ar9003_hw_bb_watchdog_dbg_info(ah);
409 spin_unlock_irqrestore(&common->cc_lock, flags);
410
411 if (ar9003_hw_bb_watchdog_check(ah)) {
412 type = RESET_TYPE_BB_WATCHDOG;
413 ath9k_queue_reset(sc, type);
414
415 ath_dbg(common, RESET,
416 "BB_WATCHDOG: Skipping interrupts\n");
417 goto out;
418 }
419 }
420
421 if (status & ATH9K_INT_GTT) {
422 sc->gtt_cnt++;
423
424 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
425 type = RESET_TYPE_TX_GTT;
426 ath9k_queue_reset(sc, type);
427 ath_dbg(common, RESET,
428 "GTT: Skipping interrupts\n");
429 goto out;
430 }
431 }
432
433 spin_lock_irqsave(&sc->sc_pm_lock, flags);
434 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
435 /*
436 * TSF sync does not look correct; remain awake to sync with
437 * the next Beacon.
438 */
439 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
440 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
441 }
442 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
443
444 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
445 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
446 ATH9K_INT_RXORN);
447 else
448 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
449
450 if (status & rxmask) {
451 /* Check for high priority Rx first */
452 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
453 (status & ATH9K_INT_RXHP))
454 ath_rx_tasklet(sc, 0, true);
455
456 ath_rx_tasklet(sc, 0, false);
457 }
458
459 if (status & ATH9K_INT_TX) {
460 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
461 /*
462 * For EDMA chips, TX completion is enabled for the
463 * beacon queue, so if a beacon has been transmitted
464 * successfully after a GTT interrupt, the GTT counter
465 * gets reset to zero here.
466 */
467 sc->gtt_cnt = 0;
468
469 ath_tx_edma_tasklet(sc);
470 } else {
471 ath_tx_tasklet(sc);
472 }
473
474 wake_up(&sc->tx_wait);
475 }
476
477 if (status & ATH9K_INT_GENTIMER)
478 ath_gen_timer_isr(sc->sc_ah);
479
480 ath9k_btcoex_handle_interrupt(sc, status);
481
482 /* re-enable hardware interrupt */
483 ath9k_hw_resume_interrupts(ah);
484out:
485 spin_unlock(&sc->sc_pcu_lock);
486 ath9k_ps_restore(sc);
487}
488
489irqreturn_t ath_isr(int irq, void *dev)
490{
491#define SCHED_INTR ( \
492 ATH9K_INT_FATAL | \
493 ATH9K_INT_BB_WATCHDOG | \
494 ATH9K_INT_RXORN | \
495 ATH9K_INT_RXEOL | \
496 ATH9K_INT_RX | \
497 ATH9K_INT_RXLP | \
498 ATH9K_INT_RXHP | \
499 ATH9K_INT_TX | \
500 ATH9K_INT_BMISS | \
501 ATH9K_INT_CST | \
502 ATH9K_INT_GTT | \
503 ATH9K_INT_TSFOOR | \
504 ATH9K_INT_GENTIMER | \
505 ATH9K_INT_MCI)
506
507 struct ath_softc *sc = dev;
508 struct ath_hw *ah = sc->sc_ah;
509 struct ath_common *common = ath9k_hw_common(ah);
510 enum ath9k_int status;
511 u32 sync_cause = 0;
512 bool sched = false;
513
514 /*
515 * The hardware is not ready/present, don't
516 * touch anything. Note this can happen early
517 * on if the IRQ is shared.
518 */
519 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
520 return IRQ_NONE;
521
522 /* shared irq, not for us */
523 if (!ath9k_hw_intrpend(ah))
524 return IRQ_NONE;
525
526 /*
527 * Figure out the reason(s) for the interrupt. Note
528 * that the hal returns a pseudo-ISR that may include
529 * bits we haven't explicitly enabled so we mask the
530 * value to insure we only process bits we requested.
531 */
532 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
533 ath9k_debug_sync_cause(sc, sync_cause);
534 status &= ah->imask; /* discard unasked-for bits */
535
536 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
537 ath9k_hw_kill_interrupts(sc->sc_ah);
538 return IRQ_HANDLED;
539 }
540
541 /*
542 * If there are no status bits set, then this interrupt was not
543 * for me (should have been caught above).
544 */
545 if (!status)
546 return IRQ_NONE;
547
548 /* Cache the status */
549 spin_lock(&sc->intr_lock);
550 sc->intrstatus |= status;
551 spin_unlock(&sc->intr_lock);
552
553 if (status & SCHED_INTR)
554 sched = true;
555
556 /*
557 * If a FATAL interrupt is received, we have to reset the chip
558 * immediately.
559 */
560 if (status & ATH9K_INT_FATAL)
561 goto chip_reset;
562
563 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
564 (status & ATH9K_INT_BB_WATCHDOG))
565 goto chip_reset;
566
567 if (status & ATH9K_INT_SWBA)
568 tasklet_schedule(&sc->bcon_tasklet);
569
570 if (status & ATH9K_INT_TXURN)
571 ath9k_hw_updatetxtriglevel(ah, true);
572
573 if (status & ATH9K_INT_RXEOL) {
574 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
575 ath9k_hw_set_interrupts(ah);
576 }
577
578 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
579 if (status & ATH9K_INT_TIM_TIMER) {
580 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
581 goto chip_reset;
582 /* Clear RxAbort bit so that we can
583 * receive frames */
584 ath9k_setpower(sc, ATH9K_PM_AWAKE);
585 spin_lock(&sc->sc_pm_lock);
586 ath9k_hw_setrxabort(sc->sc_ah, 0);
587 sc->ps_flags |= PS_WAIT_FOR_BEACON;
588 spin_unlock(&sc->sc_pm_lock);
589 }
590
591chip_reset:
592
593 ath_debug_stat_interrupt(sc, status);
594
595 if (sched) {
596 /* turn off every interrupt */
597 ath9k_hw_kill_interrupts(ah);
598 tasklet_schedule(&sc->intr_tq);
599 }
600
601 return IRQ_HANDLED;
602
603#undef SCHED_INTR
604}
605
606/*
607 * This function is called when a HW reset cannot be deferred
608 * and has to be immediate.
609 */
610int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
611{
612 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
613 int r;
614
615 ath9k_hw_kill_interrupts(sc->sc_ah);
616 set_bit(ATH_OP_HW_RESET, &common->op_flags);
617
618 ath9k_ps_wakeup(sc);
619 r = ath_reset_internal(sc, hchan);
620 ath9k_ps_restore(sc);
621
622 return r;
623}
624
625/*
626 * When a HW reset can be deferred, it is added to the
627 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
628 * queueing.
629 */
630void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
631{
632 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
633#ifdef CONFIG_ATH9K_DEBUGFS
634 RESET_STAT_INC(sc, type);
635#endif
636 ath9k_hw_kill_interrupts(sc->sc_ah);
637 set_bit(ATH_OP_HW_RESET, &common->op_flags);
638 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
639}
640
641void ath_reset_work(struct work_struct *work)
642{
643 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
644
645 ath9k_ps_wakeup(sc);
646 ath_reset_internal(sc, NULL);
647 ath9k_ps_restore(sc);
648}
649
650/**********************/
651/* mac80211 callbacks */
652/**********************/
653
654static int ath9k_start(struct ieee80211_hw *hw)
655{
656 struct ath_softc *sc = hw->priv;
657 struct ath_hw *ah = sc->sc_ah;
658 struct ath_common *common = ath9k_hw_common(ah);
659 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
660 struct ath_chanctx *ctx = sc->cur_chan;
661 struct ath9k_channel *init_channel;
662 int r;
663
664 ath_dbg(common, CONFIG,
665 "Starting driver with initial channel: %d MHz\n",
666 curchan->center_freq);
667
668 ath9k_ps_wakeup(sc);
669 mutex_lock(&sc->mutex);
670
671 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
672 sc->cur_chandef = hw->conf.chandef;
673
674 /* Reset SERDES registers */
675 ath9k_hw_configpcipowersave(ah, false);
676
677 /*
678 * The basic interface to setting the hardware in a good
679 * state is ``reset''. On return the hardware is known to
680 * be powered up and with interrupts disabled. This must
681 * be followed by initialization of the appropriate bits
682 * and then setup of the interrupt mask.
683 */
684 spin_lock_bh(&sc->sc_pcu_lock);
685
686 atomic_set(&ah->intr_ref_cnt, -1);
687
688 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
689 if (r) {
690 ath_err(common,
691 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
692 r, curchan->center_freq);
693 ah->reset_power_on = false;
694 }
695
696 /* Setup our intr mask. */
697 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
698 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
699 ATH9K_INT_GLOBAL;
700
701 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
702 ah->imask |= ATH9K_INT_RXHP |
703 ATH9K_INT_RXLP;
704 else
705 ah->imask |= ATH9K_INT_RX;
706
707 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
708 ah->imask |= ATH9K_INT_BB_WATCHDOG;
709
710 /*
711 * Enable GTT interrupts only for AR9003/AR9004 chips
712 * for now.
713 */
714 if (AR_SREV_9300_20_OR_LATER(ah))
715 ah->imask |= ATH9K_INT_GTT;
716
717 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
718 ah->imask |= ATH9K_INT_CST;
719
720 ath_mci_enable(sc);
721
722 clear_bit(ATH_OP_INVALID, &common->op_flags);
723 sc->sc_ah->is_monitoring = false;
724
725 if (!ath_complete_reset(sc, false))
726 ah->reset_power_on = false;
727
728 if (ah->led_pin >= 0) {
729 ath9k_hw_set_gpio(ah, ah->led_pin,
730 (ah->config.led_active_high) ? 1 : 0);
731 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
732 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
733 }
734
735 /*
736 * Reset key cache to sane defaults (all entries cleared) instead of
737 * semi-random values after suspend/resume.
738 */
739 ath9k_cmn_init_crypto(sc->sc_ah);
740
741 ath9k_hw_reset_tsf(ah);
742
743 spin_unlock_bh(&sc->sc_pcu_lock);
744
745 ath9k_rng_start(sc);
746
747 mutex_unlock(&sc->mutex);
748
749 ath9k_ps_restore(sc);
750
751 return 0;
752}
753
754static void ath9k_tx(struct ieee80211_hw *hw,
755 struct ieee80211_tx_control *control,
756 struct sk_buff *skb)
757{
758 struct ath_softc *sc = hw->priv;
759 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
760 struct ath_tx_control txctl;
761 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
762 unsigned long flags;
763
764 if (sc->ps_enabled) {
765 /*
766 * mac80211 does not set PM field for normal data frames, so we
767 * need to update that based on the current PS mode.
768 */
769 if (ieee80211_is_data(hdr->frame_control) &&
770 !ieee80211_is_nullfunc(hdr->frame_control) &&
771 !ieee80211_has_pm(hdr->frame_control)) {
772 ath_dbg(common, PS,
773 "Add PM=1 for a TX frame while in PS mode\n");
774 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
775 }
776 }
777
778 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
779 /*
780 * We are using PS-Poll and mac80211 can request TX while in
781 * power save mode. Need to wake up hardware for the TX to be
782 * completed and if needed, also for RX of buffered frames.
783 */
784 ath9k_ps_wakeup(sc);
785 spin_lock_irqsave(&sc->sc_pm_lock, flags);
786 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
787 ath9k_hw_setrxabort(sc->sc_ah, 0);
788 if (ieee80211_is_pspoll(hdr->frame_control)) {
789 ath_dbg(common, PS,
790 "Sending PS-Poll to pick a buffered frame\n");
791 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
792 } else {
793 ath_dbg(common, PS, "Wake up to complete TX\n");
794 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
795 }
796 /*
797 * The actual restore operation will happen only after
798 * the ps_flags bit is cleared. We are just dropping
799 * the ps_usecount here.
800 */
801 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
802 ath9k_ps_restore(sc);
803 }
804
805 /*
806 * Cannot tx while the hardware is in full sleep, it first needs a full
807 * chip reset to recover from that
808 */
809 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
810 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
811 goto exit;
812 }
813
814 memset(&txctl, 0, sizeof(struct ath_tx_control));
815 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
816 txctl.sta = control->sta;
817
818 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
819
820 if (ath_tx_start(hw, skb, &txctl) != 0) {
821 ath_dbg(common, XMIT, "TX failed\n");
822 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
823 goto exit;
824 }
825
826 return;
827exit:
828 ieee80211_free_txskb(hw, skb);
829}
830
831static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
832{
833 struct ath_buf *bf;
834 struct ieee80211_tx_info *txinfo;
835 struct ath_frame_info *fi;
836
837 list_for_each_entry(bf, txq_list, list) {
838 if (bf->bf_state.stale || !bf->bf_mpdu)
839 continue;
840
841 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
842 fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0];
843 if (fi->keyix == keyix)
844 return true;
845 }
846
847 return false;
848}
849
850static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
851{
852 struct ath_hw *ah = sc->sc_ah;
853 int i, j;
854 struct ath_txq *txq;
855 bool key_in_use = false;
856
857 for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
858 if (!ATH_TXQ_SETUP(sc, i))
859 continue;
860 txq = &sc->tx.txq[i];
861 if (!txq->axq_depth)
862 continue;
863 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
864 continue;
865
866 ath_txq_lock(sc, txq);
867 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
868 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
869 int idx = txq->txq_tailidx;
870
871 for (j = 0; !key_in_use &&
872 !list_empty(&txq->txq_fifo[idx]) &&
873 j < ATH_TXFIFO_DEPTH; j++) {
874 key_in_use = ath9k_txq_list_has_key(
875 &txq->txq_fifo[idx], keyix);
876 INCR(idx, ATH_TXFIFO_DEPTH);
877 }
878 }
879 ath_txq_unlock(sc, txq);
880 }
881
882 return key_in_use;
883}
884
885static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
886{
887 struct ath_hw *ah = sc->sc_ah;
888 struct ath_common *common = ath9k_hw_common(ah);
889
890 if (!test_bit(keyix, ah->pending_del_keymap) ||
891 ath9k_txq_has_key(sc, keyix))
892 return;
893
894 /* No more TXQ frames point to this key cache entry, so delete it. */
895 clear_bit(keyix, ah->pending_del_keymap);
896 ath_key_delete(common, keyix);
897}
898
899static void ath9k_stop(struct ieee80211_hw *hw)
900{
901 struct ath_softc *sc = hw->priv;
902 struct ath_hw *ah = sc->sc_ah;
903 struct ath_common *common = ath9k_hw_common(ah);
904 bool prev_idle;
905 int i;
906
907 ath9k_deinit_channel_context(sc);
908
909 mutex_lock(&sc->mutex);
910
911 ath9k_rng_stop(sc);
912
913 ath_cancel_work(sc);
914
915 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
916 ath_dbg(common, ANY, "Device not present\n");
917 mutex_unlock(&sc->mutex);
918 return;
919 }
920
921 /* Ensure HW is awake when we try to shut it down. */
922 ath9k_ps_wakeup(sc);
923
924 spin_lock_bh(&sc->sc_pcu_lock);
925
926 /* prevent tasklets to enable interrupts once we disable them */
927 ah->imask &= ~ATH9K_INT_GLOBAL;
928
929 /* make sure h/w will not generate any interrupt
930 * before setting the invalid flag. */
931 ath9k_hw_disable_interrupts(ah);
932
933 spin_unlock_bh(&sc->sc_pcu_lock);
934
935 /* we can now sync irq and kill any running tasklets, since we already
936 * disabled interrupts and not holding a spin lock */
937 synchronize_irq(sc->irq);
938 tasklet_kill(&sc->intr_tq);
939 tasklet_kill(&sc->bcon_tasklet);
940
941 prev_idle = sc->ps_idle;
942 sc->ps_idle = true;
943
944 spin_lock_bh(&sc->sc_pcu_lock);
945
946 if (ah->led_pin >= 0) {
947 ath9k_hw_set_gpio(ah, ah->led_pin,
948 (ah->config.led_active_high) ? 0 : 1);
949 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
950 }
951
952 ath_prepare_reset(sc);
953
954 if (sc->rx.frag) {
955 dev_kfree_skb_any(sc->rx.frag);
956 sc->rx.frag = NULL;
957 }
958
959 if (!ah->curchan)
960 ah->curchan = ath9k_cmn_get_channel(hw, ah,
961 &sc->cur_chan->chandef);
962
963 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
964
965 set_bit(ATH_OP_INVALID, &common->op_flags);
966
967 ath9k_hw_phy_disable(ah);
968
969 ath9k_hw_configpcipowersave(ah, true);
970
971 spin_unlock_bh(&sc->sc_pcu_lock);
972
973 for (i = 0; i < ATH_KEYMAX; i++)
974 ath9k_pending_key_del(sc, i);
975
976 /* Clear key cache entries explicitly to get rid of any potentially
977 * remaining keys.
978 */
979 ath9k_cmn_init_crypto(sc->sc_ah);
980
981 ath9k_ps_restore(sc);
982
983 sc->ps_idle = prev_idle;
984
985 mutex_unlock(&sc->mutex);
986
987 ath_dbg(common, CONFIG, "Driver halt\n");
988}
989
990static bool ath9k_uses_beacons(int type)
991{
992 switch (type) {
993 case NL80211_IFTYPE_AP:
994 case NL80211_IFTYPE_ADHOC:
995 case NL80211_IFTYPE_MESH_POINT:
996 return true;
997 default:
998 return false;
999 }
1000}
1001
1002static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
1003 struct ieee80211_vif *vif)
1004{
1005 /* Use the first (configured) interface, but prefering AP interfaces. */
1006 if (!iter_data->primary_beacon_vif) {
1007 iter_data->primary_beacon_vif = vif;
1008 } else {
1009 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1010 vif->type == NL80211_IFTYPE_AP)
1011 iter_data->primary_beacon_vif = vif;
1012 }
1013
1014 iter_data->beacons = true;
1015 iter_data->nbcnvifs += 1;
1016}
1017
1018static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1019 u8 *mac, struct ieee80211_vif *vif)
1020{
1021 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1022 int i;
1023
1024 if (iter_data->has_hw_macaddr) {
1025 for (i = 0; i < ETH_ALEN; i++)
1026 iter_data->mask[i] &=
1027 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1028 } else {
1029 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1030 iter_data->has_hw_macaddr = true;
1031 }
1032
1033 if (!vif->bss_conf.use_short_slot)
1034 iter_data->slottime = 20;
1035
1036 switch (vif->type) {
1037 case NL80211_IFTYPE_AP:
1038 iter_data->naps++;
1039 if (vif->bss_conf.enable_beacon)
1040 ath9k_vif_iter_set_beacon(iter_data, vif);
1041 break;
1042 case NL80211_IFTYPE_STATION:
1043 iter_data->nstations++;
1044 if (avp->assoc && !iter_data->primary_sta)
1045 iter_data->primary_sta = vif;
1046 break;
1047 case NL80211_IFTYPE_OCB:
1048 iter_data->nocbs++;
1049 break;
1050 case NL80211_IFTYPE_ADHOC:
1051 iter_data->nadhocs++;
1052 if (vif->bss_conf.enable_beacon)
1053 ath9k_vif_iter_set_beacon(iter_data, vif);
1054 break;
1055 case NL80211_IFTYPE_MESH_POINT:
1056 iter_data->nmeshes++;
1057 if (vif->bss_conf.enable_beacon)
1058 ath9k_vif_iter_set_beacon(iter_data, vif);
1059 break;
1060 default:
1061 break;
1062 }
1063}
1064
1065static void ath9k_update_bssid_mask(struct ath_softc *sc,
1066 struct ath_chanctx *ctx,
1067 struct ath9k_vif_iter_data *iter_data)
1068{
1069 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1070 struct ath_vif *avp;
1071 int i;
1072
1073 if (!ath9k_is_chanctx_enabled())
1074 return;
1075
1076 list_for_each_entry(avp, &ctx->vifs, list) {
1077 if (ctx->nvifs_assigned != 1)
1078 continue;
1079
1080 if (!iter_data->has_hw_macaddr)
1081 continue;
1082
1083 ether_addr_copy(common->curbssid, avp->bssid);
1084
1085 /* perm_addr will be used as the p2p device address. */
1086 for (i = 0; i < ETH_ALEN; i++)
1087 iter_data->mask[i] &=
1088 ~(iter_data->hw_macaddr[i] ^
1089 sc->hw->wiphy->perm_addr[i]);
1090 }
1091}
1092
1093/* Called with sc->mutex held. */
1094void ath9k_calculate_iter_data(struct ath_softc *sc,
1095 struct ath_chanctx *ctx,
1096 struct ath9k_vif_iter_data *iter_data)
1097{
1098 struct ath_vif *avp;
1099
1100 /*
1101 * The hardware will use primary station addr together with the
1102 * BSSID mask when matching addresses.
1103 */
1104 memset(iter_data, 0, sizeof(*iter_data));
1105 eth_broadcast_addr(iter_data->mask);
1106 iter_data->slottime = 9;
1107
1108 list_for_each_entry(avp, &ctx->vifs, list)
1109 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1110
1111 ath9k_update_bssid_mask(sc, ctx, iter_data);
1112}
1113
1114static void ath9k_set_assoc_state(struct ath_softc *sc,
1115 struct ieee80211_vif *vif, bool changed)
1116{
1117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1118 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1119 unsigned long flags;
1120
1121 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1122
1123 ether_addr_copy(common->curbssid, avp->bssid);
1124 common->curaid = avp->aid;
1125 ath9k_hw_write_associd(sc->sc_ah);
1126
1127 if (changed) {
1128 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1129 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1130
1131 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1132 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1134 }
1135
1136 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1137 ath9k_mci_update_wlan_channels(sc, false);
1138
1139 ath_dbg(common, CONFIG,
1140 "Primary Station interface: %pM, BSSID: %pM\n",
1141 vif->addr, common->curbssid);
1142}
1143
1144#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1145static void ath9k_set_offchannel_state(struct ath_softc *sc)
1146{
1147 struct ath_hw *ah = sc->sc_ah;
1148 struct ath_common *common = ath9k_hw_common(ah);
1149 struct ieee80211_vif *vif = NULL;
1150
1151 ath9k_ps_wakeup(sc);
1152
1153 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1154 vif = sc->offchannel.scan_vif;
1155 else
1156 vif = sc->offchannel.roc_vif;
1157
1158 if (WARN_ON(!vif))
1159 goto exit;
1160
1161 eth_zero_addr(common->curbssid);
1162 eth_broadcast_addr(common->bssidmask);
1163 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1164 common->curaid = 0;
1165 ah->opmode = vif->type;
1166 ah->imask &= ~ATH9K_INT_SWBA;
1167 ah->imask &= ~ATH9K_INT_TSFOOR;
1168 ah->slottime = 9;
1169
1170 ath_hw_setbssidmask(common);
1171 ath9k_hw_setopmode(ah);
1172 ath9k_hw_write_associd(sc->sc_ah);
1173 ath9k_hw_set_interrupts(ah);
1174 ath9k_hw_init_global_settings(ah);
1175
1176exit:
1177 ath9k_ps_restore(sc);
1178}
1179#endif
1180
1181/* Called with sc->mutex held. */
1182void ath9k_calculate_summary_state(struct ath_softc *sc,
1183 struct ath_chanctx *ctx)
1184{
1185 struct ath_hw *ah = sc->sc_ah;
1186 struct ath_common *common = ath9k_hw_common(ah);
1187 struct ath9k_vif_iter_data iter_data;
1188
1189 ath_chanctx_check_active(sc, ctx);
1190
1191 if (ctx != sc->cur_chan)
1192 return;
1193
1194#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1195 if (ctx == &sc->offchannel.chan)
1196 return ath9k_set_offchannel_state(sc);
1197#endif
1198
1199 ath9k_ps_wakeup(sc);
1200 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1201
1202 if (iter_data.has_hw_macaddr)
1203 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1204
1205 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1206 ath_hw_setbssidmask(common);
1207
1208 if (iter_data.naps > 0) {
1209 ath9k_hw_set_tsfadjust(ah, true);
1210 ah->opmode = NL80211_IFTYPE_AP;
1211 } else {
1212 ath9k_hw_set_tsfadjust(ah, false);
1213 if (iter_data.beacons)
1214 ath9k_beacon_ensure_primary_slot(sc);
1215
1216 if (iter_data.nmeshes)
1217 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1218 else if (iter_data.nocbs)
1219 ah->opmode = NL80211_IFTYPE_OCB;
1220 else if (iter_data.nadhocs)
1221 ah->opmode = NL80211_IFTYPE_ADHOC;
1222 else
1223 ah->opmode = NL80211_IFTYPE_STATION;
1224 }
1225
1226 ath9k_hw_setopmode(ah);
1227
1228 ctx->switch_after_beacon = false;
1229 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1230 ah->imask |= ATH9K_INT_TSFOOR;
1231 else {
1232 ah->imask &= ~ATH9K_INT_TSFOOR;
1233 if (iter_data.naps == 1 && iter_data.beacons)
1234 ctx->switch_after_beacon = true;
1235 }
1236
1237 if (ah->opmode == NL80211_IFTYPE_STATION) {
1238 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1239
1240 if (iter_data.primary_sta) {
1241 iter_data.primary_beacon_vif = iter_data.primary_sta;
1242 iter_data.beacons = true;
1243 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1244 changed);
1245 ctx->primary_sta = iter_data.primary_sta;
1246 } else {
1247 ctx->primary_sta = NULL;
1248 eth_zero_addr(common->curbssid);
1249 common->curaid = 0;
1250 ath9k_hw_write_associd(sc->sc_ah);
1251 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1252 ath9k_mci_update_wlan_channels(sc, true);
1253 }
1254 }
1255 sc->nbcnvifs = iter_data.nbcnvifs;
1256 ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1257 iter_data.beacons);
1258 ath9k_hw_set_interrupts(ah);
1259
1260 if (ah->slottime != iter_data.slottime) {
1261 ah->slottime = iter_data.slottime;
1262 ath9k_hw_init_global_settings(ah);
1263 }
1264
1265 if (iter_data.primary_sta)
1266 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1267 else
1268 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1269
1270 ath_dbg(common, CONFIG,
1271 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1272 common->macaddr, common->curbssid, common->bssidmask);
1273
1274 ath9k_ps_restore(sc);
1275}
1276
1277static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1278{
1279 int *power = data;
1280
1281 if (vif->bss_conf.txpower == INT_MIN)
1282 return;
1283
1284 if (*power < vif->bss_conf.txpower)
1285 *power = vif->bss_conf.txpower;
1286}
1287
1288/* Called with sc->mutex held. */
1289void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1290{
1291 int power;
1292 struct ath_hw *ah = sc->sc_ah;
1293 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1294
1295 ath9k_ps_wakeup(sc);
1296 if (ah->tpc_enabled) {
1297 power = (vif) ? vif->bss_conf.txpower : -1;
1298 ieee80211_iterate_active_interfaces_atomic(
1299 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1300 ath9k_tpc_vif_iter, &power);
1301 if (power == -1)
1302 power = sc->hw->conf.power_level;
1303 } else {
1304 power = sc->hw->conf.power_level;
1305 }
1306 sc->cur_chan->txpower = 2 * power;
1307 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1308 sc->cur_chan->cur_txpower = reg->max_power_level;
1309 ath9k_ps_restore(sc);
1310}
1311
1312static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1313 struct ieee80211_vif *vif)
1314{
1315 int i;
1316
1317 if (!ath9k_is_chanctx_enabled())
1318 return;
1319
1320 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1321 vif->hw_queue[i] = i;
1322
1323 if (vif->type == NL80211_IFTYPE_AP ||
1324 vif->type == NL80211_IFTYPE_MESH_POINT)
1325 vif->cab_queue = hw->queues - 2;
1326 else
1327 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1328}
1329
1330static int ath9k_add_interface(struct ieee80211_hw *hw,
1331 struct ieee80211_vif *vif)
1332{
1333 struct ath_softc *sc = hw->priv;
1334 struct ath_hw *ah = sc->sc_ah;
1335 struct ath_common *common = ath9k_hw_common(ah);
1336 struct ath_vif *avp = (void *)vif->drv_priv;
1337 struct ath_node *an = &avp->mcast_node;
1338
1339 mutex_lock(&sc->mutex);
1340 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1341 if (sc->cur_chan->nvifs >= 1) {
1342 mutex_unlock(&sc->mutex);
1343 return -EOPNOTSUPP;
1344 }
1345 sc->tx99_vif = vif;
1346 }
1347
1348 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1349 sc->cur_chan->nvifs++;
1350
1351 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1352 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1353
1354 if (ath9k_uses_beacons(vif->type))
1355 ath9k_beacon_assign_slot(sc, vif);
1356
1357 avp->vif = vif;
1358 if (!ath9k_is_chanctx_enabled()) {
1359 avp->chanctx = sc->cur_chan;
1360 list_add_tail(&avp->list, &avp->chanctx->vifs);
1361 }
1362
1363 ath9k_calculate_summary_state(sc, avp->chanctx);
1364
1365 ath9k_assign_hw_queues(hw, vif);
1366
1367 ath9k_set_txpower(sc, vif);
1368
1369 an->sc = sc;
1370 an->sta = NULL;
1371 an->vif = vif;
1372 an->no_ps_filter = true;
1373 ath_tx_node_init(sc, an);
1374
1375 mutex_unlock(&sc->mutex);
1376 return 0;
1377}
1378
1379static int ath9k_change_interface(struct ieee80211_hw *hw,
1380 struct ieee80211_vif *vif,
1381 enum nl80211_iftype new_type,
1382 bool p2p)
1383{
1384 struct ath_softc *sc = hw->priv;
1385 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1386 struct ath_vif *avp = (void *)vif->drv_priv;
1387
1388 mutex_lock(&sc->mutex);
1389
1390 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1391 mutex_unlock(&sc->mutex);
1392 return -EOPNOTSUPP;
1393 }
1394
1395 ath_dbg(common, CONFIG, "Change Interface\n");
1396
1397 if (ath9k_uses_beacons(vif->type))
1398 ath9k_beacon_remove_slot(sc, vif);
1399
1400 vif->type = new_type;
1401 vif->p2p = p2p;
1402
1403 if (ath9k_uses_beacons(vif->type))
1404 ath9k_beacon_assign_slot(sc, vif);
1405
1406 ath9k_assign_hw_queues(hw, vif);
1407 ath9k_calculate_summary_state(sc, avp->chanctx);
1408
1409 ath9k_set_txpower(sc, vif);
1410
1411 mutex_unlock(&sc->mutex);
1412 return 0;
1413}
1414
1415static void ath9k_remove_interface(struct ieee80211_hw *hw,
1416 struct ieee80211_vif *vif)
1417{
1418 struct ath_softc *sc = hw->priv;
1419 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1420 struct ath_vif *avp = (void *)vif->drv_priv;
1421
1422 ath_dbg(common, CONFIG, "Detach Interface\n");
1423
1424 mutex_lock(&sc->mutex);
1425
1426 ath9k_p2p_remove_vif(sc, vif);
1427
1428 sc->cur_chan->nvifs--;
1429 sc->tx99_vif = NULL;
1430 if (!ath9k_is_chanctx_enabled())
1431 list_del(&avp->list);
1432
1433 if (ath9k_uses_beacons(vif->type))
1434 ath9k_beacon_remove_slot(sc, vif);
1435
1436 ath_tx_node_cleanup(sc, &avp->mcast_node);
1437
1438 ath9k_calculate_summary_state(sc, avp->chanctx);
1439
1440 ath9k_set_txpower(sc, NULL);
1441
1442 mutex_unlock(&sc->mutex);
1443}
1444
1445static void ath9k_enable_ps(struct ath_softc *sc)
1446{
1447 struct ath_hw *ah = sc->sc_ah;
1448 struct ath_common *common = ath9k_hw_common(ah);
1449
1450 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1451 return;
1452
1453 sc->ps_enabled = true;
1454 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1455 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1456 ah->imask |= ATH9K_INT_TIM_TIMER;
1457 ath9k_hw_set_interrupts(ah);
1458 }
1459 ath9k_hw_setrxabort(ah, 1);
1460 }
1461 ath_dbg(common, PS, "PowerSave enabled\n");
1462}
1463
1464static void ath9k_disable_ps(struct ath_softc *sc)
1465{
1466 struct ath_hw *ah = sc->sc_ah;
1467 struct ath_common *common = ath9k_hw_common(ah);
1468
1469 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1470 return;
1471
1472 sc->ps_enabled = false;
1473 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1474 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1475 ath9k_hw_setrxabort(ah, 0);
1476 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1477 PS_WAIT_FOR_CAB |
1478 PS_WAIT_FOR_PSPOLL_DATA |
1479 PS_WAIT_FOR_TX_ACK);
1480 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1481 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1482 ath9k_hw_set_interrupts(ah);
1483 }
1484 }
1485 ath_dbg(common, PS, "PowerSave disabled\n");
1486}
1487
1488static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1489{
1490 struct ath_softc *sc = hw->priv;
1491 struct ath_hw *ah = sc->sc_ah;
1492 struct ath_common *common = ath9k_hw_common(ah);
1493 struct ieee80211_conf *conf = &hw->conf;
1494 struct ath_chanctx *ctx = sc->cur_chan;
1495
1496 ath9k_ps_wakeup(sc);
1497 mutex_lock(&sc->mutex);
1498
1499 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1500 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1501 if (sc->ps_idle) {
1502 ath_cancel_work(sc);
1503 ath9k_stop_btcoex(sc);
1504 } else {
1505 ath9k_start_btcoex(sc);
1506 /*
1507 * The chip needs a reset to properly wake up from
1508 * full sleep
1509 */
1510 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1511 }
1512 }
1513
1514 /*
1515 * We just prepare to enable PS. We have to wait until our AP has
1516 * ACK'd our null data frame to disable RX otherwise we'll ignore
1517 * those ACKs and end up retransmitting the same null data frames.
1518 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1519 */
1520 if (changed & IEEE80211_CONF_CHANGE_PS) {
1521 unsigned long flags;
1522 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1523 if (conf->flags & IEEE80211_CONF_PS)
1524 ath9k_enable_ps(sc);
1525 else
1526 ath9k_disable_ps(sc);
1527 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1528 }
1529
1530 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1531 if (conf->flags & IEEE80211_CONF_MONITOR) {
1532 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1533 sc->sc_ah->is_monitoring = true;
1534 } else {
1535 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1536 sc->sc_ah->is_monitoring = false;
1537 }
1538 }
1539
1540 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1541 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1542 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1543 }
1544
1545 if (changed & IEEE80211_CONF_CHANGE_POWER)
1546 ath9k_set_txpower(sc, NULL);
1547
1548 mutex_unlock(&sc->mutex);
1549 ath9k_ps_restore(sc);
1550
1551 return 0;
1552}
1553
1554#define SUPPORTED_FILTERS \
1555 (FIF_ALLMULTI | \
1556 FIF_CONTROL | \
1557 FIF_PSPOLL | \
1558 FIF_OTHER_BSS | \
1559 FIF_BCN_PRBRESP_PROMISC | \
1560 FIF_PROBE_REQ | \
1561 FIF_MCAST_ACTION | \
1562 FIF_FCSFAIL)
1563
1564/* FIXME: sc->sc_full_reset ? */
1565static void ath9k_configure_filter(struct ieee80211_hw *hw,
1566 unsigned int changed_flags,
1567 unsigned int *total_flags,
1568 u64 multicast)
1569{
1570 struct ath_softc *sc = hw->priv;
1571 struct ath_chanctx *ctx;
1572 u32 rfilt;
1573
1574 *total_flags &= SUPPORTED_FILTERS;
1575
1576 spin_lock_bh(&sc->chan_lock);
1577 ath_for_each_chanctx(sc, ctx)
1578 ctx->rxfilter = *total_flags;
1579#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1580 sc->offchannel.chan.rxfilter = *total_flags;
1581#endif
1582 spin_unlock_bh(&sc->chan_lock);
1583
1584 ath9k_ps_wakeup(sc);
1585 rfilt = ath_calcrxfilter(sc);
1586 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1587 ath9k_ps_restore(sc);
1588
1589 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1590 rfilt);
1591}
1592
1593static int ath9k_sta_add(struct ieee80211_hw *hw,
1594 struct ieee80211_vif *vif,
1595 struct ieee80211_sta *sta)
1596{
1597 struct ath_softc *sc = hw->priv;
1598 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1599 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1600 struct ieee80211_key_conf ps_key = { };
1601 int key;
1602
1603 ath_node_attach(sc, sta, vif);
1604
1605 if (vif->type != NL80211_IFTYPE_AP &&
1606 vif->type != NL80211_IFTYPE_AP_VLAN)
1607 return 0;
1608
1609 key = ath_key_config(common, vif, sta, &ps_key);
1610 if (key > 0) {
1611 an->ps_key = key;
1612 an->key_idx[0] = key;
1613 }
1614
1615 return 0;
1616}
1617
1618static void ath9k_del_ps_key(struct ath_softc *sc,
1619 struct ieee80211_vif *vif,
1620 struct ieee80211_sta *sta)
1621{
1622 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1623 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1624
1625 if (!an->ps_key)
1626 return;
1627
1628 ath_key_delete(common, an->ps_key);
1629 an->ps_key = 0;
1630 an->key_idx[0] = 0;
1631}
1632
1633static int ath9k_sta_remove(struct ieee80211_hw *hw,
1634 struct ieee80211_vif *vif,
1635 struct ieee80211_sta *sta)
1636{
1637 struct ath_softc *sc = hw->priv;
1638
1639 ath9k_del_ps_key(sc, vif, sta);
1640 ath_node_detach(sc, sta);
1641
1642 return 0;
1643}
1644
1645static int ath9k_sta_state(struct ieee80211_hw *hw,
1646 struct ieee80211_vif *vif,
1647 struct ieee80211_sta *sta,
1648 enum ieee80211_sta_state old_state,
1649 enum ieee80211_sta_state new_state)
1650{
1651 struct ath_softc *sc = hw->priv;
1652 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1653 int ret = 0;
1654
1655 if (old_state == IEEE80211_STA_NOTEXIST &&
1656 new_state == IEEE80211_STA_NONE) {
1657 ret = ath9k_sta_add(hw, vif, sta);
1658 ath_dbg(common, CONFIG,
1659 "Add station: %pM\n", sta->addr);
1660 } else if (old_state == IEEE80211_STA_NONE &&
1661 new_state == IEEE80211_STA_NOTEXIST) {
1662 ret = ath9k_sta_remove(hw, vif, sta);
1663 ath_dbg(common, CONFIG,
1664 "Remove station: %pM\n", sta->addr);
1665 }
1666
1667 if (ath9k_is_chanctx_enabled()) {
1668 if (vif->type == NL80211_IFTYPE_STATION) {
1669 if (old_state == IEEE80211_STA_ASSOC &&
1670 new_state == IEEE80211_STA_AUTHORIZED)
1671 ath_chanctx_event(sc, vif,
1672 ATH_CHANCTX_EVENT_AUTHORIZED);
1673 }
1674 }
1675
1676 return ret;
1677}
1678
1679static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1680 struct ath_node *an,
1681 bool set)
1682{
1683 int i;
1684
1685 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1686 if (!an->key_idx[i])
1687 continue;
1688 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1689 }
1690}
1691
1692static void ath9k_sta_notify(struct ieee80211_hw *hw,
1693 struct ieee80211_vif *vif,
1694 enum sta_notify_cmd cmd,
1695 struct ieee80211_sta *sta)
1696{
1697 struct ath_softc *sc = hw->priv;
1698 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1699
1700 switch (cmd) {
1701 case STA_NOTIFY_SLEEP:
1702 an->sleeping = true;
1703 ath_tx_aggr_sleep(sta, sc, an);
1704 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1705 break;
1706 case STA_NOTIFY_AWAKE:
1707 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1708 an->sleeping = false;
1709 ath_tx_aggr_wakeup(sc, an);
1710 break;
1711 }
1712}
1713
1714static int ath9k_conf_tx(struct ieee80211_hw *hw,
1715 struct ieee80211_vif *vif,
1716 unsigned int link_id, u16 queue,
1717 const struct ieee80211_tx_queue_params *params)
1718{
1719 struct ath_softc *sc = hw->priv;
1720 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1721 struct ath_txq *txq;
1722 struct ath9k_tx_queue_info qi;
1723 int ret = 0;
1724
1725 if (queue >= IEEE80211_NUM_ACS)
1726 return 0;
1727
1728 txq = sc->tx.txq_map[queue];
1729
1730 ath9k_ps_wakeup(sc);
1731 mutex_lock(&sc->mutex);
1732
1733 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1734
1735 qi.tqi_aifs = params->aifs;
1736 qi.tqi_cwmin = params->cw_min;
1737 qi.tqi_cwmax = params->cw_max;
1738 qi.tqi_burstTime = params->txop * 32;
1739
1740 ath_dbg(common, CONFIG,
1741 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1742 queue, txq->axq_qnum, params->aifs, params->cw_min,
1743 params->cw_max, params->txop);
1744
1745 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1746 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1747 if (ret)
1748 ath_err(common, "TXQ Update failed\n");
1749
1750 mutex_unlock(&sc->mutex);
1751 ath9k_ps_restore(sc);
1752
1753 return ret;
1754}
1755
1756static int ath9k_set_key(struct ieee80211_hw *hw,
1757 enum set_key_cmd cmd,
1758 struct ieee80211_vif *vif,
1759 struct ieee80211_sta *sta,
1760 struct ieee80211_key_conf *key)
1761{
1762 struct ath_softc *sc = hw->priv;
1763 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1764 struct ath_node *an = NULL;
1765 int ret = 0, i;
1766
1767 if (ath9k_modparam_nohwcrypt)
1768 return -ENOSPC;
1769
1770 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1771 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1772 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1773 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1774 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1775 /*
1776 * For now, disable hw crypto for the RSN IBSS group keys. This
1777 * could be optimized in the future to use a modified key cache
1778 * design to support per-STA RX GTK, but until that gets
1779 * implemented, use of software crypto for group addressed
1780 * frames is a acceptable to allow RSN IBSS to be used.
1781 */
1782 return -EOPNOTSUPP;
1783 }
1784
1785 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
1786 * make sure these are not send unencrypted or with a wrong (new) key
1787 */
1788 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
1789 ieee80211_stop_queues(hw);
1790 ath9k_flush(hw, vif, 0, true);
1791 ieee80211_wake_queues(hw);
1792 }
1793
1794 mutex_lock(&sc->mutex);
1795 ath9k_ps_wakeup(sc);
1796 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1797 if (sta)
1798 an = (struct ath_node *)sta->drv_priv;
1799
1800 /* Delete pending key cache entries if no more frames are pointing to
1801 * them in TXQs.
1802 */
1803 for (i = 0; i < ATH_KEYMAX; i++)
1804 ath9k_pending_key_del(sc, i);
1805
1806 switch (cmd) {
1807 case SET_KEY:
1808 if (sta)
1809 ath9k_del_ps_key(sc, vif, sta);
1810
1811 key->hw_key_idx = 0;
1812 ret = ath_key_config(common, vif, sta, key);
1813 if (ret >= 0) {
1814 key->hw_key_idx = ret;
1815 /* push IV and Michael MIC generation to stack */
1816 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1817 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1818 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1819 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1820 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1821 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1822 ret = 0;
1823 }
1824 if (an && key->hw_key_idx) {
1825 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1826 if (an->key_idx[i])
1827 continue;
1828 an->key_idx[i] = key->hw_key_idx;
1829 break;
1830 }
1831 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1832 }
1833 break;
1834 case DISABLE_KEY:
1835 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1836 /* Delay key cache entry deletion until there are no
1837 * remaining TXQ frames pointing to this entry.
1838 */
1839 set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1840 ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1841 } else {
1842 ath_key_delete(common, key->hw_key_idx);
1843 }
1844 if (an) {
1845 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1846 if (an->key_idx[i] != key->hw_key_idx)
1847 continue;
1848 an->key_idx[i] = 0;
1849 break;
1850 }
1851 }
1852 key->hw_key_idx = 0;
1853 break;
1854 default:
1855 ret = -EINVAL;
1856 }
1857
1858 ath9k_ps_restore(sc);
1859 mutex_unlock(&sc->mutex);
1860
1861 return ret;
1862}
1863
1864static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1865 struct ieee80211_vif *vif,
1866 struct ieee80211_bss_conf *bss_conf,
1867 u64 changed)
1868{
1869#define CHECK_ANI \
1870 (BSS_CHANGED_ASSOC | \
1871 BSS_CHANGED_IBSS | \
1872 BSS_CHANGED_BEACON_ENABLED)
1873
1874 struct ath_softc *sc = hw->priv;
1875 struct ath_hw *ah = sc->sc_ah;
1876 struct ath_common *common = ath9k_hw_common(ah);
1877 struct ath_vif *avp = (void *)vif->drv_priv;
1878 int slottime;
1879
1880 ath9k_ps_wakeup(sc);
1881 mutex_lock(&sc->mutex);
1882
1883 if (changed & BSS_CHANGED_ASSOC) {
1884 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1885 bss_conf->bssid, vif->cfg.assoc);
1886
1887 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1888 avp->aid = vif->cfg.aid;
1889 avp->assoc = vif->cfg.assoc;
1890
1891 ath9k_calculate_summary_state(sc, avp->chanctx);
1892 }
1893
1894 if ((changed & BSS_CHANGED_IBSS) ||
1895 (changed & BSS_CHANGED_OCB)) {
1896 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1897 common->curaid = vif->cfg.aid;
1898 ath9k_hw_write_associd(sc->sc_ah);
1899 }
1900
1901 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1902 (changed & BSS_CHANGED_BEACON_INT) ||
1903 (changed & BSS_CHANGED_BEACON_INFO)) {
1904 ath9k_calculate_summary_state(sc, avp->chanctx);
1905 }
1906
1907 if ((avp->chanctx == sc->cur_chan) &&
1908 (changed & BSS_CHANGED_ERP_SLOT)) {
1909 if (bss_conf->use_short_slot)
1910 slottime = 9;
1911 else
1912 slottime = 20;
1913
1914 if (vif->type == NL80211_IFTYPE_AP) {
1915 /*
1916 * Defer update, so that connected stations can adjust
1917 * their settings at the same time.
1918 * See beacon.c for more details
1919 */
1920 sc->beacon.slottime = slottime;
1921 sc->beacon.updateslot = UPDATE;
1922 } else {
1923 ah->slottime = slottime;
1924 ath9k_hw_init_global_settings(ah);
1925 }
1926 }
1927
1928 if (changed & BSS_CHANGED_P2P_PS)
1929 ath9k_p2p_bss_info_changed(sc, vif);
1930
1931 if (changed & CHECK_ANI)
1932 ath_check_ani(sc);
1933
1934 if (changed & BSS_CHANGED_TXPOWER) {
1935 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1936 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1937 ath9k_set_txpower(sc, vif);
1938 }
1939
1940 mutex_unlock(&sc->mutex);
1941 ath9k_ps_restore(sc);
1942
1943#undef CHECK_ANI
1944}
1945
1946static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1947{
1948 struct ath_softc *sc = hw->priv;
1949 struct ath_vif *avp = (void *)vif->drv_priv;
1950 u64 tsf;
1951
1952 mutex_lock(&sc->mutex);
1953 ath9k_ps_wakeup(sc);
1954 /* Get current TSF either from HW or kernel time. */
1955 if (sc->cur_chan == avp->chanctx) {
1956 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1957 } else {
1958 tsf = sc->cur_chan->tsf_val +
1959 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1960 }
1961 tsf += le64_to_cpu(avp->tsf_adjust);
1962 ath9k_ps_restore(sc);
1963 mutex_unlock(&sc->mutex);
1964
1965 return tsf;
1966}
1967
1968static void ath9k_set_tsf(struct ieee80211_hw *hw,
1969 struct ieee80211_vif *vif,
1970 u64 tsf)
1971{
1972 struct ath_softc *sc = hw->priv;
1973 struct ath_vif *avp = (void *)vif->drv_priv;
1974
1975 mutex_lock(&sc->mutex);
1976 ath9k_ps_wakeup(sc);
1977 tsf -= le64_to_cpu(avp->tsf_adjust);
1978 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1979 if (sc->cur_chan == avp->chanctx)
1980 ath9k_hw_settsf64(sc->sc_ah, tsf);
1981 avp->chanctx->tsf_val = tsf;
1982 ath9k_ps_restore(sc);
1983 mutex_unlock(&sc->mutex);
1984}
1985
1986static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1987{
1988 struct ath_softc *sc = hw->priv;
1989 struct ath_vif *avp = (void *)vif->drv_priv;
1990
1991 mutex_lock(&sc->mutex);
1992
1993 ath9k_ps_wakeup(sc);
1994 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1995 if (sc->cur_chan == avp->chanctx)
1996 ath9k_hw_reset_tsf(sc->sc_ah);
1997 avp->chanctx->tsf_val = 0;
1998 ath9k_ps_restore(sc);
1999
2000 mutex_unlock(&sc->mutex);
2001}
2002
2003static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2004 struct ieee80211_vif *vif,
2005 struct ieee80211_ampdu_params *params)
2006{
2007 struct ath_softc *sc = hw->priv;
2008 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2009 bool flush = false;
2010 int ret = 0;
2011 struct ieee80211_sta *sta = params->sta;
2012 struct ath_node *an = (struct ath_node *)sta->drv_priv;
2013 enum ieee80211_ampdu_mlme_action action = params->action;
2014 u16 tid = params->tid;
2015 u16 *ssn = ¶ms->ssn;
2016 struct ath_atx_tid *atid;
2017
2018 mutex_lock(&sc->mutex);
2019
2020 switch (action) {
2021 case IEEE80211_AMPDU_RX_START:
2022 break;
2023 case IEEE80211_AMPDU_RX_STOP:
2024 break;
2025 case IEEE80211_AMPDU_TX_START:
2026 if (ath9k_is_chanctx_enabled()) {
2027 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2028 ret = -EBUSY;
2029 break;
2030 }
2031 }
2032 ath9k_ps_wakeup(sc);
2033 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2034 if (!ret)
2035 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
2036 ath9k_ps_restore(sc);
2037 break;
2038 case IEEE80211_AMPDU_TX_STOP_FLUSH:
2039 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
2040 flush = true;
2041 fallthrough;
2042 case IEEE80211_AMPDU_TX_STOP_CONT:
2043 ath9k_ps_wakeup(sc);
2044 ath_tx_aggr_stop(sc, sta, tid);
2045 if (!flush)
2046 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2047 ath9k_ps_restore(sc);
2048 break;
2049 case IEEE80211_AMPDU_TX_OPERATIONAL:
2050 atid = ath_node_to_tid(an, tid);
2051 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2052 sta->deflink.ht_cap.ampdu_factor;
2053 break;
2054 default:
2055 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2056 }
2057
2058 mutex_unlock(&sc->mutex);
2059
2060 return ret;
2061}
2062
2063static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2064 struct survey_info *survey)
2065{
2066 struct ath_softc *sc = hw->priv;
2067 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2068 struct ieee80211_supported_band *sband;
2069 struct ieee80211_channel *chan;
2070 unsigned long flags;
2071 int pos;
2072
2073 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2074 return -EOPNOTSUPP;
2075
2076 spin_lock_irqsave(&common->cc_lock, flags);
2077 if (idx == 0)
2078 ath_update_survey_stats(sc);
2079
2080 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
2081 if (sband && idx >= sband->n_channels) {
2082 idx -= sband->n_channels;
2083 sband = NULL;
2084 }
2085
2086 if (!sband)
2087 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
2088
2089 if (!sband || idx >= sband->n_channels) {
2090 spin_unlock_irqrestore(&common->cc_lock, flags);
2091 return -ENOENT;
2092 }
2093
2094 chan = &sband->channels[idx];
2095 pos = chan->hw_value;
2096 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2097 survey->channel = chan;
2098 spin_unlock_irqrestore(&common->cc_lock, flags);
2099
2100 return 0;
2101}
2102
2103static void ath9k_enable_dynack(struct ath_softc *sc)
2104{
2105#ifdef CONFIG_ATH9K_DYNACK
2106 u32 rfilt;
2107 struct ath_hw *ah = sc->sc_ah;
2108
2109 ath_dynack_reset(ah);
2110
2111 ah->dynack.enabled = true;
2112 rfilt = ath_calcrxfilter(sc);
2113 ath9k_hw_setrxfilter(ah, rfilt);
2114#endif
2115}
2116
2117static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2118 s16 coverage_class)
2119{
2120 struct ath_softc *sc = hw->priv;
2121 struct ath_hw *ah = sc->sc_ah;
2122
2123 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2124 return;
2125
2126 mutex_lock(&sc->mutex);
2127
2128 if (coverage_class >= 0) {
2129 ah->coverage_class = coverage_class;
2130 if (ah->dynack.enabled) {
2131 u32 rfilt;
2132
2133 ah->dynack.enabled = false;
2134 rfilt = ath_calcrxfilter(sc);
2135 ath9k_hw_setrxfilter(ah, rfilt);
2136 }
2137 ath9k_ps_wakeup(sc);
2138 ath9k_hw_init_global_settings(ah);
2139 ath9k_ps_restore(sc);
2140 } else if (!ah->dynack.enabled) {
2141 ath9k_enable_dynack(sc);
2142 }
2143
2144 mutex_unlock(&sc->mutex);
2145}
2146
2147static bool ath9k_has_tx_pending(struct ath_softc *sc,
2148 bool sw_pending)
2149{
2150 int i, npend = 0;
2151
2152 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2153 if (!ATH_TXQ_SETUP(sc, i))
2154 continue;
2155
2156 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2157 sw_pending);
2158 if (npend)
2159 break;
2160 }
2161
2162 return !!npend;
2163}
2164
2165static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2166 u32 queues, bool drop)
2167{
2168 struct ath_softc *sc = hw->priv;
2169 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2170
2171 if (ath9k_is_chanctx_enabled()) {
2172 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2173 goto flush;
2174
2175 /*
2176 * If MCC is active, extend the flush timeout
2177 * and wait for the HW/SW queues to become
2178 * empty. This needs to be done outside the
2179 * sc->mutex lock to allow the channel scheduler
2180 * to switch channel contexts.
2181 *
2182 * The vif queues have been stopped in mac80211,
2183 * so there won't be any incoming frames.
2184 */
2185 __ath9k_flush(hw, queues, drop, true, true);
2186 return;
2187 }
2188flush:
2189 mutex_lock(&sc->mutex);
2190 __ath9k_flush(hw, queues, drop, true, false);
2191 mutex_unlock(&sc->mutex);
2192}
2193
2194void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2195 bool sw_pending, bool timeout_override)
2196{
2197 struct ath_softc *sc = hw->priv;
2198 struct ath_hw *ah = sc->sc_ah;
2199 struct ath_common *common = ath9k_hw_common(ah);
2200 int timeout;
2201 bool drain_txq;
2202
2203 cancel_delayed_work_sync(&sc->hw_check_work);
2204
2205 if (ah->ah_flags & AH_UNPLUGGED) {
2206 ath_dbg(common, ANY, "Device has been unplugged!\n");
2207 return;
2208 }
2209
2210 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2211 ath_dbg(common, ANY, "Device not present\n");
2212 return;
2213 }
2214
2215 spin_lock_bh(&sc->chan_lock);
2216 if (timeout_override)
2217 timeout = HZ / 5;
2218 else
2219 timeout = sc->cur_chan->flush_timeout;
2220 spin_unlock_bh(&sc->chan_lock);
2221
2222 ath_dbg(common, CHAN_CTX,
2223 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2224
2225 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2226 timeout) > 0)
2227 drop = false;
2228
2229 if (drop) {
2230 ath9k_ps_wakeup(sc);
2231 spin_lock_bh(&sc->sc_pcu_lock);
2232 drain_txq = ath_drain_all_txq(sc);
2233 spin_unlock_bh(&sc->sc_pcu_lock);
2234
2235 if (!drain_txq)
2236 ath_reset(sc, NULL);
2237
2238 ath9k_ps_restore(sc);
2239 }
2240
2241 ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2242 msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
2243}
2244
2245static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2246{
2247 struct ath_softc *sc = hw->priv;
2248
2249 return ath9k_has_tx_pending(sc, true);
2250}
2251
2252static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2253{
2254 struct ath_softc *sc = hw->priv;
2255 struct ath_hw *ah = sc->sc_ah;
2256 struct ieee80211_vif *vif;
2257 struct ath_vif *avp;
2258 struct ath_buf *bf;
2259 struct ath_tx_status ts;
2260 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2261 int status;
2262
2263 vif = sc->beacon.bslot[0];
2264 if (!vif)
2265 return 0;
2266
2267 if (!vif->bss_conf.enable_beacon)
2268 return 0;
2269
2270 avp = (void *)vif->drv_priv;
2271
2272 if (!sc->beacon.tx_processed && !edma) {
2273 tasklet_disable(&sc->bcon_tasklet);
2274
2275 bf = avp->av_bcbuf;
2276 if (!bf || !bf->bf_mpdu)
2277 goto skip;
2278
2279 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2280 if (status == -EINPROGRESS)
2281 goto skip;
2282
2283 sc->beacon.tx_processed = true;
2284 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2285
2286skip:
2287 tasklet_enable(&sc->bcon_tasklet);
2288 }
2289
2290 return sc->beacon.tx_last;
2291}
2292
2293static int ath9k_get_stats(struct ieee80211_hw *hw,
2294 struct ieee80211_low_level_stats *stats)
2295{
2296 struct ath_softc *sc = hw->priv;
2297 struct ath_hw *ah = sc->sc_ah;
2298 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2299
2300 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2301 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2302 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2303 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2304 return 0;
2305}
2306
2307static u32 fill_chainmask(u32 cap, u32 new)
2308{
2309 u32 filled = 0;
2310 int i;
2311
2312 for (i = 0; cap && new; i++, cap >>= 1) {
2313 if (!(cap & BIT(0)))
2314 continue;
2315
2316 if (new & BIT(0))
2317 filled |= BIT(i);
2318
2319 new >>= 1;
2320 }
2321
2322 return filled;
2323}
2324
2325static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2326{
2327 if (AR_SREV_9300_20_OR_LATER(ah))
2328 return true;
2329
2330 switch (val & 0x7) {
2331 case 0x1:
2332 case 0x3:
2333 case 0x7:
2334 return true;
2335 case 0x2:
2336 return (ah->caps.rx_chainmask == 1);
2337 default:
2338 return false;
2339 }
2340}
2341
2342static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2343{
2344 struct ath_softc *sc = hw->priv;
2345 struct ath_hw *ah = sc->sc_ah;
2346
2347 if (ah->caps.rx_chainmask != 1)
2348 rx_ant |= tx_ant;
2349
2350 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2351 return -EINVAL;
2352
2353 sc->ant_rx = rx_ant;
2354 sc->ant_tx = tx_ant;
2355
2356 if (ah->caps.rx_chainmask == 1)
2357 return 0;
2358
2359 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2360 if (AR_SREV_9100(ah))
2361 ah->rxchainmask = 0x7;
2362 else
2363 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2364
2365 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2366 ath9k_cmn_reload_chainmask(ah);
2367
2368 return 0;
2369}
2370
2371static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2372{
2373 struct ath_softc *sc = hw->priv;
2374
2375 *tx_ant = sc->ant_tx;
2376 *rx_ant = sc->ant_rx;
2377 return 0;
2378}
2379
2380static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2381 struct ieee80211_vif *vif,
2382 const u8 *mac_addr)
2383{
2384 struct ath_softc *sc = hw->priv;
2385 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2386 struct cfg80211_chan_def *chandef = &sc->cur_chan->chandef;
2387 struct ieee80211_channel *chan = chandef->chan;
2388 int pos = chan->hw_value;
2389 set_bit(ATH_OP_SCANNING, &common->op_flags);
2390
2391 /* Reset current survey */
2392 if (!sc->cur_chan->offchannel) {
2393 if (sc->cur_survey != &sc->survey[pos]) {
2394 if (sc->cur_survey)
2395 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
2396 sc->cur_survey = &sc->survey[pos];
2397 }
2398
2399 memset(sc->cur_survey, 0, sizeof(struct survey_info));
2400 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
2401 }
2402}
2403
2404static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2405 struct ieee80211_vif *vif)
2406{
2407 struct ath_softc *sc = hw->priv;
2408 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2409 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2410}
2411
2412#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2413
2414static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2415{
2416 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2417
2418 if (sc->offchannel.roc_vif) {
2419 ath_dbg(common, CHAN_CTX,
2420 "%s: Aborting RoC\n", __func__);
2421
2422 del_timer_sync(&sc->offchannel.timer);
2423 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2424 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2425 }
2426
2427 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2428 ath_dbg(common, CHAN_CTX,
2429 "%s: Aborting HW scan\n", __func__);
2430
2431 del_timer_sync(&sc->offchannel.timer);
2432 ath_scan_complete(sc, true);
2433 }
2434}
2435
2436static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2437 struct ieee80211_scan_request *hw_req)
2438{
2439 struct cfg80211_scan_request *req = &hw_req->req;
2440 struct ath_softc *sc = hw->priv;
2441 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2442 int ret = 0;
2443
2444 mutex_lock(&sc->mutex);
2445
2446 if (WARN_ON(sc->offchannel.scan_req)) {
2447 ret = -EBUSY;
2448 goto out;
2449 }
2450
2451 ath9k_ps_wakeup(sc);
2452 set_bit(ATH_OP_SCANNING, &common->op_flags);
2453 sc->offchannel.scan_vif = vif;
2454 sc->offchannel.scan_req = req;
2455 sc->offchannel.scan_idx = 0;
2456
2457 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2458 vif->addr);
2459
2460 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2461 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2462 ath_offchannel_next(sc);
2463 }
2464
2465out:
2466 mutex_unlock(&sc->mutex);
2467
2468 return ret;
2469}
2470
2471static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2472 struct ieee80211_vif *vif)
2473{
2474 struct ath_softc *sc = hw->priv;
2475 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2476
2477 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2478
2479 mutex_lock(&sc->mutex);
2480 del_timer_sync(&sc->offchannel.timer);
2481 ath_scan_complete(sc, true);
2482 mutex_unlock(&sc->mutex);
2483}
2484
2485static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2486 struct ieee80211_vif *vif,
2487 struct ieee80211_channel *chan, int duration,
2488 enum ieee80211_roc_type type)
2489{
2490 struct ath_softc *sc = hw->priv;
2491 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2492 int ret = 0;
2493
2494 mutex_lock(&sc->mutex);
2495
2496 if (WARN_ON(sc->offchannel.roc_vif)) {
2497 ret = -EBUSY;
2498 goto out;
2499 }
2500
2501 ath9k_ps_wakeup(sc);
2502 sc->offchannel.roc_vif = vif;
2503 sc->offchannel.roc_chan = chan;
2504 sc->offchannel.roc_duration = duration;
2505
2506 ath_dbg(common, CHAN_CTX,
2507 "RoC request on vif: %pM, type: %d duration: %d\n",
2508 vif->addr, type, duration);
2509
2510 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2511 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2512 ath_offchannel_next(sc);
2513 }
2514
2515out:
2516 mutex_unlock(&sc->mutex);
2517
2518 return ret;
2519}
2520
2521static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
2522 struct ieee80211_vif *vif)
2523{
2524 struct ath_softc *sc = hw->priv;
2525 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2526
2527 mutex_lock(&sc->mutex);
2528
2529 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2530 del_timer_sync(&sc->offchannel.timer);
2531
2532 if (sc->offchannel.roc_vif) {
2533 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2534 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2535 }
2536
2537 mutex_unlock(&sc->mutex);
2538
2539 return 0;
2540}
2541
2542static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2543 struct ieee80211_chanctx_conf *conf)
2544{
2545 struct ath_softc *sc = hw->priv;
2546 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2547 struct ath_chanctx *ctx, **ptr;
2548 int pos;
2549
2550 mutex_lock(&sc->mutex);
2551
2552 ath_for_each_chanctx(sc, ctx) {
2553 if (ctx->assigned)
2554 continue;
2555
2556 ptr = (void *) conf->drv_priv;
2557 *ptr = ctx;
2558 ctx->assigned = true;
2559 pos = ctx - &sc->chanctx[0];
2560 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2561
2562 ath_dbg(common, CHAN_CTX,
2563 "Add channel context: %d MHz\n",
2564 conf->def.chan->center_freq);
2565
2566 ath_chanctx_set_channel(sc, ctx, &conf->def);
2567
2568 mutex_unlock(&sc->mutex);
2569 return 0;
2570 }
2571
2572 mutex_unlock(&sc->mutex);
2573 return -ENOSPC;
2574}
2575
2576
2577static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2578 struct ieee80211_chanctx_conf *conf)
2579{
2580 struct ath_softc *sc = hw->priv;
2581 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2582 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2583
2584 mutex_lock(&sc->mutex);
2585
2586 ath_dbg(common, CHAN_CTX,
2587 "Remove channel context: %d MHz\n",
2588 conf->def.chan->center_freq);
2589
2590 ctx->assigned = false;
2591 ctx->hw_queue_base = 0;
2592 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2593
2594 mutex_unlock(&sc->mutex);
2595}
2596
2597static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2598 struct ieee80211_chanctx_conf *conf,
2599 u32 changed)
2600{
2601 struct ath_softc *sc = hw->priv;
2602 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2603 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2604
2605 mutex_lock(&sc->mutex);
2606 ath_dbg(common, CHAN_CTX,
2607 "Change channel context: %d MHz\n",
2608 conf->def.chan->center_freq);
2609 ath_chanctx_set_channel(sc, ctx, &conf->def);
2610 mutex_unlock(&sc->mutex);
2611}
2612
2613static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2614 struct ieee80211_vif *vif,
2615 struct ieee80211_bss_conf *link_conf,
2616 struct ieee80211_chanctx_conf *conf)
2617{
2618 struct ath_softc *sc = hw->priv;
2619 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2620 struct ath_vif *avp = (void *)vif->drv_priv;
2621 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2622 int i;
2623
2624 ath9k_cancel_pending_offchannel(sc);
2625
2626 mutex_lock(&sc->mutex);
2627
2628 ath_dbg(common, CHAN_CTX,
2629 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2630 vif->addr, vif->type, vif->p2p,
2631 conf->def.chan->center_freq);
2632
2633 avp->chanctx = ctx;
2634 ctx->nvifs_assigned++;
2635 list_add_tail(&avp->list, &ctx->vifs);
2636 ath9k_calculate_summary_state(sc, ctx);
2637 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2638 vif->hw_queue[i] = ctx->hw_queue_base + i;
2639
2640 mutex_unlock(&sc->mutex);
2641
2642 return 0;
2643}
2644
2645static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2646 struct ieee80211_vif *vif,
2647 struct ieee80211_bss_conf *link_conf,
2648 struct ieee80211_chanctx_conf *conf)
2649{
2650 struct ath_softc *sc = hw->priv;
2651 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2652 struct ath_vif *avp = (void *)vif->drv_priv;
2653 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2654 int ac;
2655
2656 ath9k_cancel_pending_offchannel(sc);
2657
2658 mutex_lock(&sc->mutex);
2659
2660 ath_dbg(common, CHAN_CTX,
2661 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2662 vif->addr, vif->type, vif->p2p,
2663 conf->def.chan->center_freq);
2664
2665 avp->chanctx = NULL;
2666 ctx->nvifs_assigned--;
2667 list_del(&avp->list);
2668 ath9k_calculate_summary_state(sc, ctx);
2669 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2670 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2671
2672 mutex_unlock(&sc->mutex);
2673}
2674
2675static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2676 struct ieee80211_vif *vif,
2677 struct ieee80211_prep_tx_info *info)
2678{
2679 struct ath_softc *sc = hw->priv;
2680 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2681 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2682 struct ath_beacon_config *cur_conf;
2683 struct ath_chanctx *go_ctx;
2684 unsigned long timeout;
2685 bool changed = false;
2686 u32 beacon_int;
2687
2688 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2689 return;
2690
2691 if (!avp->chanctx)
2692 return;
2693
2694 mutex_lock(&sc->mutex);
2695
2696 spin_lock_bh(&sc->chan_lock);
2697 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2698 changed = true;
2699 spin_unlock_bh(&sc->chan_lock);
2700
2701 if (!changed)
2702 goto out;
2703
2704 ath9k_cancel_pending_offchannel(sc);
2705
2706 go_ctx = ath_is_go_chanctx_present(sc);
2707
2708 if (go_ctx) {
2709 /*
2710 * Wait till the GO interface gets a chance
2711 * to send out an NoA.
2712 */
2713 spin_lock_bh(&sc->chan_lock);
2714 sc->sched.mgd_prepare_tx = true;
2715 cur_conf = &go_ctx->beacon;
2716 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2717 spin_unlock_bh(&sc->chan_lock);
2718
2719 timeout = usecs_to_jiffies(beacon_int * 2);
2720 init_completion(&sc->go_beacon);
2721
2722 mutex_unlock(&sc->mutex);
2723
2724 if (wait_for_completion_timeout(&sc->go_beacon,
2725 timeout) == 0) {
2726 ath_dbg(common, CHAN_CTX,
2727 "Failed to send new NoA\n");
2728
2729 spin_lock_bh(&sc->chan_lock);
2730 sc->sched.mgd_prepare_tx = false;
2731 spin_unlock_bh(&sc->chan_lock);
2732 }
2733
2734 mutex_lock(&sc->mutex);
2735 }
2736
2737 ath_dbg(common, CHAN_CTX,
2738 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2739 __func__, vif->addr);
2740
2741 spin_lock_bh(&sc->chan_lock);
2742 sc->next_chan = avp->chanctx;
2743 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2744 spin_unlock_bh(&sc->chan_lock);
2745
2746 ath_chanctx_set_next(sc, true);
2747out:
2748 mutex_unlock(&sc->mutex);
2749}
2750
2751void ath9k_fill_chanctx_ops(void)
2752{
2753 if (!ath9k_is_chanctx_enabled())
2754 return;
2755
2756 ath9k_ops.hw_scan = ath9k_hw_scan;
2757 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2758 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2759 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2760 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2761 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2762 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2763 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2764 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2765 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2766}
2767
2768#endif
2769
2770static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2771 int *dbm)
2772{
2773 struct ath_softc *sc = hw->priv;
2774 struct ath_vif *avp = (void *)vif->drv_priv;
2775
2776 mutex_lock(&sc->mutex);
2777 if (avp->chanctx)
2778 *dbm = avp->chanctx->cur_txpower;
2779 else
2780 *dbm = sc->cur_chan->cur_txpower;
2781 mutex_unlock(&sc->mutex);
2782
2783 *dbm /= 2;
2784
2785 return 0;
2786}
2787
2788struct ieee80211_ops ath9k_ops = {
2789 .tx = ath9k_tx,
2790 .start = ath9k_start,
2791 .stop = ath9k_stop,
2792 .add_interface = ath9k_add_interface,
2793 .change_interface = ath9k_change_interface,
2794 .remove_interface = ath9k_remove_interface,
2795 .config = ath9k_config,
2796 .configure_filter = ath9k_configure_filter,
2797 .sta_state = ath9k_sta_state,
2798 .sta_notify = ath9k_sta_notify,
2799 .conf_tx = ath9k_conf_tx,
2800 .bss_info_changed = ath9k_bss_info_changed,
2801 .set_key = ath9k_set_key,
2802 .get_tsf = ath9k_get_tsf,
2803 .set_tsf = ath9k_set_tsf,
2804 .reset_tsf = ath9k_reset_tsf,
2805 .ampdu_action = ath9k_ampdu_action,
2806 .get_survey = ath9k_get_survey,
2807 .rfkill_poll = ath9k_rfkill_poll_state,
2808 .set_coverage_class = ath9k_set_coverage_class,
2809 .flush = ath9k_flush,
2810 .tx_frames_pending = ath9k_tx_frames_pending,
2811 .tx_last_beacon = ath9k_tx_last_beacon,
2812 .release_buffered_frames = ath9k_release_buffered_frames,
2813 .get_stats = ath9k_get_stats,
2814 .set_antenna = ath9k_set_antenna,
2815 .get_antenna = ath9k_get_antenna,
2816
2817#ifdef CONFIG_ATH9K_WOW
2818 .suspend = ath9k_suspend,
2819 .resume = ath9k_resume,
2820 .set_wakeup = ath9k_set_wakeup,
2821#endif
2822
2823#ifdef CONFIG_ATH9K_DEBUGFS
2824 .get_et_sset_count = ath9k_get_et_sset_count,
2825 .get_et_stats = ath9k_get_et_stats,
2826 .get_et_strings = ath9k_get_et_strings,
2827#endif
2828
2829#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2830 .sta_add_debugfs = ath9k_sta_add_debugfs,
2831#endif
2832 .sw_scan_start = ath9k_sw_scan_start,
2833 .sw_scan_complete = ath9k_sw_scan_complete,
2834 .get_txpower = ath9k_get_txpower,
2835 .wake_tx_queue = ath9k_wake_tx_queue,
2836};
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/nl80211.h>
18#include <linux/delay.h>
19#include "ath9k.h"
20#include "btcoex.h"
21
22u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 bool sw_pending)
59{
60 bool pending = false;
61
62 spin_lock_bh(&txq->axq_lock);
63
64 if (txq->axq_depth) {
65 pending = true;
66 goto out;
67 }
68
69 if (!sw_pending)
70 goto out;
71
72 if (txq->mac80211_qnum >= 0) {
73 struct list_head *list;
74
75 list = &sc->cur_chan->acq[txq->mac80211_qnum];
76 if (!list_empty(list))
77 pending = true;
78 }
79out:
80 spin_unlock_bh(&txq->axq_lock);
81 return pending;
82}
83
84static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
85{
86 unsigned long flags;
87 bool ret;
88
89 spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
92
93 return ret;
94}
95
96void ath_ps_full_sleep(unsigned long data)
97{
98 struct ath_softc *sc = (struct ath_softc *) data;
99 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 bool reset;
101
102 spin_lock(&common->cc_lock);
103 ath_hw_cycle_counters_update(common);
104 spin_unlock(&common->cc_lock);
105
106 ath9k_hw_setrxabort(sc->sc_ah, 1);
107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
108
109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
110}
111
112void ath9k_ps_wakeup(struct ath_softc *sc)
113{
114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
115 unsigned long flags;
116 enum ath9k_power_mode power_mode;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (++sc->ps_usecount != 1)
120 goto unlock;
121
122 del_timer_sync(&sc->sleep_timer);
123 power_mode = sc->sc_ah->power_mode;
124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
125
126 /*
127 * While the hardware is asleep, the cycle counters contain no
128 * useful data. Better clear them now so that they don't mess up
129 * survey data results.
130 */
131 if (power_mode != ATH9K_PM_AWAKE) {
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
135 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
136 spin_unlock(&common->cc_lock);
137 }
138
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141}
142
143void ath9k_ps_restore(struct ath_softc *sc)
144{
145 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
146 enum ath9k_power_mode mode;
147 unsigned long flags;
148
149 spin_lock_irqsave(&sc->sc_pm_lock, flags);
150 if (--sc->ps_usecount != 0)
151 goto unlock;
152
153 if (sc->ps_idle) {
154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
155 goto unlock;
156 }
157
158 if (sc->ps_enabled &&
159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
160 PS_WAIT_FOR_CAB |
161 PS_WAIT_FOR_PSPOLL_DATA |
162 PS_WAIT_FOR_TX_ACK |
163 PS_WAIT_FOR_ANI))) {
164 mode = ATH9K_PM_NETWORK_SLEEP;
165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
166 ath9k_btcoex_stop_gen_timer(sc);
167 } else {
168 goto unlock;
169 }
170
171 spin_lock(&common->cc_lock);
172 ath_hw_cycle_counters_update(common);
173 spin_unlock(&common->cc_lock);
174
175 ath9k_hw_setpower(sc->sc_ah, mode);
176
177 unlock:
178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
179}
180
181static void __ath_cancel_work(struct ath_softc *sc)
182{
183 cancel_work_sync(&sc->paprd_work);
184 cancel_delayed_work_sync(&sc->tx_complete_work);
185 cancel_delayed_work_sync(&sc->hw_pll_work);
186
187#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
188 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
189 cancel_work_sync(&sc->mci_work);
190#endif
191}
192
193void ath_cancel_work(struct ath_softc *sc)
194{
195 __ath_cancel_work(sc);
196 cancel_work_sync(&sc->hw_reset_work);
197}
198
199void ath_restart_work(struct ath_softc *sc)
200{
201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
202
203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
206
207 ath_start_ani(sc);
208}
209
210static bool ath_prepare_reset(struct ath_softc *sc)
211{
212 struct ath_hw *ah = sc->sc_ah;
213 bool ret = true;
214
215 ieee80211_stop_queues(sc->hw);
216 ath_stop_ani(sc);
217 ath9k_hw_disable_interrupts(ah);
218
219 if (AR_SREV_9300_20_OR_LATER(ah)) {
220 ret &= ath_stoprecv(sc);
221 ret &= ath_drain_all_txq(sc);
222 } else {
223 ret &= ath_drain_all_txq(sc);
224 ret &= ath_stoprecv(sc);
225 }
226
227 return ret;
228}
229
230static bool ath_complete_reset(struct ath_softc *sc, bool start)
231{
232 struct ath_hw *ah = sc->sc_ah;
233 struct ath_common *common = ath9k_hw_common(ah);
234 unsigned long flags;
235
236 ath9k_calculate_summary_state(sc, sc->cur_chan);
237 ath_startrecv(sc);
238 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
239 sc->cur_chan->txpower,
240 &sc->cur_chan->cur_txpower);
241 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
242
243 if (!sc->cur_chan->offchannel && start) {
244 /* restore per chanctx TSF timer */
245 if (sc->cur_chan->tsf_val) {
246 u32 offset;
247
248 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
249 NULL);
250 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
251 }
252
253
254 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
255 goto work;
256
257 if (ah->opmode == NL80211_IFTYPE_STATION &&
258 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
259 spin_lock_irqsave(&sc->sc_pm_lock, flags);
260 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
261 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
262 } else {
263 ath9k_set_beacon(sc);
264 }
265 work:
266 ath_restart_work(sc);
267 ath_txq_schedule_all(sc);
268 }
269
270 sc->gtt_cnt = 0;
271
272 ath9k_hw_set_interrupts(ah);
273 ath9k_hw_enable_interrupts(ah);
274 ieee80211_wake_queues(sc->hw);
275 ath9k_p2p_ps_timer(sc);
276
277 return true;
278}
279
280static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
281{
282 struct ath_hw *ah = sc->sc_ah;
283 struct ath_common *common = ath9k_hw_common(ah);
284 struct ath9k_hw_cal_data *caldata = NULL;
285 bool fastcc = true;
286 int r;
287
288 __ath_cancel_work(sc);
289
290 disable_irq(sc->irq);
291 tasklet_disable(&sc->intr_tq);
292 tasklet_disable(&sc->bcon_tasklet);
293 spin_lock_bh(&sc->sc_pcu_lock);
294
295 if (!sc->cur_chan->offchannel) {
296 fastcc = false;
297 caldata = &sc->cur_chan->caldata;
298 }
299
300 if (!hchan) {
301 fastcc = false;
302 hchan = ah->curchan;
303 }
304
305 if (!ath_prepare_reset(sc))
306 fastcc = false;
307
308 if (ath9k_is_chanctx_enabled())
309 fastcc = false;
310
311 spin_lock_bh(&sc->chan_lock);
312 sc->cur_chandef = sc->cur_chan->chandef;
313 spin_unlock_bh(&sc->chan_lock);
314
315 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
316 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
317
318 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
319 if (r) {
320 ath_err(common,
321 "Unable to reset channel, reset status %d\n", r);
322
323 ath9k_hw_enable_interrupts(ah);
324 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
325
326 goto out;
327 }
328
329 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
330 sc->cur_chan->offchannel)
331 ath9k_mci_set_txpower(sc, true, false);
332
333 if (!ath_complete_reset(sc, true))
334 r = -EIO;
335
336out:
337 enable_irq(sc->irq);
338 spin_unlock_bh(&sc->sc_pcu_lock);
339 tasklet_enable(&sc->bcon_tasklet);
340 tasklet_enable(&sc->intr_tq);
341
342 return r;
343}
344
345static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
346 struct ieee80211_vif *vif)
347{
348 struct ath_node *an;
349 an = (struct ath_node *)sta->drv_priv;
350
351 an->sc = sc;
352 an->sta = sta;
353 an->vif = vif;
354 memset(&an->key_idx, 0, sizeof(an->key_idx));
355
356 ath_tx_node_init(sc, an);
357
358 ath_dynack_node_init(sc->sc_ah, an);
359}
360
361static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
362{
363 struct ath_node *an = (struct ath_node *)sta->drv_priv;
364 ath_tx_node_cleanup(sc, an);
365
366 ath_dynack_node_deinit(sc->sc_ah, an);
367}
368
369void ath9k_tasklet(unsigned long data)
370{
371 struct ath_softc *sc = (struct ath_softc *)data;
372 struct ath_hw *ah = sc->sc_ah;
373 struct ath_common *common = ath9k_hw_common(ah);
374 enum ath_reset_type type;
375 unsigned long flags;
376 u32 status = sc->intrstatus;
377 u32 rxmask;
378
379 ath9k_ps_wakeup(sc);
380 spin_lock(&sc->sc_pcu_lock);
381
382 if (status & ATH9K_INT_FATAL) {
383 type = RESET_TYPE_FATAL_INT;
384 ath9k_queue_reset(sc, type);
385
386 /*
387 * Increment the ref. counter here so that
388 * interrupts are enabled in the reset routine.
389 */
390 atomic_inc(&ah->intr_ref_cnt);
391 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
392 goto out;
393 }
394
395 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
396 (status & ATH9K_INT_BB_WATCHDOG)) {
397 spin_lock(&common->cc_lock);
398 ath_hw_cycle_counters_update(common);
399 ar9003_hw_bb_watchdog_dbg_info(ah);
400 spin_unlock(&common->cc_lock);
401
402 if (ar9003_hw_bb_watchdog_check(ah)) {
403 type = RESET_TYPE_BB_WATCHDOG;
404 ath9k_queue_reset(sc, type);
405
406 /*
407 * Increment the ref. counter here so that
408 * interrupts are enabled in the reset routine.
409 */
410 atomic_inc(&ah->intr_ref_cnt);
411 ath_dbg(common, RESET,
412 "BB_WATCHDOG: Skipping interrupts\n");
413 goto out;
414 }
415 }
416
417 if (status & ATH9K_INT_GTT) {
418 sc->gtt_cnt++;
419
420 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
421 type = RESET_TYPE_TX_GTT;
422 ath9k_queue_reset(sc, type);
423 atomic_inc(&ah->intr_ref_cnt);
424 ath_dbg(common, RESET,
425 "GTT: Skipping interrupts\n");
426 goto out;
427 }
428 }
429
430 spin_lock_irqsave(&sc->sc_pm_lock, flags);
431 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
432 /*
433 * TSF sync does not look correct; remain awake to sync with
434 * the next Beacon.
435 */
436 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
437 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
438 }
439 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
440
441 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
442 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
443 ATH9K_INT_RXORN);
444 else
445 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
446
447 if (status & rxmask) {
448 /* Check for high priority Rx first */
449 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
450 (status & ATH9K_INT_RXHP))
451 ath_rx_tasklet(sc, 0, true);
452
453 ath_rx_tasklet(sc, 0, false);
454 }
455
456 if (status & ATH9K_INT_TX) {
457 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
458 /*
459 * For EDMA chips, TX completion is enabled for the
460 * beacon queue, so if a beacon has been transmitted
461 * successfully after a GTT interrupt, the GTT counter
462 * gets reset to zero here.
463 */
464 sc->gtt_cnt = 0;
465
466 ath_tx_edma_tasklet(sc);
467 } else {
468 ath_tx_tasklet(sc);
469 }
470
471 wake_up(&sc->tx_wait);
472 }
473
474 if (status & ATH9K_INT_GENTIMER)
475 ath_gen_timer_isr(sc->sc_ah);
476
477 ath9k_btcoex_handle_interrupt(sc, status);
478
479 /* re-enable hardware interrupt */
480 ath9k_hw_enable_interrupts(ah);
481out:
482 spin_unlock(&sc->sc_pcu_lock);
483 ath9k_ps_restore(sc);
484}
485
486irqreturn_t ath_isr(int irq, void *dev)
487{
488#define SCHED_INTR ( \
489 ATH9K_INT_FATAL | \
490 ATH9K_INT_BB_WATCHDOG | \
491 ATH9K_INT_RXORN | \
492 ATH9K_INT_RXEOL | \
493 ATH9K_INT_RX | \
494 ATH9K_INT_RXLP | \
495 ATH9K_INT_RXHP | \
496 ATH9K_INT_TX | \
497 ATH9K_INT_BMISS | \
498 ATH9K_INT_CST | \
499 ATH9K_INT_GTT | \
500 ATH9K_INT_TSFOOR | \
501 ATH9K_INT_GENTIMER | \
502 ATH9K_INT_MCI)
503
504 struct ath_softc *sc = dev;
505 struct ath_hw *ah = sc->sc_ah;
506 struct ath_common *common = ath9k_hw_common(ah);
507 enum ath9k_int status;
508 u32 sync_cause = 0;
509 bool sched = false;
510
511 /*
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
515 */
516 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
517 return IRQ_NONE;
518
519 /* shared irq, not for us */
520 if (!ath9k_hw_intrpend(ah))
521 return IRQ_NONE;
522
523 /*
524 * Figure out the reason(s) for the interrupt. Note
525 * that the hal returns a pseudo-ISR that may include
526 * bits we haven't explicitly enabled so we mask the
527 * value to insure we only process bits we requested.
528 */
529 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
530 ath9k_debug_sync_cause(sc, sync_cause);
531 status &= ah->imask; /* discard unasked-for bits */
532
533 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
534 return IRQ_HANDLED;
535
536 /*
537 * If there are no status bits set, then this interrupt was not
538 * for me (should have been caught above).
539 */
540 if (!status)
541 return IRQ_NONE;
542
543 /* Cache the status */
544 sc->intrstatus = status;
545
546 if (status & SCHED_INTR)
547 sched = true;
548
549 /*
550 * If a FATAL interrupt is received, we have to reset the chip
551 * immediately.
552 */
553 if (status & ATH9K_INT_FATAL)
554 goto chip_reset;
555
556 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
557 (status & ATH9K_INT_BB_WATCHDOG))
558 goto chip_reset;
559
560 if (status & ATH9K_INT_SWBA)
561 tasklet_schedule(&sc->bcon_tasklet);
562
563 if (status & ATH9K_INT_TXURN)
564 ath9k_hw_updatetxtriglevel(ah, true);
565
566 if (status & ATH9K_INT_RXEOL) {
567 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
568 ath9k_hw_set_interrupts(ah);
569 }
570
571 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
572 if (status & ATH9K_INT_TIM_TIMER) {
573 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
574 goto chip_reset;
575 /* Clear RxAbort bit so that we can
576 * receive frames */
577 ath9k_setpower(sc, ATH9K_PM_AWAKE);
578 spin_lock(&sc->sc_pm_lock);
579 ath9k_hw_setrxabort(sc->sc_ah, 0);
580 sc->ps_flags |= PS_WAIT_FOR_BEACON;
581 spin_unlock(&sc->sc_pm_lock);
582 }
583
584chip_reset:
585
586 ath_debug_stat_interrupt(sc, status);
587
588 if (sched) {
589 /* turn off every interrupt */
590 ath9k_hw_disable_interrupts(ah);
591 tasklet_schedule(&sc->intr_tq);
592 }
593
594 return IRQ_HANDLED;
595
596#undef SCHED_INTR
597}
598
599/*
600 * This function is called when a HW reset cannot be deferred
601 * and has to be immediate.
602 */
603int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
604{
605 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
606 int r;
607
608 ath9k_hw_kill_interrupts(sc->sc_ah);
609 set_bit(ATH_OP_HW_RESET, &common->op_flags);
610
611 ath9k_ps_wakeup(sc);
612 r = ath_reset_internal(sc, hchan);
613 ath9k_ps_restore(sc);
614
615 return r;
616}
617
618/*
619 * When a HW reset can be deferred, it is added to the
620 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
621 * queueing.
622 */
623void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
624{
625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
626#ifdef CONFIG_ATH9K_DEBUGFS
627 RESET_STAT_INC(sc, type);
628#endif
629 ath9k_hw_kill_interrupts(sc->sc_ah);
630 set_bit(ATH_OP_HW_RESET, &common->op_flags);
631 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
632}
633
634void ath_reset_work(struct work_struct *work)
635{
636 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
637
638 ath9k_ps_wakeup(sc);
639 ath_reset_internal(sc, NULL);
640 ath9k_ps_restore(sc);
641}
642
643/**********************/
644/* mac80211 callbacks */
645/**********************/
646
647static int ath9k_start(struct ieee80211_hw *hw)
648{
649 struct ath_softc *sc = hw->priv;
650 struct ath_hw *ah = sc->sc_ah;
651 struct ath_common *common = ath9k_hw_common(ah);
652 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
653 struct ath_chanctx *ctx = sc->cur_chan;
654 struct ath9k_channel *init_channel;
655 int r;
656
657 ath_dbg(common, CONFIG,
658 "Starting driver with initial channel: %d MHz\n",
659 curchan->center_freq);
660
661 ath9k_ps_wakeup(sc);
662 mutex_lock(&sc->mutex);
663
664 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
665 sc->cur_chandef = hw->conf.chandef;
666
667 /* Reset SERDES registers */
668 ath9k_hw_configpcipowersave(ah, false);
669
670 /*
671 * The basic interface to setting the hardware in a good
672 * state is ``reset''. On return the hardware is known to
673 * be powered up and with interrupts disabled. This must
674 * be followed by initialization of the appropriate bits
675 * and then setup of the interrupt mask.
676 */
677 spin_lock_bh(&sc->sc_pcu_lock);
678
679 atomic_set(&ah->intr_ref_cnt, -1);
680
681 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
682 if (r) {
683 ath_err(common,
684 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
685 r, curchan->center_freq);
686 ah->reset_power_on = false;
687 }
688
689 /* Setup our intr mask. */
690 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
691 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
692 ATH9K_INT_GLOBAL;
693
694 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
695 ah->imask |= ATH9K_INT_RXHP |
696 ATH9K_INT_RXLP;
697 else
698 ah->imask |= ATH9K_INT_RX;
699
700 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
701 ah->imask |= ATH9K_INT_BB_WATCHDOG;
702
703 /*
704 * Enable GTT interrupts only for AR9003/AR9004 chips
705 * for now.
706 */
707 if (AR_SREV_9300_20_OR_LATER(ah))
708 ah->imask |= ATH9K_INT_GTT;
709
710 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
711 ah->imask |= ATH9K_INT_CST;
712
713 ath_mci_enable(sc);
714
715 clear_bit(ATH_OP_INVALID, &common->op_flags);
716 sc->sc_ah->is_monitoring = false;
717
718 if (!ath_complete_reset(sc, false))
719 ah->reset_power_on = false;
720
721 if (ah->led_pin >= 0) {
722 ath9k_hw_cfg_output(ah, ah->led_pin,
723 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
724 ath9k_hw_set_gpio(ah, ah->led_pin,
725 (ah->config.led_active_high) ? 1 : 0);
726 }
727
728 /*
729 * Reset key cache to sane defaults (all entries cleared) instead of
730 * semi-random values after suspend/resume.
731 */
732 ath9k_cmn_init_crypto(sc->sc_ah);
733
734 ath9k_hw_reset_tsf(ah);
735
736 spin_unlock_bh(&sc->sc_pcu_lock);
737
738 mutex_unlock(&sc->mutex);
739
740 ath9k_ps_restore(sc);
741
742 ath9k_rng_start(sc);
743
744 return 0;
745}
746
747static void ath9k_tx(struct ieee80211_hw *hw,
748 struct ieee80211_tx_control *control,
749 struct sk_buff *skb)
750{
751 struct ath_softc *sc = hw->priv;
752 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
753 struct ath_tx_control txctl;
754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
755 unsigned long flags;
756
757 if (sc->ps_enabled) {
758 /*
759 * mac80211 does not set PM field for normal data frames, so we
760 * need to update that based on the current PS mode.
761 */
762 if (ieee80211_is_data(hdr->frame_control) &&
763 !ieee80211_is_nullfunc(hdr->frame_control) &&
764 !ieee80211_has_pm(hdr->frame_control)) {
765 ath_dbg(common, PS,
766 "Add PM=1 for a TX frame while in PS mode\n");
767 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
768 }
769 }
770
771 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
772 /*
773 * We are using PS-Poll and mac80211 can request TX while in
774 * power save mode. Need to wake up hardware for the TX to be
775 * completed and if needed, also for RX of buffered frames.
776 */
777 ath9k_ps_wakeup(sc);
778 spin_lock_irqsave(&sc->sc_pm_lock, flags);
779 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
780 ath9k_hw_setrxabort(sc->sc_ah, 0);
781 if (ieee80211_is_pspoll(hdr->frame_control)) {
782 ath_dbg(common, PS,
783 "Sending PS-Poll to pick a buffered frame\n");
784 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
785 } else {
786 ath_dbg(common, PS, "Wake up to complete TX\n");
787 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
788 }
789 /*
790 * The actual restore operation will happen only after
791 * the ps_flags bit is cleared. We are just dropping
792 * the ps_usecount here.
793 */
794 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
795 ath9k_ps_restore(sc);
796 }
797
798 /*
799 * Cannot tx while the hardware is in full sleep, it first needs a full
800 * chip reset to recover from that
801 */
802 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
803 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
804 goto exit;
805 }
806
807 memset(&txctl, 0, sizeof(struct ath_tx_control));
808 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
809 txctl.sta = control->sta;
810
811 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
812
813 if (ath_tx_start(hw, skb, &txctl) != 0) {
814 ath_dbg(common, XMIT, "TX failed\n");
815 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
816 goto exit;
817 }
818
819 return;
820exit:
821 ieee80211_free_txskb(hw, skb);
822}
823
824static void ath9k_stop(struct ieee80211_hw *hw)
825{
826 struct ath_softc *sc = hw->priv;
827 struct ath_hw *ah = sc->sc_ah;
828 struct ath_common *common = ath9k_hw_common(ah);
829 bool prev_idle;
830
831 ath9k_deinit_channel_context(sc);
832
833 ath9k_rng_stop(sc);
834
835 mutex_lock(&sc->mutex);
836
837 ath_cancel_work(sc);
838
839 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
840 ath_dbg(common, ANY, "Device not present\n");
841 mutex_unlock(&sc->mutex);
842 return;
843 }
844
845 /* Ensure HW is awake when we try to shut it down. */
846 ath9k_ps_wakeup(sc);
847
848 spin_lock_bh(&sc->sc_pcu_lock);
849
850 /* prevent tasklets to enable interrupts once we disable them */
851 ah->imask &= ~ATH9K_INT_GLOBAL;
852
853 /* make sure h/w will not generate any interrupt
854 * before setting the invalid flag. */
855 ath9k_hw_disable_interrupts(ah);
856
857 spin_unlock_bh(&sc->sc_pcu_lock);
858
859 /* we can now sync irq and kill any running tasklets, since we already
860 * disabled interrupts and not holding a spin lock */
861 synchronize_irq(sc->irq);
862 tasklet_kill(&sc->intr_tq);
863 tasklet_kill(&sc->bcon_tasklet);
864
865 prev_idle = sc->ps_idle;
866 sc->ps_idle = true;
867
868 spin_lock_bh(&sc->sc_pcu_lock);
869
870 if (ah->led_pin >= 0) {
871 ath9k_hw_set_gpio(ah, ah->led_pin,
872 (ah->config.led_active_high) ? 0 : 1);
873 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
874 }
875
876 ath_prepare_reset(sc);
877
878 if (sc->rx.frag) {
879 dev_kfree_skb_any(sc->rx.frag);
880 sc->rx.frag = NULL;
881 }
882
883 if (!ah->curchan)
884 ah->curchan = ath9k_cmn_get_channel(hw, ah,
885 &sc->cur_chan->chandef);
886
887 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
888
889 set_bit(ATH_OP_INVALID, &common->op_flags);
890
891 ath9k_hw_phy_disable(ah);
892
893 ath9k_hw_configpcipowersave(ah, true);
894
895 spin_unlock_bh(&sc->sc_pcu_lock);
896
897 ath9k_ps_restore(sc);
898
899 sc->ps_idle = prev_idle;
900
901 mutex_unlock(&sc->mutex);
902
903 ath_dbg(common, CONFIG, "Driver halt\n");
904}
905
906static bool ath9k_uses_beacons(int type)
907{
908 switch (type) {
909 case NL80211_IFTYPE_AP:
910 case NL80211_IFTYPE_ADHOC:
911 case NL80211_IFTYPE_MESH_POINT:
912 return true;
913 default:
914 return false;
915 }
916}
917
918static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
919 u8 *mac, struct ieee80211_vif *vif)
920{
921 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
922 int i;
923
924 if (iter_data->has_hw_macaddr) {
925 for (i = 0; i < ETH_ALEN; i++)
926 iter_data->mask[i] &=
927 ~(iter_data->hw_macaddr[i] ^ mac[i]);
928 } else {
929 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
930 iter_data->has_hw_macaddr = true;
931 }
932
933 if (!vif->bss_conf.use_short_slot)
934 iter_data->slottime = ATH9K_SLOT_TIME_20;
935
936 switch (vif->type) {
937 case NL80211_IFTYPE_AP:
938 iter_data->naps++;
939 break;
940 case NL80211_IFTYPE_STATION:
941 iter_data->nstations++;
942 if (avp->assoc && !iter_data->primary_sta)
943 iter_data->primary_sta = vif;
944 break;
945 case NL80211_IFTYPE_OCB:
946 iter_data->nocbs++;
947 break;
948 case NL80211_IFTYPE_ADHOC:
949 iter_data->nadhocs++;
950 if (vif->bss_conf.enable_beacon)
951 iter_data->beacons = true;
952 break;
953 case NL80211_IFTYPE_MESH_POINT:
954 iter_data->nmeshes++;
955 if (vif->bss_conf.enable_beacon)
956 iter_data->beacons = true;
957 break;
958 case NL80211_IFTYPE_WDS:
959 iter_data->nwds++;
960 break;
961 default:
962 break;
963 }
964}
965
966static void ath9k_update_bssid_mask(struct ath_softc *sc,
967 struct ath_chanctx *ctx,
968 struct ath9k_vif_iter_data *iter_data)
969{
970 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
971 struct ath_vif *avp;
972 int i;
973
974 if (!ath9k_is_chanctx_enabled())
975 return;
976
977 list_for_each_entry(avp, &ctx->vifs, list) {
978 if (ctx->nvifs_assigned != 1)
979 continue;
980
981 if (!iter_data->has_hw_macaddr)
982 continue;
983
984 ether_addr_copy(common->curbssid, avp->bssid);
985
986 /* perm_addr will be used as the p2p device address. */
987 for (i = 0; i < ETH_ALEN; i++)
988 iter_data->mask[i] &=
989 ~(iter_data->hw_macaddr[i] ^
990 sc->hw->wiphy->perm_addr[i]);
991 }
992}
993
994/* Called with sc->mutex held. */
995void ath9k_calculate_iter_data(struct ath_softc *sc,
996 struct ath_chanctx *ctx,
997 struct ath9k_vif_iter_data *iter_data)
998{
999 struct ath_vif *avp;
1000
1001 /*
1002 * The hardware will use primary station addr together with the
1003 * BSSID mask when matching addresses.
1004 */
1005 memset(iter_data, 0, sizeof(*iter_data));
1006 eth_broadcast_addr(iter_data->mask);
1007 iter_data->slottime = ATH9K_SLOT_TIME_9;
1008
1009 list_for_each_entry(avp, &ctx->vifs, list)
1010 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1011
1012 ath9k_update_bssid_mask(sc, ctx, iter_data);
1013}
1014
1015static void ath9k_set_assoc_state(struct ath_softc *sc,
1016 struct ieee80211_vif *vif, bool changed)
1017{
1018 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1019 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1020 unsigned long flags;
1021
1022 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1023
1024 ether_addr_copy(common->curbssid, avp->bssid);
1025 common->curaid = avp->aid;
1026 ath9k_hw_write_associd(sc->sc_ah);
1027
1028 if (changed) {
1029 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1030 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1031
1032 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1033 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1034 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1035 }
1036
1037 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1038 ath9k_mci_update_wlan_channels(sc, false);
1039
1040 ath_dbg(common, CONFIG,
1041 "Primary Station interface: %pM, BSSID: %pM\n",
1042 vif->addr, common->curbssid);
1043}
1044
1045#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1046static void ath9k_set_offchannel_state(struct ath_softc *sc)
1047{
1048 struct ath_hw *ah = sc->sc_ah;
1049 struct ath_common *common = ath9k_hw_common(ah);
1050 struct ieee80211_vif *vif = NULL;
1051
1052 ath9k_ps_wakeup(sc);
1053
1054 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1055 vif = sc->offchannel.scan_vif;
1056 else
1057 vif = sc->offchannel.roc_vif;
1058
1059 if (WARN_ON(!vif))
1060 goto exit;
1061
1062 eth_zero_addr(common->curbssid);
1063 eth_broadcast_addr(common->bssidmask);
1064 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1065 common->curaid = 0;
1066 ah->opmode = vif->type;
1067 ah->imask &= ~ATH9K_INT_SWBA;
1068 ah->imask &= ~ATH9K_INT_TSFOOR;
1069 ah->slottime = ATH9K_SLOT_TIME_9;
1070
1071 ath_hw_setbssidmask(common);
1072 ath9k_hw_setopmode(ah);
1073 ath9k_hw_write_associd(sc->sc_ah);
1074 ath9k_hw_set_interrupts(ah);
1075 ath9k_hw_init_global_settings(ah);
1076
1077exit:
1078 ath9k_ps_restore(sc);
1079}
1080#endif
1081
1082/* Called with sc->mutex held. */
1083void ath9k_calculate_summary_state(struct ath_softc *sc,
1084 struct ath_chanctx *ctx)
1085{
1086 struct ath_hw *ah = sc->sc_ah;
1087 struct ath_common *common = ath9k_hw_common(ah);
1088 struct ath9k_vif_iter_data iter_data;
1089 struct ath_beacon_config *cur_conf;
1090
1091 ath_chanctx_check_active(sc, ctx);
1092
1093 if (ctx != sc->cur_chan)
1094 return;
1095
1096#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1097 if (ctx == &sc->offchannel.chan)
1098 return ath9k_set_offchannel_state(sc);
1099#endif
1100
1101 ath9k_ps_wakeup(sc);
1102 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1103
1104 if (iter_data.has_hw_macaddr)
1105 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1106
1107 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1108 ath_hw_setbssidmask(common);
1109
1110 if (iter_data.naps > 0) {
1111 cur_conf = &ctx->beacon;
1112 ath9k_hw_set_tsfadjust(ah, true);
1113 ah->opmode = NL80211_IFTYPE_AP;
1114 if (cur_conf->enable_beacon)
1115 iter_data.beacons = true;
1116 } else {
1117 ath9k_hw_set_tsfadjust(ah, false);
1118
1119 if (iter_data.nmeshes)
1120 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1121 else if (iter_data.nocbs)
1122 ah->opmode = NL80211_IFTYPE_OCB;
1123 else if (iter_data.nwds)
1124 ah->opmode = NL80211_IFTYPE_AP;
1125 else if (iter_data.nadhocs)
1126 ah->opmode = NL80211_IFTYPE_ADHOC;
1127 else
1128 ah->opmode = NL80211_IFTYPE_STATION;
1129 }
1130
1131 ath9k_hw_setopmode(ah);
1132
1133 ctx->switch_after_beacon = false;
1134 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1135 ah->imask |= ATH9K_INT_TSFOOR;
1136 else {
1137 ah->imask &= ~ATH9K_INT_TSFOOR;
1138 if (iter_data.naps == 1 && iter_data.beacons)
1139 ctx->switch_after_beacon = true;
1140 }
1141
1142 ah->imask &= ~ATH9K_INT_SWBA;
1143 if (ah->opmode == NL80211_IFTYPE_STATION) {
1144 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1145
1146 if (iter_data.primary_sta) {
1147 iter_data.beacons = true;
1148 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1149 changed);
1150 ctx->primary_sta = iter_data.primary_sta;
1151 } else {
1152 ctx->primary_sta = NULL;
1153 eth_zero_addr(common->curbssid);
1154 common->curaid = 0;
1155 ath9k_hw_write_associd(sc->sc_ah);
1156 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1157 ath9k_mci_update_wlan_channels(sc, true);
1158 }
1159 } else if (iter_data.beacons) {
1160 ah->imask |= ATH9K_INT_SWBA;
1161 }
1162 ath9k_hw_set_interrupts(ah);
1163
1164 if (iter_data.beacons)
1165 set_bit(ATH_OP_BEACONS, &common->op_flags);
1166 else
1167 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1168
1169 if (ah->slottime != iter_data.slottime) {
1170 ah->slottime = iter_data.slottime;
1171 ath9k_hw_init_global_settings(ah);
1172 }
1173
1174 if (iter_data.primary_sta)
1175 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1176 else
1177 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1178
1179 ath_dbg(common, CONFIG,
1180 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1181 common->macaddr, common->curbssid, common->bssidmask);
1182
1183 ath9k_ps_restore(sc);
1184}
1185
1186static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1187{
1188 int *power = (int *)data;
1189
1190 if (*power < vif->bss_conf.txpower)
1191 *power = vif->bss_conf.txpower;
1192}
1193
1194/* Called with sc->mutex held. */
1195void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1196{
1197 int power;
1198 struct ath_hw *ah = sc->sc_ah;
1199 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1200
1201 ath9k_ps_wakeup(sc);
1202 if (ah->tpc_enabled) {
1203 power = (vif) ? vif->bss_conf.txpower : -1;
1204 ieee80211_iterate_active_interfaces_atomic(
1205 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1206 ath9k_tpc_vif_iter, &power);
1207 if (power == -1)
1208 power = sc->hw->conf.power_level;
1209 } else {
1210 power = sc->hw->conf.power_level;
1211 }
1212 sc->cur_chan->txpower = 2 * power;
1213 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1214 sc->cur_chan->cur_txpower = reg->max_power_level;
1215 ath9k_ps_restore(sc);
1216}
1217
1218static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1219 struct ieee80211_vif *vif)
1220{
1221 int i;
1222
1223 if (!ath9k_is_chanctx_enabled())
1224 return;
1225
1226 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1227 vif->hw_queue[i] = i;
1228
1229 if (vif->type == NL80211_IFTYPE_AP ||
1230 vif->type == NL80211_IFTYPE_MESH_POINT)
1231 vif->cab_queue = hw->queues - 2;
1232 else
1233 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1234}
1235
1236static int ath9k_add_interface(struct ieee80211_hw *hw,
1237 struct ieee80211_vif *vif)
1238{
1239 struct ath_softc *sc = hw->priv;
1240 struct ath_hw *ah = sc->sc_ah;
1241 struct ath_common *common = ath9k_hw_common(ah);
1242 struct ath_vif *avp = (void *)vif->drv_priv;
1243 struct ath_node *an = &avp->mcast_node;
1244
1245 mutex_lock(&sc->mutex);
1246
1247 if (config_enabled(CONFIG_ATH9K_TX99)) {
1248 if (sc->cur_chan->nvifs >= 1) {
1249 mutex_unlock(&sc->mutex);
1250 return -EOPNOTSUPP;
1251 }
1252 sc->tx99_vif = vif;
1253 }
1254
1255 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1256 sc->cur_chan->nvifs++;
1257
1258 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1259 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1260
1261 if (ath9k_uses_beacons(vif->type))
1262 ath9k_beacon_assign_slot(sc, vif);
1263
1264 avp->vif = vif;
1265 if (!ath9k_is_chanctx_enabled()) {
1266 avp->chanctx = sc->cur_chan;
1267 list_add_tail(&avp->list, &avp->chanctx->vifs);
1268 }
1269
1270 ath9k_calculate_summary_state(sc, avp->chanctx);
1271
1272 ath9k_assign_hw_queues(hw, vif);
1273
1274 ath9k_set_txpower(sc, vif);
1275
1276 an->sc = sc;
1277 an->sta = NULL;
1278 an->vif = vif;
1279 an->no_ps_filter = true;
1280 ath_tx_node_init(sc, an);
1281
1282 mutex_unlock(&sc->mutex);
1283 return 0;
1284}
1285
1286static int ath9k_change_interface(struct ieee80211_hw *hw,
1287 struct ieee80211_vif *vif,
1288 enum nl80211_iftype new_type,
1289 bool p2p)
1290{
1291 struct ath_softc *sc = hw->priv;
1292 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1293 struct ath_vif *avp = (void *)vif->drv_priv;
1294
1295 mutex_lock(&sc->mutex);
1296
1297 if (config_enabled(CONFIG_ATH9K_TX99)) {
1298 mutex_unlock(&sc->mutex);
1299 return -EOPNOTSUPP;
1300 }
1301
1302 ath_dbg(common, CONFIG, "Change Interface\n");
1303
1304 if (ath9k_uses_beacons(vif->type))
1305 ath9k_beacon_remove_slot(sc, vif);
1306
1307 vif->type = new_type;
1308 vif->p2p = p2p;
1309
1310 if (ath9k_uses_beacons(vif->type))
1311 ath9k_beacon_assign_slot(sc, vif);
1312
1313 ath9k_assign_hw_queues(hw, vif);
1314 ath9k_calculate_summary_state(sc, avp->chanctx);
1315
1316 ath9k_set_txpower(sc, vif);
1317
1318 mutex_unlock(&sc->mutex);
1319 return 0;
1320}
1321
1322static void ath9k_remove_interface(struct ieee80211_hw *hw,
1323 struct ieee80211_vif *vif)
1324{
1325 struct ath_softc *sc = hw->priv;
1326 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1327 struct ath_vif *avp = (void *)vif->drv_priv;
1328
1329 ath_dbg(common, CONFIG, "Detach Interface\n");
1330
1331 mutex_lock(&sc->mutex);
1332
1333 ath9k_p2p_remove_vif(sc, vif);
1334
1335 sc->cur_chan->nvifs--;
1336 sc->tx99_vif = NULL;
1337 if (!ath9k_is_chanctx_enabled())
1338 list_del(&avp->list);
1339
1340 if (ath9k_uses_beacons(vif->type))
1341 ath9k_beacon_remove_slot(sc, vif);
1342
1343 ath_tx_node_cleanup(sc, &avp->mcast_node);
1344
1345 ath9k_calculate_summary_state(sc, avp->chanctx);
1346
1347 ath9k_set_txpower(sc, NULL);
1348
1349 mutex_unlock(&sc->mutex);
1350}
1351
1352static void ath9k_enable_ps(struct ath_softc *sc)
1353{
1354 struct ath_hw *ah = sc->sc_ah;
1355 struct ath_common *common = ath9k_hw_common(ah);
1356
1357 if (config_enabled(CONFIG_ATH9K_TX99))
1358 return;
1359
1360 sc->ps_enabled = true;
1361 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1362 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1363 ah->imask |= ATH9K_INT_TIM_TIMER;
1364 ath9k_hw_set_interrupts(ah);
1365 }
1366 ath9k_hw_setrxabort(ah, 1);
1367 }
1368 ath_dbg(common, PS, "PowerSave enabled\n");
1369}
1370
1371static void ath9k_disable_ps(struct ath_softc *sc)
1372{
1373 struct ath_hw *ah = sc->sc_ah;
1374 struct ath_common *common = ath9k_hw_common(ah);
1375
1376 if (config_enabled(CONFIG_ATH9K_TX99))
1377 return;
1378
1379 sc->ps_enabled = false;
1380 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1381 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1382 ath9k_hw_setrxabort(ah, 0);
1383 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1384 PS_WAIT_FOR_CAB |
1385 PS_WAIT_FOR_PSPOLL_DATA |
1386 PS_WAIT_FOR_TX_ACK);
1387 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1388 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1389 ath9k_hw_set_interrupts(ah);
1390 }
1391 }
1392 ath_dbg(common, PS, "PowerSave disabled\n");
1393}
1394
1395static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1396{
1397 struct ath_softc *sc = hw->priv;
1398 struct ath_hw *ah = sc->sc_ah;
1399 struct ath_common *common = ath9k_hw_common(ah);
1400 struct ieee80211_conf *conf = &hw->conf;
1401 struct ath_chanctx *ctx = sc->cur_chan;
1402
1403 ath9k_ps_wakeup(sc);
1404 mutex_lock(&sc->mutex);
1405
1406 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1407 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1408 if (sc->ps_idle) {
1409 ath_cancel_work(sc);
1410 ath9k_stop_btcoex(sc);
1411 } else {
1412 ath9k_start_btcoex(sc);
1413 /*
1414 * The chip needs a reset to properly wake up from
1415 * full sleep
1416 */
1417 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1418 }
1419 }
1420
1421 /*
1422 * We just prepare to enable PS. We have to wait until our AP has
1423 * ACK'd our null data frame to disable RX otherwise we'll ignore
1424 * those ACKs and end up retransmitting the same null data frames.
1425 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1426 */
1427 if (changed & IEEE80211_CONF_CHANGE_PS) {
1428 unsigned long flags;
1429 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1430 if (conf->flags & IEEE80211_CONF_PS)
1431 ath9k_enable_ps(sc);
1432 else
1433 ath9k_disable_ps(sc);
1434 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1435 }
1436
1437 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1438 if (conf->flags & IEEE80211_CONF_MONITOR) {
1439 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1440 sc->sc_ah->is_monitoring = true;
1441 } else {
1442 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1443 sc->sc_ah->is_monitoring = false;
1444 }
1445 }
1446
1447 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1448 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1449 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1450 }
1451
1452 mutex_unlock(&sc->mutex);
1453 ath9k_ps_restore(sc);
1454
1455 return 0;
1456}
1457
1458#define SUPPORTED_FILTERS \
1459 (FIF_ALLMULTI | \
1460 FIF_CONTROL | \
1461 FIF_PSPOLL | \
1462 FIF_OTHER_BSS | \
1463 FIF_BCN_PRBRESP_PROMISC | \
1464 FIF_PROBE_REQ | \
1465 FIF_FCSFAIL)
1466
1467/* FIXME: sc->sc_full_reset ? */
1468static void ath9k_configure_filter(struct ieee80211_hw *hw,
1469 unsigned int changed_flags,
1470 unsigned int *total_flags,
1471 u64 multicast)
1472{
1473 struct ath_softc *sc = hw->priv;
1474 struct ath_chanctx *ctx;
1475 u32 rfilt;
1476
1477 changed_flags &= SUPPORTED_FILTERS;
1478 *total_flags &= SUPPORTED_FILTERS;
1479
1480 spin_lock_bh(&sc->chan_lock);
1481 ath_for_each_chanctx(sc, ctx)
1482 ctx->rxfilter = *total_flags;
1483#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1484 sc->offchannel.chan.rxfilter = *total_flags;
1485#endif
1486 spin_unlock_bh(&sc->chan_lock);
1487
1488 ath9k_ps_wakeup(sc);
1489 rfilt = ath_calcrxfilter(sc);
1490 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1491 ath9k_ps_restore(sc);
1492
1493 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1494 rfilt);
1495}
1496
1497static int ath9k_sta_add(struct ieee80211_hw *hw,
1498 struct ieee80211_vif *vif,
1499 struct ieee80211_sta *sta)
1500{
1501 struct ath_softc *sc = hw->priv;
1502 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1503 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1504 struct ieee80211_key_conf ps_key = { };
1505 int key;
1506
1507 ath_node_attach(sc, sta, vif);
1508
1509 if (vif->type != NL80211_IFTYPE_AP &&
1510 vif->type != NL80211_IFTYPE_AP_VLAN)
1511 return 0;
1512
1513 key = ath_key_config(common, vif, sta, &ps_key);
1514 if (key > 0) {
1515 an->ps_key = key;
1516 an->key_idx[0] = key;
1517 }
1518
1519 return 0;
1520}
1521
1522static void ath9k_del_ps_key(struct ath_softc *sc,
1523 struct ieee80211_vif *vif,
1524 struct ieee80211_sta *sta)
1525{
1526 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1527 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1528 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1529
1530 if (!an->ps_key)
1531 return;
1532
1533 ath_key_delete(common, &ps_key);
1534 an->ps_key = 0;
1535 an->key_idx[0] = 0;
1536}
1537
1538static int ath9k_sta_remove(struct ieee80211_hw *hw,
1539 struct ieee80211_vif *vif,
1540 struct ieee80211_sta *sta)
1541{
1542 struct ath_softc *sc = hw->priv;
1543
1544 ath9k_del_ps_key(sc, vif, sta);
1545 ath_node_detach(sc, sta);
1546
1547 return 0;
1548}
1549
1550static int ath9k_sta_state(struct ieee80211_hw *hw,
1551 struct ieee80211_vif *vif,
1552 struct ieee80211_sta *sta,
1553 enum ieee80211_sta_state old_state,
1554 enum ieee80211_sta_state new_state)
1555{
1556 struct ath_softc *sc = hw->priv;
1557 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1558 int ret = 0;
1559
1560 if (old_state == IEEE80211_STA_AUTH &&
1561 new_state == IEEE80211_STA_ASSOC) {
1562 ret = ath9k_sta_add(hw, vif, sta);
1563 ath_dbg(common, CONFIG,
1564 "Add station: %pM\n", sta->addr);
1565 } else if (old_state == IEEE80211_STA_ASSOC &&
1566 new_state == IEEE80211_STA_AUTH) {
1567 ret = ath9k_sta_remove(hw, vif, sta);
1568 ath_dbg(common, CONFIG,
1569 "Remove station: %pM\n", sta->addr);
1570 }
1571
1572 if (ath9k_is_chanctx_enabled()) {
1573 if (vif->type == NL80211_IFTYPE_STATION) {
1574 if (old_state == IEEE80211_STA_ASSOC &&
1575 new_state == IEEE80211_STA_AUTHORIZED)
1576 ath_chanctx_event(sc, vif,
1577 ATH_CHANCTX_EVENT_AUTHORIZED);
1578 }
1579 }
1580
1581 return ret;
1582}
1583
1584static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1585 struct ath_node *an,
1586 bool set)
1587{
1588 int i;
1589
1590 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1591 if (!an->key_idx[i])
1592 continue;
1593 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1594 }
1595}
1596
1597static void ath9k_sta_notify(struct ieee80211_hw *hw,
1598 struct ieee80211_vif *vif,
1599 enum sta_notify_cmd cmd,
1600 struct ieee80211_sta *sta)
1601{
1602 struct ath_softc *sc = hw->priv;
1603 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1604
1605 switch (cmd) {
1606 case STA_NOTIFY_SLEEP:
1607 an->sleeping = true;
1608 ath_tx_aggr_sleep(sta, sc, an);
1609 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1610 break;
1611 case STA_NOTIFY_AWAKE:
1612 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1613 an->sleeping = false;
1614 ath_tx_aggr_wakeup(sc, an);
1615 break;
1616 }
1617}
1618
1619static int ath9k_conf_tx(struct ieee80211_hw *hw,
1620 struct ieee80211_vif *vif, u16 queue,
1621 const struct ieee80211_tx_queue_params *params)
1622{
1623 struct ath_softc *sc = hw->priv;
1624 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1625 struct ath_txq *txq;
1626 struct ath9k_tx_queue_info qi;
1627 int ret = 0;
1628
1629 if (queue >= IEEE80211_NUM_ACS)
1630 return 0;
1631
1632 txq = sc->tx.txq_map[queue];
1633
1634 ath9k_ps_wakeup(sc);
1635 mutex_lock(&sc->mutex);
1636
1637 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1638
1639 qi.tqi_aifs = params->aifs;
1640 qi.tqi_cwmin = params->cw_min;
1641 qi.tqi_cwmax = params->cw_max;
1642 qi.tqi_burstTime = params->txop * 32;
1643
1644 ath_dbg(common, CONFIG,
1645 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1646 queue, txq->axq_qnum, params->aifs, params->cw_min,
1647 params->cw_max, params->txop);
1648
1649 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1650 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1651 if (ret)
1652 ath_err(common, "TXQ Update failed\n");
1653
1654 mutex_unlock(&sc->mutex);
1655 ath9k_ps_restore(sc);
1656
1657 return ret;
1658}
1659
1660static int ath9k_set_key(struct ieee80211_hw *hw,
1661 enum set_key_cmd cmd,
1662 struct ieee80211_vif *vif,
1663 struct ieee80211_sta *sta,
1664 struct ieee80211_key_conf *key)
1665{
1666 struct ath_softc *sc = hw->priv;
1667 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1668 struct ath_node *an = NULL;
1669 int ret = 0, i;
1670
1671 if (ath9k_modparam_nohwcrypt)
1672 return -ENOSPC;
1673
1674 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1675 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1676 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1677 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1678 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1679 /*
1680 * For now, disable hw crypto for the RSN IBSS group keys. This
1681 * could be optimized in the future to use a modified key cache
1682 * design to support per-STA RX GTK, but until that gets
1683 * implemented, use of software crypto for group addressed
1684 * frames is a acceptable to allow RSN IBSS to be used.
1685 */
1686 return -EOPNOTSUPP;
1687 }
1688
1689 mutex_lock(&sc->mutex);
1690 ath9k_ps_wakeup(sc);
1691 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1692 if (sta)
1693 an = (struct ath_node *)sta->drv_priv;
1694
1695 switch (cmd) {
1696 case SET_KEY:
1697 if (sta)
1698 ath9k_del_ps_key(sc, vif, sta);
1699
1700 key->hw_key_idx = 0;
1701 ret = ath_key_config(common, vif, sta, key);
1702 if (ret >= 0) {
1703 key->hw_key_idx = ret;
1704 /* push IV and Michael MIC generation to stack */
1705 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1706 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1707 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1708 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1709 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1710 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1711 ret = 0;
1712 }
1713 if (an && key->hw_key_idx) {
1714 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1715 if (an->key_idx[i])
1716 continue;
1717 an->key_idx[i] = key->hw_key_idx;
1718 break;
1719 }
1720 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1721 }
1722 break;
1723 case DISABLE_KEY:
1724 ath_key_delete(common, key);
1725 if (an) {
1726 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1727 if (an->key_idx[i] != key->hw_key_idx)
1728 continue;
1729 an->key_idx[i] = 0;
1730 break;
1731 }
1732 }
1733 key->hw_key_idx = 0;
1734 break;
1735 default:
1736 ret = -EINVAL;
1737 }
1738
1739 ath9k_ps_restore(sc);
1740 mutex_unlock(&sc->mutex);
1741
1742 return ret;
1743}
1744
1745static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1746 struct ieee80211_vif *vif,
1747 struct ieee80211_bss_conf *bss_conf,
1748 u32 changed)
1749{
1750#define CHECK_ANI \
1751 (BSS_CHANGED_ASSOC | \
1752 BSS_CHANGED_IBSS | \
1753 BSS_CHANGED_BEACON_ENABLED)
1754
1755 struct ath_softc *sc = hw->priv;
1756 struct ath_hw *ah = sc->sc_ah;
1757 struct ath_common *common = ath9k_hw_common(ah);
1758 struct ath_vif *avp = (void *)vif->drv_priv;
1759 int slottime;
1760
1761 ath9k_ps_wakeup(sc);
1762 mutex_lock(&sc->mutex);
1763
1764 if (changed & BSS_CHANGED_ASSOC) {
1765 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1766 bss_conf->bssid, bss_conf->assoc);
1767
1768 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1769 avp->aid = bss_conf->aid;
1770 avp->assoc = bss_conf->assoc;
1771
1772 ath9k_calculate_summary_state(sc, avp->chanctx);
1773 }
1774
1775 if ((changed & BSS_CHANGED_IBSS) ||
1776 (changed & BSS_CHANGED_OCB)) {
1777 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1778 common->curaid = bss_conf->aid;
1779 ath9k_hw_write_associd(sc->sc_ah);
1780 }
1781
1782 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1783 (changed & BSS_CHANGED_BEACON_INT) ||
1784 (changed & BSS_CHANGED_BEACON_INFO)) {
1785 ath9k_beacon_config(sc, vif, changed);
1786 if (changed & BSS_CHANGED_BEACON_ENABLED)
1787 ath9k_calculate_summary_state(sc, avp->chanctx);
1788 }
1789
1790 if ((avp->chanctx == sc->cur_chan) &&
1791 (changed & BSS_CHANGED_ERP_SLOT)) {
1792 if (bss_conf->use_short_slot)
1793 slottime = 9;
1794 else
1795 slottime = 20;
1796 if (vif->type == NL80211_IFTYPE_AP) {
1797 /*
1798 * Defer update, so that connected stations can adjust
1799 * their settings at the same time.
1800 * See beacon.c for more details
1801 */
1802 sc->beacon.slottime = slottime;
1803 sc->beacon.updateslot = UPDATE;
1804 } else {
1805 ah->slottime = slottime;
1806 ath9k_hw_init_global_settings(ah);
1807 }
1808 }
1809
1810 if (changed & BSS_CHANGED_P2P_PS)
1811 ath9k_p2p_bss_info_changed(sc, vif);
1812
1813 if (changed & CHECK_ANI)
1814 ath_check_ani(sc);
1815
1816 if (changed & BSS_CHANGED_TXPOWER) {
1817 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1818 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1819 ath9k_set_txpower(sc, vif);
1820 }
1821
1822 mutex_unlock(&sc->mutex);
1823 ath9k_ps_restore(sc);
1824
1825#undef CHECK_ANI
1826}
1827
1828static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1829{
1830 struct ath_softc *sc = hw->priv;
1831 u64 tsf;
1832
1833 mutex_lock(&sc->mutex);
1834 ath9k_ps_wakeup(sc);
1835 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1836 ath9k_ps_restore(sc);
1837 mutex_unlock(&sc->mutex);
1838
1839 return tsf;
1840}
1841
1842static void ath9k_set_tsf(struct ieee80211_hw *hw,
1843 struct ieee80211_vif *vif,
1844 u64 tsf)
1845{
1846 struct ath_softc *sc = hw->priv;
1847
1848 mutex_lock(&sc->mutex);
1849 ath9k_ps_wakeup(sc);
1850 ath9k_hw_settsf64(sc->sc_ah, tsf);
1851 ath9k_ps_restore(sc);
1852 mutex_unlock(&sc->mutex);
1853}
1854
1855static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1856{
1857 struct ath_softc *sc = hw->priv;
1858
1859 mutex_lock(&sc->mutex);
1860
1861 ath9k_ps_wakeup(sc);
1862 ath9k_hw_reset_tsf(sc->sc_ah);
1863 ath9k_ps_restore(sc);
1864
1865 mutex_unlock(&sc->mutex);
1866}
1867
1868static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1869 struct ieee80211_vif *vif,
1870 struct ieee80211_ampdu_params *params)
1871{
1872 struct ath_softc *sc = hw->priv;
1873 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1874 bool flush = false;
1875 int ret = 0;
1876 struct ieee80211_sta *sta = params->sta;
1877 enum ieee80211_ampdu_mlme_action action = params->action;
1878 u16 tid = params->tid;
1879 u16 *ssn = ¶ms->ssn;
1880
1881 mutex_lock(&sc->mutex);
1882
1883 switch (action) {
1884 case IEEE80211_AMPDU_RX_START:
1885 break;
1886 case IEEE80211_AMPDU_RX_STOP:
1887 break;
1888 case IEEE80211_AMPDU_TX_START:
1889 if (ath9k_is_chanctx_enabled()) {
1890 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1891 ret = -EBUSY;
1892 break;
1893 }
1894 }
1895 ath9k_ps_wakeup(sc);
1896 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1897 if (!ret)
1898 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1899 ath9k_ps_restore(sc);
1900 break;
1901 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1902 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1903 flush = true;
1904 case IEEE80211_AMPDU_TX_STOP_CONT:
1905 ath9k_ps_wakeup(sc);
1906 ath_tx_aggr_stop(sc, sta, tid);
1907 if (!flush)
1908 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1909 ath9k_ps_restore(sc);
1910 break;
1911 case IEEE80211_AMPDU_TX_OPERATIONAL:
1912 ath9k_ps_wakeup(sc);
1913 ath_tx_aggr_resume(sc, sta, tid);
1914 ath9k_ps_restore(sc);
1915 break;
1916 default:
1917 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1918 }
1919
1920 mutex_unlock(&sc->mutex);
1921
1922 return ret;
1923}
1924
1925static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1926 struct survey_info *survey)
1927{
1928 struct ath_softc *sc = hw->priv;
1929 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1930 struct ieee80211_supported_band *sband;
1931 struct ieee80211_channel *chan;
1932 int pos;
1933
1934 if (config_enabled(CONFIG_ATH9K_TX99))
1935 return -EOPNOTSUPP;
1936
1937 spin_lock_bh(&common->cc_lock);
1938 if (idx == 0)
1939 ath_update_survey_stats(sc);
1940
1941 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1942 if (sband && idx >= sband->n_channels) {
1943 idx -= sband->n_channels;
1944 sband = NULL;
1945 }
1946
1947 if (!sband)
1948 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1949
1950 if (!sband || idx >= sband->n_channels) {
1951 spin_unlock_bh(&common->cc_lock);
1952 return -ENOENT;
1953 }
1954
1955 chan = &sband->channels[idx];
1956 pos = chan->hw_value;
1957 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1958 survey->channel = chan;
1959 spin_unlock_bh(&common->cc_lock);
1960
1961 return 0;
1962}
1963
1964static void ath9k_enable_dynack(struct ath_softc *sc)
1965{
1966#ifdef CONFIG_ATH9K_DYNACK
1967 u32 rfilt;
1968 struct ath_hw *ah = sc->sc_ah;
1969
1970 ath_dynack_reset(ah);
1971
1972 ah->dynack.enabled = true;
1973 rfilt = ath_calcrxfilter(sc);
1974 ath9k_hw_setrxfilter(ah, rfilt);
1975#endif
1976}
1977
1978static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1979 s16 coverage_class)
1980{
1981 struct ath_softc *sc = hw->priv;
1982 struct ath_hw *ah = sc->sc_ah;
1983
1984 if (config_enabled(CONFIG_ATH9K_TX99))
1985 return;
1986
1987 mutex_lock(&sc->mutex);
1988
1989 if (coverage_class >= 0) {
1990 ah->coverage_class = coverage_class;
1991 if (ah->dynack.enabled) {
1992 u32 rfilt;
1993
1994 ah->dynack.enabled = false;
1995 rfilt = ath_calcrxfilter(sc);
1996 ath9k_hw_setrxfilter(ah, rfilt);
1997 }
1998 ath9k_ps_wakeup(sc);
1999 ath9k_hw_init_global_settings(ah);
2000 ath9k_ps_restore(sc);
2001 } else if (!ah->dynack.enabled) {
2002 ath9k_enable_dynack(sc);
2003 }
2004
2005 mutex_unlock(&sc->mutex);
2006}
2007
2008static bool ath9k_has_tx_pending(struct ath_softc *sc,
2009 bool sw_pending)
2010{
2011 int i, npend = 0;
2012
2013 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2014 if (!ATH_TXQ_SETUP(sc, i))
2015 continue;
2016
2017 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2018 sw_pending);
2019 if (npend)
2020 break;
2021 }
2022
2023 return !!npend;
2024}
2025
2026static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2027 u32 queues, bool drop)
2028{
2029 struct ath_softc *sc = hw->priv;
2030 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2031
2032 if (ath9k_is_chanctx_enabled()) {
2033 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2034 goto flush;
2035
2036 /*
2037 * If MCC is active, extend the flush timeout
2038 * and wait for the HW/SW queues to become
2039 * empty. This needs to be done outside the
2040 * sc->mutex lock to allow the channel scheduler
2041 * to switch channel contexts.
2042 *
2043 * The vif queues have been stopped in mac80211,
2044 * so there won't be any incoming frames.
2045 */
2046 __ath9k_flush(hw, queues, drop, true, true);
2047 return;
2048 }
2049flush:
2050 mutex_lock(&sc->mutex);
2051 __ath9k_flush(hw, queues, drop, true, false);
2052 mutex_unlock(&sc->mutex);
2053}
2054
2055void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2056 bool sw_pending, bool timeout_override)
2057{
2058 struct ath_softc *sc = hw->priv;
2059 struct ath_hw *ah = sc->sc_ah;
2060 struct ath_common *common = ath9k_hw_common(ah);
2061 int timeout;
2062 bool drain_txq;
2063
2064 cancel_delayed_work_sync(&sc->tx_complete_work);
2065
2066 if (ah->ah_flags & AH_UNPLUGGED) {
2067 ath_dbg(common, ANY, "Device has been unplugged!\n");
2068 return;
2069 }
2070
2071 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2072 ath_dbg(common, ANY, "Device not present\n");
2073 return;
2074 }
2075
2076 spin_lock_bh(&sc->chan_lock);
2077 if (timeout_override)
2078 timeout = HZ / 5;
2079 else
2080 timeout = sc->cur_chan->flush_timeout;
2081 spin_unlock_bh(&sc->chan_lock);
2082
2083 ath_dbg(common, CHAN_CTX,
2084 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2085
2086 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2087 timeout) > 0)
2088 drop = false;
2089
2090 if (drop) {
2091 ath9k_ps_wakeup(sc);
2092 spin_lock_bh(&sc->sc_pcu_lock);
2093 drain_txq = ath_drain_all_txq(sc);
2094 spin_unlock_bh(&sc->sc_pcu_lock);
2095
2096 if (!drain_txq)
2097 ath_reset(sc, NULL);
2098
2099 ath9k_ps_restore(sc);
2100 }
2101
2102 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2103}
2104
2105static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2106{
2107 struct ath_softc *sc = hw->priv;
2108
2109 return ath9k_has_tx_pending(sc, true);
2110}
2111
2112static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2113{
2114 struct ath_softc *sc = hw->priv;
2115 struct ath_hw *ah = sc->sc_ah;
2116 struct ieee80211_vif *vif;
2117 struct ath_vif *avp;
2118 struct ath_buf *bf;
2119 struct ath_tx_status ts;
2120 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2121 int status;
2122
2123 vif = sc->beacon.bslot[0];
2124 if (!vif)
2125 return 0;
2126
2127 if (!vif->bss_conf.enable_beacon)
2128 return 0;
2129
2130 avp = (void *)vif->drv_priv;
2131
2132 if (!sc->beacon.tx_processed && !edma) {
2133 tasklet_disable(&sc->bcon_tasklet);
2134
2135 bf = avp->av_bcbuf;
2136 if (!bf || !bf->bf_mpdu)
2137 goto skip;
2138
2139 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2140 if (status == -EINPROGRESS)
2141 goto skip;
2142
2143 sc->beacon.tx_processed = true;
2144 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2145
2146skip:
2147 tasklet_enable(&sc->bcon_tasklet);
2148 }
2149
2150 return sc->beacon.tx_last;
2151}
2152
2153static int ath9k_get_stats(struct ieee80211_hw *hw,
2154 struct ieee80211_low_level_stats *stats)
2155{
2156 struct ath_softc *sc = hw->priv;
2157 struct ath_hw *ah = sc->sc_ah;
2158 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2159
2160 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2161 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2162 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2163 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2164 return 0;
2165}
2166
2167static u32 fill_chainmask(u32 cap, u32 new)
2168{
2169 u32 filled = 0;
2170 int i;
2171
2172 for (i = 0; cap && new; i++, cap >>= 1) {
2173 if (!(cap & BIT(0)))
2174 continue;
2175
2176 if (new & BIT(0))
2177 filled |= BIT(i);
2178
2179 new >>= 1;
2180 }
2181
2182 return filled;
2183}
2184
2185static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2186{
2187 if (AR_SREV_9300_20_OR_LATER(ah))
2188 return true;
2189
2190 switch (val & 0x7) {
2191 case 0x1:
2192 case 0x3:
2193 case 0x7:
2194 return true;
2195 case 0x2:
2196 return (ah->caps.rx_chainmask == 1);
2197 default:
2198 return false;
2199 }
2200}
2201
2202static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2203{
2204 struct ath_softc *sc = hw->priv;
2205 struct ath_hw *ah = sc->sc_ah;
2206
2207 if (ah->caps.rx_chainmask != 1)
2208 rx_ant |= tx_ant;
2209
2210 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2211 return -EINVAL;
2212
2213 sc->ant_rx = rx_ant;
2214 sc->ant_tx = tx_ant;
2215
2216 if (ah->caps.rx_chainmask == 1)
2217 return 0;
2218
2219 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2220 if (AR_SREV_9100(ah))
2221 ah->rxchainmask = 0x7;
2222 else
2223 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2224
2225 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2226 ath9k_cmn_reload_chainmask(ah);
2227
2228 return 0;
2229}
2230
2231static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2232{
2233 struct ath_softc *sc = hw->priv;
2234
2235 *tx_ant = sc->ant_tx;
2236 *rx_ant = sc->ant_rx;
2237 return 0;
2238}
2239
2240static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2241 struct ieee80211_vif *vif,
2242 const u8 *mac_addr)
2243{
2244 struct ath_softc *sc = hw->priv;
2245 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2246 set_bit(ATH_OP_SCANNING, &common->op_flags);
2247}
2248
2249static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2250 struct ieee80211_vif *vif)
2251{
2252 struct ath_softc *sc = hw->priv;
2253 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2254 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2255}
2256
2257#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2258
2259static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2260{
2261 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2262
2263 if (sc->offchannel.roc_vif) {
2264 ath_dbg(common, CHAN_CTX,
2265 "%s: Aborting RoC\n", __func__);
2266
2267 del_timer_sync(&sc->offchannel.timer);
2268 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2269 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2270 }
2271
2272 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2273 ath_dbg(common, CHAN_CTX,
2274 "%s: Aborting HW scan\n", __func__);
2275
2276 del_timer_sync(&sc->offchannel.timer);
2277 ath_scan_complete(sc, true);
2278 }
2279}
2280
2281static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2282 struct ieee80211_scan_request *hw_req)
2283{
2284 struct cfg80211_scan_request *req = &hw_req->req;
2285 struct ath_softc *sc = hw->priv;
2286 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2287 int ret = 0;
2288
2289 mutex_lock(&sc->mutex);
2290
2291 if (WARN_ON(sc->offchannel.scan_req)) {
2292 ret = -EBUSY;
2293 goto out;
2294 }
2295
2296 ath9k_ps_wakeup(sc);
2297 set_bit(ATH_OP_SCANNING, &common->op_flags);
2298 sc->offchannel.scan_vif = vif;
2299 sc->offchannel.scan_req = req;
2300 sc->offchannel.scan_idx = 0;
2301
2302 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2303 vif->addr);
2304
2305 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2306 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2307 ath_offchannel_next(sc);
2308 }
2309
2310out:
2311 mutex_unlock(&sc->mutex);
2312
2313 return ret;
2314}
2315
2316static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2317 struct ieee80211_vif *vif)
2318{
2319 struct ath_softc *sc = hw->priv;
2320 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2321
2322 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2323
2324 mutex_lock(&sc->mutex);
2325 del_timer_sync(&sc->offchannel.timer);
2326 ath_scan_complete(sc, true);
2327 mutex_unlock(&sc->mutex);
2328}
2329
2330static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2331 struct ieee80211_vif *vif,
2332 struct ieee80211_channel *chan, int duration,
2333 enum ieee80211_roc_type type)
2334{
2335 struct ath_softc *sc = hw->priv;
2336 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2337 int ret = 0;
2338
2339 mutex_lock(&sc->mutex);
2340
2341 if (WARN_ON(sc->offchannel.roc_vif)) {
2342 ret = -EBUSY;
2343 goto out;
2344 }
2345
2346 ath9k_ps_wakeup(sc);
2347 sc->offchannel.roc_vif = vif;
2348 sc->offchannel.roc_chan = chan;
2349 sc->offchannel.roc_duration = duration;
2350
2351 ath_dbg(common, CHAN_CTX,
2352 "RoC request on vif: %pM, type: %d duration: %d\n",
2353 vif->addr, type, duration);
2354
2355 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2356 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2357 ath_offchannel_next(sc);
2358 }
2359
2360out:
2361 mutex_unlock(&sc->mutex);
2362
2363 return ret;
2364}
2365
2366static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2367{
2368 struct ath_softc *sc = hw->priv;
2369 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2370
2371 mutex_lock(&sc->mutex);
2372
2373 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2374 del_timer_sync(&sc->offchannel.timer);
2375
2376 if (sc->offchannel.roc_vif) {
2377 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2378 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2379 }
2380
2381 mutex_unlock(&sc->mutex);
2382
2383 return 0;
2384}
2385
2386static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2387 struct ieee80211_chanctx_conf *conf)
2388{
2389 struct ath_softc *sc = hw->priv;
2390 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2391 struct ath_chanctx *ctx, **ptr;
2392 int pos;
2393
2394 mutex_lock(&sc->mutex);
2395
2396 ath_for_each_chanctx(sc, ctx) {
2397 if (ctx->assigned)
2398 continue;
2399
2400 ptr = (void *) conf->drv_priv;
2401 *ptr = ctx;
2402 ctx->assigned = true;
2403 pos = ctx - &sc->chanctx[0];
2404 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2405
2406 ath_dbg(common, CHAN_CTX,
2407 "Add channel context: %d MHz\n",
2408 conf->def.chan->center_freq);
2409
2410 ath_chanctx_set_channel(sc, ctx, &conf->def);
2411
2412 mutex_unlock(&sc->mutex);
2413 return 0;
2414 }
2415
2416 mutex_unlock(&sc->mutex);
2417 return -ENOSPC;
2418}
2419
2420
2421static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2422 struct ieee80211_chanctx_conf *conf)
2423{
2424 struct ath_softc *sc = hw->priv;
2425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2426 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2427
2428 mutex_lock(&sc->mutex);
2429
2430 ath_dbg(common, CHAN_CTX,
2431 "Remove channel context: %d MHz\n",
2432 conf->def.chan->center_freq);
2433
2434 ctx->assigned = false;
2435 ctx->hw_queue_base = 0;
2436 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2437
2438 mutex_unlock(&sc->mutex);
2439}
2440
2441static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2442 struct ieee80211_chanctx_conf *conf,
2443 u32 changed)
2444{
2445 struct ath_softc *sc = hw->priv;
2446 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2447 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2448
2449 mutex_lock(&sc->mutex);
2450 ath_dbg(common, CHAN_CTX,
2451 "Change channel context: %d MHz\n",
2452 conf->def.chan->center_freq);
2453 ath_chanctx_set_channel(sc, ctx, &conf->def);
2454 mutex_unlock(&sc->mutex);
2455}
2456
2457static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2458 struct ieee80211_vif *vif,
2459 struct ieee80211_chanctx_conf *conf)
2460{
2461 struct ath_softc *sc = hw->priv;
2462 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2463 struct ath_vif *avp = (void *)vif->drv_priv;
2464 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2465 int i;
2466
2467 ath9k_cancel_pending_offchannel(sc);
2468
2469 mutex_lock(&sc->mutex);
2470
2471 ath_dbg(common, CHAN_CTX,
2472 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2473 vif->addr, vif->type, vif->p2p,
2474 conf->def.chan->center_freq);
2475
2476 avp->chanctx = ctx;
2477 ctx->nvifs_assigned++;
2478 list_add_tail(&avp->list, &ctx->vifs);
2479 ath9k_calculate_summary_state(sc, ctx);
2480 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2481 vif->hw_queue[i] = ctx->hw_queue_base + i;
2482
2483 mutex_unlock(&sc->mutex);
2484
2485 return 0;
2486}
2487
2488static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2489 struct ieee80211_vif *vif,
2490 struct ieee80211_chanctx_conf *conf)
2491{
2492 struct ath_softc *sc = hw->priv;
2493 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2494 struct ath_vif *avp = (void *)vif->drv_priv;
2495 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2496 int ac;
2497
2498 ath9k_cancel_pending_offchannel(sc);
2499
2500 mutex_lock(&sc->mutex);
2501
2502 ath_dbg(common, CHAN_CTX,
2503 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2504 vif->addr, vif->type, vif->p2p,
2505 conf->def.chan->center_freq);
2506
2507 avp->chanctx = NULL;
2508 ctx->nvifs_assigned--;
2509 list_del(&avp->list);
2510 ath9k_calculate_summary_state(sc, ctx);
2511 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2512 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2513
2514 mutex_unlock(&sc->mutex);
2515}
2516
2517static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2518 struct ieee80211_vif *vif)
2519{
2520 struct ath_softc *sc = hw->priv;
2521 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2522 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2523 struct ath_beacon_config *cur_conf;
2524 struct ath_chanctx *go_ctx;
2525 unsigned long timeout;
2526 bool changed = false;
2527 u32 beacon_int;
2528
2529 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2530 return;
2531
2532 if (!avp->chanctx)
2533 return;
2534
2535 mutex_lock(&sc->mutex);
2536
2537 spin_lock_bh(&sc->chan_lock);
2538 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2539 changed = true;
2540 spin_unlock_bh(&sc->chan_lock);
2541
2542 if (!changed)
2543 goto out;
2544
2545 ath9k_cancel_pending_offchannel(sc);
2546
2547 go_ctx = ath_is_go_chanctx_present(sc);
2548
2549 if (go_ctx) {
2550 /*
2551 * Wait till the GO interface gets a chance
2552 * to send out an NoA.
2553 */
2554 spin_lock_bh(&sc->chan_lock);
2555 sc->sched.mgd_prepare_tx = true;
2556 cur_conf = &go_ctx->beacon;
2557 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2558 spin_unlock_bh(&sc->chan_lock);
2559
2560 timeout = usecs_to_jiffies(beacon_int * 2);
2561 init_completion(&sc->go_beacon);
2562
2563 mutex_unlock(&sc->mutex);
2564
2565 if (wait_for_completion_timeout(&sc->go_beacon,
2566 timeout) == 0) {
2567 ath_dbg(common, CHAN_CTX,
2568 "Failed to send new NoA\n");
2569
2570 spin_lock_bh(&sc->chan_lock);
2571 sc->sched.mgd_prepare_tx = false;
2572 spin_unlock_bh(&sc->chan_lock);
2573 }
2574
2575 mutex_lock(&sc->mutex);
2576 }
2577
2578 ath_dbg(common, CHAN_CTX,
2579 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2580 __func__, vif->addr);
2581
2582 spin_lock_bh(&sc->chan_lock);
2583 sc->next_chan = avp->chanctx;
2584 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2585 spin_unlock_bh(&sc->chan_lock);
2586
2587 ath_chanctx_set_next(sc, true);
2588out:
2589 mutex_unlock(&sc->mutex);
2590}
2591
2592void ath9k_fill_chanctx_ops(void)
2593{
2594 if (!ath9k_is_chanctx_enabled())
2595 return;
2596
2597 ath9k_ops.hw_scan = ath9k_hw_scan;
2598 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2599 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2600 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2601 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2602 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2603 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2604 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2605 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2606 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2607}
2608
2609#endif
2610
2611static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2612 int *dbm)
2613{
2614 struct ath_softc *sc = hw->priv;
2615 struct ath_vif *avp = (void *)vif->drv_priv;
2616
2617 mutex_lock(&sc->mutex);
2618 if (avp->chanctx)
2619 *dbm = avp->chanctx->cur_txpower;
2620 else
2621 *dbm = sc->cur_chan->cur_txpower;
2622 mutex_unlock(&sc->mutex);
2623
2624 *dbm /= 2;
2625
2626 return 0;
2627}
2628
2629struct ieee80211_ops ath9k_ops = {
2630 .tx = ath9k_tx,
2631 .start = ath9k_start,
2632 .stop = ath9k_stop,
2633 .add_interface = ath9k_add_interface,
2634 .change_interface = ath9k_change_interface,
2635 .remove_interface = ath9k_remove_interface,
2636 .config = ath9k_config,
2637 .configure_filter = ath9k_configure_filter,
2638 .sta_state = ath9k_sta_state,
2639 .sta_notify = ath9k_sta_notify,
2640 .conf_tx = ath9k_conf_tx,
2641 .bss_info_changed = ath9k_bss_info_changed,
2642 .set_key = ath9k_set_key,
2643 .get_tsf = ath9k_get_tsf,
2644 .set_tsf = ath9k_set_tsf,
2645 .reset_tsf = ath9k_reset_tsf,
2646 .ampdu_action = ath9k_ampdu_action,
2647 .get_survey = ath9k_get_survey,
2648 .rfkill_poll = ath9k_rfkill_poll_state,
2649 .set_coverage_class = ath9k_set_coverage_class,
2650 .flush = ath9k_flush,
2651 .tx_frames_pending = ath9k_tx_frames_pending,
2652 .tx_last_beacon = ath9k_tx_last_beacon,
2653 .release_buffered_frames = ath9k_release_buffered_frames,
2654 .get_stats = ath9k_get_stats,
2655 .set_antenna = ath9k_set_antenna,
2656 .get_antenna = ath9k_get_antenna,
2657
2658#ifdef CONFIG_ATH9K_WOW
2659 .suspend = ath9k_suspend,
2660 .resume = ath9k_resume,
2661 .set_wakeup = ath9k_set_wakeup,
2662#endif
2663
2664#ifdef CONFIG_ATH9K_DEBUGFS
2665 .get_et_sset_count = ath9k_get_et_sset_count,
2666 .get_et_stats = ath9k_get_et_stats,
2667 .get_et_strings = ath9k_get_et_strings,
2668#endif
2669
2670#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2671 .sta_add_debugfs = ath9k_sta_add_debugfs,
2672#endif
2673 .sw_scan_start = ath9k_sw_scan_start,
2674 .sw_scan_complete = ath9k_sw_scan_complete,
2675 .get_txpower = ath9k_get_txpower,
2676};