1/* SPDX-License-Identifier: ISC */
 2/*
 3 * Copyright (c) 2015-2016 Qualcomm Atheros, Inc.
 
 
 
 
 
 
 
 
 
 
 
 
 4 */
 5
 6#ifndef _SWAP_H_
 7#define _SWAP_H_
 8
 9#define ATH10K_SWAP_CODE_SEG_BIN_LEN_MAX	(512 * 1024)
10#define ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ	12
11#define ATH10K_SWAP_CODE_SEG_NUM_MAX		16
12/* Currently only one swap segment is supported */
13#define ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED	1
14
15struct ath10k_fw_file;
16
17struct ath10k_swap_code_seg_tlv {
18	__le32 address;
19	__le32 length;
20	u8 data[];
21} __packed;
22
23struct ath10k_swap_code_seg_tail {
24	u8 magic_signature[ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ];
25	__le32 bmi_write_addr;
26} __packed;
27
28union ath10k_swap_code_seg_item {
29	struct ath10k_swap_code_seg_tlv tlv;
30	struct ath10k_swap_code_seg_tail tail;
31} __packed;
32
 
 
 
 
 
 
33struct ath10k_swap_code_seg_hw_info {
34	/* Swap binary image size */
35	__le32 swap_size;
36	__le32 num_segs;
37
38	/* Swap data size */
39	__le32 size;
40	__le32 size_log2;
41	__le32 bus_addr[ATH10K_SWAP_CODE_SEG_NUM_MAX];
42	__le64 reserved[ATH10K_SWAP_CODE_SEG_NUM_MAX];
43} __packed;
44
45struct ath10k_swap_code_seg_info {
46	struct ath10k_swap_code_seg_hw_info seg_hw_info;
47	void *virt_address[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
48	u32 target_addr;
49	dma_addr_t paddr[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
50};
51
52int ath10k_swap_code_seg_configure(struct ath10k *ar,
53				   const struct ath10k_fw_file *fw_file);
54void ath10k_swap_code_seg_release(struct ath10k *ar,
55				  struct ath10k_fw_file *fw_file);
56int ath10k_swap_code_seg_init(struct ath10k *ar,
57			      struct ath10k_fw_file *fw_file);
58
59#endif

 
 1/*
 2 * Copyright (c) 2015 Qualcomm Atheros, Inc.
 3 *
 4 * Permission to use, copy, modify, and/or distribute this software for any
 5 * purpose with or without fee is hereby granted, provided that the above
 6 * copyright notice and this permission notice appear in all copies.
 7 *
 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _SWAP_H_
18#define _SWAP_H_
19
20#define ATH10K_SWAP_CODE_SEG_BIN_LEN_MAX	(512 * 1024)
21#define ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ	12
22#define ATH10K_SWAP_CODE_SEG_NUM_MAX		16
23/* Currently only one swap segment is supported */
24#define ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED	1
25
 
 
26struct ath10k_swap_code_seg_tlv {
27	__le32 address;
28	__le32 length;
29	u8 data[0];
30} __packed;
31
32struct ath10k_swap_code_seg_tail {
33	u8 magic_signature[ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ];
34	__le32 bmi_write_addr;
35} __packed;
36
37union ath10k_swap_code_seg_item {
38	struct ath10k_swap_code_seg_tlv tlv;
39	struct ath10k_swap_code_seg_tail tail;
40} __packed;
41
42enum ath10k_swap_code_seg_bin_type {
43	 ATH10K_SWAP_CODE_SEG_BIN_TYPE_OTP,
44	 ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW,
45	 ATH10K_SWAP_CODE_SEG_BIN_TYPE_UTF,
46};
47
48struct ath10k_swap_code_seg_hw_info {
49	/* Swap binary image size */
50	__le32 swap_size;
51	__le32 num_segs;
52
53	/* Swap data size */
54	__le32 size;
55	__le32 size_log2;
56	__le32 bus_addr[ATH10K_SWAP_CODE_SEG_NUM_MAX];
57	__le64 reserved[ATH10K_SWAP_CODE_SEG_NUM_MAX];
58} __packed;
59
60struct ath10k_swap_code_seg_info {
61	struct ath10k_swap_code_seg_hw_info seg_hw_info;
62	void *virt_address[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
63	u32 target_addr;
64	dma_addr_t paddr[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
65};
66
67int ath10k_swap_code_seg_configure(struct ath10k *ar,
68				   enum ath10k_swap_code_seg_bin_type type);
69void ath10k_swap_code_seg_release(struct ath10k *ar);
70int ath10k_swap_code_seg_init(struct ath10k *ar);
 
 
71
72#endif