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1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device.
3 *
4 * This is a new flat driver which is based on the original emac_lite
5 * driver from John Williams <john.williams@xilinx.com>.
6 *
7 * Copyright (c) 2007 - 2013 Xilinx, Inc.
8 */
9
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/uaccess.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/ethtool.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_mdio.h>
22#include <linux/of_net.h>
23#include <linux/phy.h>
24#include <linux/interrupt.h>
25#include <linux/iopoll.h>
26
27#define DRIVER_NAME "xilinx_emaclite"
28
29/* Register offsets for the EmacLite Core */
30#define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */
31#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */
32#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */
33#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */
34#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */
35#define XEL_GIER_OFFSET 0x07F8 /* GIE Register */
36#define XEL_TSR_OFFSET 0x07FC /* Tx status */
37#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
38
39#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
40#define XEL_RPLR_OFFSET 0x100C /* Rx packet length */
41#define XEL_RSR_OFFSET 0x17FC /* Rx status */
42
43#define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */
44
45/* MDIO Address Register Bit Masks */
46#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
47#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
48#define XEL_MDIOADDR_PHYADR_SHIFT 5
49#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
50
51/* MDIO Write Data Register Bit Masks */
52#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
53
54/* MDIO Read Data Register Bit Masks */
55#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
56
57/* MDIO Control Register Bit Masks */
58#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
59#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
60
61/* Global Interrupt Enable Register (GIER) Bit Masks */
62#define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */
63
64/* Transmit Status Register (TSR) Bit Masks */
65#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */
66#define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */
67#define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */
68#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit
69 * only. This is not documented
70 * in the HW spec
71 */
72
73/* Define for programming the MAC address into the EmacLite */
74#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
75
76/* Receive Status Register (RSR) */
77#define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */
78#define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */
79
80/* Transmit Packet Length Register (TPLR) */
81#define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */
82
83/* Receive Packet Length Register (RPLR) */
84#define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */
85
86#define XEL_HEADER_OFFSET 12 /* Offset to length field */
87#define XEL_HEADER_SHIFT 16 /* Shift value for length */
88
89/* General Ethernet Definitions */
90#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */
91#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */
92
93#define TX_TIMEOUT (60 * HZ) /* Tx timeout is 60 seconds. */
94
95#ifdef __BIG_ENDIAN
96#define xemaclite_readl ioread32be
97#define xemaclite_writel iowrite32be
98#else
99#define xemaclite_readl ioread32
100#define xemaclite_writel iowrite32
101#endif
102
103/**
104 * struct net_local - Our private per device data
105 * @ndev: instance of the network device
106 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW
107 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW
108 * @next_tx_buf_to_use: next Tx buffer to write to
109 * @next_rx_buf_to_use: next Rx buffer to read from
110 * @base_addr: base address of the Emaclite device
111 * @reset_lock: lock to serialize xmit and tx_timeout execution
112 * @deferred_skb: holds an skb (for transmission at a later time) when the
113 * Tx buffer is not free
114 * @phy_dev: pointer to the PHY device
115 * @phy_node: pointer to the PHY device node
116 * @mii_bus: pointer to the MII bus
117 * @last_link: last link status
118 */
119struct net_local {
120 struct net_device *ndev;
121
122 bool tx_ping_pong;
123 bool rx_ping_pong;
124 u32 next_tx_buf_to_use;
125 u32 next_rx_buf_to_use;
126 void __iomem *base_addr;
127
128 spinlock_t reset_lock; /* serialize xmit and tx_timeout execution */
129 struct sk_buff *deferred_skb;
130
131 struct phy_device *phy_dev;
132 struct device_node *phy_node;
133
134 struct mii_bus *mii_bus;
135
136 int last_link;
137};
138
139/*************************/
140/* EmacLite driver calls */
141/*************************/
142
143/**
144 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device
145 * @drvdata: Pointer to the Emaclite device private data
146 *
147 * This function enables the Tx and Rx interrupts for the Emaclite device along
148 * with the Global Interrupt Enable.
149 */
150static void xemaclite_enable_interrupts(struct net_local *drvdata)
151{
152 u32 reg_data;
153
154 /* Enable the Tx interrupts for the first Buffer */
155 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
156 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
157 drvdata->base_addr + XEL_TSR_OFFSET);
158
159 /* Enable the Rx interrupts for the first buffer */
160 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
161
162 /* Enable the Global Interrupt Enable */
163 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
164}
165
166/**
167 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device
168 * @drvdata: Pointer to the Emaclite device private data
169 *
170 * This function disables the Tx and Rx interrupts for the Emaclite device,
171 * along with the Global Interrupt Enable.
172 */
173static void xemaclite_disable_interrupts(struct net_local *drvdata)
174{
175 u32 reg_data;
176
177 /* Disable the Global Interrupt Enable */
178 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
179
180 /* Disable the Tx interrupts for the first buffer */
181 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
182 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
183 drvdata->base_addr + XEL_TSR_OFFSET);
184
185 /* Disable the Rx interrupts for the first buffer */
186 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET);
187 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
188 drvdata->base_addr + XEL_RSR_OFFSET);
189}
190
191/**
192 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address
193 * @src_ptr: Void pointer to the 16-bit aligned source address
194 * @dest_ptr: Pointer to the 32-bit aligned destination address
195 * @length: Number bytes to write from source to destination
196 *
197 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned
198 * address in the EmacLite device.
199 */
200static void xemaclite_aligned_write(const void *src_ptr, u32 *dest_ptr,
201 unsigned int length)
202{
203 const u16 *from_u16_ptr;
204 u32 align_buffer;
205 u32 *to_u32_ptr;
206 u16 *to_u16_ptr;
207
208 to_u32_ptr = dest_ptr;
209 from_u16_ptr = src_ptr;
210 align_buffer = 0;
211
212 for (; length > 3; length -= 4) {
213 to_u16_ptr = (u16 *)&align_buffer;
214 *to_u16_ptr++ = *from_u16_ptr++;
215 *to_u16_ptr++ = *from_u16_ptr++;
216
217 /* This barrier resolves occasional issues seen around
218 * cases where the data is not properly flushed out
219 * from the processor store buffers to the destination
220 * memory locations.
221 */
222 wmb();
223
224 /* Output a word */
225 *to_u32_ptr++ = align_buffer;
226 }
227 if (length) {
228 u8 *from_u8_ptr, *to_u8_ptr;
229
230 /* Set up to output the remaining data */
231 align_buffer = 0;
232 to_u8_ptr = (u8 *)&align_buffer;
233 from_u8_ptr = (u8 *)from_u16_ptr;
234
235 /* Output the remaining data */
236 for (; length > 0; length--)
237 *to_u8_ptr++ = *from_u8_ptr++;
238
239 /* This barrier resolves occasional issues seen around
240 * cases where the data is not properly flushed out
241 * from the processor store buffers to the destination
242 * memory locations.
243 */
244 wmb();
245 *to_u32_ptr = align_buffer;
246 }
247}
248
249/**
250 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer
251 * @src_ptr: Pointer to the 32-bit aligned source address
252 * @dest_ptr: Pointer to the 16-bit aligned destination address
253 * @length: Number bytes to read from source to destination
254 *
255 * This function reads data from a 32-bit aligned address in the EmacLite device
256 * to a 16-bit aligned buffer.
257 */
258static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr,
259 unsigned int length)
260{
261 u16 *to_u16_ptr, *from_u16_ptr;
262 u32 *from_u32_ptr;
263 u32 align_buffer;
264
265 from_u32_ptr = src_ptr;
266 to_u16_ptr = (u16 *)dest_ptr;
267
268 for (; length > 3; length -= 4) {
269 /* Copy each word into the temporary buffer */
270 align_buffer = *from_u32_ptr++;
271 from_u16_ptr = (u16 *)&align_buffer;
272
273 /* Read data from source */
274 *to_u16_ptr++ = *from_u16_ptr++;
275 *to_u16_ptr++ = *from_u16_ptr++;
276 }
277
278 if (length) {
279 u8 *to_u8_ptr, *from_u8_ptr;
280
281 /* Set up to read the remaining data */
282 to_u8_ptr = (u8 *)to_u16_ptr;
283 align_buffer = *from_u32_ptr++;
284 from_u8_ptr = (u8 *)&align_buffer;
285
286 /* Read the remaining data */
287 for (; length > 0; length--)
288 *to_u8_ptr = *from_u8_ptr;
289 }
290}
291
292/**
293 * xemaclite_send_data - Send an Ethernet frame
294 * @drvdata: Pointer to the Emaclite device private data
295 * @data: Pointer to the data to be sent
296 * @byte_count: Total frame size, including header
297 *
298 * This function checks if the Tx buffer of the Emaclite device is free to send
299 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it
300 * returns an error.
301 *
302 * Return: 0 upon success or -1 if the buffer(s) are full.
303 *
304 * Note: The maximum Tx packet size can not be more than Ethernet header
305 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS.
306 */
307static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
308 unsigned int byte_count)
309{
310 u32 reg_data;
311 void __iomem *addr;
312
313 /* Determine the expected Tx buffer address */
314 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
315
316 /* If the length is too large, truncate it */
317 if (byte_count > ETH_FRAME_LEN)
318 byte_count = ETH_FRAME_LEN;
319
320 /* Check if the expected buffer is available */
321 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
322 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
323 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
324 /* Switch to next buffer if configured */
325 if (drvdata->tx_ping_pong != 0)
326 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET;
327 } else if (drvdata->tx_ping_pong != 0) {
328 /* If the expected buffer is full, try the other buffer,
329 * if it is configured in HW
330 */
331
332 addr = (void __iomem __force *)((uintptr_t __force)addr ^
333 XEL_BUFFER_OFFSET);
334 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
335
336 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
337 XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
338 return -1; /* Buffers were full, return failure */
339 } else {
340 return -1; /* Buffer was full, return failure */
341 }
342
343 /* Write the frame to the buffer */
344 xemaclite_aligned_write(data, (u32 __force *)addr, byte_count);
345
346 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK),
347 addr + XEL_TPLR_OFFSET);
348
349 /* Update the Tx Status Register to indicate that there is a
350 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
351 * is used by the interrupt handler to check whether a frame
352 * has been transmitted
353 */
354 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
355 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
356 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET);
357
358 return 0;
359}
360
361/**
362 * xemaclite_recv_data - Receive a frame
363 * @drvdata: Pointer to the Emaclite device private data
364 * @data: Address where the data is to be received
365 * @maxlen: Maximum supported ethernet packet length
366 *
367 * This function is intended to be called from the interrupt context or
368 * with a wrapper which waits for the receive frame to be available.
369 *
370 * Return: Total number of bytes received
371 */
372static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen)
373{
374 void __iomem *addr;
375 u16 length, proto_type;
376 u32 reg_data;
377
378 /* Determine the expected buffer address */
379 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
380
381 /* Verify which buffer has valid data */
382 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
383
384 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
385 if (drvdata->rx_ping_pong != 0)
386 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET;
387 } else {
388 /* The instance is out of sync, try other buffer if other
389 * buffer is configured, return 0 otherwise. If the instance is
390 * out of sync, do not update the 'next_rx_buf_to_use' since it
391 * will correct on subsequent calls
392 */
393 if (drvdata->rx_ping_pong != 0)
394 addr = (void __iomem __force *)
395 ((uintptr_t __force)addr ^
396 XEL_BUFFER_OFFSET);
397 else
398 return 0; /* No data was available */
399
400 /* Verify that buffer has valid data */
401 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
402 if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
403 XEL_RSR_RECV_DONE_MASK)
404 return 0; /* No data was available */
405 }
406
407 /* Get the protocol type of the ethernet frame that arrived
408 */
409 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET +
410 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
411 XEL_RPLR_LENGTH_MASK);
412
413 /* Check if received ethernet frame is a raw ethernet frame
414 * or an IP packet or an ARP packet
415 */
416 if (proto_type > ETH_DATA_LEN) {
417 if (proto_type == ETH_P_IP) {
418 length = ((ntohl(xemaclite_readl(addr +
419 XEL_HEADER_IP_LENGTH_OFFSET +
420 XEL_RXBUFF_OFFSET)) >>
421 XEL_HEADER_SHIFT) &
422 XEL_RPLR_LENGTH_MASK);
423 length = min_t(u16, length, ETH_DATA_LEN);
424 length += ETH_HLEN + ETH_FCS_LEN;
425
426 } else if (proto_type == ETH_P_ARP) {
427 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN;
428 } else {
429 /* Field contains type other than IP or ARP, use max
430 * frame size and let user parse it
431 */
432 length = ETH_FRAME_LEN + ETH_FCS_LEN;
433 }
434 } else {
435 /* Use the length in the frame, plus the header and trailer */
436 length = proto_type + ETH_HLEN + ETH_FCS_LEN;
437 }
438
439 if (WARN_ON(length > maxlen))
440 length = maxlen;
441
442 /* Read from the EmacLite device */
443 xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET),
444 data, length);
445
446 /* Acknowledge the frame */
447 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
448 reg_data &= ~XEL_RSR_RECV_DONE_MASK;
449 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET);
450
451 return length;
452}
453
454/**
455 * xemaclite_update_address - Update the MAC address in the device
456 * @drvdata: Pointer to the Emaclite device private data
457 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value)
458 *
459 * Tx must be idle and Rx should be idle for deterministic results.
460 * It is recommended that this function should be called after the
461 * initialization and before transmission of any packets from the device.
462 * The MAC address can be programmed using any of the two transmit
463 * buffers (if configured).
464 */
465static void xemaclite_update_address(struct net_local *drvdata,
466 const u8 *address_ptr)
467{
468 void __iomem *addr;
469 u32 reg_data;
470
471 /* Determine the expected Tx buffer address */
472 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
473
474 xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN);
475
476 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);
477
478 /* Update the MAC address in the EmacLite */
479 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
480 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
481
482 /* Wait for EmacLite to finish with the MAC address update */
483 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) &
484 XEL_TSR_PROG_MAC_ADDR) != 0)
485 ;
486}
487
488/**
489 * xemaclite_set_mac_address - Set the MAC address for this device
490 * @dev: Pointer to the network device instance
491 * @address: Void pointer to the sockaddr structure
492 *
493 * This function copies the HW address from the sockaddr structure to the
494 * net_device structure and updates the address in HW.
495 *
496 * Return: Error if the net device is busy or 0 if the addr is set
497 * successfully
498 */
499static int xemaclite_set_mac_address(struct net_device *dev, void *address)
500{
501 struct net_local *lp = netdev_priv(dev);
502 struct sockaddr *addr = address;
503
504 if (netif_running(dev))
505 return -EBUSY;
506
507 eth_hw_addr_set(dev, addr->sa_data);
508 xemaclite_update_address(lp, dev->dev_addr);
509 return 0;
510}
511
512/**
513 * xemaclite_tx_timeout - Callback for Tx Timeout
514 * @dev: Pointer to the network device
515 * @txqueue: Unused
516 *
517 * This function is called when Tx time out occurs for Emaclite device.
518 */
519static void xemaclite_tx_timeout(struct net_device *dev, unsigned int txqueue)
520{
521 struct net_local *lp = netdev_priv(dev);
522 unsigned long flags;
523
524 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n",
525 TX_TIMEOUT * 1000UL / HZ);
526
527 dev->stats.tx_errors++;
528
529 /* Reset the device */
530 spin_lock_irqsave(&lp->reset_lock, flags);
531
532 /* Shouldn't really be necessary, but shouldn't hurt */
533 netif_stop_queue(dev);
534
535 xemaclite_disable_interrupts(lp);
536 xemaclite_enable_interrupts(lp);
537
538 if (lp->deferred_skb) {
539 dev_kfree_skb_irq(lp->deferred_skb);
540 lp->deferred_skb = NULL;
541 dev->stats.tx_errors++;
542 }
543
544 /* To exclude tx timeout */
545 netif_trans_update(dev); /* prevent tx timeout */
546
547 /* We're all ready to go. Start the queue */
548 netif_wake_queue(dev);
549 spin_unlock_irqrestore(&lp->reset_lock, flags);
550}
551
552/**********************/
553/* Interrupt Handlers */
554/**********************/
555
556/**
557 * xemaclite_tx_handler - Interrupt handler for frames sent
558 * @dev: Pointer to the network device
559 *
560 * This function updates the number of packets transmitted and handles the
561 * deferred skb, if there is one.
562 */
563static void xemaclite_tx_handler(struct net_device *dev)
564{
565 struct net_local *lp = netdev_priv(dev);
566
567 dev->stats.tx_packets++;
568
569 if (!lp->deferred_skb)
570 return;
571
572 if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data,
573 lp->deferred_skb->len))
574 return;
575
576 dev->stats.tx_bytes += lp->deferred_skb->len;
577 dev_consume_skb_irq(lp->deferred_skb);
578 lp->deferred_skb = NULL;
579 netif_trans_update(dev); /* prevent tx timeout */
580 netif_wake_queue(dev);
581}
582
583/**
584 * xemaclite_rx_handler- Interrupt handler for frames received
585 * @dev: Pointer to the network device
586 *
587 * This function allocates memory for a socket buffer, fills it with data
588 * received and hands it over to the TCP/IP stack.
589 */
590static void xemaclite_rx_handler(struct net_device *dev)
591{
592 struct net_local *lp = netdev_priv(dev);
593 struct sk_buff *skb;
594 u32 len;
595
596 len = ETH_FRAME_LEN + ETH_FCS_LEN;
597 skb = netdev_alloc_skb(dev, len + NET_IP_ALIGN);
598 if (!skb) {
599 /* Couldn't get memory. */
600 dev->stats.rx_dropped++;
601 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n");
602 return;
603 }
604
605 skb_reserve(skb, NET_IP_ALIGN);
606
607 len = xemaclite_recv_data(lp, (u8 *)skb->data, len);
608
609 if (!len) {
610 dev->stats.rx_errors++;
611 dev_kfree_skb_irq(skb);
612 return;
613 }
614
615 skb_put(skb, len); /* Tell the skb how much data we got */
616
617 skb->protocol = eth_type_trans(skb, dev);
618 skb_checksum_none_assert(skb);
619
620 dev->stats.rx_packets++;
621 dev->stats.rx_bytes += len;
622
623 if (!skb_defer_rx_timestamp(skb))
624 netif_rx(skb); /* Send the packet upstream */
625}
626
627/**
628 * xemaclite_interrupt - Interrupt handler for this driver
629 * @irq: Irq of the Emaclite device
630 * @dev_id: Void pointer to the network device instance used as callback
631 * reference
632 *
633 * Return: IRQ_HANDLED
634 *
635 * This function handles the Tx and Rx interrupts of the EmacLite device.
636 */
637static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
638{
639 bool tx_complete = false;
640 struct net_device *dev = dev_id;
641 struct net_local *lp = netdev_priv(dev);
642 void __iomem *base_addr = lp->base_addr;
643 u32 tx_status;
644
645 /* Check if there is Rx Data available */
646 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) &
647 XEL_RSR_RECV_DONE_MASK) ||
648 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
649 & XEL_RSR_RECV_DONE_MASK))
650
651 xemaclite_rx_handler(dev);
652
653 /* Check if the Transmission for the first buffer is completed */
654 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET);
655 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
656 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
657 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
658 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET);
659
660 tx_complete = true;
661 }
662
663 /* Check if the Transmission for the second buffer is completed */
664 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
665 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
666 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
667 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
668 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
669 XEL_TSR_OFFSET);
670
671 tx_complete = true;
672 }
673
674 /* If there was a Tx interrupt, call the Tx Handler */
675 if (tx_complete != 0)
676 xemaclite_tx_handler(dev);
677
678 return IRQ_HANDLED;
679}
680
681/**********************/
682/* MDIO Bus functions */
683/**********************/
684
685/**
686 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use
687 * @lp: Pointer to the Emaclite device private data
688 *
689 * This function waits till the device is ready to accept a new MDIO
690 * request.
691 *
692 * Return: 0 for success or ETIMEDOUT for a timeout
693 */
694
695static int xemaclite_mdio_wait(struct net_local *lp)
696{
697 u32 val;
698
699 /* wait for the MDIO interface to not be busy or timeout
700 * after some time.
701 */
702 return readx_poll_timeout(xemaclite_readl,
703 lp->base_addr + XEL_MDIOCTRL_OFFSET,
704 val, !(val & XEL_MDIOCTRL_MDIOSTS_MASK),
705 1000, 20000);
706}
707
708/**
709 * xemaclite_mdio_read - Read from a given MII management register
710 * @bus: the mii_bus struct
711 * @phy_id: the phy address
712 * @reg: register number to read from
713 *
714 * This function waits till the device is ready to accept a new MDIO
715 * request and then writes the phy address to the MDIO Address register
716 * and reads data from MDIO Read Data register, when its available.
717 *
718 * Return: Value read from the MII management register
719 */
720static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg)
721{
722 struct net_local *lp = bus->priv;
723 u32 ctrl_reg;
724 u32 rc;
725
726 if (xemaclite_mdio_wait(lp))
727 return -ETIMEDOUT;
728
729 /* Write the PHY address, register number and set the OP bit in the
730 * MDIO Address register. Set the Status bit in the MDIO Control
731 * register to start a MDIO read transaction.
732 */
733 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
734 xemaclite_writel(XEL_MDIOADDR_OP_MASK |
735 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
736 lp->base_addr + XEL_MDIOADDR_OFFSET);
737 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
738 lp->base_addr + XEL_MDIOCTRL_OFFSET);
739
740 if (xemaclite_mdio_wait(lp))
741 return -ETIMEDOUT;
742
743 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET);
744
745 dev_dbg(&lp->ndev->dev,
746 "%s(phy_id=%i, reg=%x) == %x\n", __func__,
747 phy_id, reg, rc);
748
749 return rc;
750}
751
752/**
753 * xemaclite_mdio_write - Write to a given MII management register
754 * @bus: the mii_bus struct
755 * @phy_id: the phy address
756 * @reg: register number to write to
757 * @val: value to write to the register number specified by reg
758 *
759 * This function waits till the device is ready to accept a new MDIO
760 * request and then writes the val to the MDIO Write Data register.
761 *
762 * Return: 0 upon success or a negative error upon failure
763 */
764static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg,
765 u16 val)
766{
767 struct net_local *lp = bus->priv;
768 u32 ctrl_reg;
769
770 dev_dbg(&lp->ndev->dev,
771 "%s(phy_id=%i, reg=%x, val=%x)\n", __func__,
772 phy_id, reg, val);
773
774 if (xemaclite_mdio_wait(lp))
775 return -ETIMEDOUT;
776
777 /* Write the PHY address, register number and clear the OP bit in the
778 * MDIO Address register and then write the value into the MDIO Write
779 * Data register. Finally, set the Status bit in the MDIO Control
780 * register to start a MDIO write transaction.
781 */
782 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
783 xemaclite_writel(~XEL_MDIOADDR_OP_MASK &
784 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
785 lp->base_addr + XEL_MDIOADDR_OFFSET);
786 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
787 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
788 lp->base_addr + XEL_MDIOCTRL_OFFSET);
789
790 return 0;
791}
792
793/**
794 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device
795 * @lp: Pointer to the Emaclite device private data
796 * @dev: Pointer to OF device structure
797 *
798 * This function enables MDIO bus in the Emaclite device and registers a
799 * mii_bus.
800 *
801 * Return: 0 upon success or a negative error upon failure
802 */
803static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
804{
805 struct mii_bus *bus;
806 struct resource res;
807 struct device_node *np = of_get_parent(lp->phy_node);
808 struct device_node *npp;
809 int rc, ret;
810
811 /* Don't register the MDIO bus if the phy_node or its parent node
812 * can't be found.
813 */
814 if (!np) {
815 dev_err(dev, "Failed to register mdio bus.\n");
816 return -ENODEV;
817 }
818 npp = of_get_parent(np);
819 ret = of_address_to_resource(npp, 0, &res);
820 of_node_put(npp);
821 if (ret) {
822 dev_err(dev, "%s resource error!\n",
823 dev->of_node->full_name);
824 of_node_put(np);
825 return ret;
826 }
827 if (lp->ndev->mem_start != res.start) {
828 struct phy_device *phydev;
829
830 phydev = of_phy_find_device(lp->phy_node);
831 if (!phydev)
832 dev_info(dev,
833 "MDIO of the phy is not registered yet\n");
834 else
835 put_device(&phydev->mdio.dev);
836 of_node_put(np);
837 return 0;
838 }
839
840 /* Enable the MDIO bus by asserting the enable bit in MDIO Control
841 * register.
842 */
843 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK,
844 lp->base_addr + XEL_MDIOCTRL_OFFSET);
845
846 bus = mdiobus_alloc();
847 if (!bus) {
848 dev_err(dev, "Failed to allocate mdiobus\n");
849 of_node_put(np);
850 return -ENOMEM;
851 }
852
853 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
854 (unsigned long long)res.start);
855 bus->priv = lp;
856 bus->name = "Xilinx Emaclite MDIO";
857 bus->read = xemaclite_mdio_read;
858 bus->write = xemaclite_mdio_write;
859 bus->parent = dev;
860
861 rc = of_mdiobus_register(bus, np);
862 of_node_put(np);
863 if (rc) {
864 dev_err(dev, "Failed to register mdio bus.\n");
865 goto err_register;
866 }
867
868 lp->mii_bus = bus;
869
870 return 0;
871
872err_register:
873 mdiobus_free(bus);
874 return rc;
875}
876
877/**
878 * xemaclite_adjust_link - Link state callback for the Emaclite device
879 * @ndev: pointer to net_device struct
880 *
881 * There's nothing in the Emaclite device to be configured when the link
882 * state changes. We just print the status.
883 */
884static void xemaclite_adjust_link(struct net_device *ndev)
885{
886 struct net_local *lp = netdev_priv(ndev);
887 struct phy_device *phy = lp->phy_dev;
888 int link_state;
889
890 /* hash together the state values to decide if something has changed */
891 link_state = phy->speed | (phy->duplex << 1) | phy->link;
892
893 if (lp->last_link != link_state) {
894 lp->last_link = link_state;
895 phy_print_status(phy);
896 }
897}
898
899/**
900 * xemaclite_open - Open the network device
901 * @dev: Pointer to the network device
902 *
903 * This function sets the MAC address, requests an IRQ and enables interrupts
904 * for the Emaclite device and starts the Tx queue.
905 * It also connects to the phy device, if MDIO is included in Emaclite device.
906 *
907 * Return: 0 on success. -ENODEV, if PHY cannot be connected.
908 * Non-zero error value on failure.
909 */
910static int xemaclite_open(struct net_device *dev)
911{
912 struct net_local *lp = netdev_priv(dev);
913 int retval;
914
915 /* Just to be safe, stop the device first */
916 xemaclite_disable_interrupts(lp);
917
918 if (lp->phy_node) {
919 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
920 xemaclite_adjust_link, 0,
921 PHY_INTERFACE_MODE_MII);
922 if (!lp->phy_dev) {
923 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n");
924 return -ENODEV;
925 }
926
927 /* EmacLite doesn't support giga-bit speeds */
928 phy_set_max_speed(lp->phy_dev, SPEED_100);
929 phy_start(lp->phy_dev);
930 }
931
932 /* Set the MAC address each time opened */
933 xemaclite_update_address(lp, dev->dev_addr);
934
935 /* Grab the IRQ */
936 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev);
937 if (retval) {
938 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n",
939 dev->irq);
940 if (lp->phy_dev)
941 phy_disconnect(lp->phy_dev);
942 lp->phy_dev = NULL;
943
944 return retval;
945 }
946
947 /* Enable Interrupts */
948 xemaclite_enable_interrupts(lp);
949
950 /* We're ready to go */
951 netif_start_queue(dev);
952
953 return 0;
954}
955
956/**
957 * xemaclite_close - Close the network device
958 * @dev: Pointer to the network device
959 *
960 * This function stops the Tx queue, disables interrupts and frees the IRQ for
961 * the Emaclite device.
962 * It also disconnects the phy device associated with the Emaclite device.
963 *
964 * Return: 0, always.
965 */
966static int xemaclite_close(struct net_device *dev)
967{
968 struct net_local *lp = netdev_priv(dev);
969
970 netif_stop_queue(dev);
971 xemaclite_disable_interrupts(lp);
972 free_irq(dev->irq, dev);
973
974 if (lp->phy_dev)
975 phy_disconnect(lp->phy_dev);
976 lp->phy_dev = NULL;
977
978 return 0;
979}
980
981/**
982 * xemaclite_send - Transmit a frame
983 * @orig_skb: Pointer to the socket buffer to be transmitted
984 * @dev: Pointer to the network device
985 *
986 * This function checks if the Tx buffer of the Emaclite device is free to send
987 * data. If so, it fills the Tx buffer with data from socket buffer data,
988 * updates the stats and frees the socket buffer. The Tx completion is signaled
989 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is
990 * deferred and the Tx queue is stopped so that the deferred socket buffer can
991 * be transmitted when the Emaclite device is free to transmit data.
992 *
993 * Return: NETDEV_TX_OK, always.
994 */
995static netdev_tx_t
996xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
997{
998 struct net_local *lp = netdev_priv(dev);
999 struct sk_buff *new_skb;
1000 unsigned int len;
1001 unsigned long flags;
1002
1003 len = orig_skb->len;
1004
1005 new_skb = orig_skb;
1006
1007 spin_lock_irqsave(&lp->reset_lock, flags);
1008 if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) {
1009 /* If the Emaclite Tx buffer is busy, stop the Tx queue and
1010 * defer the skb for transmission during the ISR, after the
1011 * current transmission is complete
1012 */
1013 netif_stop_queue(dev);
1014 lp->deferred_skb = new_skb;
1015 /* Take the time stamp now, since we can't do this in an ISR. */
1016 skb_tx_timestamp(new_skb);
1017 spin_unlock_irqrestore(&lp->reset_lock, flags);
1018 return NETDEV_TX_OK;
1019 }
1020 spin_unlock_irqrestore(&lp->reset_lock, flags);
1021
1022 skb_tx_timestamp(new_skb);
1023
1024 dev->stats.tx_bytes += len;
1025 dev_consume_skb_any(new_skb);
1026
1027 return NETDEV_TX_OK;
1028}
1029
1030/**
1031 * get_bool - Get a parameter from the OF device
1032 * @ofdev: Pointer to OF device structure
1033 * @s: Property to be retrieved
1034 *
1035 * This function looks for a property in the device node and returns the value
1036 * of the property if its found or 0 if the property is not found.
1037 *
1038 * Return: Value of the parameter if the parameter is found, or 0 otherwise
1039 */
1040static bool get_bool(struct platform_device *ofdev, const char *s)
1041{
1042 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL);
1043
1044 if (!p) {
1045 dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s);
1046 return false;
1047 }
1048
1049 return (bool)*p;
1050}
1051
1052/**
1053 * xemaclite_ethtools_get_drvinfo - Get various Axi Emac Lite driver info
1054 * @ndev: Pointer to net_device structure
1055 * @ed: Pointer to ethtool_drvinfo structure
1056 *
1057 * This implements ethtool command for getting the driver information.
1058 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1059 */
1060static void xemaclite_ethtools_get_drvinfo(struct net_device *ndev,
1061 struct ethtool_drvinfo *ed)
1062{
1063 strscpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1064}
1065
1066static const struct ethtool_ops xemaclite_ethtool_ops = {
1067 .get_drvinfo = xemaclite_ethtools_get_drvinfo,
1068 .get_link = ethtool_op_get_link,
1069 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1070 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1071};
1072
1073static const struct net_device_ops xemaclite_netdev_ops;
1074
1075/**
1076 * xemaclite_of_probe - Probe method for the Emaclite device.
1077 * @ofdev: Pointer to OF device structure
1078 *
1079 * This function probes for the Emaclite device in the device tree.
1080 * It initializes the driver data structure and the hardware, sets the MAC
1081 * address and registers the network device.
1082 * It also registers a mii_bus for the Emaclite device, if MDIO is included
1083 * in the device.
1084 *
1085 * Return: 0, if the driver is bound to the Emaclite device, or
1086 * a negative error if there is failure.
1087 */
1088static int xemaclite_of_probe(struct platform_device *ofdev)
1089{
1090 struct resource *res;
1091 struct net_device *ndev = NULL;
1092 struct net_local *lp = NULL;
1093 struct device *dev = &ofdev->dev;
1094
1095 int rc = 0;
1096
1097 dev_info(dev, "Device Tree Probing\n");
1098
1099 /* Create an ethernet device instance */
1100 ndev = alloc_etherdev(sizeof(struct net_local));
1101 if (!ndev)
1102 return -ENOMEM;
1103
1104 dev_set_drvdata(dev, ndev);
1105 SET_NETDEV_DEV(ndev, &ofdev->dev);
1106
1107 lp = netdev_priv(ndev);
1108 lp->ndev = ndev;
1109
1110 /* Get IRQ for the device */
1111 rc = platform_get_irq(ofdev, 0);
1112 if (rc < 0)
1113 goto error;
1114
1115 ndev->irq = rc;
1116
1117 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1118 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res);
1119 if (IS_ERR(lp->base_addr)) {
1120 rc = PTR_ERR(lp->base_addr);
1121 goto error;
1122 }
1123
1124 ndev->mem_start = res->start;
1125 ndev->mem_end = res->end;
1126
1127 spin_lock_init(&lp->reset_lock);
1128 lp->next_tx_buf_to_use = 0x0;
1129 lp->next_rx_buf_to_use = 0x0;
1130 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong");
1131 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong");
1132
1133 rc = of_get_ethdev_address(ofdev->dev.of_node, ndev);
1134 if (rc) {
1135 dev_warn(dev, "No MAC address found, using random\n");
1136 eth_hw_addr_random(ndev);
1137 }
1138
1139 /* Clear the Tx CSR's in case this is a restart */
1140 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET);
1141 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
1142
1143 /* Set the MAC address in the EmacLite device */
1144 xemaclite_update_address(lp, ndev->dev_addr);
1145
1146 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
1147 xemaclite_mdio_setup(lp, &ofdev->dev);
1148
1149 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
1150
1151 ndev->netdev_ops = &xemaclite_netdev_ops;
1152 ndev->ethtool_ops = &xemaclite_ethtool_ops;
1153 ndev->flags &= ~IFF_MULTICAST;
1154 ndev->watchdog_timeo = TX_TIMEOUT;
1155
1156 /* Finally, register the device */
1157 rc = register_netdev(ndev);
1158 if (rc) {
1159 dev_err(dev,
1160 "Cannot register network device, aborting\n");
1161 goto put_node;
1162 }
1163
1164 dev_info(dev,
1165 "Xilinx EmacLite at 0x%08lX mapped to 0x%p, irq=%d\n",
1166 (unsigned long __force)ndev->mem_start, lp->base_addr, ndev->irq);
1167 return 0;
1168
1169put_node:
1170 of_node_put(lp->phy_node);
1171error:
1172 free_netdev(ndev);
1173 return rc;
1174}
1175
1176/**
1177 * xemaclite_of_remove - Unbind the driver from the Emaclite device.
1178 * @of_dev: Pointer to OF device structure
1179 *
1180 * This function is called if a device is physically removed from the system or
1181 * if the driver module is being unloaded. It frees any resources allocated to
1182 * the device.
1183 */
1184static void xemaclite_of_remove(struct platform_device *of_dev)
1185{
1186 struct net_device *ndev = platform_get_drvdata(of_dev);
1187
1188 struct net_local *lp = netdev_priv(ndev);
1189
1190 /* Un-register the mii_bus, if configured */
1191 if (lp->mii_bus) {
1192 mdiobus_unregister(lp->mii_bus);
1193 mdiobus_free(lp->mii_bus);
1194 lp->mii_bus = NULL;
1195 }
1196
1197 unregister_netdev(ndev);
1198
1199 of_node_put(lp->phy_node);
1200 lp->phy_node = NULL;
1201
1202 free_netdev(ndev);
1203}
1204
1205#ifdef CONFIG_NET_POLL_CONTROLLER
1206static void
1207xemaclite_poll_controller(struct net_device *ndev)
1208{
1209 disable_irq(ndev->irq);
1210 xemaclite_interrupt(ndev->irq, ndev);
1211 enable_irq(ndev->irq);
1212}
1213#endif
1214
1215/* Ioctl MII Interface */
1216static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1217{
1218 if (!dev->phydev || !netif_running(dev))
1219 return -EINVAL;
1220
1221 switch (cmd) {
1222 case SIOCGMIIPHY:
1223 case SIOCGMIIREG:
1224 case SIOCSMIIREG:
1225 return phy_mii_ioctl(dev->phydev, rq, cmd);
1226 default:
1227 return -EOPNOTSUPP;
1228 }
1229}
1230
1231static const struct net_device_ops xemaclite_netdev_ops = {
1232 .ndo_open = xemaclite_open,
1233 .ndo_stop = xemaclite_close,
1234 .ndo_start_xmit = xemaclite_send,
1235 .ndo_set_mac_address = xemaclite_set_mac_address,
1236 .ndo_tx_timeout = xemaclite_tx_timeout,
1237 .ndo_eth_ioctl = xemaclite_ioctl,
1238#ifdef CONFIG_NET_POLL_CONTROLLER
1239 .ndo_poll_controller = xemaclite_poll_controller,
1240#endif
1241};
1242
1243/* Match table for OF platform binding */
1244static const struct of_device_id xemaclite_of_match[] = {
1245 { .compatible = "xlnx,opb-ethernetlite-1.01.a", },
1246 { .compatible = "xlnx,opb-ethernetlite-1.01.b", },
1247 { .compatible = "xlnx,xps-ethernetlite-1.00.a", },
1248 { .compatible = "xlnx,xps-ethernetlite-2.00.a", },
1249 { .compatible = "xlnx,xps-ethernetlite-2.01.a", },
1250 { .compatible = "xlnx,xps-ethernetlite-3.00.a", },
1251 { /* end of list */ },
1252};
1253MODULE_DEVICE_TABLE(of, xemaclite_of_match);
1254
1255static struct platform_driver xemaclite_of_driver = {
1256 .driver = {
1257 .name = DRIVER_NAME,
1258 .of_match_table = xemaclite_of_match,
1259 },
1260 .probe = xemaclite_of_probe,
1261 .remove_new = xemaclite_of_remove,
1262};
1263
1264module_platform_driver(xemaclite_of_driver);
1265
1266MODULE_AUTHOR("Xilinx, Inc.");
1267MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver");
1268MODULE_LICENSE("GPL");
1/*
2 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device.
3 *
4 * This is a new flat driver which is based on the original emac_lite
5 * driver from John Williams <john.williams@xilinx.com>.
6 *
7 * 2007 - 2013 (c) Xilinx, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/uaccess.h>
17#include <linux/netdevice.h>
18#include <linux/etherdevice.h>
19#include <linux/skbuff.h>
20#include <linux/io.h>
21#include <linux/slab.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/of_platform.h>
25#include <linux/of_mdio.h>
26#include <linux/of_net.h>
27#include <linux/phy.h>
28#include <linux/interrupt.h>
29
30#define DRIVER_NAME "xilinx_emaclite"
31
32/* Register offsets for the EmacLite Core */
33#define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */
34#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */
35#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */
36#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */
37#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */
38#define XEL_GIER_OFFSET 0x07F8 /* GIE Register */
39#define XEL_TSR_OFFSET 0x07FC /* Tx status */
40#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
41
42#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
43#define XEL_RPLR_OFFSET 0x100C /* Rx packet length */
44#define XEL_RSR_OFFSET 0x17FC /* Rx status */
45
46#define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */
47
48/* MDIO Address Register Bit Masks */
49#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
50#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
51#define XEL_MDIOADDR_PHYADR_SHIFT 5
52#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
53
54/* MDIO Write Data Register Bit Masks */
55#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
56
57/* MDIO Read Data Register Bit Masks */
58#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
59
60/* MDIO Control Register Bit Masks */
61#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
62#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
63
64/* Global Interrupt Enable Register (GIER) Bit Masks */
65#define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */
66
67/* Transmit Status Register (TSR) Bit Masks */
68#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */
69#define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */
70#define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */
71#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit
72 * only. This is not documented
73 * in the HW spec */
74
75/* Define for programming the MAC address into the EmacLite */
76#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
77
78/* Receive Status Register (RSR) */
79#define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */
80#define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */
81
82/* Transmit Packet Length Register (TPLR) */
83#define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */
84
85/* Receive Packet Length Register (RPLR) */
86#define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */
87
88#define XEL_HEADER_OFFSET 12 /* Offset to length field */
89#define XEL_HEADER_SHIFT 16 /* Shift value for length */
90
91/* General Ethernet Definitions */
92#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */
93#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */
94
95
96
97#define TX_TIMEOUT (60*HZ) /* Tx timeout is 60 seconds. */
98#define ALIGNMENT 4
99
100/* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */
101#define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT)
102
103/**
104 * struct net_local - Our private per device data
105 * @ndev: instance of the network device
106 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW
107 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW
108 * @next_tx_buf_to_use: next Tx buffer to write to
109 * @next_rx_buf_to_use: next Rx buffer to read from
110 * @base_addr: base address of the Emaclite device
111 * @reset_lock: lock used for synchronization
112 * @deferred_skb: holds an skb (for transmission at a later time) when the
113 * Tx buffer is not free
114 * @phy_dev: pointer to the PHY device
115 * @phy_node: pointer to the PHY device node
116 * @mii_bus: pointer to the MII bus
117 * @last_link: last link status
118 * @has_mdio: indicates whether MDIO is included in the HW
119 */
120struct net_local {
121
122 struct net_device *ndev;
123
124 bool tx_ping_pong;
125 bool rx_ping_pong;
126 u32 next_tx_buf_to_use;
127 u32 next_rx_buf_to_use;
128 void __iomem *base_addr;
129
130 spinlock_t reset_lock;
131 struct sk_buff *deferred_skb;
132
133 struct phy_device *phy_dev;
134 struct device_node *phy_node;
135
136 struct mii_bus *mii_bus;
137
138 int last_link;
139 bool has_mdio;
140};
141
142
143/*************************/
144/* EmacLite driver calls */
145/*************************/
146
147/**
148 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device
149 * @drvdata: Pointer to the Emaclite device private data
150 *
151 * This function enables the Tx and Rx interrupts for the Emaclite device along
152 * with the Global Interrupt Enable.
153 */
154static void xemaclite_enable_interrupts(struct net_local *drvdata)
155{
156 u32 reg_data;
157
158 /* Enable the Tx interrupts for the first Buffer */
159 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);
160 __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
161 drvdata->base_addr + XEL_TSR_OFFSET);
162
163 /* Enable the Rx interrupts for the first buffer */
164 __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
165
166 /* Enable the Global Interrupt Enable */
167 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
168}
169
170/**
171 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device
172 * @drvdata: Pointer to the Emaclite device private data
173 *
174 * This function disables the Tx and Rx interrupts for the Emaclite device,
175 * along with the Global Interrupt Enable.
176 */
177static void xemaclite_disable_interrupts(struct net_local *drvdata)
178{
179 u32 reg_data;
180
181 /* Disable the Global Interrupt Enable */
182 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
183
184 /* Disable the Tx interrupts for the first buffer */
185 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);
186 __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
187 drvdata->base_addr + XEL_TSR_OFFSET);
188
189 /* Disable the Rx interrupts for the first buffer */
190 reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET);
191 __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
192 drvdata->base_addr + XEL_RSR_OFFSET);
193}
194
195/**
196 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address
197 * @src_ptr: Void pointer to the 16-bit aligned source address
198 * @dest_ptr: Pointer to the 32-bit aligned destination address
199 * @length: Number bytes to write from source to destination
200 *
201 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned
202 * address in the EmacLite device.
203 */
204static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr,
205 unsigned length)
206{
207 u32 align_buffer;
208 u32 *to_u32_ptr;
209 u16 *from_u16_ptr, *to_u16_ptr;
210
211 to_u32_ptr = dest_ptr;
212 from_u16_ptr = src_ptr;
213 align_buffer = 0;
214
215 for (; length > 3; length -= 4) {
216 to_u16_ptr = (u16 *)&align_buffer;
217 *to_u16_ptr++ = *from_u16_ptr++;
218 *to_u16_ptr++ = *from_u16_ptr++;
219
220 /* This barrier resolves occasional issues seen around
221 * cases where the data is not properly flushed out
222 * from the processor store buffers to the destination
223 * memory locations.
224 */
225 wmb();
226
227 /* Output a word */
228 *to_u32_ptr++ = align_buffer;
229 }
230 if (length) {
231 u8 *from_u8_ptr, *to_u8_ptr;
232
233 /* Set up to output the remaining data */
234 align_buffer = 0;
235 to_u8_ptr = (u8 *) &align_buffer;
236 from_u8_ptr = (u8 *) from_u16_ptr;
237
238 /* Output the remaining data */
239 for (; length > 0; length--)
240 *to_u8_ptr++ = *from_u8_ptr++;
241
242 /* This barrier resolves occasional issues seen around
243 * cases where the data is not properly flushed out
244 * from the processor store buffers to the destination
245 * memory locations.
246 */
247 wmb();
248 *to_u32_ptr = align_buffer;
249 }
250}
251
252/**
253 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer
254 * @src_ptr: Pointer to the 32-bit aligned source address
255 * @dest_ptr: Pointer to the 16-bit aligned destination address
256 * @length: Number bytes to read from source to destination
257 *
258 * This function reads data from a 32-bit aligned address in the EmacLite device
259 * to a 16-bit aligned buffer.
260 */
261static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr,
262 unsigned length)
263{
264 u16 *to_u16_ptr, *from_u16_ptr;
265 u32 *from_u32_ptr;
266 u32 align_buffer;
267
268 from_u32_ptr = src_ptr;
269 to_u16_ptr = (u16 *) dest_ptr;
270
271 for (; length > 3; length -= 4) {
272 /* Copy each word into the temporary buffer */
273 align_buffer = *from_u32_ptr++;
274 from_u16_ptr = (u16 *)&align_buffer;
275
276 /* Read data from source */
277 *to_u16_ptr++ = *from_u16_ptr++;
278 *to_u16_ptr++ = *from_u16_ptr++;
279 }
280
281 if (length) {
282 u8 *to_u8_ptr, *from_u8_ptr;
283
284 /* Set up to read the remaining data */
285 to_u8_ptr = (u8 *) to_u16_ptr;
286 align_buffer = *from_u32_ptr++;
287 from_u8_ptr = (u8 *) &align_buffer;
288
289 /* Read the remaining data */
290 for (; length > 0; length--)
291 *to_u8_ptr = *from_u8_ptr;
292 }
293}
294
295/**
296 * xemaclite_send_data - Send an Ethernet frame
297 * @drvdata: Pointer to the Emaclite device private data
298 * @data: Pointer to the data to be sent
299 * @byte_count: Total frame size, including header
300 *
301 * This function checks if the Tx buffer of the Emaclite device is free to send
302 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it
303 * returns an error.
304 *
305 * Return: 0 upon success or -1 if the buffer(s) are full.
306 *
307 * Note: The maximum Tx packet size can not be more than Ethernet header
308 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS.
309 */
310static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
311 unsigned int byte_count)
312{
313 u32 reg_data;
314 void __iomem *addr;
315
316 /* Determine the expected Tx buffer address */
317 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
318
319 /* If the length is too large, truncate it */
320 if (byte_count > ETH_FRAME_LEN)
321 byte_count = ETH_FRAME_LEN;
322
323 /* Check if the expected buffer is available */
324 reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
325 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
326 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
327
328 /* Switch to next buffer if configured */
329 if (drvdata->tx_ping_pong != 0)
330 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET;
331 } else if (drvdata->tx_ping_pong != 0) {
332 /* If the expected buffer is full, try the other buffer,
333 * if it is configured in HW */
334
335 addr = (void __iomem __force *)((u32 __force)addr ^
336 XEL_BUFFER_OFFSET);
337 reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
338
339 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
340 XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
341 return -1; /* Buffers were full, return failure */
342 } else
343 return -1; /* Buffer was full, return failure */
344
345 /* Write the frame to the buffer */
346 xemaclite_aligned_write(data, (u32 __force *) addr, byte_count);
347
348 __raw_writel((byte_count & XEL_TPLR_LENGTH_MASK),
349 addr + XEL_TPLR_OFFSET);
350
351 /* Update the Tx Status Register to indicate that there is a
352 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
353 * is used by the interrupt handler to check whether a frame
354 * has been transmitted */
355 reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
356 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
357 __raw_writel(reg_data, addr + XEL_TSR_OFFSET);
358
359 return 0;
360}
361
362/**
363 * xemaclite_recv_data - Receive a frame
364 * @drvdata: Pointer to the Emaclite device private data
365 * @data: Address where the data is to be received
366 *
367 * This function is intended to be called from the interrupt context or
368 * with a wrapper which waits for the receive frame to be available.
369 *
370 * Return: Total number of bytes received
371 */
372static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
373{
374 void __iomem *addr;
375 u16 length, proto_type;
376 u32 reg_data;
377
378 /* Determine the expected buffer address */
379 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
380
381 /* Verify which buffer has valid data */
382 reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
383
384 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
385 if (drvdata->rx_ping_pong != 0)
386 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET;
387 } else {
388 /* The instance is out of sync, try other buffer if other
389 * buffer is configured, return 0 otherwise. If the instance is
390 * out of sync, do not update the 'next_rx_buf_to_use' since it
391 * will correct on subsequent calls */
392 if (drvdata->rx_ping_pong != 0)
393 addr = (void __iomem __force *)((u32 __force)addr ^
394 XEL_BUFFER_OFFSET);
395 else
396 return 0; /* No data was available */
397
398 /* Verify that buffer has valid data */
399 reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
400 if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
401 XEL_RSR_RECV_DONE_MASK)
402 return 0; /* No data was available */
403 }
404
405 /* Get the protocol type of the ethernet frame that arrived */
406 proto_type = ((ntohl(__raw_readl(addr + XEL_HEADER_OFFSET +
407 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
408 XEL_RPLR_LENGTH_MASK);
409
410 /* Check if received ethernet frame is a raw ethernet frame
411 * or an IP packet or an ARP packet */
412 if (proto_type > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
413
414 if (proto_type == ETH_P_IP) {
415 length = ((ntohl(__raw_readl(addr +
416 XEL_HEADER_IP_LENGTH_OFFSET +
417 XEL_RXBUFF_OFFSET)) >>
418 XEL_HEADER_SHIFT) &
419 XEL_RPLR_LENGTH_MASK);
420 length += ETH_HLEN + ETH_FCS_LEN;
421
422 } else if (proto_type == ETH_P_ARP)
423 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN;
424 else
425 /* Field contains type other than IP or ARP, use max
426 * frame size and let user parse it */
427 length = ETH_FRAME_LEN + ETH_FCS_LEN;
428 } else
429 /* Use the length in the frame, plus the header and trailer */
430 length = proto_type + ETH_HLEN + ETH_FCS_LEN;
431
432 /* Read from the EmacLite device */
433 xemaclite_aligned_read((u32 __force *) (addr + XEL_RXBUFF_OFFSET),
434 data, length);
435
436 /* Acknowledge the frame */
437 reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
438 reg_data &= ~XEL_RSR_RECV_DONE_MASK;
439 __raw_writel(reg_data, addr + XEL_RSR_OFFSET);
440
441 return length;
442}
443
444/**
445 * xemaclite_update_address - Update the MAC address in the device
446 * @drvdata: Pointer to the Emaclite device private data
447 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value)
448 *
449 * Tx must be idle and Rx should be idle for deterministic results.
450 * It is recommended that this function should be called after the
451 * initialization and before transmission of any packets from the device.
452 * The MAC address can be programmed using any of the two transmit
453 * buffers (if configured).
454 */
455static void xemaclite_update_address(struct net_local *drvdata,
456 u8 *address_ptr)
457{
458 void __iomem *addr;
459 u32 reg_data;
460
461 /* Determine the expected Tx buffer address */
462 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
463
464 xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN);
465
466 __raw_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);
467
468 /* Update the MAC address in the EmacLite */
469 reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
470 __raw_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
471
472 /* Wait for EmacLite to finish with the MAC address update */
473 while ((__raw_readl(addr + XEL_TSR_OFFSET) &
474 XEL_TSR_PROG_MAC_ADDR) != 0)
475 ;
476}
477
478/**
479 * xemaclite_set_mac_address - Set the MAC address for this device
480 * @dev: Pointer to the network device instance
481 * @addr: Void pointer to the sockaddr structure
482 *
483 * This function copies the HW address from the sockaddr strucutre to the
484 * net_device structure and updates the address in HW.
485 *
486 * Return: Error if the net device is busy or 0 if the addr is set
487 * successfully
488 */
489static int xemaclite_set_mac_address(struct net_device *dev, void *address)
490{
491 struct net_local *lp = netdev_priv(dev);
492 struct sockaddr *addr = address;
493
494 if (netif_running(dev))
495 return -EBUSY;
496
497 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
498 xemaclite_update_address(lp, dev->dev_addr);
499 return 0;
500}
501
502/**
503 * xemaclite_tx_timeout - Callback for Tx Timeout
504 * @dev: Pointer to the network device
505 *
506 * This function is called when Tx time out occurs for Emaclite device.
507 */
508static void xemaclite_tx_timeout(struct net_device *dev)
509{
510 struct net_local *lp = netdev_priv(dev);
511 unsigned long flags;
512
513 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n",
514 TX_TIMEOUT * 1000UL / HZ);
515
516 dev->stats.tx_errors++;
517
518 /* Reset the device */
519 spin_lock_irqsave(&lp->reset_lock, flags);
520
521 /* Shouldn't really be necessary, but shouldn't hurt */
522 netif_stop_queue(dev);
523
524 xemaclite_disable_interrupts(lp);
525 xemaclite_enable_interrupts(lp);
526
527 if (lp->deferred_skb) {
528 dev_kfree_skb(lp->deferred_skb);
529 lp->deferred_skb = NULL;
530 dev->stats.tx_errors++;
531 }
532
533 /* To exclude tx timeout */
534 dev->trans_start = jiffies; /* prevent tx timeout */
535
536 /* We're all ready to go. Start the queue */
537 netif_wake_queue(dev);
538 spin_unlock_irqrestore(&lp->reset_lock, flags);
539}
540
541/**********************/
542/* Interrupt Handlers */
543/**********************/
544
545/**
546 * xemaclite_tx_handler - Interrupt handler for frames sent
547 * @dev: Pointer to the network device
548 *
549 * This function updates the number of packets transmitted and handles the
550 * deferred skb, if there is one.
551 */
552static void xemaclite_tx_handler(struct net_device *dev)
553{
554 struct net_local *lp = netdev_priv(dev);
555
556 dev->stats.tx_packets++;
557 if (lp->deferred_skb) {
558 if (xemaclite_send_data(lp,
559 (u8 *) lp->deferred_skb->data,
560 lp->deferred_skb->len) != 0)
561 return;
562 else {
563 dev->stats.tx_bytes += lp->deferred_skb->len;
564 dev_kfree_skb_irq(lp->deferred_skb);
565 lp->deferred_skb = NULL;
566 dev->trans_start = jiffies; /* prevent tx timeout */
567 netif_wake_queue(dev);
568 }
569 }
570}
571
572/**
573 * xemaclite_rx_handler- Interrupt handler for frames received
574 * @dev: Pointer to the network device
575 *
576 * This function allocates memory for a socket buffer, fills it with data
577 * received and hands it over to the TCP/IP stack.
578 */
579static void xemaclite_rx_handler(struct net_device *dev)
580{
581 struct net_local *lp = netdev_priv(dev);
582 struct sk_buff *skb;
583 unsigned int align;
584 u32 len;
585
586 len = ETH_FRAME_LEN + ETH_FCS_LEN;
587 skb = netdev_alloc_skb(dev, len + ALIGNMENT);
588 if (!skb) {
589 /* Couldn't get memory. */
590 dev->stats.rx_dropped++;
591 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n");
592 return;
593 }
594
595 /*
596 * A new skb should have the data halfword aligned, but this code is
597 * here just in case that isn't true. Calculate how many
598 * bytes we should reserve to get the data to start on a word
599 * boundary */
600 align = BUFFER_ALIGN(skb->data);
601 if (align)
602 skb_reserve(skb, align);
603
604 skb_reserve(skb, 2);
605
606 len = xemaclite_recv_data(lp, (u8 *) skb->data);
607
608 if (!len) {
609 dev->stats.rx_errors++;
610 dev_kfree_skb_irq(skb);
611 return;
612 }
613
614 skb_put(skb, len); /* Tell the skb how much data we got */
615
616 skb->protocol = eth_type_trans(skb, dev);
617 skb_checksum_none_assert(skb);
618
619 dev->stats.rx_packets++;
620 dev->stats.rx_bytes += len;
621
622 if (!skb_defer_rx_timestamp(skb))
623 netif_rx(skb); /* Send the packet upstream */
624}
625
626/**
627 * xemaclite_interrupt - Interrupt handler for this driver
628 * @irq: Irq of the Emaclite device
629 * @dev_id: Void pointer to the network device instance used as callback
630 * reference
631 *
632 * This function handles the Tx and Rx interrupts of the EmacLite device.
633 */
634static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
635{
636 bool tx_complete = false;
637 struct net_device *dev = dev_id;
638 struct net_local *lp = netdev_priv(dev);
639 void __iomem *base_addr = lp->base_addr;
640 u32 tx_status;
641
642 /* Check if there is Rx Data available */
643 if ((__raw_readl(base_addr + XEL_RSR_OFFSET) &
644 XEL_RSR_RECV_DONE_MASK) ||
645 (__raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
646 & XEL_RSR_RECV_DONE_MASK))
647
648 xemaclite_rx_handler(dev);
649
650 /* Check if the Transmission for the first buffer is completed */
651 tx_status = __raw_readl(base_addr + XEL_TSR_OFFSET);
652 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
653 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
654
655 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
656 __raw_writel(tx_status, base_addr + XEL_TSR_OFFSET);
657
658 tx_complete = true;
659 }
660
661 /* Check if the Transmission for the second buffer is completed */
662 tx_status = __raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
663 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
664 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
665
666 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
667 __raw_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
668 XEL_TSR_OFFSET);
669
670 tx_complete = true;
671 }
672
673 /* If there was a Tx interrupt, call the Tx Handler */
674 if (tx_complete != 0)
675 xemaclite_tx_handler(dev);
676
677 return IRQ_HANDLED;
678}
679
680/**********************/
681/* MDIO Bus functions */
682/**********************/
683
684/**
685 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use
686 * @lp: Pointer to the Emaclite device private data
687 *
688 * This function waits till the device is ready to accept a new MDIO
689 * request.
690 *
691 * Return: 0 for success or ETIMEDOUT for a timeout
692 */
693
694static int xemaclite_mdio_wait(struct net_local *lp)
695{
696 unsigned long end = jiffies + 2;
697
698 /* wait for the MDIO interface to not be busy or timeout
699 after some time.
700 */
701 while (__raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) &
702 XEL_MDIOCTRL_MDIOSTS_MASK) {
703 if (time_before_eq(end, jiffies)) {
704 WARN_ON(1);
705 return -ETIMEDOUT;
706 }
707 msleep(1);
708 }
709 return 0;
710}
711
712/**
713 * xemaclite_mdio_read - Read from a given MII management register
714 * @bus: the mii_bus struct
715 * @phy_id: the phy address
716 * @reg: register number to read from
717 *
718 * This function waits till the device is ready to accept a new MDIO
719 * request and then writes the phy address to the MDIO Address register
720 * and reads data from MDIO Read Data register, when its available.
721 *
722 * Return: Value read from the MII management register
723 */
724static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg)
725{
726 struct net_local *lp = bus->priv;
727 u32 ctrl_reg;
728 u32 rc;
729
730 if (xemaclite_mdio_wait(lp))
731 return -ETIMEDOUT;
732
733 /* Write the PHY address, register number and set the OP bit in the
734 * MDIO Address register. Set the Status bit in the MDIO Control
735 * register to start a MDIO read transaction.
736 */
737 ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
738 __raw_writel(XEL_MDIOADDR_OP_MASK |
739 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
740 lp->base_addr + XEL_MDIOADDR_OFFSET);
741 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
742 lp->base_addr + XEL_MDIOCTRL_OFFSET);
743
744 if (xemaclite_mdio_wait(lp))
745 return -ETIMEDOUT;
746
747 rc = __raw_readl(lp->base_addr + XEL_MDIORD_OFFSET);
748
749 dev_dbg(&lp->ndev->dev,
750 "xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n",
751 phy_id, reg, rc);
752
753 return rc;
754}
755
756/**
757 * xemaclite_mdio_write - Write to a given MII management register
758 * @bus: the mii_bus struct
759 * @phy_id: the phy address
760 * @reg: register number to write to
761 * @val: value to write to the register number specified by reg
762 *
763 * This function waits till the device is ready to accept a new MDIO
764 * request and then writes the val to the MDIO Write Data register.
765 */
766static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg,
767 u16 val)
768{
769 struct net_local *lp = bus->priv;
770 u32 ctrl_reg;
771
772 dev_dbg(&lp->ndev->dev,
773 "xemaclite_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
774 phy_id, reg, val);
775
776 if (xemaclite_mdio_wait(lp))
777 return -ETIMEDOUT;
778
779 /* Write the PHY address, register number and clear the OP bit in the
780 * MDIO Address register and then write the value into the MDIO Write
781 * Data register. Finally, set the Status bit in the MDIO Control
782 * register to start a MDIO write transaction.
783 */
784 ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
785 __raw_writel(~XEL_MDIOADDR_OP_MASK &
786 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
787 lp->base_addr + XEL_MDIOADDR_OFFSET);
788 __raw_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
789 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
790 lp->base_addr + XEL_MDIOCTRL_OFFSET);
791
792 return 0;
793}
794
795/**
796 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device
797 * @lp: Pointer to the Emaclite device private data
798 * @ofdev: Pointer to OF device structure
799 *
800 * This function enables MDIO bus in the Emaclite device and registers a
801 * mii_bus.
802 *
803 * Return: 0 upon success or a negative error upon failure
804 */
805static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
806{
807 struct mii_bus *bus;
808 int rc;
809 struct resource res;
810 struct device_node *np = of_get_parent(lp->phy_node);
811 struct device_node *npp;
812
813 /* Don't register the MDIO bus if the phy_node or its parent node
814 * can't be found.
815 */
816 if (!np) {
817 dev_err(dev, "Failed to register mdio bus.\n");
818 return -ENODEV;
819 }
820 npp = of_get_parent(np);
821
822 of_address_to_resource(npp, 0, &res);
823 if (lp->ndev->mem_start != res.start) {
824 struct phy_device *phydev;
825 phydev = of_phy_find_device(lp->phy_node);
826 if (!phydev)
827 dev_info(dev,
828 "MDIO of the phy is not registered yet\n");
829 else
830 put_device(&phydev->mdio.dev);
831 return 0;
832 }
833
834 /* Enable the MDIO bus by asserting the enable bit in MDIO Control
835 * register.
836 */
837 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK,
838 lp->base_addr + XEL_MDIOCTRL_OFFSET);
839
840 bus = mdiobus_alloc();
841 if (!bus) {
842 dev_err(dev, "Failed to allocate mdiobus\n");
843 return -ENOMEM;
844 }
845
846 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
847 (unsigned long long)res.start);
848 bus->priv = lp;
849 bus->name = "Xilinx Emaclite MDIO";
850 bus->read = xemaclite_mdio_read;
851 bus->write = xemaclite_mdio_write;
852 bus->parent = dev;
853
854 lp->mii_bus = bus;
855
856 rc = of_mdiobus_register(bus, np);
857 if (rc) {
858 dev_err(dev, "Failed to register mdio bus.\n");
859 goto err_register;
860 }
861
862 return 0;
863
864err_register:
865 mdiobus_free(bus);
866 return rc;
867}
868
869/**
870 * xemaclite_adjust_link - Link state callback for the Emaclite device
871 * @ndev: pointer to net_device struct
872 *
873 * There's nothing in the Emaclite device to be configured when the link
874 * state changes. We just print the status.
875 */
876static void xemaclite_adjust_link(struct net_device *ndev)
877{
878 struct net_local *lp = netdev_priv(ndev);
879 struct phy_device *phy = lp->phy_dev;
880 int link_state;
881
882 /* hash together the state values to decide if something has changed */
883 link_state = phy->speed | (phy->duplex << 1) | phy->link;
884
885 if (lp->last_link != link_state) {
886 lp->last_link = link_state;
887 phy_print_status(phy);
888 }
889}
890
891/**
892 * xemaclite_open - Open the network device
893 * @dev: Pointer to the network device
894 *
895 * This function sets the MAC address, requests an IRQ and enables interrupts
896 * for the Emaclite device and starts the Tx queue.
897 * It also connects to the phy device, if MDIO is included in Emaclite device.
898 */
899static int xemaclite_open(struct net_device *dev)
900{
901 struct net_local *lp = netdev_priv(dev);
902 int retval;
903
904 /* Just to be safe, stop the device first */
905 xemaclite_disable_interrupts(lp);
906
907 if (lp->phy_node) {
908 u32 bmcr;
909
910 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
911 xemaclite_adjust_link, 0,
912 PHY_INTERFACE_MODE_MII);
913 if (!lp->phy_dev) {
914 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n");
915 return -ENODEV;
916 }
917
918 /* EmacLite doesn't support giga-bit speeds */
919 lp->phy_dev->supported &= (PHY_BASIC_FEATURES);
920 lp->phy_dev->advertising = lp->phy_dev->supported;
921
922 /* Don't advertise 1000BASE-T Full/Half duplex speeds */
923 phy_write(lp->phy_dev, MII_CTRL1000, 0);
924
925 /* Advertise only 10 and 100mbps full/half duplex speeds */
926 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL |
927 ADVERTISE_CSMA);
928
929 /* Restart auto negotiation */
930 bmcr = phy_read(lp->phy_dev, MII_BMCR);
931 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
932 phy_write(lp->phy_dev, MII_BMCR, bmcr);
933
934 phy_start(lp->phy_dev);
935 }
936
937 /* Set the MAC address each time opened */
938 xemaclite_update_address(lp, dev->dev_addr);
939
940 /* Grab the IRQ */
941 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev);
942 if (retval) {
943 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n",
944 dev->irq);
945 if (lp->phy_dev)
946 phy_disconnect(lp->phy_dev);
947 lp->phy_dev = NULL;
948
949 return retval;
950 }
951
952 /* Enable Interrupts */
953 xemaclite_enable_interrupts(lp);
954
955 /* We're ready to go */
956 netif_start_queue(dev);
957
958 return 0;
959}
960
961/**
962 * xemaclite_close - Close the network device
963 * @dev: Pointer to the network device
964 *
965 * This function stops the Tx queue, disables interrupts and frees the IRQ for
966 * the Emaclite device.
967 * It also disconnects the phy device associated with the Emaclite device.
968 */
969static int xemaclite_close(struct net_device *dev)
970{
971 struct net_local *lp = netdev_priv(dev);
972
973 netif_stop_queue(dev);
974 xemaclite_disable_interrupts(lp);
975 free_irq(dev->irq, dev);
976
977 if (lp->phy_dev)
978 phy_disconnect(lp->phy_dev);
979 lp->phy_dev = NULL;
980
981 return 0;
982}
983
984/**
985 * xemaclite_send - Transmit a frame
986 * @orig_skb: Pointer to the socket buffer to be transmitted
987 * @dev: Pointer to the network device
988 *
989 * This function checks if the Tx buffer of the Emaclite device is free to send
990 * data. If so, it fills the Tx buffer with data from socket buffer data,
991 * updates the stats and frees the socket buffer. The Tx completion is signaled
992 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is
993 * deferred and the Tx queue is stopped so that the deferred socket buffer can
994 * be transmitted when the Emaclite device is free to transmit data.
995 *
996 * Return: 0, always.
997 */
998static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
999{
1000 struct net_local *lp = netdev_priv(dev);
1001 struct sk_buff *new_skb;
1002 unsigned int len;
1003 unsigned long flags;
1004
1005 len = orig_skb->len;
1006
1007 new_skb = orig_skb;
1008
1009 spin_lock_irqsave(&lp->reset_lock, flags);
1010 if (xemaclite_send_data(lp, (u8 *) new_skb->data, len) != 0) {
1011 /* If the Emaclite Tx buffer is busy, stop the Tx queue and
1012 * defer the skb for transmission during the ISR, after the
1013 * current transmission is complete */
1014 netif_stop_queue(dev);
1015 lp->deferred_skb = new_skb;
1016 /* Take the time stamp now, since we can't do this in an ISR. */
1017 skb_tx_timestamp(new_skb);
1018 spin_unlock_irqrestore(&lp->reset_lock, flags);
1019 return 0;
1020 }
1021 spin_unlock_irqrestore(&lp->reset_lock, flags);
1022
1023 skb_tx_timestamp(new_skb);
1024
1025 dev->stats.tx_bytes += len;
1026 dev_consume_skb_any(new_skb);
1027
1028 return 0;
1029}
1030
1031/**
1032 * xemaclite_remove_ndev - Free the network device
1033 * @ndev: Pointer to the network device to be freed
1034 *
1035 * This function un maps the IO region of the Emaclite device and frees the net
1036 * device.
1037 */
1038static void xemaclite_remove_ndev(struct net_device *ndev)
1039{
1040 if (ndev) {
1041 free_netdev(ndev);
1042 }
1043}
1044
1045/**
1046 * get_bool - Get a parameter from the OF device
1047 * @ofdev: Pointer to OF device structure
1048 * @s: Property to be retrieved
1049 *
1050 * This function looks for a property in the device node and returns the value
1051 * of the property if its found or 0 if the property is not found.
1052 *
1053 * Return: Value of the parameter if the parameter is found, or 0 otherwise
1054 */
1055static bool get_bool(struct platform_device *ofdev, const char *s)
1056{
1057 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL);
1058
1059 if (p) {
1060 return (bool)*p;
1061 } else {
1062 dev_warn(&ofdev->dev, "Parameter %s not found,"
1063 "defaulting to false\n", s);
1064 return false;
1065 }
1066}
1067
1068static struct net_device_ops xemaclite_netdev_ops;
1069
1070/**
1071 * xemaclite_of_probe - Probe method for the Emaclite device.
1072 * @ofdev: Pointer to OF device structure
1073 * @match: Pointer to the structure used for matching a device
1074 *
1075 * This function probes for the Emaclite device in the device tree.
1076 * It initializes the driver data structure and the hardware, sets the MAC
1077 * address and registers the network device.
1078 * It also registers a mii_bus for the Emaclite device, if MDIO is included
1079 * in the device.
1080 *
1081 * Return: 0, if the driver is bound to the Emaclite device, or
1082 * a negative error if there is failure.
1083 */
1084static int xemaclite_of_probe(struct platform_device *ofdev)
1085{
1086 struct resource *res;
1087 struct net_device *ndev = NULL;
1088 struct net_local *lp = NULL;
1089 struct device *dev = &ofdev->dev;
1090 const void *mac_address;
1091
1092 int rc = 0;
1093
1094 dev_info(dev, "Device Tree Probing\n");
1095
1096 /* Create an ethernet device instance */
1097 ndev = alloc_etherdev(sizeof(struct net_local));
1098 if (!ndev)
1099 return -ENOMEM;
1100
1101 dev_set_drvdata(dev, ndev);
1102 SET_NETDEV_DEV(ndev, &ofdev->dev);
1103
1104 lp = netdev_priv(ndev);
1105 lp->ndev = ndev;
1106
1107 /* Get IRQ for the device */
1108 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0);
1109 if (!res) {
1110 dev_err(dev, "no IRQ found\n");
1111 rc = -ENXIO;
1112 goto error;
1113 }
1114
1115 ndev->irq = res->start;
1116
1117 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1118 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res);
1119 if (IS_ERR(lp->base_addr)) {
1120 rc = PTR_ERR(lp->base_addr);
1121 goto error;
1122 }
1123
1124 ndev->mem_start = res->start;
1125 ndev->mem_end = res->end;
1126
1127 spin_lock_init(&lp->reset_lock);
1128 lp->next_tx_buf_to_use = 0x0;
1129 lp->next_rx_buf_to_use = 0x0;
1130 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong");
1131 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong");
1132 mac_address = of_get_mac_address(ofdev->dev.of_node);
1133
1134 if (mac_address)
1135 /* Set the MAC address. */
1136 memcpy(ndev->dev_addr, mac_address, ETH_ALEN);
1137 else
1138 dev_warn(dev, "No MAC address found\n");
1139
1140 /* Clear the Tx CSR's in case this is a restart */
1141 __raw_writel(0, lp->base_addr + XEL_TSR_OFFSET);
1142 __raw_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
1143
1144 /* Set the MAC address in the EmacLite device */
1145 xemaclite_update_address(lp, ndev->dev_addr);
1146
1147 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
1148 rc = xemaclite_mdio_setup(lp, &ofdev->dev);
1149 if (rc)
1150 dev_warn(&ofdev->dev, "error registering MDIO bus\n");
1151
1152 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
1153
1154 ndev->netdev_ops = &xemaclite_netdev_ops;
1155 ndev->flags &= ~IFF_MULTICAST;
1156 ndev->watchdog_timeo = TX_TIMEOUT;
1157
1158 /* Finally, register the device */
1159 rc = register_netdev(ndev);
1160 if (rc) {
1161 dev_err(dev,
1162 "Cannot register network device, aborting\n");
1163 goto error;
1164 }
1165
1166 dev_info(dev,
1167 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n",
1168 (unsigned int __force)ndev->mem_start,
1169 (unsigned int __force)lp->base_addr, ndev->irq);
1170 return 0;
1171
1172error:
1173 xemaclite_remove_ndev(ndev);
1174 return rc;
1175}
1176
1177/**
1178 * xemaclite_of_remove - Unbind the driver from the Emaclite device.
1179 * @of_dev: Pointer to OF device structure
1180 *
1181 * This function is called if a device is physically removed from the system or
1182 * if the driver module is being unloaded. It frees any resources allocated to
1183 * the device.
1184 *
1185 * Return: 0, always.
1186 */
1187static int xemaclite_of_remove(struct platform_device *of_dev)
1188{
1189 struct net_device *ndev = platform_get_drvdata(of_dev);
1190
1191 struct net_local *lp = netdev_priv(ndev);
1192
1193 /* Un-register the mii_bus, if configured */
1194 if (lp->has_mdio) {
1195 mdiobus_unregister(lp->mii_bus);
1196 mdiobus_free(lp->mii_bus);
1197 lp->mii_bus = NULL;
1198 }
1199
1200 unregister_netdev(ndev);
1201
1202 of_node_put(lp->phy_node);
1203 lp->phy_node = NULL;
1204
1205 xemaclite_remove_ndev(ndev);
1206
1207 return 0;
1208}
1209
1210#ifdef CONFIG_NET_POLL_CONTROLLER
1211static void
1212xemaclite_poll_controller(struct net_device *ndev)
1213{
1214 disable_irq(ndev->irq);
1215 xemaclite_interrupt(ndev->irq, ndev);
1216 enable_irq(ndev->irq);
1217}
1218#endif
1219
1220static struct net_device_ops xemaclite_netdev_ops = {
1221 .ndo_open = xemaclite_open,
1222 .ndo_stop = xemaclite_close,
1223 .ndo_start_xmit = xemaclite_send,
1224 .ndo_set_mac_address = xemaclite_set_mac_address,
1225 .ndo_tx_timeout = xemaclite_tx_timeout,
1226#ifdef CONFIG_NET_POLL_CONTROLLER
1227 .ndo_poll_controller = xemaclite_poll_controller,
1228#endif
1229};
1230
1231/* Match table for OF platform binding */
1232static const struct of_device_id xemaclite_of_match[] = {
1233 { .compatible = "xlnx,opb-ethernetlite-1.01.a", },
1234 { .compatible = "xlnx,opb-ethernetlite-1.01.b", },
1235 { .compatible = "xlnx,xps-ethernetlite-1.00.a", },
1236 { .compatible = "xlnx,xps-ethernetlite-2.00.a", },
1237 { .compatible = "xlnx,xps-ethernetlite-2.01.a", },
1238 { .compatible = "xlnx,xps-ethernetlite-3.00.a", },
1239 { /* end of list */ },
1240};
1241MODULE_DEVICE_TABLE(of, xemaclite_of_match);
1242
1243static struct platform_driver xemaclite_of_driver = {
1244 .driver = {
1245 .name = DRIVER_NAME,
1246 .of_match_table = xemaclite_of_match,
1247 },
1248 .probe = xemaclite_of_probe,
1249 .remove = xemaclite_of_remove,
1250};
1251
1252module_platform_driver(xemaclite_of_driver);
1253
1254MODULE_AUTHOR("Xilinx, Inc.");
1255MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver");
1256MODULE_LICENSE("GPL");