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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Alchemy Au1x00 ethernet driver
5 *
6 * Copyright 2001-2003, 2006 MontaVista Software Inc.
7 * Copyright 2002 TimeSys Corp.
8 * Added ethtool/mii-tool support,
9 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
10 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
11 * or riemer@riemer-nt.de: fixed the link beat detection with
12 * ioctls (SIOCGMIIPHY)
13 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
14 * converted to use linux-2.6.x's PHY framework
15 *
16 * Author: MontaVista Software, Inc.
17 * ppopov@mvista.com or source@mvista.com
18 */
19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21#include <linux/capability.h>
22#include <linux/dma-mapping.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/string.h>
26#include <linux/timer.h>
27#include <linux/errno.h>
28#include <linux/in.h>
29#include <linux/ioport.h>
30#include <linux/bitops.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/skbuff.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
40#include <linux/phy.h>
41#include <linux/platform_device.h>
42#include <linux/cpu.h>
43#include <linux/io.h>
44
45#include <asm/mipsregs.h>
46#include <asm/irq.h>
47#include <asm/processor.h>
48
49#include <au1000.h>
50#include <au1xxx_eth.h>
51#include <prom.h>
52
53#include "au1000_eth.h"
54
55#ifdef AU1000_ETH_DEBUG
56static int au1000_debug = 5;
57#else
58static int au1000_debug = 3;
59#endif
60
61#define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
62 NETIF_MSG_PROBE | \
63 NETIF_MSG_LINK)
64
65#define DRV_NAME "au1000_eth"
66#define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
67#define DRV_DESC "Au1xxx on-chip Ethernet driver"
68
69MODULE_AUTHOR(DRV_AUTHOR);
70MODULE_DESCRIPTION(DRV_DESC);
71MODULE_LICENSE("GPL");
72
73/* AU1000 MAC registers and bits */
74#define MAC_CONTROL 0x0
75# define MAC_RX_ENABLE (1 << 2)
76# define MAC_TX_ENABLE (1 << 3)
77# define MAC_DEF_CHECK (1 << 5)
78# define MAC_SET_BL(X) (((X) & 0x3) << 6)
79# define MAC_AUTO_PAD (1 << 8)
80# define MAC_DISABLE_RETRY (1 << 10)
81# define MAC_DISABLE_BCAST (1 << 11)
82# define MAC_LATE_COL (1 << 12)
83# define MAC_HASH_MODE (1 << 13)
84# define MAC_HASH_ONLY (1 << 15)
85# define MAC_PASS_ALL (1 << 16)
86# define MAC_INVERSE_FILTER (1 << 17)
87# define MAC_PROMISCUOUS (1 << 18)
88# define MAC_PASS_ALL_MULTI (1 << 19)
89# define MAC_FULL_DUPLEX (1 << 20)
90# define MAC_NORMAL_MODE 0
91# define MAC_INT_LOOPBACK (1 << 21)
92# define MAC_EXT_LOOPBACK (1 << 22)
93# define MAC_DISABLE_RX_OWN (1 << 23)
94# define MAC_BIG_ENDIAN (1 << 30)
95# define MAC_RX_ALL (1 << 31)
96#define MAC_ADDRESS_HIGH 0x4
97#define MAC_ADDRESS_LOW 0x8
98#define MAC_MCAST_HIGH 0xC
99#define MAC_MCAST_LOW 0x10
100#define MAC_MII_CNTRL 0x14
101# define MAC_MII_BUSY (1 << 0)
102# define MAC_MII_READ 0
103# define MAC_MII_WRITE (1 << 1)
104# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
105# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
106#define MAC_MII_DATA 0x18
107#define MAC_FLOW_CNTRL 0x1C
108# define MAC_FLOW_CNTRL_BUSY (1 << 0)
109# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
110# define MAC_PASS_CONTROL (1 << 2)
111# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
112#define MAC_VLAN1_TAG 0x20
113#define MAC_VLAN2_TAG 0x24
114
115/* Ethernet Controller Enable */
116# define MAC_EN_CLOCK_ENABLE (1 << 0)
117# define MAC_EN_RESET0 (1 << 1)
118# define MAC_EN_TOSS (0 << 2)
119# define MAC_EN_CACHEABLE (1 << 3)
120# define MAC_EN_RESET1 (1 << 4)
121# define MAC_EN_RESET2 (1 << 5)
122# define MAC_DMA_RESET (1 << 6)
123
124/* Ethernet Controller DMA Channels */
125/* offsets from MAC_TX_RING_ADDR address */
126#define MAC_TX_BUFF0_STATUS 0x0
127# define TX_FRAME_ABORTED (1 << 0)
128# define TX_JAB_TIMEOUT (1 << 1)
129# define TX_NO_CARRIER (1 << 2)
130# define TX_LOSS_CARRIER (1 << 3)
131# define TX_EXC_DEF (1 << 4)
132# define TX_LATE_COLL_ABORT (1 << 5)
133# define TX_EXC_COLL (1 << 6)
134# define TX_UNDERRUN (1 << 7)
135# define TX_DEFERRED (1 << 8)
136# define TX_LATE_COLL (1 << 9)
137# define TX_COLL_CNT_MASK (0xF << 10)
138# define TX_PKT_RETRY (1 << 31)
139#define MAC_TX_BUFF0_ADDR 0x4
140# define TX_DMA_ENABLE (1 << 0)
141# define TX_T_DONE (1 << 1)
142# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
143#define MAC_TX_BUFF0_LEN 0x8
144#define MAC_TX_BUFF1_STATUS 0x10
145#define MAC_TX_BUFF1_ADDR 0x14
146#define MAC_TX_BUFF1_LEN 0x18
147#define MAC_TX_BUFF2_STATUS 0x20
148#define MAC_TX_BUFF2_ADDR 0x24
149#define MAC_TX_BUFF2_LEN 0x28
150#define MAC_TX_BUFF3_STATUS 0x30
151#define MAC_TX_BUFF3_ADDR 0x34
152#define MAC_TX_BUFF3_LEN 0x38
153
154/* offsets from MAC_RX_RING_ADDR */
155#define MAC_RX_BUFF0_STATUS 0x0
156# define RX_FRAME_LEN_MASK 0x3fff
157# define RX_WDOG_TIMER (1 << 14)
158# define RX_RUNT (1 << 15)
159# define RX_OVERLEN (1 << 16)
160# define RX_COLL (1 << 17)
161# define RX_ETHER (1 << 18)
162# define RX_MII_ERROR (1 << 19)
163# define RX_DRIBBLING (1 << 20)
164# define RX_CRC_ERROR (1 << 21)
165# define RX_VLAN1 (1 << 22)
166# define RX_VLAN2 (1 << 23)
167# define RX_LEN_ERROR (1 << 24)
168# define RX_CNTRL_FRAME (1 << 25)
169# define RX_U_CNTRL_FRAME (1 << 26)
170# define RX_MCAST_FRAME (1 << 27)
171# define RX_BCAST_FRAME (1 << 28)
172# define RX_FILTER_FAIL (1 << 29)
173# define RX_PACKET_FILTER (1 << 30)
174# define RX_MISSED_FRAME (1 << 31)
175
176# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
177 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
178 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
179#define MAC_RX_BUFF0_ADDR 0x4
180# define RX_DMA_ENABLE (1 << 0)
181# define RX_T_DONE (1 << 1)
182# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
183# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
184#define MAC_RX_BUFF1_STATUS 0x10
185#define MAC_RX_BUFF1_ADDR 0x14
186#define MAC_RX_BUFF2_STATUS 0x20
187#define MAC_RX_BUFF2_ADDR 0x24
188#define MAC_RX_BUFF3_STATUS 0x30
189#define MAC_RX_BUFF3_ADDR 0x34
190
191/*
192 * Theory of operation
193 *
194 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
195 * There are four receive and four transmit descriptors. These
196 * descriptors are not in memory; rather, they are just a set of
197 * hardware registers.
198 *
199 * Since the Au1000 has a coherent data cache, the receive and
200 * transmit buffers are allocated from the KSEG0 segment. The
201 * hardware registers, however, are still mapped at KSEG1 to
202 * make sure there's no out-of-order writes, and that all writes
203 * complete immediately.
204 */
205
206/*
207 * board-specific configurations
208 *
209 * PHY detection algorithm
210 *
211 * If phy_static_config is undefined, the PHY setup is
212 * autodetected:
213 *
214 * mii_probe() first searches the current MAC's MII bus for a PHY,
215 * selecting the first (or last, if phy_search_highest_addr is
216 * defined) PHY address not already claimed by another netdev.
217 *
218 * If nothing was found that way when searching for the 2nd ethernet
219 * controller's PHY and phy1_search_mac0 is defined, then
220 * the first MII bus is searched as well for an unclaimed PHY; this is
221 * needed in case of a dual-PHY accessible only through the MAC0's MII
222 * bus.
223 *
224 * Finally, if no PHY is found, then the corresponding ethernet
225 * controller is not registered to the network subsystem.
226 */
227
228/* autodetection defaults: phy1_search_mac0 */
229
230/* static PHY setup
231 *
232 * most boards PHY setup should be detectable properly with the
233 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
234 * you have a switch attached, or want to use the PHY's interrupt
235 * notification capabilities) you can provide a static PHY
236 * configuration here
237 *
238 * IRQs may only be set, if a PHY address was configured
239 * If a PHY address is given, also a bus id is required to be set
240 *
241 * ps: make sure the used irqs are configured properly in the board
242 * specific irq-map
243 */
244static void au1000_enable_mac(struct net_device *dev, int force_reset)
245{
246 unsigned long flags;
247 struct au1000_private *aup = netdev_priv(dev);
248
249 spin_lock_irqsave(&aup->lock, flags);
250
251 if (force_reset || (!aup->mac_enabled)) {
252 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
253 wmb(); /* drain writebuffer */
254 mdelay(2);
255 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
256 | MAC_EN_CLOCK_ENABLE), aup->enable);
257 wmb(); /* drain writebuffer */
258 mdelay(2);
259
260 aup->mac_enabled = 1;
261 }
262
263 spin_unlock_irqrestore(&aup->lock, flags);
264}
265
266/*
267 * MII operations
268 */
269static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
270{
271 struct au1000_private *aup = netdev_priv(dev);
272 u32 *const mii_control_reg = &aup->mac->mii_control;
273 u32 *const mii_data_reg = &aup->mac->mii_data;
274 u32 timedout = 20;
275 u32 mii_control;
276
277 while (readl(mii_control_reg) & MAC_MII_BUSY) {
278 mdelay(1);
279 if (--timedout == 0) {
280 netdev_err(dev, "read_MII busy timeout!!\n");
281 return -1;
282 }
283 }
284
285 mii_control = MAC_SET_MII_SELECT_REG(reg) |
286 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
287
288 writel(mii_control, mii_control_reg);
289
290 timedout = 20;
291 while (readl(mii_control_reg) & MAC_MII_BUSY) {
292 mdelay(1);
293 if (--timedout == 0) {
294 netdev_err(dev, "mdio_read busy timeout!!\n");
295 return -1;
296 }
297 }
298 return readl(mii_data_reg);
299}
300
301static void au1000_mdio_write(struct net_device *dev, int phy_addr,
302 int reg, u16 value)
303{
304 struct au1000_private *aup = netdev_priv(dev);
305 u32 *const mii_control_reg = &aup->mac->mii_control;
306 u32 *const mii_data_reg = &aup->mac->mii_data;
307 u32 timedout = 20;
308 u32 mii_control;
309
310 while (readl(mii_control_reg) & MAC_MII_BUSY) {
311 mdelay(1);
312 if (--timedout == 0) {
313 netdev_err(dev, "mdio_write busy timeout!!\n");
314 return;
315 }
316 }
317
318 mii_control = MAC_SET_MII_SELECT_REG(reg) |
319 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
320
321 writel(value, mii_data_reg);
322 writel(mii_control, mii_control_reg);
323}
324
325static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
326{
327 struct net_device *const dev = bus->priv;
328
329 /* make sure the MAC associated with this
330 * mii_bus is enabled
331 */
332 au1000_enable_mac(dev, 0);
333
334 return au1000_mdio_read(dev, phy_addr, regnum);
335}
336
337static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
338 u16 value)
339{
340 struct net_device *const dev = bus->priv;
341
342 /* make sure the MAC associated with this
343 * mii_bus is enabled
344 */
345 au1000_enable_mac(dev, 0);
346
347 au1000_mdio_write(dev, phy_addr, regnum, value);
348 return 0;
349}
350
351static int au1000_mdiobus_reset(struct mii_bus *bus)
352{
353 struct net_device *const dev = bus->priv;
354
355 /* make sure the MAC associated with this
356 * mii_bus is enabled
357 */
358 au1000_enable_mac(dev, 0);
359
360 return 0;
361}
362
363static void au1000_hard_stop(struct net_device *dev)
364{
365 struct au1000_private *aup = netdev_priv(dev);
366 u32 reg;
367
368 netif_dbg(aup, drv, dev, "hard stop\n");
369
370 reg = readl(&aup->mac->control);
371 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
372 writel(reg, &aup->mac->control);
373 wmb(); /* drain writebuffer */
374 mdelay(10);
375}
376
377static void au1000_enable_rx_tx(struct net_device *dev)
378{
379 struct au1000_private *aup = netdev_priv(dev);
380 u32 reg;
381
382 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
383
384 reg = readl(&aup->mac->control);
385 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
386 writel(reg, &aup->mac->control);
387 wmb(); /* drain writebuffer */
388 mdelay(10);
389}
390
391static void
392au1000_adjust_link(struct net_device *dev)
393{
394 struct au1000_private *aup = netdev_priv(dev);
395 struct phy_device *phydev = dev->phydev;
396 unsigned long flags;
397 u32 reg;
398
399 int status_change = 0;
400
401 BUG_ON(!phydev);
402
403 spin_lock_irqsave(&aup->lock, flags);
404
405 if (phydev->link && (aup->old_speed != phydev->speed)) {
406 /* speed changed */
407
408 switch (phydev->speed) {
409 case SPEED_10:
410 case SPEED_100:
411 break;
412 default:
413 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
414 phydev->speed);
415 break;
416 }
417
418 aup->old_speed = phydev->speed;
419
420 status_change = 1;
421 }
422
423 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
424 /* duplex mode changed */
425
426 /* switching duplex mode requires to disable rx and tx! */
427 au1000_hard_stop(dev);
428
429 reg = readl(&aup->mac->control);
430 if (DUPLEX_FULL == phydev->duplex) {
431 reg |= MAC_FULL_DUPLEX;
432 reg &= ~MAC_DISABLE_RX_OWN;
433 } else {
434 reg &= ~MAC_FULL_DUPLEX;
435 reg |= MAC_DISABLE_RX_OWN;
436 }
437 writel(reg, &aup->mac->control);
438 wmb(); /* drain writebuffer */
439 mdelay(1);
440
441 au1000_enable_rx_tx(dev);
442 aup->old_duplex = phydev->duplex;
443
444 status_change = 1;
445 }
446
447 if (phydev->link != aup->old_link) {
448 /* link state changed */
449
450 if (!phydev->link) {
451 /* link went down */
452 aup->old_speed = 0;
453 aup->old_duplex = -1;
454 }
455
456 aup->old_link = phydev->link;
457 status_change = 1;
458 }
459
460 spin_unlock_irqrestore(&aup->lock, flags);
461
462 if (status_change) {
463 if (phydev->link)
464 netdev_info(dev, "link up (%d/%s)\n",
465 phydev->speed,
466 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
467 else
468 netdev_info(dev, "link down\n");
469 }
470}
471
472static int au1000_mii_probe(struct net_device *dev)
473{
474 struct au1000_private *const aup = netdev_priv(dev);
475 struct phy_device *phydev = NULL;
476 int phy_addr;
477
478 if (aup->phy_static_config) {
479 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
480
481 if (aup->phy_addr)
482 phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
483 else
484 netdev_info(dev, "using PHY-less setup\n");
485 return 0;
486 }
487
488 /* find the first (lowest address) PHY
489 * on the current MAC's MII bus
490 */
491 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
492 if (mdiobus_get_phy(aup->mii_bus, phy_addr)) {
493 phydev = mdiobus_get_phy(aup->mii_bus, phy_addr);
494 if (!aup->phy_search_highest_addr)
495 /* break out with first one found */
496 break;
497 }
498
499 if (aup->phy1_search_mac0) {
500 /* try harder to find a PHY */
501 if (!phydev && (aup->mac_id == 1)) {
502 /* no PHY found, maybe we have a dual PHY? */
503 dev_info(&dev->dev, ": no PHY found on MAC1, "
504 "let's see if it's attached to MAC0...\n");
505
506 /* find the first (lowest address) non-attached
507 * PHY on the MAC0 MII bus
508 */
509 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
510 struct phy_device *const tmp_phydev =
511 mdiobus_get_phy(aup->mii_bus,
512 phy_addr);
513
514 if (aup->mac_id == 1)
515 break;
516
517 /* no PHY here... */
518 if (!tmp_phydev)
519 continue;
520
521 /* already claimed by MAC0 */
522 if (tmp_phydev->attached_dev)
523 continue;
524
525 phydev = tmp_phydev;
526 break; /* found it */
527 }
528 }
529 }
530
531 if (!phydev) {
532 netdev_err(dev, "no PHY found\n");
533 return -1;
534 }
535
536 /* now we are supposed to have a proper phydev, to attach to... */
537 BUG_ON(phydev->attached_dev);
538
539 phydev = phy_connect(dev, phydev_name(phydev),
540 &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
541
542 if (IS_ERR(phydev)) {
543 netdev_err(dev, "Could not attach to PHY\n");
544 return PTR_ERR(phydev);
545 }
546
547 phy_set_max_speed(phydev, SPEED_100);
548
549 aup->old_link = 0;
550 aup->old_speed = 0;
551 aup->old_duplex = -1;
552
553 phy_attached_info(phydev);
554
555 return 0;
556}
557
558/*
559 * Buffer allocation/deallocation routines. The buffer descriptor returned
560 * has the virtual and dma address of a buffer suitable for
561 * both, receive and transmit operations.
562 */
563static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
564{
565 struct db_dest *pDB;
566 pDB = aup->pDBfree;
567
568 if (pDB)
569 aup->pDBfree = pDB->pnext;
570
571 return pDB;
572}
573
574void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
575{
576 struct db_dest *pDBfree = aup->pDBfree;
577 if (pDBfree)
578 pDBfree->pnext = pDB;
579 aup->pDBfree = pDB;
580}
581
582static void au1000_reset_mac_unlocked(struct net_device *dev)
583{
584 struct au1000_private *const aup = netdev_priv(dev);
585 int i;
586
587 au1000_hard_stop(dev);
588
589 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
590 wmb(); /* drain writebuffer */
591 mdelay(2);
592 writel(0, aup->enable);
593 wmb(); /* drain writebuffer */
594 mdelay(2);
595
596 aup->tx_full = 0;
597 for (i = 0; i < NUM_RX_DMA; i++) {
598 /* reset control bits */
599 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
600 }
601 for (i = 0; i < NUM_TX_DMA; i++) {
602 /* reset control bits */
603 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
604 }
605
606 aup->mac_enabled = 0;
607
608}
609
610static void au1000_reset_mac(struct net_device *dev)
611{
612 struct au1000_private *const aup = netdev_priv(dev);
613 unsigned long flags;
614
615 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
616 (unsigned)aup);
617
618 spin_lock_irqsave(&aup->lock, flags);
619
620 au1000_reset_mac_unlocked(dev);
621
622 spin_unlock_irqrestore(&aup->lock, flags);
623}
624
625/*
626 * Setup the receive and transmit "rings". These pointers are the addresses
627 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
628 * these are not descriptors sitting in memory.
629 */
630static void
631au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
632{
633 int i;
634
635 for (i = 0; i < NUM_RX_DMA; i++) {
636 aup->rx_dma_ring[i] = (struct rx_dma *)
637 (tx_base + 0x100 + sizeof(struct rx_dma) * i);
638 }
639 for (i = 0; i < NUM_TX_DMA; i++) {
640 aup->tx_dma_ring[i] = (struct tx_dma *)
641 (tx_base + sizeof(struct tx_dma) * i);
642 }
643}
644
645/*
646 * ethtool operations
647 */
648static void
649au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
650{
651 struct au1000_private *aup = netdev_priv(dev);
652
653 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
654 snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
655 aup->mac_id);
656}
657
658static void au1000_set_msglevel(struct net_device *dev, u32 value)
659{
660 struct au1000_private *aup = netdev_priv(dev);
661 aup->msg_enable = value;
662}
663
664static u32 au1000_get_msglevel(struct net_device *dev)
665{
666 struct au1000_private *aup = netdev_priv(dev);
667 return aup->msg_enable;
668}
669
670static const struct ethtool_ops au1000_ethtool_ops = {
671 .get_drvinfo = au1000_get_drvinfo,
672 .get_link = ethtool_op_get_link,
673 .get_msglevel = au1000_get_msglevel,
674 .set_msglevel = au1000_set_msglevel,
675 .get_link_ksettings = phy_ethtool_get_link_ksettings,
676 .set_link_ksettings = phy_ethtool_set_link_ksettings,
677};
678
679/*
680 * Initialize the interface.
681 *
682 * When the device powers up, the clocks are disabled and the
683 * mac is in reset state. When the interface is closed, we
684 * do the same -- reset the device and disable the clocks to
685 * conserve power. Thus, whenever au1000_init() is called,
686 * the device should already be in reset state.
687 */
688static int au1000_init(struct net_device *dev)
689{
690 struct au1000_private *aup = netdev_priv(dev);
691 unsigned long flags;
692 int i;
693 u32 control;
694
695 netif_dbg(aup, hw, dev, "au1000_init\n");
696
697 /* bring the device out of reset */
698 au1000_enable_mac(dev, 1);
699
700 spin_lock_irqsave(&aup->lock, flags);
701
702 writel(0, &aup->mac->control);
703 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
704 aup->tx_tail = aup->tx_head;
705 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
706
707 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
708 &aup->mac->mac_addr_high);
709 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
710 dev->dev_addr[1]<<8 | dev->dev_addr[0],
711 &aup->mac->mac_addr_low);
712
713
714 for (i = 0; i < NUM_RX_DMA; i++)
715 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
716
717 wmb(); /* drain writebuffer */
718
719 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
720#ifndef CONFIG_CPU_LITTLE_ENDIAN
721 control |= MAC_BIG_ENDIAN;
722#endif
723 if (dev->phydev) {
724 if (dev->phydev->link && (DUPLEX_FULL == dev->phydev->duplex))
725 control |= MAC_FULL_DUPLEX;
726 else
727 control |= MAC_DISABLE_RX_OWN;
728 } else { /* PHY-less op, assume full-duplex */
729 control |= MAC_FULL_DUPLEX;
730 }
731
732 writel(control, &aup->mac->control);
733 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
734 wmb(); /* drain writebuffer */
735
736 spin_unlock_irqrestore(&aup->lock, flags);
737 return 0;
738}
739
740static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
741{
742 struct net_device_stats *ps = &dev->stats;
743
744 ps->rx_packets++;
745 if (status & RX_MCAST_FRAME)
746 ps->multicast++;
747
748 if (status & RX_ERROR) {
749 ps->rx_errors++;
750 if (status & RX_MISSED_FRAME)
751 ps->rx_missed_errors++;
752 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
753 ps->rx_length_errors++;
754 if (status & RX_CRC_ERROR)
755 ps->rx_crc_errors++;
756 if (status & RX_COLL)
757 ps->collisions++;
758 } else
759 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
760
761}
762
763/*
764 * Au1000 receive routine.
765 */
766static int au1000_rx(struct net_device *dev)
767{
768 struct au1000_private *aup = netdev_priv(dev);
769 struct sk_buff *skb;
770 struct rx_dma *prxd;
771 u32 buff_stat, status;
772 struct db_dest *pDB;
773 u32 frmlen;
774
775 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
776
777 prxd = aup->rx_dma_ring[aup->rx_head];
778 buff_stat = prxd->buff_stat;
779 while (buff_stat & RX_T_DONE) {
780 status = prxd->status;
781 pDB = aup->rx_db_inuse[aup->rx_head];
782 au1000_update_rx_stats(dev, status);
783 if (!(status & RX_ERROR)) {
784
785 /* good frame */
786 frmlen = (status & RX_FRAME_LEN_MASK);
787 frmlen -= 4; /* Remove FCS */
788 skb = netdev_alloc_skb(dev, frmlen + 2);
789 if (!skb) {
790 dev->stats.rx_dropped++;
791 continue;
792 }
793 skb_reserve(skb, 2); /* 16 byte IP header align */
794 skb_copy_to_linear_data(skb,
795 (unsigned char *)pDB->vaddr, frmlen);
796 skb_put(skb, frmlen);
797 skb->protocol = eth_type_trans(skb, dev);
798 netif_rx(skb); /* pass the packet to upper layers */
799 } else {
800 if (au1000_debug > 4) {
801 pr_err("rx_error(s):");
802 if (status & RX_MISSED_FRAME)
803 pr_cont(" miss");
804 if (status & RX_WDOG_TIMER)
805 pr_cont(" wdog");
806 if (status & RX_RUNT)
807 pr_cont(" runt");
808 if (status & RX_OVERLEN)
809 pr_cont(" overlen");
810 if (status & RX_COLL)
811 pr_cont(" coll");
812 if (status & RX_MII_ERROR)
813 pr_cont(" mii error");
814 if (status & RX_CRC_ERROR)
815 pr_cont(" crc error");
816 if (status & RX_LEN_ERROR)
817 pr_cont(" len error");
818 if (status & RX_U_CNTRL_FRAME)
819 pr_cont(" u control frame");
820 pr_cont("\n");
821 }
822 }
823 prxd->buff_stat = lower_32_bits(pDB->dma_addr) | RX_DMA_ENABLE;
824 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
825 wmb(); /* drain writebuffer */
826
827 /* next descriptor */
828 prxd = aup->rx_dma_ring[aup->rx_head];
829 buff_stat = prxd->buff_stat;
830 }
831 return 0;
832}
833
834static void au1000_update_tx_stats(struct net_device *dev, u32 status)
835{
836 struct net_device_stats *ps = &dev->stats;
837
838 if (status & TX_FRAME_ABORTED) {
839 if (!dev->phydev || (DUPLEX_FULL == dev->phydev->duplex)) {
840 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
841 /* any other tx errors are only valid
842 * in half duplex mode
843 */
844 ps->tx_errors++;
845 ps->tx_aborted_errors++;
846 }
847 } else {
848 ps->tx_errors++;
849 ps->tx_aborted_errors++;
850 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
851 ps->tx_carrier_errors++;
852 }
853 }
854}
855
856/*
857 * Called from the interrupt service routine to acknowledge
858 * the TX DONE bits. This is a must if the irq is setup as
859 * edge triggered.
860 */
861static void au1000_tx_ack(struct net_device *dev)
862{
863 struct au1000_private *aup = netdev_priv(dev);
864 struct tx_dma *ptxd;
865
866 ptxd = aup->tx_dma_ring[aup->tx_tail];
867
868 while (ptxd->buff_stat & TX_T_DONE) {
869 au1000_update_tx_stats(dev, ptxd->status);
870 ptxd->buff_stat &= ~TX_T_DONE;
871 ptxd->len = 0;
872 wmb(); /* drain writebuffer */
873
874 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
875 ptxd = aup->tx_dma_ring[aup->tx_tail];
876
877 if (aup->tx_full) {
878 aup->tx_full = 0;
879 netif_wake_queue(dev);
880 }
881 }
882}
883
884/*
885 * Au1000 interrupt service routine.
886 */
887static irqreturn_t au1000_interrupt(int irq, void *dev_id)
888{
889 struct net_device *dev = dev_id;
890
891 /* Handle RX interrupts first to minimize chance of overrun */
892
893 au1000_rx(dev);
894 au1000_tx_ack(dev);
895 return IRQ_RETVAL(1);
896}
897
898static int au1000_open(struct net_device *dev)
899{
900 int retval;
901 struct au1000_private *aup = netdev_priv(dev);
902
903 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
904
905 retval = request_irq(dev->irq, au1000_interrupt, 0,
906 dev->name, dev);
907 if (retval) {
908 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
909 return retval;
910 }
911
912 retval = au1000_init(dev);
913 if (retval) {
914 netdev_err(dev, "error in au1000_init\n");
915 free_irq(dev->irq, dev);
916 return retval;
917 }
918
919 if (dev->phydev)
920 phy_start(dev->phydev);
921
922 netif_start_queue(dev);
923
924 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
925
926 return 0;
927}
928
929static int au1000_close(struct net_device *dev)
930{
931 unsigned long flags;
932 struct au1000_private *const aup = netdev_priv(dev);
933
934 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
935
936 if (dev->phydev)
937 phy_stop(dev->phydev);
938
939 spin_lock_irqsave(&aup->lock, flags);
940
941 au1000_reset_mac_unlocked(dev);
942
943 /* stop the device */
944 netif_stop_queue(dev);
945
946 /* disable the interrupt */
947 free_irq(dev->irq, dev);
948 spin_unlock_irqrestore(&aup->lock, flags);
949
950 return 0;
951}
952
953/*
954 * Au1000 transmit routine.
955 */
956static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
957{
958 struct au1000_private *aup = netdev_priv(dev);
959 struct net_device_stats *ps = &dev->stats;
960 struct tx_dma *ptxd;
961 u32 buff_stat;
962 struct db_dest *pDB;
963 int i;
964
965 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
966 (unsigned)aup, skb->len,
967 skb->data, aup->tx_head);
968
969 ptxd = aup->tx_dma_ring[aup->tx_head];
970 buff_stat = ptxd->buff_stat;
971 if (buff_stat & TX_DMA_ENABLE) {
972 /* We've wrapped around and the transmitter is still busy */
973 netif_stop_queue(dev);
974 aup->tx_full = 1;
975 return NETDEV_TX_BUSY;
976 } else if (buff_stat & TX_T_DONE) {
977 au1000_update_tx_stats(dev, ptxd->status);
978 ptxd->len = 0;
979 }
980
981 if (aup->tx_full) {
982 aup->tx_full = 0;
983 netif_wake_queue(dev);
984 }
985
986 pDB = aup->tx_db_inuse[aup->tx_head];
987 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
988 if (skb->len < ETH_ZLEN) {
989 for (i = skb->len; i < ETH_ZLEN; i++)
990 ((char *)pDB->vaddr)[i] = 0;
991
992 ptxd->len = ETH_ZLEN;
993 } else
994 ptxd->len = skb->len;
995
996 ps->tx_packets++;
997 ps->tx_bytes += ptxd->len;
998
999 ptxd->buff_stat = lower_32_bits(pDB->dma_addr) | TX_DMA_ENABLE;
1000 wmb(); /* drain writebuffer */
1001 dev_kfree_skb(skb);
1002 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1003 return NETDEV_TX_OK;
1004}
1005
1006/*
1007 * The Tx ring has been full longer than the watchdog timeout
1008 * value. The transmitter must be hung?
1009 */
1010static void au1000_tx_timeout(struct net_device *dev, unsigned int txqueue)
1011{
1012 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
1013 au1000_reset_mac(dev);
1014 au1000_init(dev);
1015 netif_trans_update(dev); /* prevent tx timeout */
1016 netif_wake_queue(dev);
1017}
1018
1019static void au1000_multicast_list(struct net_device *dev)
1020{
1021 struct au1000_private *aup = netdev_priv(dev);
1022 u32 reg;
1023
1024 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
1025 reg = readl(&aup->mac->control);
1026 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1027 reg |= MAC_PROMISCUOUS;
1028 } else if ((dev->flags & IFF_ALLMULTI) ||
1029 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1030 reg |= MAC_PASS_ALL_MULTI;
1031 reg &= ~MAC_PROMISCUOUS;
1032 netdev_info(dev, "Pass all multicast\n");
1033 } else {
1034 struct netdev_hw_addr *ha;
1035 u32 mc_filter[2]; /* Multicast hash filter */
1036
1037 mc_filter[1] = mc_filter[0] = 0;
1038 netdev_for_each_mc_addr(ha, dev)
1039 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1040 (long *)mc_filter);
1041 writel(mc_filter[1], &aup->mac->multi_hash_high);
1042 writel(mc_filter[0], &aup->mac->multi_hash_low);
1043 reg &= ~MAC_PROMISCUOUS;
1044 reg |= MAC_HASH_MODE;
1045 }
1046 writel(reg, &aup->mac->control);
1047}
1048
1049static const struct net_device_ops au1000_netdev_ops = {
1050 .ndo_open = au1000_open,
1051 .ndo_stop = au1000_close,
1052 .ndo_start_xmit = au1000_tx,
1053 .ndo_set_rx_mode = au1000_multicast_list,
1054 .ndo_eth_ioctl = phy_do_ioctl_running,
1055 .ndo_tx_timeout = au1000_tx_timeout,
1056 .ndo_set_mac_address = eth_mac_addr,
1057 .ndo_validate_addr = eth_validate_addr,
1058};
1059
1060static int au1000_probe(struct platform_device *pdev)
1061{
1062 struct au1000_private *aup = NULL;
1063 struct au1000_eth_platform_data *pd;
1064 struct net_device *dev = NULL;
1065 struct db_dest *pDB, *pDBfree;
1066 int irq, i, err = 0;
1067 struct resource *base, *macen, *macdma;
1068
1069 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1070 if (!base) {
1071 dev_err(&pdev->dev, "failed to retrieve base register\n");
1072 err = -ENODEV;
1073 goto out;
1074 }
1075
1076 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1077 if (!macen) {
1078 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1079 err = -ENODEV;
1080 goto out;
1081 }
1082
1083 irq = platform_get_irq(pdev, 0);
1084 if (irq < 0) {
1085 err = -ENODEV;
1086 goto out;
1087 }
1088
1089 macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1090 if (!macdma) {
1091 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1092 err = -ENODEV;
1093 goto out;
1094 }
1095
1096 if (!request_mem_region(base->start, resource_size(base),
1097 pdev->name)) {
1098 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1099 err = -ENXIO;
1100 goto out;
1101 }
1102
1103 if (!request_mem_region(macen->start, resource_size(macen),
1104 pdev->name)) {
1105 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1106 err = -ENXIO;
1107 goto err_request;
1108 }
1109
1110 if (!request_mem_region(macdma->start, resource_size(macdma),
1111 pdev->name)) {
1112 dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1113 err = -ENXIO;
1114 goto err_macdma;
1115 }
1116
1117 dev = alloc_etherdev(sizeof(struct au1000_private));
1118 if (!dev) {
1119 err = -ENOMEM;
1120 goto err_alloc;
1121 }
1122
1123 SET_NETDEV_DEV(dev, &pdev->dev);
1124 platform_set_drvdata(pdev, dev);
1125 aup = netdev_priv(dev);
1126
1127 spin_lock_init(&aup->lock);
1128 aup->msg_enable = (au1000_debug < 4 ?
1129 AU1000_DEF_MSG_ENABLE : au1000_debug);
1130
1131 /* Allocate the data buffers
1132 * Snooping works fine with eth on all au1xxx
1133 */
1134 aup->vaddr = dma_alloc_coherent(&pdev->dev, MAX_BUF_SIZE *
1135 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1136 &aup->dma_addr, 0);
1137 if (!aup->vaddr) {
1138 dev_err(&pdev->dev, "failed to allocate data buffers\n");
1139 err = -ENOMEM;
1140 goto err_vaddr;
1141 }
1142
1143 /* aup->mac is the base address of the MAC's registers */
1144 aup->mac = (struct mac_reg *)
1145 ioremap(base->start, resource_size(base));
1146 if (!aup->mac) {
1147 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1148 err = -ENXIO;
1149 goto err_remap1;
1150 }
1151
1152 /* Setup some variables for quick register address access */
1153 aup->enable = (u32 *)ioremap(macen->start,
1154 resource_size(macen));
1155 if (!aup->enable) {
1156 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1157 err = -ENXIO;
1158 goto err_remap2;
1159 }
1160 aup->mac_id = pdev->id;
1161
1162 aup->macdma = ioremap(macdma->start, resource_size(macdma));
1163 if (!aup->macdma) {
1164 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1165 err = -ENXIO;
1166 goto err_remap3;
1167 }
1168
1169 au1000_setup_hw_rings(aup, aup->macdma);
1170
1171 writel(0, aup->enable);
1172 aup->mac_enabled = 0;
1173
1174 pd = dev_get_platdata(&pdev->dev);
1175 if (!pd) {
1176 dev_info(&pdev->dev, "no platform_data passed,"
1177 " PHY search on MAC0\n");
1178 aup->phy1_search_mac0 = 1;
1179 } else {
1180 if (is_valid_ether_addr(pd->mac)) {
1181 eth_hw_addr_set(dev, pd->mac);
1182 } else {
1183 /* Set a random MAC since no valid provided by platform_data. */
1184 eth_hw_addr_random(dev);
1185 }
1186
1187 aup->phy_static_config = pd->phy_static_config;
1188 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1189 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1190 aup->phy_addr = pd->phy_addr;
1191 aup->phy_busid = pd->phy_busid;
1192 aup->phy_irq = pd->phy_irq;
1193 }
1194
1195 if (aup->phy_busid > 0) {
1196 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1197 err = -ENODEV;
1198 goto err_mdiobus_alloc;
1199 }
1200
1201 aup->mii_bus = mdiobus_alloc();
1202 if (!aup->mii_bus) {
1203 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1204 err = -ENOMEM;
1205 goto err_mdiobus_alloc;
1206 }
1207
1208 aup->mii_bus->priv = dev;
1209 aup->mii_bus->read = au1000_mdiobus_read;
1210 aup->mii_bus->write = au1000_mdiobus_write;
1211 aup->mii_bus->reset = au1000_mdiobus_reset;
1212 aup->mii_bus->name = "au1000_eth_mii";
1213 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1214 pdev->name, aup->mac_id);
1215
1216 /* if known, set corresponding PHY IRQs */
1217 if (aup->phy_static_config)
1218 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1219 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1220
1221 err = mdiobus_register(aup->mii_bus);
1222 if (err) {
1223 dev_err(&pdev->dev, "failed to register MDIO bus\n");
1224 goto err_mdiobus_reg;
1225 }
1226
1227 err = au1000_mii_probe(dev);
1228 if (err != 0)
1229 goto err_out;
1230
1231 pDBfree = NULL;
1232 /* setup the data buffer descriptors and attach a buffer to each one */
1233 pDB = aup->db;
1234 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1235 pDB->pnext = pDBfree;
1236 pDBfree = pDB;
1237 pDB->vaddr = aup->vaddr + MAX_BUF_SIZE * i;
1238 pDB->dma_addr = aup->dma_addr + MAX_BUF_SIZE * i;
1239 pDB++;
1240 }
1241 aup->pDBfree = pDBfree;
1242
1243 err = -ENODEV;
1244 for (i = 0; i < NUM_RX_DMA; i++) {
1245 pDB = au1000_GetFreeDB(aup);
1246 if (!pDB)
1247 goto err_out;
1248
1249 aup->rx_dma_ring[i]->buff_stat = lower_32_bits(pDB->dma_addr);
1250 aup->rx_db_inuse[i] = pDB;
1251 }
1252
1253 for (i = 0; i < NUM_TX_DMA; i++) {
1254 pDB = au1000_GetFreeDB(aup);
1255 if (!pDB)
1256 goto err_out;
1257
1258 aup->tx_dma_ring[i]->buff_stat = lower_32_bits(pDB->dma_addr);
1259 aup->tx_dma_ring[i]->len = 0;
1260 aup->tx_db_inuse[i] = pDB;
1261 }
1262
1263 dev->base_addr = base->start;
1264 dev->irq = irq;
1265 dev->netdev_ops = &au1000_netdev_ops;
1266 dev->ethtool_ops = &au1000_ethtool_ops;
1267 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1268
1269 /*
1270 * The boot code uses the ethernet controller, so reset it to start
1271 * fresh. au1000_init() expects that the device is in reset state.
1272 */
1273 au1000_reset_mac(dev);
1274
1275 err = register_netdev(dev);
1276 if (err) {
1277 netdev_err(dev, "Cannot register net device, aborting.\n");
1278 goto err_out;
1279 }
1280
1281 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1282 (unsigned long)base->start, irq);
1283
1284 return 0;
1285
1286err_out:
1287 if (aup->mii_bus)
1288 mdiobus_unregister(aup->mii_bus);
1289
1290 /* here we should have a valid dev plus aup-> register addresses
1291 * so we can reset the mac properly.
1292 */
1293 au1000_reset_mac(dev);
1294
1295 for (i = 0; i < NUM_RX_DMA; i++) {
1296 if (aup->rx_db_inuse[i])
1297 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1298 }
1299 for (i = 0; i < NUM_TX_DMA; i++) {
1300 if (aup->tx_db_inuse[i])
1301 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1302 }
1303err_mdiobus_reg:
1304 mdiobus_free(aup->mii_bus);
1305err_mdiobus_alloc:
1306 iounmap(aup->macdma);
1307err_remap3:
1308 iounmap(aup->enable);
1309err_remap2:
1310 iounmap(aup->mac);
1311err_remap1:
1312 dma_free_coherent(&pdev->dev, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1313 aup->vaddr, aup->dma_addr);
1314err_vaddr:
1315 free_netdev(dev);
1316err_alloc:
1317 release_mem_region(macdma->start, resource_size(macdma));
1318err_macdma:
1319 release_mem_region(macen->start, resource_size(macen));
1320err_request:
1321 release_mem_region(base->start, resource_size(base));
1322out:
1323 return err;
1324}
1325
1326static void au1000_remove(struct platform_device *pdev)
1327{
1328 struct net_device *dev = platform_get_drvdata(pdev);
1329 struct au1000_private *aup = netdev_priv(dev);
1330 int i;
1331 struct resource *base, *macen;
1332
1333 unregister_netdev(dev);
1334 mdiobus_unregister(aup->mii_bus);
1335 mdiobus_free(aup->mii_bus);
1336
1337 for (i = 0; i < NUM_RX_DMA; i++)
1338 if (aup->rx_db_inuse[i])
1339 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1340
1341 for (i = 0; i < NUM_TX_DMA; i++)
1342 if (aup->tx_db_inuse[i])
1343 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1344
1345 dma_free_coherent(&pdev->dev, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1346 aup->vaddr, aup->dma_addr);
1347
1348 iounmap(aup->macdma);
1349 iounmap(aup->mac);
1350 iounmap(aup->enable);
1351
1352 base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1353 release_mem_region(base->start, resource_size(base));
1354
1355 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356 release_mem_region(base->start, resource_size(base));
1357
1358 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1359 release_mem_region(macen->start, resource_size(macen));
1360
1361 free_netdev(dev);
1362}
1363
1364static struct platform_driver au1000_eth_driver = {
1365 .probe = au1000_probe,
1366 .remove_new = au1000_remove,
1367 .driver = {
1368 .name = "au1000-eth",
1369 },
1370};
1371
1372module_platform_driver(au1000_eth_driver);
1373
1374MODULE_ALIAS("platform:au1000-eth");
1/*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, see <http://www.gnu.org/licenses/>.
31 *
32 * ########################################################################
33 *
34 *
35 */
36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38#include <linux/capability.h>
39#include <linux/dma-mapping.h>
40#include <linux/module.h>
41#include <linux/kernel.h>
42#include <linux/string.h>
43#include <linux/timer.h>
44#include <linux/errno.h>
45#include <linux/in.h>
46#include <linux/ioport.h>
47#include <linux/bitops.h>
48#include <linux/slab.h>
49#include <linux/interrupt.h>
50#include <linux/netdevice.h>
51#include <linux/etherdevice.h>
52#include <linux/ethtool.h>
53#include <linux/mii.h>
54#include <linux/skbuff.h>
55#include <linux/delay.h>
56#include <linux/crc32.h>
57#include <linux/phy.h>
58#include <linux/platform_device.h>
59#include <linux/cpu.h>
60#include <linux/io.h>
61
62#include <asm/mipsregs.h>
63#include <asm/irq.h>
64#include <asm/processor.h>
65
66#include <au1000.h>
67#include <au1xxx_eth.h>
68#include <prom.h>
69
70#include "au1000_eth.h"
71
72#ifdef AU1000_ETH_DEBUG
73static int au1000_debug = 5;
74#else
75static int au1000_debug = 3;
76#endif
77
78#define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK)
81
82#define DRV_NAME "au1000_eth"
83#define DRV_VERSION "1.7"
84#define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
85#define DRV_DESC "Au1xxx on-chip Ethernet driver"
86
87MODULE_AUTHOR(DRV_AUTHOR);
88MODULE_DESCRIPTION(DRV_DESC);
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/* AU1000 MAC registers and bits */
93#define MAC_CONTROL 0x0
94# define MAC_RX_ENABLE (1 << 2)
95# define MAC_TX_ENABLE (1 << 3)
96# define MAC_DEF_CHECK (1 << 5)
97# define MAC_SET_BL(X) (((X) & 0x3) << 6)
98# define MAC_AUTO_PAD (1 << 8)
99# define MAC_DISABLE_RETRY (1 << 10)
100# define MAC_DISABLE_BCAST (1 << 11)
101# define MAC_LATE_COL (1 << 12)
102# define MAC_HASH_MODE (1 << 13)
103# define MAC_HASH_ONLY (1 << 15)
104# define MAC_PASS_ALL (1 << 16)
105# define MAC_INVERSE_FILTER (1 << 17)
106# define MAC_PROMISCUOUS (1 << 18)
107# define MAC_PASS_ALL_MULTI (1 << 19)
108# define MAC_FULL_DUPLEX (1 << 20)
109# define MAC_NORMAL_MODE 0
110# define MAC_INT_LOOPBACK (1 << 21)
111# define MAC_EXT_LOOPBACK (1 << 22)
112# define MAC_DISABLE_RX_OWN (1 << 23)
113# define MAC_BIG_ENDIAN (1 << 30)
114# define MAC_RX_ALL (1 << 31)
115#define MAC_ADDRESS_HIGH 0x4
116#define MAC_ADDRESS_LOW 0x8
117#define MAC_MCAST_HIGH 0xC
118#define MAC_MCAST_LOW 0x10
119#define MAC_MII_CNTRL 0x14
120# define MAC_MII_BUSY (1 << 0)
121# define MAC_MII_READ 0
122# define MAC_MII_WRITE (1 << 1)
123# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
124# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
125#define MAC_MII_DATA 0x18
126#define MAC_FLOW_CNTRL 0x1C
127# define MAC_FLOW_CNTRL_BUSY (1 << 0)
128# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
129# define MAC_PASS_CONTROL (1 << 2)
130# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
131#define MAC_VLAN1_TAG 0x20
132#define MAC_VLAN2_TAG 0x24
133
134/* Ethernet Controller Enable */
135# define MAC_EN_CLOCK_ENABLE (1 << 0)
136# define MAC_EN_RESET0 (1 << 1)
137# define MAC_EN_TOSS (0 << 2)
138# define MAC_EN_CACHEABLE (1 << 3)
139# define MAC_EN_RESET1 (1 << 4)
140# define MAC_EN_RESET2 (1 << 5)
141# define MAC_DMA_RESET (1 << 6)
142
143/* Ethernet Controller DMA Channels */
144/* offsets from MAC_TX_RING_ADDR address */
145#define MAC_TX_BUFF0_STATUS 0x0
146# define TX_FRAME_ABORTED (1 << 0)
147# define TX_JAB_TIMEOUT (1 << 1)
148# define TX_NO_CARRIER (1 << 2)
149# define TX_LOSS_CARRIER (1 << 3)
150# define TX_EXC_DEF (1 << 4)
151# define TX_LATE_COLL_ABORT (1 << 5)
152# define TX_EXC_COLL (1 << 6)
153# define TX_UNDERRUN (1 << 7)
154# define TX_DEFERRED (1 << 8)
155# define TX_LATE_COLL (1 << 9)
156# define TX_COLL_CNT_MASK (0xF << 10)
157# define TX_PKT_RETRY (1 << 31)
158#define MAC_TX_BUFF0_ADDR 0x4
159# define TX_DMA_ENABLE (1 << 0)
160# define TX_T_DONE (1 << 1)
161# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
162#define MAC_TX_BUFF0_LEN 0x8
163#define MAC_TX_BUFF1_STATUS 0x10
164#define MAC_TX_BUFF1_ADDR 0x14
165#define MAC_TX_BUFF1_LEN 0x18
166#define MAC_TX_BUFF2_STATUS 0x20
167#define MAC_TX_BUFF2_ADDR 0x24
168#define MAC_TX_BUFF2_LEN 0x28
169#define MAC_TX_BUFF3_STATUS 0x30
170#define MAC_TX_BUFF3_ADDR 0x34
171#define MAC_TX_BUFF3_LEN 0x38
172
173/* offsets from MAC_RX_RING_ADDR */
174#define MAC_RX_BUFF0_STATUS 0x0
175# define RX_FRAME_LEN_MASK 0x3fff
176# define RX_WDOG_TIMER (1 << 14)
177# define RX_RUNT (1 << 15)
178# define RX_OVERLEN (1 << 16)
179# define RX_COLL (1 << 17)
180# define RX_ETHER (1 << 18)
181# define RX_MII_ERROR (1 << 19)
182# define RX_DRIBBLING (1 << 20)
183# define RX_CRC_ERROR (1 << 21)
184# define RX_VLAN1 (1 << 22)
185# define RX_VLAN2 (1 << 23)
186# define RX_LEN_ERROR (1 << 24)
187# define RX_CNTRL_FRAME (1 << 25)
188# define RX_U_CNTRL_FRAME (1 << 26)
189# define RX_MCAST_FRAME (1 << 27)
190# define RX_BCAST_FRAME (1 << 28)
191# define RX_FILTER_FAIL (1 << 29)
192# define RX_PACKET_FILTER (1 << 30)
193# define RX_MISSED_FRAME (1 << 31)
194
195# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
196 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
197 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
198#define MAC_RX_BUFF0_ADDR 0x4
199# define RX_DMA_ENABLE (1 << 0)
200# define RX_T_DONE (1 << 1)
201# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
202# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
203#define MAC_RX_BUFF1_STATUS 0x10
204#define MAC_RX_BUFF1_ADDR 0x14
205#define MAC_RX_BUFF2_STATUS 0x20
206#define MAC_RX_BUFF2_ADDR 0x24
207#define MAC_RX_BUFF3_STATUS 0x30
208#define MAC_RX_BUFF3_ADDR 0x34
209
210/*
211 * Theory of operation
212 *
213 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
214 * There are four receive and four transmit descriptors. These
215 * descriptors are not in memory; rather, they are just a set of
216 * hardware registers.
217 *
218 * Since the Au1000 has a coherent data cache, the receive and
219 * transmit buffers are allocated from the KSEG0 segment. The
220 * hardware registers, however, are still mapped at KSEG1 to
221 * make sure there's no out-of-order writes, and that all writes
222 * complete immediately.
223 */
224
225/*
226 * board-specific configurations
227 *
228 * PHY detection algorithm
229 *
230 * If phy_static_config is undefined, the PHY setup is
231 * autodetected:
232 *
233 * mii_probe() first searches the current MAC's MII bus for a PHY,
234 * selecting the first (or last, if phy_search_highest_addr is
235 * defined) PHY address not already claimed by another netdev.
236 *
237 * If nothing was found that way when searching for the 2nd ethernet
238 * controller's PHY and phy1_search_mac0 is defined, then
239 * the first MII bus is searched as well for an unclaimed PHY; this is
240 * needed in case of a dual-PHY accessible only through the MAC0's MII
241 * bus.
242 *
243 * Finally, if no PHY is found, then the corresponding ethernet
244 * controller is not registered to the network subsystem.
245 */
246
247/* autodetection defaults: phy1_search_mac0 */
248
249/* static PHY setup
250 *
251 * most boards PHY setup should be detectable properly with the
252 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
253 * you have a switch attached, or want to use the PHY's interrupt
254 * notification capabilities) you can provide a static PHY
255 * configuration here
256 *
257 * IRQs may only be set, if a PHY address was configured
258 * If a PHY address is given, also a bus id is required to be set
259 *
260 * ps: make sure the used irqs are configured properly in the board
261 * specific irq-map
262 */
263
264static void au1000_enable_mac(struct net_device *dev, int force_reset)
265{
266 unsigned long flags;
267 struct au1000_private *aup = netdev_priv(dev);
268
269 spin_lock_irqsave(&aup->lock, flags);
270
271 if (force_reset || (!aup->mac_enabled)) {
272 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
273 wmb(); /* drain writebuffer */
274 mdelay(2);
275 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
276 | MAC_EN_CLOCK_ENABLE), aup->enable);
277 wmb(); /* drain writebuffer */
278 mdelay(2);
279
280 aup->mac_enabled = 1;
281 }
282
283 spin_unlock_irqrestore(&aup->lock, flags);
284}
285
286/*
287 * MII operations
288 */
289static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
290{
291 struct au1000_private *aup = netdev_priv(dev);
292 u32 *const mii_control_reg = &aup->mac->mii_control;
293 u32 *const mii_data_reg = &aup->mac->mii_data;
294 u32 timedout = 20;
295 u32 mii_control;
296
297 while (readl(mii_control_reg) & MAC_MII_BUSY) {
298 mdelay(1);
299 if (--timedout == 0) {
300 netdev_err(dev, "read_MII busy timeout!!\n");
301 return -1;
302 }
303 }
304
305 mii_control = MAC_SET_MII_SELECT_REG(reg) |
306 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
307
308 writel(mii_control, mii_control_reg);
309
310 timedout = 20;
311 while (readl(mii_control_reg) & MAC_MII_BUSY) {
312 mdelay(1);
313 if (--timedout == 0) {
314 netdev_err(dev, "mdio_read busy timeout!!\n");
315 return -1;
316 }
317 }
318 return readl(mii_data_reg);
319}
320
321static void au1000_mdio_write(struct net_device *dev, int phy_addr,
322 int reg, u16 value)
323{
324 struct au1000_private *aup = netdev_priv(dev);
325 u32 *const mii_control_reg = &aup->mac->mii_control;
326 u32 *const mii_data_reg = &aup->mac->mii_data;
327 u32 timedout = 20;
328 u32 mii_control;
329
330 while (readl(mii_control_reg) & MAC_MII_BUSY) {
331 mdelay(1);
332 if (--timedout == 0) {
333 netdev_err(dev, "mdio_write busy timeout!!\n");
334 return;
335 }
336 }
337
338 mii_control = MAC_SET_MII_SELECT_REG(reg) |
339 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
340
341 writel(value, mii_data_reg);
342 writel(mii_control, mii_control_reg);
343}
344
345static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
346{
347 struct net_device *const dev = bus->priv;
348
349 /* make sure the MAC associated with this
350 * mii_bus is enabled
351 */
352 au1000_enable_mac(dev, 0);
353
354 return au1000_mdio_read(dev, phy_addr, regnum);
355}
356
357static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
358 u16 value)
359{
360 struct net_device *const dev = bus->priv;
361
362 /* make sure the MAC associated with this
363 * mii_bus is enabled
364 */
365 au1000_enable_mac(dev, 0);
366
367 au1000_mdio_write(dev, phy_addr, regnum, value);
368 return 0;
369}
370
371static int au1000_mdiobus_reset(struct mii_bus *bus)
372{
373 struct net_device *const dev = bus->priv;
374
375 /* make sure the MAC associated with this
376 * mii_bus is enabled
377 */
378 au1000_enable_mac(dev, 0);
379
380 return 0;
381}
382
383static void au1000_hard_stop(struct net_device *dev)
384{
385 struct au1000_private *aup = netdev_priv(dev);
386 u32 reg;
387
388 netif_dbg(aup, drv, dev, "hard stop\n");
389
390 reg = readl(&aup->mac->control);
391 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
392 writel(reg, &aup->mac->control);
393 wmb(); /* drain writebuffer */
394 mdelay(10);
395}
396
397static void au1000_enable_rx_tx(struct net_device *dev)
398{
399 struct au1000_private *aup = netdev_priv(dev);
400 u32 reg;
401
402 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
403
404 reg = readl(&aup->mac->control);
405 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
406 writel(reg, &aup->mac->control);
407 wmb(); /* drain writebuffer */
408 mdelay(10);
409}
410
411static void
412au1000_adjust_link(struct net_device *dev)
413{
414 struct au1000_private *aup = netdev_priv(dev);
415 struct phy_device *phydev = aup->phy_dev;
416 unsigned long flags;
417 u32 reg;
418
419 int status_change = 0;
420
421 BUG_ON(!aup->phy_dev);
422
423 spin_lock_irqsave(&aup->lock, flags);
424
425 if (phydev->link && (aup->old_speed != phydev->speed)) {
426 /* speed changed */
427
428 switch (phydev->speed) {
429 case SPEED_10:
430 case SPEED_100:
431 break;
432 default:
433 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
434 phydev->speed);
435 break;
436 }
437
438 aup->old_speed = phydev->speed;
439
440 status_change = 1;
441 }
442
443 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
444 /* duplex mode changed */
445
446 /* switching duplex mode requires to disable rx and tx! */
447 au1000_hard_stop(dev);
448
449 reg = readl(&aup->mac->control);
450 if (DUPLEX_FULL == phydev->duplex) {
451 reg |= MAC_FULL_DUPLEX;
452 reg &= ~MAC_DISABLE_RX_OWN;
453 } else {
454 reg &= ~MAC_FULL_DUPLEX;
455 reg |= MAC_DISABLE_RX_OWN;
456 }
457 writel(reg, &aup->mac->control);
458 wmb(); /* drain writebuffer */
459 mdelay(1);
460
461 au1000_enable_rx_tx(dev);
462 aup->old_duplex = phydev->duplex;
463
464 status_change = 1;
465 }
466
467 if (phydev->link != aup->old_link) {
468 /* link state changed */
469
470 if (!phydev->link) {
471 /* link went down */
472 aup->old_speed = 0;
473 aup->old_duplex = -1;
474 }
475
476 aup->old_link = phydev->link;
477 status_change = 1;
478 }
479
480 spin_unlock_irqrestore(&aup->lock, flags);
481
482 if (status_change) {
483 if (phydev->link)
484 netdev_info(dev, "link up (%d/%s)\n",
485 phydev->speed,
486 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
487 else
488 netdev_info(dev, "link down\n");
489 }
490}
491
492static int au1000_mii_probe(struct net_device *dev)
493{
494 struct au1000_private *const aup = netdev_priv(dev);
495 struct phy_device *phydev = NULL;
496 int phy_addr;
497
498 if (aup->phy_static_config) {
499 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
500
501 if (aup->phy_addr)
502 phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
503 else
504 netdev_info(dev, "using PHY-less setup\n");
505 return 0;
506 }
507
508 /* find the first (lowest address) PHY
509 * on the current MAC's MII bus
510 */
511 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
512 if (mdiobus_get_phy(aup->mii_bus, aup->phy_addr)) {
513 phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
514 if (!aup->phy_search_highest_addr)
515 /* break out with first one found */
516 break;
517 }
518
519 if (aup->phy1_search_mac0) {
520 /* try harder to find a PHY */
521 if (!phydev && (aup->mac_id == 1)) {
522 /* no PHY found, maybe we have a dual PHY? */
523 dev_info(&dev->dev, ": no PHY found on MAC1, "
524 "let's see if it's attached to MAC0...\n");
525
526 /* find the first (lowest address) non-attached
527 * PHY on the MAC0 MII bus
528 */
529 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
530 struct phy_device *const tmp_phydev =
531 mdiobus_get_phy(aup->mii_bus,
532 phy_addr);
533
534 if (aup->mac_id == 1)
535 break;
536
537 /* no PHY here... */
538 if (!tmp_phydev)
539 continue;
540
541 /* already claimed by MAC0 */
542 if (tmp_phydev->attached_dev)
543 continue;
544
545 phydev = tmp_phydev;
546 break; /* found it */
547 }
548 }
549 }
550
551 if (!phydev) {
552 netdev_err(dev, "no PHY found\n");
553 return -1;
554 }
555
556 /* now we are supposed to have a proper phydev, to attach to... */
557 BUG_ON(phydev->attached_dev);
558
559 phydev = phy_connect(dev, phydev_name(phydev),
560 &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
561
562 if (IS_ERR(phydev)) {
563 netdev_err(dev, "Could not attach to PHY\n");
564 return PTR_ERR(phydev);
565 }
566
567 /* mask with MAC supported features */
568 phydev->supported &= (SUPPORTED_10baseT_Half
569 | SUPPORTED_10baseT_Full
570 | SUPPORTED_100baseT_Half
571 | SUPPORTED_100baseT_Full
572 | SUPPORTED_Autoneg
573 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
574 | SUPPORTED_MII
575 | SUPPORTED_TP);
576
577 phydev->advertising = phydev->supported;
578
579 aup->old_link = 0;
580 aup->old_speed = 0;
581 aup->old_duplex = -1;
582 aup->phy_dev = phydev;
583
584 phy_attached_info(phydev);
585
586 return 0;
587}
588
589
590/*
591 * Buffer allocation/deallocation routines. The buffer descriptor returned
592 * has the virtual and dma address of a buffer suitable for
593 * both, receive and transmit operations.
594 */
595static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
596{
597 struct db_dest *pDB;
598 pDB = aup->pDBfree;
599
600 if (pDB)
601 aup->pDBfree = pDB->pnext;
602
603 return pDB;
604}
605
606void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
607{
608 struct db_dest *pDBfree = aup->pDBfree;
609 if (pDBfree)
610 pDBfree->pnext = pDB;
611 aup->pDBfree = pDB;
612}
613
614static void au1000_reset_mac_unlocked(struct net_device *dev)
615{
616 struct au1000_private *const aup = netdev_priv(dev);
617 int i;
618
619 au1000_hard_stop(dev);
620
621 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
622 wmb(); /* drain writebuffer */
623 mdelay(2);
624 writel(0, aup->enable);
625 wmb(); /* drain writebuffer */
626 mdelay(2);
627
628 aup->tx_full = 0;
629 for (i = 0; i < NUM_RX_DMA; i++) {
630 /* reset control bits */
631 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
632 }
633 for (i = 0; i < NUM_TX_DMA; i++) {
634 /* reset control bits */
635 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
636 }
637
638 aup->mac_enabled = 0;
639
640}
641
642static void au1000_reset_mac(struct net_device *dev)
643{
644 struct au1000_private *const aup = netdev_priv(dev);
645 unsigned long flags;
646
647 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
648 (unsigned)aup);
649
650 spin_lock_irqsave(&aup->lock, flags);
651
652 au1000_reset_mac_unlocked(dev);
653
654 spin_unlock_irqrestore(&aup->lock, flags);
655}
656
657/*
658 * Setup the receive and transmit "rings". These pointers are the addresses
659 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
660 * these are not descriptors sitting in memory.
661 */
662static void
663au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
664{
665 int i;
666
667 for (i = 0; i < NUM_RX_DMA; i++) {
668 aup->rx_dma_ring[i] = (struct rx_dma *)
669 (tx_base + 0x100 + sizeof(struct rx_dma) * i);
670 }
671 for (i = 0; i < NUM_TX_DMA; i++) {
672 aup->tx_dma_ring[i] = (struct tx_dma *)
673 (tx_base + sizeof(struct tx_dma) * i);
674 }
675}
676
677/*
678 * ethtool operations
679 */
680
681static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
682{
683 struct au1000_private *aup = netdev_priv(dev);
684
685 if (aup->phy_dev)
686 return phy_ethtool_gset(aup->phy_dev, cmd);
687
688 return -EINVAL;
689}
690
691static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
692{
693 struct au1000_private *aup = netdev_priv(dev);
694
695 if (!capable(CAP_NET_ADMIN))
696 return -EPERM;
697
698 if (aup->phy_dev)
699 return phy_ethtool_sset(aup->phy_dev, cmd);
700
701 return -EINVAL;
702}
703
704static void
705au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
706{
707 struct au1000_private *aup = netdev_priv(dev);
708
709 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
710 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
711 snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
712 aup->mac_id);
713}
714
715static void au1000_set_msglevel(struct net_device *dev, u32 value)
716{
717 struct au1000_private *aup = netdev_priv(dev);
718 aup->msg_enable = value;
719}
720
721static u32 au1000_get_msglevel(struct net_device *dev)
722{
723 struct au1000_private *aup = netdev_priv(dev);
724 return aup->msg_enable;
725}
726
727static const struct ethtool_ops au1000_ethtool_ops = {
728 .get_settings = au1000_get_settings,
729 .set_settings = au1000_set_settings,
730 .get_drvinfo = au1000_get_drvinfo,
731 .get_link = ethtool_op_get_link,
732 .get_msglevel = au1000_get_msglevel,
733 .set_msglevel = au1000_set_msglevel,
734};
735
736
737/*
738 * Initialize the interface.
739 *
740 * When the device powers up, the clocks are disabled and the
741 * mac is in reset state. When the interface is closed, we
742 * do the same -- reset the device and disable the clocks to
743 * conserve power. Thus, whenever au1000_init() is called,
744 * the device should already be in reset state.
745 */
746static int au1000_init(struct net_device *dev)
747{
748 struct au1000_private *aup = netdev_priv(dev);
749 unsigned long flags;
750 int i;
751 u32 control;
752
753 netif_dbg(aup, hw, dev, "au1000_init\n");
754
755 /* bring the device out of reset */
756 au1000_enable_mac(dev, 1);
757
758 spin_lock_irqsave(&aup->lock, flags);
759
760 writel(0, &aup->mac->control);
761 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
762 aup->tx_tail = aup->tx_head;
763 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
764
765 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
766 &aup->mac->mac_addr_high);
767 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
768 dev->dev_addr[1]<<8 | dev->dev_addr[0],
769 &aup->mac->mac_addr_low);
770
771
772 for (i = 0; i < NUM_RX_DMA; i++)
773 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
774
775 wmb(); /* drain writebuffer */
776
777 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
778#ifndef CONFIG_CPU_LITTLE_ENDIAN
779 control |= MAC_BIG_ENDIAN;
780#endif
781 if (aup->phy_dev) {
782 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
783 control |= MAC_FULL_DUPLEX;
784 else
785 control |= MAC_DISABLE_RX_OWN;
786 } else { /* PHY-less op, assume full-duplex */
787 control |= MAC_FULL_DUPLEX;
788 }
789
790 writel(control, &aup->mac->control);
791 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
792 wmb(); /* drain writebuffer */
793
794 spin_unlock_irqrestore(&aup->lock, flags);
795 return 0;
796}
797
798static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
799{
800 struct net_device_stats *ps = &dev->stats;
801
802 ps->rx_packets++;
803 if (status & RX_MCAST_FRAME)
804 ps->multicast++;
805
806 if (status & RX_ERROR) {
807 ps->rx_errors++;
808 if (status & RX_MISSED_FRAME)
809 ps->rx_missed_errors++;
810 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
811 ps->rx_length_errors++;
812 if (status & RX_CRC_ERROR)
813 ps->rx_crc_errors++;
814 if (status & RX_COLL)
815 ps->collisions++;
816 } else
817 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
818
819}
820
821/*
822 * Au1000 receive routine.
823 */
824static int au1000_rx(struct net_device *dev)
825{
826 struct au1000_private *aup = netdev_priv(dev);
827 struct sk_buff *skb;
828 struct rx_dma *prxd;
829 u32 buff_stat, status;
830 struct db_dest *pDB;
831 u32 frmlen;
832
833 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
834
835 prxd = aup->rx_dma_ring[aup->rx_head];
836 buff_stat = prxd->buff_stat;
837 while (buff_stat & RX_T_DONE) {
838 status = prxd->status;
839 pDB = aup->rx_db_inuse[aup->rx_head];
840 au1000_update_rx_stats(dev, status);
841 if (!(status & RX_ERROR)) {
842
843 /* good frame */
844 frmlen = (status & RX_FRAME_LEN_MASK);
845 frmlen -= 4; /* Remove FCS */
846 skb = netdev_alloc_skb(dev, frmlen + 2);
847 if (skb == NULL) {
848 dev->stats.rx_dropped++;
849 continue;
850 }
851 skb_reserve(skb, 2); /* 16 byte IP header align */
852 skb_copy_to_linear_data(skb,
853 (unsigned char *)pDB->vaddr, frmlen);
854 skb_put(skb, frmlen);
855 skb->protocol = eth_type_trans(skb, dev);
856 netif_rx(skb); /* pass the packet to upper layers */
857 } else {
858 if (au1000_debug > 4) {
859 pr_err("rx_error(s):");
860 if (status & RX_MISSED_FRAME)
861 pr_cont(" miss");
862 if (status & RX_WDOG_TIMER)
863 pr_cont(" wdog");
864 if (status & RX_RUNT)
865 pr_cont(" runt");
866 if (status & RX_OVERLEN)
867 pr_cont(" overlen");
868 if (status & RX_COLL)
869 pr_cont(" coll");
870 if (status & RX_MII_ERROR)
871 pr_cont(" mii error");
872 if (status & RX_CRC_ERROR)
873 pr_cont(" crc error");
874 if (status & RX_LEN_ERROR)
875 pr_cont(" len error");
876 if (status & RX_U_CNTRL_FRAME)
877 pr_cont(" u control frame");
878 pr_cont("\n");
879 }
880 }
881 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
882 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
883 wmb(); /* drain writebuffer */
884
885 /* next descriptor */
886 prxd = aup->rx_dma_ring[aup->rx_head];
887 buff_stat = prxd->buff_stat;
888 }
889 return 0;
890}
891
892static void au1000_update_tx_stats(struct net_device *dev, u32 status)
893{
894 struct au1000_private *aup = netdev_priv(dev);
895 struct net_device_stats *ps = &dev->stats;
896
897 if (status & TX_FRAME_ABORTED) {
898 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
899 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
900 /* any other tx errors are only valid
901 * in half duplex mode
902 */
903 ps->tx_errors++;
904 ps->tx_aborted_errors++;
905 }
906 } else {
907 ps->tx_errors++;
908 ps->tx_aborted_errors++;
909 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
910 ps->tx_carrier_errors++;
911 }
912 }
913}
914
915/*
916 * Called from the interrupt service routine to acknowledge
917 * the TX DONE bits. This is a must if the irq is setup as
918 * edge triggered.
919 */
920static void au1000_tx_ack(struct net_device *dev)
921{
922 struct au1000_private *aup = netdev_priv(dev);
923 struct tx_dma *ptxd;
924
925 ptxd = aup->tx_dma_ring[aup->tx_tail];
926
927 while (ptxd->buff_stat & TX_T_DONE) {
928 au1000_update_tx_stats(dev, ptxd->status);
929 ptxd->buff_stat &= ~TX_T_DONE;
930 ptxd->len = 0;
931 wmb(); /* drain writebuffer */
932
933 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
934 ptxd = aup->tx_dma_ring[aup->tx_tail];
935
936 if (aup->tx_full) {
937 aup->tx_full = 0;
938 netif_wake_queue(dev);
939 }
940 }
941}
942
943/*
944 * Au1000 interrupt service routine.
945 */
946static irqreturn_t au1000_interrupt(int irq, void *dev_id)
947{
948 struct net_device *dev = dev_id;
949
950 /* Handle RX interrupts first to minimize chance of overrun */
951
952 au1000_rx(dev);
953 au1000_tx_ack(dev);
954 return IRQ_RETVAL(1);
955}
956
957static int au1000_open(struct net_device *dev)
958{
959 int retval;
960 struct au1000_private *aup = netdev_priv(dev);
961
962 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
963
964 retval = request_irq(dev->irq, au1000_interrupt, 0,
965 dev->name, dev);
966 if (retval) {
967 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
968 return retval;
969 }
970
971 retval = au1000_init(dev);
972 if (retval) {
973 netdev_err(dev, "error in au1000_init\n");
974 free_irq(dev->irq, dev);
975 return retval;
976 }
977
978 if (aup->phy_dev) {
979 /* cause the PHY state machine to schedule a link state check */
980 aup->phy_dev->state = PHY_CHANGELINK;
981 phy_start(aup->phy_dev);
982 }
983
984 netif_start_queue(dev);
985
986 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
987
988 return 0;
989}
990
991static int au1000_close(struct net_device *dev)
992{
993 unsigned long flags;
994 struct au1000_private *const aup = netdev_priv(dev);
995
996 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
997
998 if (aup->phy_dev)
999 phy_stop(aup->phy_dev);
1000
1001 spin_lock_irqsave(&aup->lock, flags);
1002
1003 au1000_reset_mac_unlocked(dev);
1004
1005 /* stop the device */
1006 netif_stop_queue(dev);
1007
1008 /* disable the interrupt */
1009 free_irq(dev->irq, dev);
1010 spin_unlock_irqrestore(&aup->lock, flags);
1011
1012 return 0;
1013}
1014
1015/*
1016 * Au1000 transmit routine.
1017 */
1018static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1019{
1020 struct au1000_private *aup = netdev_priv(dev);
1021 struct net_device_stats *ps = &dev->stats;
1022 struct tx_dma *ptxd;
1023 u32 buff_stat;
1024 struct db_dest *pDB;
1025 int i;
1026
1027 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
1028 (unsigned)aup, skb->len,
1029 skb->data, aup->tx_head);
1030
1031 ptxd = aup->tx_dma_ring[aup->tx_head];
1032 buff_stat = ptxd->buff_stat;
1033 if (buff_stat & TX_DMA_ENABLE) {
1034 /* We've wrapped around and the transmitter is still busy */
1035 netif_stop_queue(dev);
1036 aup->tx_full = 1;
1037 return NETDEV_TX_BUSY;
1038 } else if (buff_stat & TX_T_DONE) {
1039 au1000_update_tx_stats(dev, ptxd->status);
1040 ptxd->len = 0;
1041 }
1042
1043 if (aup->tx_full) {
1044 aup->tx_full = 0;
1045 netif_wake_queue(dev);
1046 }
1047
1048 pDB = aup->tx_db_inuse[aup->tx_head];
1049 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1050 if (skb->len < ETH_ZLEN) {
1051 for (i = skb->len; i < ETH_ZLEN; i++)
1052 ((char *)pDB->vaddr)[i] = 0;
1053
1054 ptxd->len = ETH_ZLEN;
1055 } else
1056 ptxd->len = skb->len;
1057
1058 ps->tx_packets++;
1059 ps->tx_bytes += ptxd->len;
1060
1061 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1062 wmb(); /* drain writebuffer */
1063 dev_kfree_skb(skb);
1064 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1065 return NETDEV_TX_OK;
1066}
1067
1068/*
1069 * The Tx ring has been full longer than the watchdog timeout
1070 * value. The transmitter must be hung?
1071 */
1072static void au1000_tx_timeout(struct net_device *dev)
1073{
1074 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
1075 au1000_reset_mac(dev);
1076 au1000_init(dev);
1077 dev->trans_start = jiffies; /* prevent tx timeout */
1078 netif_wake_queue(dev);
1079}
1080
1081static void au1000_multicast_list(struct net_device *dev)
1082{
1083 struct au1000_private *aup = netdev_priv(dev);
1084 u32 reg;
1085
1086 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
1087 reg = readl(&aup->mac->control);
1088 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1089 reg |= MAC_PROMISCUOUS;
1090 } else if ((dev->flags & IFF_ALLMULTI) ||
1091 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1092 reg |= MAC_PASS_ALL_MULTI;
1093 reg &= ~MAC_PROMISCUOUS;
1094 netdev_info(dev, "Pass all multicast\n");
1095 } else {
1096 struct netdev_hw_addr *ha;
1097 u32 mc_filter[2]; /* Multicast hash filter */
1098
1099 mc_filter[1] = mc_filter[0] = 0;
1100 netdev_for_each_mc_addr(ha, dev)
1101 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1102 (long *)mc_filter);
1103 writel(mc_filter[1], &aup->mac->multi_hash_high);
1104 writel(mc_filter[0], &aup->mac->multi_hash_low);
1105 reg &= ~MAC_PROMISCUOUS;
1106 reg |= MAC_HASH_MODE;
1107 }
1108 writel(reg, &aup->mac->control);
1109}
1110
1111static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1112{
1113 struct au1000_private *aup = netdev_priv(dev);
1114
1115 if (!netif_running(dev))
1116 return -EINVAL;
1117
1118 if (!aup->phy_dev)
1119 return -EINVAL; /* PHY not controllable */
1120
1121 return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1122}
1123
1124static const struct net_device_ops au1000_netdev_ops = {
1125 .ndo_open = au1000_open,
1126 .ndo_stop = au1000_close,
1127 .ndo_start_xmit = au1000_tx,
1128 .ndo_set_rx_mode = au1000_multicast_list,
1129 .ndo_do_ioctl = au1000_ioctl,
1130 .ndo_tx_timeout = au1000_tx_timeout,
1131 .ndo_set_mac_address = eth_mac_addr,
1132 .ndo_validate_addr = eth_validate_addr,
1133 .ndo_change_mtu = eth_change_mtu,
1134};
1135
1136static int au1000_probe(struct platform_device *pdev)
1137{
1138 struct au1000_private *aup = NULL;
1139 struct au1000_eth_platform_data *pd;
1140 struct net_device *dev = NULL;
1141 struct db_dest *pDB, *pDBfree;
1142 int irq, i, err = 0;
1143 struct resource *base, *macen, *macdma;
1144
1145 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1146 if (!base) {
1147 dev_err(&pdev->dev, "failed to retrieve base register\n");
1148 err = -ENODEV;
1149 goto out;
1150 }
1151
1152 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1153 if (!macen) {
1154 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1155 err = -ENODEV;
1156 goto out;
1157 }
1158
1159 irq = platform_get_irq(pdev, 0);
1160 if (irq < 0) {
1161 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
1162 err = -ENODEV;
1163 goto out;
1164 }
1165
1166 macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1167 if (!macdma) {
1168 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1169 err = -ENODEV;
1170 goto out;
1171 }
1172
1173 if (!request_mem_region(base->start, resource_size(base),
1174 pdev->name)) {
1175 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1176 err = -ENXIO;
1177 goto out;
1178 }
1179
1180 if (!request_mem_region(macen->start, resource_size(macen),
1181 pdev->name)) {
1182 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1183 err = -ENXIO;
1184 goto err_request;
1185 }
1186
1187 if (!request_mem_region(macdma->start, resource_size(macdma),
1188 pdev->name)) {
1189 dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1190 err = -ENXIO;
1191 goto err_macdma;
1192 }
1193
1194 dev = alloc_etherdev(sizeof(struct au1000_private));
1195 if (!dev) {
1196 err = -ENOMEM;
1197 goto err_alloc;
1198 }
1199
1200 SET_NETDEV_DEV(dev, &pdev->dev);
1201 platform_set_drvdata(pdev, dev);
1202 aup = netdev_priv(dev);
1203
1204 spin_lock_init(&aup->lock);
1205 aup->msg_enable = (au1000_debug < 4 ?
1206 AU1000_DEF_MSG_ENABLE : au1000_debug);
1207
1208 /* Allocate the data buffers
1209 * Snooping works fine with eth on all au1xxx
1210 */
1211 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1212 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1213 &aup->dma_addr, 0);
1214 if (!aup->vaddr) {
1215 dev_err(&pdev->dev, "failed to allocate data buffers\n");
1216 err = -ENOMEM;
1217 goto err_vaddr;
1218 }
1219
1220 /* aup->mac is the base address of the MAC's registers */
1221 aup->mac = (struct mac_reg *)
1222 ioremap_nocache(base->start, resource_size(base));
1223 if (!aup->mac) {
1224 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1225 err = -ENXIO;
1226 goto err_remap1;
1227 }
1228
1229 /* Setup some variables for quick register address access */
1230 aup->enable = (u32 *)ioremap_nocache(macen->start,
1231 resource_size(macen));
1232 if (!aup->enable) {
1233 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1234 err = -ENXIO;
1235 goto err_remap2;
1236 }
1237 aup->mac_id = pdev->id;
1238
1239 aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma));
1240 if (!aup->macdma) {
1241 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1242 err = -ENXIO;
1243 goto err_remap3;
1244 }
1245
1246 au1000_setup_hw_rings(aup, aup->macdma);
1247
1248 writel(0, aup->enable);
1249 aup->mac_enabled = 0;
1250
1251 pd = dev_get_platdata(&pdev->dev);
1252 if (!pd) {
1253 dev_info(&pdev->dev, "no platform_data passed,"
1254 " PHY search on MAC0\n");
1255 aup->phy1_search_mac0 = 1;
1256 } else {
1257 if (is_valid_ether_addr(pd->mac)) {
1258 memcpy(dev->dev_addr, pd->mac, ETH_ALEN);
1259 } else {
1260 /* Set a random MAC since no valid provided by platform_data. */
1261 eth_hw_addr_random(dev);
1262 }
1263
1264 aup->phy_static_config = pd->phy_static_config;
1265 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1266 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1267 aup->phy_addr = pd->phy_addr;
1268 aup->phy_busid = pd->phy_busid;
1269 aup->phy_irq = pd->phy_irq;
1270 }
1271
1272 if (aup->phy_busid && aup->phy_busid > 0) {
1273 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1274 err = -ENODEV;
1275 goto err_mdiobus_alloc;
1276 }
1277
1278 aup->mii_bus = mdiobus_alloc();
1279 if (aup->mii_bus == NULL) {
1280 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1281 err = -ENOMEM;
1282 goto err_mdiobus_alloc;
1283 }
1284
1285 aup->mii_bus->priv = dev;
1286 aup->mii_bus->read = au1000_mdiobus_read;
1287 aup->mii_bus->write = au1000_mdiobus_write;
1288 aup->mii_bus->reset = au1000_mdiobus_reset;
1289 aup->mii_bus->name = "au1000_eth_mii";
1290 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1291 pdev->name, aup->mac_id);
1292
1293 /* if known, set corresponding PHY IRQs */
1294 if (aup->phy_static_config)
1295 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1296 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1297
1298 err = mdiobus_register(aup->mii_bus);
1299 if (err) {
1300 dev_err(&pdev->dev, "failed to register MDIO bus\n");
1301 goto err_mdiobus_reg;
1302 }
1303
1304 err = au1000_mii_probe(dev);
1305 if (err != 0)
1306 goto err_out;
1307
1308 pDBfree = NULL;
1309 /* setup the data buffer descriptors and attach a buffer to each one */
1310 pDB = aup->db;
1311 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1312 pDB->pnext = pDBfree;
1313 pDBfree = pDB;
1314 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1315 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1316 pDB++;
1317 }
1318 aup->pDBfree = pDBfree;
1319
1320 err = -ENODEV;
1321 for (i = 0; i < NUM_RX_DMA; i++) {
1322 pDB = au1000_GetFreeDB(aup);
1323 if (!pDB)
1324 goto err_out;
1325
1326 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1327 aup->rx_db_inuse[i] = pDB;
1328 }
1329
1330 err = -ENODEV;
1331 for (i = 0; i < NUM_TX_DMA; i++) {
1332 pDB = au1000_GetFreeDB(aup);
1333 if (!pDB)
1334 goto err_out;
1335
1336 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1337 aup->tx_dma_ring[i]->len = 0;
1338 aup->tx_db_inuse[i] = pDB;
1339 }
1340
1341 dev->base_addr = base->start;
1342 dev->irq = irq;
1343 dev->netdev_ops = &au1000_netdev_ops;
1344 dev->ethtool_ops = &au1000_ethtool_ops;
1345 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1346
1347 /*
1348 * The boot code uses the ethernet controller, so reset it to start
1349 * fresh. au1000_init() expects that the device is in reset state.
1350 */
1351 au1000_reset_mac(dev);
1352
1353 err = register_netdev(dev);
1354 if (err) {
1355 netdev_err(dev, "Cannot register net device, aborting.\n");
1356 goto err_out;
1357 }
1358
1359 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1360 (unsigned long)base->start, irq);
1361
1362 pr_info_once("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1363
1364 return 0;
1365
1366err_out:
1367 if (aup->mii_bus != NULL)
1368 mdiobus_unregister(aup->mii_bus);
1369
1370 /* here we should have a valid dev plus aup-> register addresses
1371 * so we can reset the mac properly.
1372 */
1373 au1000_reset_mac(dev);
1374
1375 for (i = 0; i < NUM_RX_DMA; i++) {
1376 if (aup->rx_db_inuse[i])
1377 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1378 }
1379 for (i = 0; i < NUM_TX_DMA; i++) {
1380 if (aup->tx_db_inuse[i])
1381 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1382 }
1383err_mdiobus_reg:
1384 mdiobus_free(aup->mii_bus);
1385err_mdiobus_alloc:
1386 iounmap(aup->macdma);
1387err_remap3:
1388 iounmap(aup->enable);
1389err_remap2:
1390 iounmap(aup->mac);
1391err_remap1:
1392 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1393 (void *)aup->vaddr, aup->dma_addr);
1394err_vaddr:
1395 free_netdev(dev);
1396err_alloc:
1397 release_mem_region(macdma->start, resource_size(macdma));
1398err_macdma:
1399 release_mem_region(macen->start, resource_size(macen));
1400err_request:
1401 release_mem_region(base->start, resource_size(base));
1402out:
1403 return err;
1404}
1405
1406static int au1000_remove(struct platform_device *pdev)
1407{
1408 struct net_device *dev = platform_get_drvdata(pdev);
1409 struct au1000_private *aup = netdev_priv(dev);
1410 int i;
1411 struct resource *base, *macen;
1412
1413 unregister_netdev(dev);
1414 mdiobus_unregister(aup->mii_bus);
1415 mdiobus_free(aup->mii_bus);
1416
1417 for (i = 0; i < NUM_RX_DMA; i++)
1418 if (aup->rx_db_inuse[i])
1419 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1420
1421 for (i = 0; i < NUM_TX_DMA; i++)
1422 if (aup->tx_db_inuse[i])
1423 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1424
1425 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1426 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1427 (void *)aup->vaddr, aup->dma_addr);
1428
1429 iounmap(aup->macdma);
1430 iounmap(aup->mac);
1431 iounmap(aup->enable);
1432
1433 base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1434 release_mem_region(base->start, resource_size(base));
1435
1436 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1437 release_mem_region(base->start, resource_size(base));
1438
1439 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1440 release_mem_region(macen->start, resource_size(macen));
1441
1442 free_netdev(dev);
1443
1444 return 0;
1445}
1446
1447static struct platform_driver au1000_eth_driver = {
1448 .probe = au1000_probe,
1449 .remove = au1000_remove,
1450 .driver = {
1451 .name = "au1000-eth",
1452 },
1453};
1454
1455module_platform_driver(au1000_eth_driver);
1456
1457MODULE_ALIAS("platform:au1000-eth");