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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-mmp/irq.c
4 *
5 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
6 * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
7 *
8 * Author: Bin Yang <bin.yang@marvell.com>
9 * Haojian Zhuang <haojian.zhuang@gmail.com>
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/irq.h>
15#include <linux/irqchip.h>
16#include <linux/irqchip/chained_irq.h>
17#include <linux/irqdomain.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22
23#include <asm/exception.h>
24#include <asm/hardirq.h>
25
26#define MAX_ICU_NR 16
27
28#define PJ1_INT_SEL 0x10c
29#define PJ4_INT_SEL 0x104
30
31/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
32#define SEL_INT_PENDING (1 << 6)
33#define SEL_INT_NUM_MASK 0x3f
34
35#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
36#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
37
38struct icu_chip_data {
39 int nr_irqs;
40 unsigned int virq_base;
41 unsigned int cascade_irq;
42 void __iomem *reg_status;
43 void __iomem *reg_mask;
44 unsigned int conf_enable;
45 unsigned int conf_disable;
46 unsigned int conf_mask;
47 unsigned int conf2_mask;
48 unsigned int clr_mfp_irq_base;
49 unsigned int clr_mfp_hwirq;
50 struct irq_domain *domain;
51};
52
53struct mmp_intc_conf {
54 unsigned int conf_enable;
55 unsigned int conf_disable;
56 unsigned int conf_mask;
57 unsigned int conf2_mask;
58};
59
60static void __iomem *mmp_icu_base;
61static void __iomem *mmp_icu2_base;
62static struct icu_chip_data icu_data[MAX_ICU_NR];
63static int max_icu_nr;
64
65extern void mmp2_clear_pmic_int(void);
66
67static void icu_mask_ack_irq(struct irq_data *d)
68{
69 struct irq_domain *domain = d->domain;
70 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
71 int hwirq;
72 u32 r;
73
74 hwirq = d->irq - data->virq_base;
75 if (data == &icu_data[0]) {
76 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
77 r &= ~data->conf_mask;
78 r |= data->conf_disable;
79 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
80 } else {
81#ifdef CONFIG_CPU_MMP2
82 if ((data->virq_base == data->clr_mfp_irq_base)
83 && (hwirq == data->clr_mfp_hwirq))
84 mmp2_clear_pmic_int();
85#endif
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
87 writel_relaxed(r, data->reg_mask);
88 }
89}
90
91static void icu_mask_irq(struct irq_data *d)
92{
93 struct irq_domain *domain = d->domain;
94 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
95 int hwirq;
96 u32 r;
97
98 hwirq = d->irq - data->virq_base;
99 if (data == &icu_data[0]) {
100 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
101 r &= ~data->conf_mask;
102 r |= data->conf_disable;
103 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
104
105 if (data->conf2_mask) {
106 /*
107 * ICU1 (above) only controls PJ4 MP1; if using SMP,
108 * we need to also mask the MP2 and MM cores via ICU2.
109 */
110 r = readl_relaxed(mmp_icu2_base + (hwirq << 2));
111 r &= ~data->conf2_mask;
112 writel_relaxed(r, mmp_icu2_base + (hwirq << 2));
113 }
114 } else {
115 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
116 writel_relaxed(r, data->reg_mask);
117 }
118}
119
120static void icu_unmask_irq(struct irq_data *d)
121{
122 struct irq_domain *domain = d->domain;
123 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
124 int hwirq;
125 u32 r;
126
127 hwirq = d->irq - data->virq_base;
128 if (data == &icu_data[0]) {
129 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
130 r &= ~data->conf_mask;
131 r |= data->conf_enable;
132 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
133 } else {
134 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
135 writel_relaxed(r, data->reg_mask);
136 }
137}
138
139struct irq_chip icu_irq_chip = {
140 .name = "icu_irq",
141 .irq_mask = icu_mask_irq,
142 .irq_mask_ack = icu_mask_ack_irq,
143 .irq_unmask = icu_unmask_irq,
144};
145
146static void icu_mux_irq_demux(struct irq_desc *desc)
147{
148 unsigned int irq = irq_desc_get_irq(desc);
149 struct irq_chip *chip = irq_desc_get_chip(desc);
150 struct irq_domain *domain;
151 struct icu_chip_data *data;
152 int i;
153 unsigned long mask, status, n;
154
155 chained_irq_enter(chip, desc);
156
157 for (i = 1; i < max_icu_nr; i++) {
158 if (irq == icu_data[i].cascade_irq) {
159 domain = icu_data[i].domain;
160 data = (struct icu_chip_data *)domain->host_data;
161 break;
162 }
163 }
164 if (i >= max_icu_nr) {
165 pr_err("Spurious irq %d in MMP INTC\n", irq);
166 goto out;
167 }
168
169 mask = readl_relaxed(data->reg_mask);
170 while (1) {
171 status = readl_relaxed(data->reg_status) & ~mask;
172 if (status == 0)
173 break;
174 for_each_set_bit(n, &status, BITS_PER_LONG) {
175 generic_handle_irq(icu_data[i].virq_base + n);
176 }
177 }
178
179out:
180 chained_irq_exit(chip, desc);
181}
182
183static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
184 irq_hw_number_t hw)
185{
186 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
187 return 0;
188}
189
190static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
191 const u32 *intspec, unsigned int intsize,
192 unsigned long *out_hwirq,
193 unsigned int *out_type)
194{
195 *out_hwirq = intspec[0];
196 return 0;
197}
198
199static const struct irq_domain_ops mmp_irq_domain_ops = {
200 .map = mmp_irq_domain_map,
201 .xlate = mmp_irq_domain_xlate,
202};
203
204static const struct mmp_intc_conf mmp_conf = {
205 .conf_enable = 0x51,
206 .conf_disable = 0x0,
207 .conf_mask = 0x7f,
208};
209
210static const struct mmp_intc_conf mmp2_conf = {
211 .conf_enable = 0x20,
212 .conf_disable = 0x0,
213 .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
214 MMP2_ICU_INT_ROUTE_PJ4_FIQ,
215};
216
217static struct mmp_intc_conf mmp3_conf = {
218 .conf_enable = 0x20,
219 .conf_disable = 0x0,
220 .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
221 MMP2_ICU_INT_ROUTE_PJ4_FIQ,
222 .conf2_mask = 0xf0,
223};
224
225static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
226{
227 int hwirq;
228
229 hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
230 if (!(hwirq & SEL_INT_PENDING))
231 return;
232 hwirq &= SEL_INT_NUM_MASK;
233 generic_handle_domain_irq(icu_data[0].domain, hwirq);
234}
235
236static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
237{
238 int hwirq;
239
240 hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
241 if (!(hwirq & SEL_INT_PENDING))
242 return;
243 hwirq &= SEL_INT_NUM_MASK;
244 generic_handle_domain_irq(icu_data[0].domain, hwirq);
245}
246
247static int __init mmp_init_bases(struct device_node *node)
248{
249 int ret, nr_irqs, irq, i = 0;
250
251 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
252 if (ret) {
253 pr_err("Not found mrvl,intc-nr-irqs property\n");
254 return ret;
255 }
256
257 mmp_icu_base = of_iomap(node, 0);
258 if (!mmp_icu_base) {
259 pr_err("Failed to get interrupt controller register\n");
260 return -ENOMEM;
261 }
262
263 icu_data[0].virq_base = 0;
264 icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
265 &mmp_irq_domain_ops,
266 &icu_data[0]);
267 for (irq = 0; irq < nr_irqs; irq++) {
268 ret = irq_create_mapping(icu_data[0].domain, irq);
269 if (!ret) {
270 pr_err("Failed to mapping hwirq\n");
271 goto err;
272 }
273 if (!irq)
274 icu_data[0].virq_base = ret;
275 }
276 icu_data[0].nr_irqs = nr_irqs;
277 return 0;
278err:
279 if (icu_data[0].virq_base) {
280 for (i = 0; i < irq; i++)
281 irq_dispose_mapping(icu_data[0].virq_base + i);
282 }
283 irq_domain_remove(icu_data[0].domain);
284 iounmap(mmp_icu_base);
285 return -EINVAL;
286}
287
288static int __init mmp_of_init(struct device_node *node,
289 struct device_node *parent)
290{
291 int ret;
292
293 ret = mmp_init_bases(node);
294 if (ret < 0)
295 return ret;
296
297 icu_data[0].conf_enable = mmp_conf.conf_enable;
298 icu_data[0].conf_disable = mmp_conf.conf_disable;
299 icu_data[0].conf_mask = mmp_conf.conf_mask;
300 set_handle_irq(mmp_handle_irq);
301 max_icu_nr = 1;
302 return 0;
303}
304IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
305
306static int __init mmp2_of_init(struct device_node *node,
307 struct device_node *parent)
308{
309 int ret;
310
311 ret = mmp_init_bases(node);
312 if (ret < 0)
313 return ret;
314
315 icu_data[0].conf_enable = mmp2_conf.conf_enable;
316 icu_data[0].conf_disable = mmp2_conf.conf_disable;
317 icu_data[0].conf_mask = mmp2_conf.conf_mask;
318 set_handle_irq(mmp2_handle_irq);
319 max_icu_nr = 1;
320 return 0;
321}
322IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
323
324static int __init mmp3_of_init(struct device_node *node,
325 struct device_node *parent)
326{
327 int ret;
328
329 mmp_icu2_base = of_iomap(node, 1);
330 if (!mmp_icu2_base) {
331 pr_err("Failed to get interrupt controller register #2\n");
332 return -ENODEV;
333 }
334
335 ret = mmp_init_bases(node);
336 if (ret < 0) {
337 iounmap(mmp_icu2_base);
338 return ret;
339 }
340
341 icu_data[0].conf_enable = mmp3_conf.conf_enable;
342 icu_data[0].conf_disable = mmp3_conf.conf_disable;
343 icu_data[0].conf_mask = mmp3_conf.conf_mask;
344 icu_data[0].conf2_mask = mmp3_conf.conf2_mask;
345
346 if (!parent) {
347 /* This is the main interrupt controller. */
348 set_handle_irq(mmp2_handle_irq);
349 }
350
351 max_icu_nr = 1;
352 return 0;
353}
354IRQCHIP_DECLARE(mmp3_intc, "marvell,mmp3-intc", mmp3_of_init);
355
356static int __init mmp2_mux_of_init(struct device_node *node,
357 struct device_node *parent)
358{
359 int i, ret, irq, j = 0;
360 u32 nr_irqs, mfp_irq;
361 u32 reg[4];
362
363 if (!parent)
364 return -ENODEV;
365
366 i = max_icu_nr;
367 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
368 &nr_irqs);
369 if (ret) {
370 pr_err("Not found mrvl,intc-nr-irqs property\n");
371 return -EINVAL;
372 }
373
374 /*
375 * For historical reasons, the "regs" property of the
376 * mrvl,mmp2-mux-intc is not a regular "regs" property containing
377 * addresses on the parent bus, but offsets from the intc's base.
378 * That is why we can't use of_address_to_resource() here.
379 */
380 ret = of_property_read_variable_u32_array(node, "reg", reg,
381 ARRAY_SIZE(reg),
382 ARRAY_SIZE(reg));
383 if (ret < 0) {
384 pr_err("Not found reg property\n");
385 return -EINVAL;
386 }
387 icu_data[i].reg_status = mmp_icu_base + reg[0];
388 icu_data[i].reg_mask = mmp_icu_base + reg[2];
389 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
390 if (!icu_data[i].cascade_irq)
391 return -EINVAL;
392
393 icu_data[i].virq_base = 0;
394 icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
395 &mmp_irq_domain_ops,
396 &icu_data[i]);
397 for (irq = 0; irq < nr_irqs; irq++) {
398 ret = irq_create_mapping(icu_data[i].domain, irq);
399 if (!ret) {
400 pr_err("Failed to mapping hwirq\n");
401 goto err;
402 }
403 if (!irq)
404 icu_data[i].virq_base = ret;
405 }
406 icu_data[i].nr_irqs = nr_irqs;
407 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
408 &mfp_irq)) {
409 icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
410 icu_data[i].clr_mfp_hwirq = mfp_irq;
411 }
412 irq_set_chained_handler(icu_data[i].cascade_irq,
413 icu_mux_irq_demux);
414 max_icu_nr++;
415 return 0;
416err:
417 if (icu_data[i].virq_base) {
418 for (j = 0; j < irq; j++)
419 irq_dispose_mapping(icu_data[i].virq_base + j);
420 }
421 irq_domain_remove(icu_data[i].domain);
422 return -EINVAL;
423}
424IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
1/*
2 * linux/arch/arm/mach-mmp/irq.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
6 *
7 * Author: Bin Yang <bin.yang@marvell.com>
8 * Haojian Zhuang <haojian.zhuang@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/irq.h>
18#include <linux/irqchip.h>
19#include <linux/irqdomain.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24
25#include <asm/exception.h>
26#include <asm/hardirq.h>
27
28#define MAX_ICU_NR 16
29
30#define PJ1_INT_SEL 0x10c
31#define PJ4_INT_SEL 0x104
32
33/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
34#define SEL_INT_PENDING (1 << 6)
35#define SEL_INT_NUM_MASK 0x3f
36
37struct icu_chip_data {
38 int nr_irqs;
39 unsigned int virq_base;
40 unsigned int cascade_irq;
41 void __iomem *reg_status;
42 void __iomem *reg_mask;
43 unsigned int conf_enable;
44 unsigned int conf_disable;
45 unsigned int conf_mask;
46 unsigned int clr_mfp_irq_base;
47 unsigned int clr_mfp_hwirq;
48 struct irq_domain *domain;
49};
50
51struct mmp_intc_conf {
52 unsigned int conf_enable;
53 unsigned int conf_disable;
54 unsigned int conf_mask;
55};
56
57static void __iomem *mmp_icu_base;
58static struct icu_chip_data icu_data[MAX_ICU_NR];
59static int max_icu_nr;
60
61extern void mmp2_clear_pmic_int(void);
62
63static void icu_mask_ack_irq(struct irq_data *d)
64{
65 struct irq_domain *domain = d->domain;
66 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
67 int hwirq;
68 u32 r;
69
70 hwirq = d->irq - data->virq_base;
71 if (data == &icu_data[0]) {
72 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
73 r &= ~data->conf_mask;
74 r |= data->conf_disable;
75 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
76 } else {
77#ifdef CONFIG_CPU_MMP2
78 if ((data->virq_base == data->clr_mfp_irq_base)
79 && (hwirq == data->clr_mfp_hwirq))
80 mmp2_clear_pmic_int();
81#endif
82 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
83 writel_relaxed(r, data->reg_mask);
84 }
85}
86
87static void icu_mask_irq(struct irq_data *d)
88{
89 struct irq_domain *domain = d->domain;
90 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
91 int hwirq;
92 u32 r;
93
94 hwirq = d->irq - data->virq_base;
95 if (data == &icu_data[0]) {
96 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
97 r &= ~data->conf_mask;
98 r |= data->conf_disable;
99 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
100 } else {
101 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
102 writel_relaxed(r, data->reg_mask);
103 }
104}
105
106static void icu_unmask_irq(struct irq_data *d)
107{
108 struct irq_domain *domain = d->domain;
109 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
110 int hwirq;
111 u32 r;
112
113 hwirq = d->irq - data->virq_base;
114 if (data == &icu_data[0]) {
115 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
116 r &= ~data->conf_mask;
117 r |= data->conf_enable;
118 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
119 } else {
120 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
121 writel_relaxed(r, data->reg_mask);
122 }
123}
124
125struct irq_chip icu_irq_chip = {
126 .name = "icu_irq",
127 .irq_mask = icu_mask_irq,
128 .irq_mask_ack = icu_mask_ack_irq,
129 .irq_unmask = icu_unmask_irq,
130};
131
132static void icu_mux_irq_demux(struct irq_desc *desc)
133{
134 unsigned int irq = irq_desc_get_irq(desc);
135 struct irq_domain *domain;
136 struct icu_chip_data *data;
137 int i;
138 unsigned long mask, status, n;
139
140 for (i = 1; i < max_icu_nr; i++) {
141 if (irq == icu_data[i].cascade_irq) {
142 domain = icu_data[i].domain;
143 data = (struct icu_chip_data *)domain->host_data;
144 break;
145 }
146 }
147 if (i >= max_icu_nr) {
148 pr_err("Spurious irq %d in MMP INTC\n", irq);
149 return;
150 }
151
152 mask = readl_relaxed(data->reg_mask);
153 while (1) {
154 status = readl_relaxed(data->reg_status) & ~mask;
155 if (status == 0)
156 break;
157 for_each_set_bit(n, &status, BITS_PER_LONG) {
158 generic_handle_irq(icu_data[i].virq_base + n);
159 }
160 }
161}
162
163static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
164 irq_hw_number_t hw)
165{
166 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
167 return 0;
168}
169
170static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
171 const u32 *intspec, unsigned int intsize,
172 unsigned long *out_hwirq,
173 unsigned int *out_type)
174{
175 *out_hwirq = intspec[0];
176 return 0;
177}
178
179const struct irq_domain_ops mmp_irq_domain_ops = {
180 .map = mmp_irq_domain_map,
181 .xlate = mmp_irq_domain_xlate,
182};
183
184static struct mmp_intc_conf mmp_conf = {
185 .conf_enable = 0x51,
186 .conf_disable = 0x0,
187 .conf_mask = 0x7f,
188};
189
190static struct mmp_intc_conf mmp2_conf = {
191 .conf_enable = 0x20,
192 .conf_disable = 0x0,
193 .conf_mask = 0x7f,
194};
195
196static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
197{
198 int hwirq;
199
200 hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
201 if (!(hwirq & SEL_INT_PENDING))
202 return;
203 hwirq &= SEL_INT_NUM_MASK;
204 handle_domain_irq(icu_data[0].domain, hwirq, regs);
205}
206
207static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
208{
209 int hwirq;
210
211 hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
212 if (!(hwirq & SEL_INT_PENDING))
213 return;
214 hwirq &= SEL_INT_NUM_MASK;
215 handle_domain_irq(icu_data[0].domain, hwirq, regs);
216}
217
218/* MMP (ARMv5) */
219void __init icu_init_irq(void)
220{
221 int irq;
222
223 max_icu_nr = 1;
224 mmp_icu_base = ioremap(0xd4282000, 0x1000);
225 icu_data[0].conf_enable = mmp_conf.conf_enable;
226 icu_data[0].conf_disable = mmp_conf.conf_disable;
227 icu_data[0].conf_mask = mmp_conf.conf_mask;
228 icu_data[0].nr_irqs = 64;
229 icu_data[0].virq_base = 0;
230 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
231 &irq_domain_simple_ops,
232 &icu_data[0]);
233 for (irq = 0; irq < 64; irq++) {
234 icu_mask_irq(irq_get_irq_data(irq));
235 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
236 }
237 irq_set_default_host(icu_data[0].domain);
238 set_handle_irq(mmp_handle_irq);
239}
240
241/* MMP2 (ARMv7) */
242void __init mmp2_init_icu(void)
243{
244 int irq, end;
245
246 max_icu_nr = 8;
247 mmp_icu_base = ioremap(0xd4282000, 0x1000);
248 icu_data[0].conf_enable = mmp2_conf.conf_enable;
249 icu_data[0].conf_disable = mmp2_conf.conf_disable;
250 icu_data[0].conf_mask = mmp2_conf.conf_mask;
251 icu_data[0].nr_irqs = 64;
252 icu_data[0].virq_base = 0;
253 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
254 &irq_domain_simple_ops,
255 &icu_data[0]);
256 icu_data[1].reg_status = mmp_icu_base + 0x150;
257 icu_data[1].reg_mask = mmp_icu_base + 0x168;
258 icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
259 icu_data[0].nr_irqs;
260 icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */
261 icu_data[1].nr_irqs = 2;
262 icu_data[1].cascade_irq = 4;
263 icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
264 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
265 icu_data[1].virq_base, 0,
266 &irq_domain_simple_ops,
267 &icu_data[1]);
268 icu_data[2].reg_status = mmp_icu_base + 0x154;
269 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
270 icu_data[2].nr_irqs = 2;
271 icu_data[2].cascade_irq = 5;
272 icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
273 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
274 icu_data[2].virq_base, 0,
275 &irq_domain_simple_ops,
276 &icu_data[2]);
277 icu_data[3].reg_status = mmp_icu_base + 0x180;
278 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
279 icu_data[3].nr_irqs = 3;
280 icu_data[3].cascade_irq = 9;
281 icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
282 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
283 icu_data[3].virq_base, 0,
284 &irq_domain_simple_ops,
285 &icu_data[3]);
286 icu_data[4].reg_status = mmp_icu_base + 0x158;
287 icu_data[4].reg_mask = mmp_icu_base + 0x170;
288 icu_data[4].nr_irqs = 5;
289 icu_data[4].cascade_irq = 17;
290 icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
291 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
292 icu_data[4].virq_base, 0,
293 &irq_domain_simple_ops,
294 &icu_data[4]);
295 icu_data[5].reg_status = mmp_icu_base + 0x15c;
296 icu_data[5].reg_mask = mmp_icu_base + 0x174;
297 icu_data[5].nr_irqs = 15;
298 icu_data[5].cascade_irq = 35;
299 icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
300 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
301 icu_data[5].virq_base, 0,
302 &irq_domain_simple_ops,
303 &icu_data[5]);
304 icu_data[6].reg_status = mmp_icu_base + 0x160;
305 icu_data[6].reg_mask = mmp_icu_base + 0x178;
306 icu_data[6].nr_irqs = 2;
307 icu_data[6].cascade_irq = 51;
308 icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
309 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
310 icu_data[6].virq_base, 0,
311 &irq_domain_simple_ops,
312 &icu_data[6]);
313 icu_data[7].reg_status = mmp_icu_base + 0x188;
314 icu_data[7].reg_mask = mmp_icu_base + 0x184;
315 icu_data[7].nr_irqs = 2;
316 icu_data[7].cascade_irq = 55;
317 icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
318 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
319 icu_data[7].virq_base, 0,
320 &irq_domain_simple_ops,
321 &icu_data[7]);
322 end = icu_data[7].virq_base + icu_data[7].nr_irqs;
323 for (irq = 0; irq < end; irq++) {
324 icu_mask_irq(irq_get_irq_data(irq));
325 if (irq == icu_data[1].cascade_irq ||
326 irq == icu_data[2].cascade_irq ||
327 irq == icu_data[3].cascade_irq ||
328 irq == icu_data[4].cascade_irq ||
329 irq == icu_data[5].cascade_irq ||
330 irq == icu_data[6].cascade_irq ||
331 irq == icu_data[7].cascade_irq) {
332 irq_set_chip(irq, &icu_irq_chip);
333 irq_set_chained_handler(irq, icu_mux_irq_demux);
334 } else {
335 irq_set_chip_and_handler(irq, &icu_irq_chip,
336 handle_level_irq);
337 }
338 }
339 irq_set_default_host(icu_data[0].domain);
340 set_handle_irq(mmp2_handle_irq);
341}
342
343#ifdef CONFIG_OF
344static int __init mmp_init_bases(struct device_node *node)
345{
346 int ret, nr_irqs, irq, i = 0;
347
348 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
349 if (ret) {
350 pr_err("Not found mrvl,intc-nr-irqs property\n");
351 return ret;
352 }
353
354 mmp_icu_base = of_iomap(node, 0);
355 if (!mmp_icu_base) {
356 pr_err("Failed to get interrupt controller register\n");
357 return -ENOMEM;
358 }
359
360 icu_data[0].virq_base = 0;
361 icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
362 &mmp_irq_domain_ops,
363 &icu_data[0]);
364 for (irq = 0; irq < nr_irqs; irq++) {
365 ret = irq_create_mapping(icu_data[0].domain, irq);
366 if (!ret) {
367 pr_err("Failed to mapping hwirq\n");
368 goto err;
369 }
370 if (!irq)
371 icu_data[0].virq_base = ret;
372 }
373 icu_data[0].nr_irqs = nr_irqs;
374 return 0;
375err:
376 if (icu_data[0].virq_base) {
377 for (i = 0; i < irq; i++)
378 irq_dispose_mapping(icu_data[0].virq_base + i);
379 }
380 irq_domain_remove(icu_data[0].domain);
381 iounmap(mmp_icu_base);
382 return -EINVAL;
383}
384
385static int __init mmp_of_init(struct device_node *node,
386 struct device_node *parent)
387{
388 int ret;
389
390 ret = mmp_init_bases(node);
391 if (ret < 0)
392 return ret;
393
394 icu_data[0].conf_enable = mmp_conf.conf_enable;
395 icu_data[0].conf_disable = mmp_conf.conf_disable;
396 icu_data[0].conf_mask = mmp_conf.conf_mask;
397 irq_set_default_host(icu_data[0].domain);
398 set_handle_irq(mmp_handle_irq);
399 max_icu_nr = 1;
400 return 0;
401}
402IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
403
404static int __init mmp2_of_init(struct device_node *node,
405 struct device_node *parent)
406{
407 int ret;
408
409 ret = mmp_init_bases(node);
410 if (ret < 0)
411 return ret;
412
413 icu_data[0].conf_enable = mmp2_conf.conf_enable;
414 icu_data[0].conf_disable = mmp2_conf.conf_disable;
415 icu_data[0].conf_mask = mmp2_conf.conf_mask;
416 irq_set_default_host(icu_data[0].domain);
417 set_handle_irq(mmp2_handle_irq);
418 max_icu_nr = 1;
419 return 0;
420}
421IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
422
423static int __init mmp2_mux_of_init(struct device_node *node,
424 struct device_node *parent)
425{
426 struct resource res;
427 int i, ret, irq, j = 0;
428 u32 nr_irqs, mfp_irq;
429
430 if (!parent)
431 return -ENODEV;
432
433 i = max_icu_nr;
434 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
435 &nr_irqs);
436 if (ret) {
437 pr_err("Not found mrvl,intc-nr-irqs property\n");
438 return -EINVAL;
439 }
440 ret = of_address_to_resource(node, 0, &res);
441 if (ret < 0) {
442 pr_err("Not found reg property\n");
443 return -EINVAL;
444 }
445 icu_data[i].reg_status = mmp_icu_base + res.start;
446 ret = of_address_to_resource(node, 1, &res);
447 if (ret < 0) {
448 pr_err("Not found reg property\n");
449 return -EINVAL;
450 }
451 icu_data[i].reg_mask = mmp_icu_base + res.start;
452 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
453 if (!icu_data[i].cascade_irq)
454 return -EINVAL;
455
456 icu_data[i].virq_base = 0;
457 icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
458 &mmp_irq_domain_ops,
459 &icu_data[i]);
460 for (irq = 0; irq < nr_irqs; irq++) {
461 ret = irq_create_mapping(icu_data[i].domain, irq);
462 if (!ret) {
463 pr_err("Failed to mapping hwirq\n");
464 goto err;
465 }
466 if (!irq)
467 icu_data[i].virq_base = ret;
468 }
469 icu_data[i].nr_irqs = nr_irqs;
470 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
471 &mfp_irq)) {
472 icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
473 icu_data[i].clr_mfp_hwirq = mfp_irq;
474 }
475 irq_set_chained_handler(icu_data[i].cascade_irq,
476 icu_mux_irq_demux);
477 max_icu_nr++;
478 return 0;
479err:
480 if (icu_data[i].virq_base) {
481 for (j = 0; j < irq; j++)
482 irq_dispose_mapping(icu_data[i].virq_base + j);
483 }
484 irq_domain_remove(icu_data[i].domain);
485 return -EINVAL;
486}
487IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
488#endif