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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * i8042 keyboard and mouse controller driver for Linux
4 *
5 * Copyright (c) 1999-2004 Vojtech Pavlik
6 */
7
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/types.h>
12#include <linux/delay.h>
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/init.h>
17#include <linux/serio.h>
18#include <linux/err.h>
19#include <linux/rcupdate.h>
20#include <linux/platform_device.h>
21#include <linux/i8042.h>
22#include <linux/slab.h>
23#include <linux/suspend.h>
24#include <linux/property.h>
25
26#include <asm/io.h>
27
28MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
29MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
30MODULE_LICENSE("GPL");
31
32static bool i8042_nokbd;
33module_param_named(nokbd, i8042_nokbd, bool, 0);
34MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
35
36static bool i8042_noaux;
37module_param_named(noaux, i8042_noaux, bool, 0);
38MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
39
40static bool i8042_nomux;
41module_param_named(nomux, i8042_nomux, bool, 0);
42MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
43
44static bool i8042_unlock;
45module_param_named(unlock, i8042_unlock, bool, 0);
46MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
47
48static bool i8042_probe_defer;
49module_param_named(probe_defer, i8042_probe_defer, bool, 0);
50MODULE_PARM_DESC(probe_defer, "Allow deferred probing.");
51
52enum i8042_controller_reset_mode {
53 I8042_RESET_NEVER,
54 I8042_RESET_ALWAYS,
55 I8042_RESET_ON_S2RAM,
56#define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM
57};
58static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT;
59static int i8042_set_reset(const char *val, const struct kernel_param *kp)
60{
61 enum i8042_controller_reset_mode *arg = kp->arg;
62 int error;
63 bool reset;
64
65 if (val) {
66 error = kstrtobool(val, &reset);
67 if (error)
68 return error;
69 } else {
70 reset = true;
71 }
72
73 *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER;
74 return 0;
75}
76
77static const struct kernel_param_ops param_ops_reset_param = {
78 .flags = KERNEL_PARAM_OPS_FL_NOARG,
79 .set = i8042_set_reset,
80};
81#define param_check_reset_param(name, p) \
82 __param_check(name, p, enum i8042_controller_reset_mode)
83module_param_named(reset, i8042_reset, reset_param, 0);
84MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both");
85
86static bool i8042_direct;
87module_param_named(direct, i8042_direct, bool, 0);
88MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
89
90static bool i8042_dumbkbd;
91module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
92MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
93
94static bool i8042_noloop;
95module_param_named(noloop, i8042_noloop, bool, 0);
96MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
97
98static bool i8042_notimeout;
99module_param_named(notimeout, i8042_notimeout, bool, 0);
100MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
101
102static bool i8042_kbdreset;
103module_param_named(kbdreset, i8042_kbdreset, bool, 0);
104MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port");
105
106#ifdef CONFIG_X86
107static bool i8042_dritek;
108module_param_named(dritek, i8042_dritek, bool, 0);
109MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
110#endif
111
112#ifdef CONFIG_PNP
113static bool i8042_nopnp;
114module_param_named(nopnp, i8042_nopnp, bool, 0);
115MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
116#endif
117
118#define DEBUG
119#ifdef DEBUG
120static bool i8042_debug;
121module_param_named(debug, i8042_debug, bool, 0600);
122MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
123
124static bool i8042_unmask_kbd_data;
125module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600);
126MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]");
127#endif
128
129static bool i8042_present;
130static bool i8042_bypass_aux_irq_test;
131static char i8042_kbd_firmware_id[128];
132static char i8042_aux_firmware_id[128];
133static struct fwnode_handle *i8042_kbd_fwnode;
134
135#include "i8042.h"
136
137/*
138 * i8042_lock protects serialization between i8042_command and
139 * the interrupt handler.
140 */
141static DEFINE_SPINLOCK(i8042_lock);
142
143/*
144 * Writers to AUX and KBD ports as well as users issuing i8042_command
145 * directly should acquire i8042_mutex (by means of calling
146 * i8042_lock_chip() and i8042_unlock_chip() helpers) to ensure that
147 * they do not disturb each other (unfortunately in many i8042
148 * implementations write to one of the ports will immediately abort
149 * command that is being processed by another port).
150 */
151static DEFINE_MUTEX(i8042_mutex);
152
153struct i8042_port {
154 struct serio *serio;
155 int irq;
156 bool exists;
157 bool driver_bound;
158 signed char mux;
159};
160
161#define I8042_KBD_PORT_NO 0
162#define I8042_AUX_PORT_NO 1
163#define I8042_MUX_PORT_NO 2
164#define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
165
166static struct i8042_port i8042_ports[I8042_NUM_PORTS];
167
168static unsigned char i8042_initial_ctr;
169static unsigned char i8042_ctr;
170static bool i8042_mux_present;
171static bool i8042_kbd_irq_registered;
172static bool i8042_aux_irq_registered;
173static unsigned char i8042_suppress_kbd_ack;
174static struct platform_device *i8042_platform_device;
175static struct notifier_block i8042_kbd_bind_notifier_block;
176
177static irqreturn_t i8042_interrupt(int irq, void *dev_id);
178static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
179 struct serio *serio);
180
181void i8042_lock_chip(void)
182{
183 mutex_lock(&i8042_mutex);
184}
185EXPORT_SYMBOL(i8042_lock_chip);
186
187void i8042_unlock_chip(void)
188{
189 mutex_unlock(&i8042_mutex);
190}
191EXPORT_SYMBOL(i8042_unlock_chip);
192
193int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
194 struct serio *serio))
195{
196 unsigned long flags;
197 int ret = 0;
198
199 spin_lock_irqsave(&i8042_lock, flags);
200
201 if (i8042_platform_filter) {
202 ret = -EBUSY;
203 goto out;
204 }
205
206 i8042_platform_filter = filter;
207
208out:
209 spin_unlock_irqrestore(&i8042_lock, flags);
210 return ret;
211}
212EXPORT_SYMBOL(i8042_install_filter);
213
214int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
215 struct serio *port))
216{
217 unsigned long flags;
218 int ret = 0;
219
220 spin_lock_irqsave(&i8042_lock, flags);
221
222 if (i8042_platform_filter != filter) {
223 ret = -EINVAL;
224 goto out;
225 }
226
227 i8042_platform_filter = NULL;
228
229out:
230 spin_unlock_irqrestore(&i8042_lock, flags);
231 return ret;
232}
233EXPORT_SYMBOL(i8042_remove_filter);
234
235/*
236 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
237 * be ready for reading values from it / writing values to it.
238 * Called always with i8042_lock held.
239 */
240
241static int i8042_wait_read(void)
242{
243 int i = 0;
244
245 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
246 udelay(50);
247 i++;
248 }
249 return -(i == I8042_CTL_TIMEOUT);
250}
251
252static int i8042_wait_write(void)
253{
254 int i = 0;
255
256 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
257 udelay(50);
258 i++;
259 }
260 return -(i == I8042_CTL_TIMEOUT);
261}
262
263/*
264 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
265 * of the i8042 down the toilet.
266 */
267
268static int i8042_flush(void)
269{
270 unsigned long flags;
271 unsigned char data, str;
272 int count = 0;
273 int retval = 0;
274
275 spin_lock_irqsave(&i8042_lock, flags);
276
277 while ((str = i8042_read_status()) & I8042_STR_OBF) {
278 if (count++ < I8042_BUFFER_SIZE) {
279 udelay(50);
280 data = i8042_read_data();
281 dbg("%02x <- i8042 (flush, %s)\n",
282 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
283 } else {
284 retval = -EIO;
285 break;
286 }
287 }
288
289 spin_unlock_irqrestore(&i8042_lock, flags);
290
291 return retval;
292}
293
294/*
295 * i8042_command() executes a command on the i8042. It also sends the input
296 * parameter(s) of the commands to it, and receives the output value(s). The
297 * parameters are to be stored in the param array, and the output is placed
298 * into the same array. The number of the parameters and output values is
299 * encoded in bits 8-11 of the command number.
300 */
301
302static int __i8042_command(unsigned char *param, int command)
303{
304 int i, error;
305
306 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
307 return -1;
308
309 error = i8042_wait_write();
310 if (error)
311 return error;
312
313 dbg("%02x -> i8042 (command)\n", command & 0xff);
314 i8042_write_command(command & 0xff);
315
316 for (i = 0; i < ((command >> 12) & 0xf); i++) {
317 error = i8042_wait_write();
318 if (error) {
319 dbg(" -- i8042 (wait write timeout)\n");
320 return error;
321 }
322 dbg("%02x -> i8042 (parameter)\n", param[i]);
323 i8042_write_data(param[i]);
324 }
325
326 for (i = 0; i < ((command >> 8) & 0xf); i++) {
327 error = i8042_wait_read();
328 if (error) {
329 dbg(" -- i8042 (wait read timeout)\n");
330 return error;
331 }
332
333 if (command == I8042_CMD_AUX_LOOP &&
334 !(i8042_read_status() & I8042_STR_AUXDATA)) {
335 dbg(" -- i8042 (auxerr)\n");
336 return -1;
337 }
338
339 param[i] = i8042_read_data();
340 dbg("%02x <- i8042 (return)\n", param[i]);
341 }
342
343 return 0;
344}
345
346int i8042_command(unsigned char *param, int command)
347{
348 unsigned long flags;
349 int retval;
350
351 if (!i8042_present)
352 return -1;
353
354 spin_lock_irqsave(&i8042_lock, flags);
355 retval = __i8042_command(param, command);
356 spin_unlock_irqrestore(&i8042_lock, flags);
357
358 return retval;
359}
360EXPORT_SYMBOL(i8042_command);
361
362/*
363 * i8042_kbd_write() sends a byte out through the keyboard interface.
364 */
365
366static int i8042_kbd_write(struct serio *port, unsigned char c)
367{
368 unsigned long flags;
369 int retval = 0;
370
371 spin_lock_irqsave(&i8042_lock, flags);
372
373 if (!(retval = i8042_wait_write())) {
374 dbg("%02x -> i8042 (kbd-data)\n", c);
375 i8042_write_data(c);
376 }
377
378 spin_unlock_irqrestore(&i8042_lock, flags);
379
380 return retval;
381}
382
383/*
384 * i8042_aux_write() sends a byte out through the aux interface.
385 */
386
387static int i8042_aux_write(struct serio *serio, unsigned char c)
388{
389 struct i8042_port *port = serio->port_data;
390
391 return i8042_command(&c, port->mux == -1 ?
392 I8042_CMD_AUX_SEND :
393 I8042_CMD_MUX_SEND + port->mux);
394}
395
396
397/*
398 * i8042_port_close attempts to clear AUX or KBD port state by disabling
399 * and then re-enabling it.
400 */
401
402static void i8042_port_close(struct serio *serio)
403{
404 int irq_bit;
405 int disable_bit;
406 const char *port_name;
407
408 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
409 irq_bit = I8042_CTR_AUXINT;
410 disable_bit = I8042_CTR_AUXDIS;
411 port_name = "AUX";
412 } else {
413 irq_bit = I8042_CTR_KBDINT;
414 disable_bit = I8042_CTR_KBDDIS;
415 port_name = "KBD";
416 }
417
418 i8042_ctr &= ~irq_bit;
419 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
420 pr_warn("Can't write CTR while closing %s port\n", port_name);
421
422 udelay(50);
423
424 i8042_ctr &= ~disable_bit;
425 i8042_ctr |= irq_bit;
426 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
427 pr_err("Can't reactivate %s port\n", port_name);
428
429 /*
430 * See if there is any data appeared while we were messing with
431 * port state.
432 */
433 i8042_interrupt(0, NULL);
434}
435
436/*
437 * i8042_start() is called by serio core when port is about to finish
438 * registering. It will mark port as existing so i8042_interrupt can
439 * start sending data through it.
440 */
441static int i8042_start(struct serio *serio)
442{
443 struct i8042_port *port = serio->port_data;
444
445 device_set_wakeup_capable(&serio->dev, true);
446
447 /*
448 * On platforms using suspend-to-idle, allow the keyboard to
449 * wake up the system from sleep by enabling keyboard wakeups
450 * by default. This is consistent with keyboard wakeup
451 * behavior on many platforms using suspend-to-RAM (ACPI S3)
452 * by default.
453 */
454 if (pm_suspend_default_s2idle() &&
455 serio == i8042_ports[I8042_KBD_PORT_NO].serio) {
456 device_set_wakeup_enable(&serio->dev, true);
457 }
458
459 spin_lock_irq(&i8042_lock);
460 port->exists = true;
461 spin_unlock_irq(&i8042_lock);
462
463 return 0;
464}
465
466/*
467 * i8042_stop() marks serio port as non-existing so i8042_interrupt
468 * will not try to send data to the port that is about to go away.
469 * The function is called by serio core as part of unregister procedure.
470 */
471static void i8042_stop(struct serio *serio)
472{
473 struct i8042_port *port = serio->port_data;
474
475 spin_lock_irq(&i8042_lock);
476 port->exists = false;
477 port->serio = NULL;
478 spin_unlock_irq(&i8042_lock);
479
480 /*
481 * We need to make sure that interrupt handler finishes using
482 * our serio port before we return from this function.
483 * We synchronize with both AUX and KBD IRQs because there is
484 * a (very unlikely) chance that AUX IRQ is raised for KBD port
485 * and vice versa.
486 */
487 synchronize_irq(I8042_AUX_IRQ);
488 synchronize_irq(I8042_KBD_IRQ);
489}
490
491/*
492 * i8042_filter() filters out unwanted bytes from the input data stream.
493 * It is called from i8042_interrupt and thus is running with interrupts
494 * off and i8042_lock held.
495 */
496static bool i8042_filter(unsigned char data, unsigned char str,
497 struct serio *serio)
498{
499 if (unlikely(i8042_suppress_kbd_ack)) {
500 if ((~str & I8042_STR_AUXDATA) &&
501 (data == 0xfa || data == 0xfe)) {
502 i8042_suppress_kbd_ack--;
503 dbg("Extra keyboard ACK - filtered out\n");
504 return true;
505 }
506 }
507
508 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
509 dbg("Filtered out by platform filter\n");
510 return true;
511 }
512
513 return false;
514}
515
516/*
517 * i8042_interrupt() is the most important function in this driver -
518 * it handles the interrupts from the i8042, and sends incoming bytes
519 * to the upper layers.
520 */
521
522static irqreturn_t i8042_interrupt(int irq, void *dev_id)
523{
524 struct i8042_port *port;
525 struct serio *serio;
526 unsigned long flags;
527 unsigned char str, data;
528 unsigned int dfl;
529 unsigned int port_no;
530 bool filtered;
531 int ret = 1;
532
533 spin_lock_irqsave(&i8042_lock, flags);
534
535 str = i8042_read_status();
536 if (unlikely(~str & I8042_STR_OBF)) {
537 spin_unlock_irqrestore(&i8042_lock, flags);
538 if (irq)
539 dbg("Interrupt %d, without any data\n", irq);
540 ret = 0;
541 goto out;
542 }
543
544 data = i8042_read_data();
545
546 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
547 static unsigned long last_transmit;
548 static unsigned char last_str;
549
550 dfl = 0;
551 if (str & I8042_STR_MUXERR) {
552 dbg("MUX error, status is %02x, data is %02x\n",
553 str, data);
554/*
555 * When MUXERR condition is signalled the data register can only contain
556 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
557 * it is not always the case. Some KBCs also report 0xfc when there is
558 * nothing connected to the port while others sometimes get confused which
559 * port the data came from and signal error leaving the data intact. They
560 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
561 * to legacy mode yet, when we see one we'll add proper handling).
562 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
563 * rest assume that the data came from the same serio last byte
564 * was transmitted (if transmission happened not too long ago).
565 */
566
567 switch (data) {
568 default:
569 if (time_before(jiffies, last_transmit + HZ/10)) {
570 str = last_str;
571 break;
572 }
573 fallthrough; /* report timeout */
574 case 0xfc:
575 case 0xfd:
576 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
577 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
578 }
579 }
580
581 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
582 last_str = str;
583 last_transmit = jiffies;
584 } else {
585
586 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
587 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0);
588
589 port_no = (str & I8042_STR_AUXDATA) ?
590 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
591 }
592
593 port = &i8042_ports[port_no];
594 serio = port->exists ? port->serio : NULL;
595
596 filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n",
597 port_no, irq,
598 dfl & SERIO_PARITY ? ", bad parity" : "",
599 dfl & SERIO_TIMEOUT ? ", timeout" : "");
600
601 filtered = i8042_filter(data, str, serio);
602
603 spin_unlock_irqrestore(&i8042_lock, flags);
604
605 if (likely(serio && !filtered))
606 serio_interrupt(serio, data, dfl);
607
608 out:
609 return IRQ_RETVAL(ret);
610}
611
612/*
613 * i8042_enable_kbd_port enables keyboard port on chip
614 */
615
616static int i8042_enable_kbd_port(void)
617{
618 i8042_ctr &= ~I8042_CTR_KBDDIS;
619 i8042_ctr |= I8042_CTR_KBDINT;
620
621 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
622 i8042_ctr &= ~I8042_CTR_KBDINT;
623 i8042_ctr |= I8042_CTR_KBDDIS;
624 pr_err("Failed to enable KBD port\n");
625 return -EIO;
626 }
627
628 return 0;
629}
630
631/*
632 * i8042_enable_aux_port enables AUX (mouse) port on chip
633 */
634
635static int i8042_enable_aux_port(void)
636{
637 i8042_ctr &= ~I8042_CTR_AUXDIS;
638 i8042_ctr |= I8042_CTR_AUXINT;
639
640 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
641 i8042_ctr &= ~I8042_CTR_AUXINT;
642 i8042_ctr |= I8042_CTR_AUXDIS;
643 pr_err("Failed to enable AUX port\n");
644 return -EIO;
645 }
646
647 return 0;
648}
649
650/*
651 * i8042_enable_mux_ports enables 4 individual AUX ports after
652 * the controller has been switched into Multiplexed mode
653 */
654
655static int i8042_enable_mux_ports(void)
656{
657 unsigned char param;
658 int i;
659
660 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
661 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
662 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
663 }
664
665 return i8042_enable_aux_port();
666}
667
668/*
669 * i8042_set_mux_mode checks whether the controller has an
670 * active multiplexor and puts the chip into Multiplexed (true)
671 * or Legacy (false) mode.
672 */
673
674static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
675{
676
677 unsigned char param, val;
678/*
679 * Get rid of bytes in the queue.
680 */
681
682 i8042_flush();
683
684/*
685 * Internal loopback test - send three bytes, they should come back from the
686 * mouse interface, the last should be version.
687 */
688
689 param = val = 0xf0;
690 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
691 return -1;
692 param = val = multiplex ? 0x56 : 0xf6;
693 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
694 return -1;
695 param = val = multiplex ? 0xa4 : 0xa5;
696 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
697 return -1;
698
699/*
700 * Workaround for interference with USB Legacy emulation
701 * that causes a v10.12 MUX to be found.
702 */
703 if (param == 0xac)
704 return -1;
705
706 if (mux_version)
707 *mux_version = param;
708
709 return 0;
710}
711
712/*
713 * i8042_check_mux() checks whether the controller supports the PS/2 Active
714 * Multiplexing specification by Synaptics, Phoenix, Insyde and
715 * LCS/Telegraphics.
716 */
717
718static int i8042_check_mux(void)
719{
720 unsigned char mux_version;
721
722 if (i8042_set_mux_mode(true, &mux_version))
723 return -1;
724
725 pr_info("Detected active multiplexing controller, rev %d.%d\n",
726 (mux_version >> 4) & 0xf, mux_version & 0xf);
727
728/*
729 * Disable all muxed ports by disabling AUX.
730 */
731 i8042_ctr |= I8042_CTR_AUXDIS;
732 i8042_ctr &= ~I8042_CTR_AUXINT;
733
734 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
735 pr_err("Failed to disable AUX port, can't use MUX\n");
736 return -EIO;
737 }
738
739 i8042_mux_present = true;
740
741 return 0;
742}
743
744/*
745 * The following is used to test AUX IRQ delivery.
746 */
747static struct completion i8042_aux_irq_delivered;
748static bool i8042_irq_being_tested;
749
750static irqreturn_t i8042_aux_test_irq(int irq, void *dev_id)
751{
752 unsigned long flags;
753 unsigned char str, data;
754 int ret = 0;
755
756 spin_lock_irqsave(&i8042_lock, flags);
757 str = i8042_read_status();
758 if (str & I8042_STR_OBF) {
759 data = i8042_read_data();
760 dbg("%02x <- i8042 (aux_test_irq, %s)\n",
761 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
762 if (i8042_irq_being_tested &&
763 data == 0xa5 && (str & I8042_STR_AUXDATA))
764 complete(&i8042_aux_irq_delivered);
765 ret = 1;
766 }
767 spin_unlock_irqrestore(&i8042_lock, flags);
768
769 return IRQ_RETVAL(ret);
770}
771
772/*
773 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
774 * verifies success by readinng CTR. Used when testing for presence of AUX
775 * port.
776 */
777static int i8042_toggle_aux(bool on)
778{
779 unsigned char param;
780 int i;
781
782 if (i8042_command(¶m,
783 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
784 return -1;
785
786 /* some chips need some time to set the I8042_CTR_AUXDIS bit */
787 for (i = 0; i < 100; i++) {
788 udelay(50);
789
790 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
791 return -1;
792
793 if (!(param & I8042_CTR_AUXDIS) == on)
794 return 0;
795 }
796
797 return -1;
798}
799
800/*
801 * i8042_check_aux() applies as much paranoia as it can at detecting
802 * the presence of an AUX interface.
803 */
804
805static int i8042_check_aux(void)
806{
807 int retval = -1;
808 bool irq_registered = false;
809 bool aux_loop_broken = false;
810 unsigned long flags;
811 unsigned char param;
812
813/*
814 * Get rid of bytes in the queue.
815 */
816
817 i8042_flush();
818
819/*
820 * Internal loopback test - filters out AT-type i8042's. Unfortunately
821 * SiS screwed up and their 5597 doesn't support the LOOP command even
822 * though it has an AUX port.
823 */
824
825 param = 0x5a;
826 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
827 if (retval || param != 0x5a) {
828
829/*
830 * External connection test - filters out AT-soldered PS/2 i8042's
831 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
832 * 0xfa - no error on some notebooks which ignore the spec
833 * Because it's common for chipsets to return error on perfectly functioning
834 * AUX ports, we test for this only when the LOOP command failed.
835 */
836
837 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
838 (param && param != 0xfa && param != 0xff))
839 return -1;
840
841/*
842 * If AUX_LOOP completed without error but returned unexpected data
843 * mark it as broken
844 */
845 if (!retval)
846 aux_loop_broken = true;
847 }
848
849/*
850 * Bit assignment test - filters out PS/2 i8042's in AT mode
851 */
852
853 if (i8042_toggle_aux(false)) {
854 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
855 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
856 }
857
858 if (i8042_toggle_aux(true))
859 return -1;
860
861/*
862 * Reset keyboard (needed on some laptops to successfully detect
863 * touchpad, e.g., some Gigabyte laptop models with Elantech
864 * touchpads).
865 */
866 if (i8042_kbdreset) {
867 pr_warn("Attempting to reset device connected to KBD port\n");
868 i8042_kbd_write(NULL, (unsigned char) 0xff);
869 }
870
871/*
872 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
873 * used it for a PCI card or somethig else.
874 */
875
876 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
877/*
878 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
879 * is working and hope we are right.
880 */
881 retval = 0;
882 goto out;
883 }
884
885 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
886 "i8042", i8042_platform_device))
887 goto out;
888
889 irq_registered = true;
890
891 if (i8042_enable_aux_port())
892 goto out;
893
894 spin_lock_irqsave(&i8042_lock, flags);
895
896 init_completion(&i8042_aux_irq_delivered);
897 i8042_irq_being_tested = true;
898
899 param = 0xa5;
900 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
901
902 spin_unlock_irqrestore(&i8042_lock, flags);
903
904 if (retval)
905 goto out;
906
907 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
908 msecs_to_jiffies(250)) == 0) {
909/*
910 * AUX IRQ was never delivered so we need to flush the controller to
911 * get rid of the byte we put there; otherwise keyboard may not work.
912 */
913 dbg(" -- i8042 (aux irq test timeout)\n");
914 i8042_flush();
915 retval = -1;
916 }
917
918 out:
919
920/*
921 * Disable the interface.
922 */
923
924 i8042_ctr |= I8042_CTR_AUXDIS;
925 i8042_ctr &= ~I8042_CTR_AUXINT;
926
927 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
928 retval = -1;
929
930 if (irq_registered)
931 free_irq(I8042_AUX_IRQ, i8042_platform_device);
932
933 return retval;
934}
935
936static int i8042_controller_check(void)
937{
938 if (i8042_flush()) {
939 pr_info("No controller found\n");
940 return -ENODEV;
941 }
942
943 return 0;
944}
945
946static int i8042_controller_selftest(void)
947{
948 unsigned char param;
949 int i = 0;
950
951 /*
952 * We try this 5 times; on some really fragile systems this does not
953 * take the first time...
954 */
955 do {
956
957 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
958 pr_err("i8042 controller selftest timeout\n");
959 return -ENODEV;
960 }
961
962 if (param == I8042_RET_CTL_TEST)
963 return 0;
964
965 dbg("i8042 controller selftest: %#x != %#x\n",
966 param, I8042_RET_CTL_TEST);
967 msleep(50);
968 } while (i++ < 5);
969
970#ifdef CONFIG_X86
971 /*
972 * On x86, we don't fail entire i8042 initialization if controller
973 * reset fails in hopes that keyboard port will still be functional
974 * and user will still get a working keyboard. This is especially
975 * important on netbooks. On other arches we trust hardware more.
976 */
977 pr_info("giving up on controller selftest, continuing anyway...\n");
978 return 0;
979#else
980 pr_err("i8042 controller selftest failed\n");
981 return -EIO;
982#endif
983}
984
985/*
986 * i8042_controller_init initializes the i8042 controller, and,
987 * most importantly, sets it into non-xlated mode if that's
988 * desired.
989 */
990
991static int i8042_controller_init(void)
992{
993 unsigned long flags;
994 int n = 0;
995 unsigned char ctr[2];
996
997/*
998 * Save the CTR for restore on unload / reboot.
999 */
1000
1001 do {
1002 if (n >= 10) {
1003 pr_err("Unable to get stable CTR read\n");
1004 return -EIO;
1005 }
1006
1007 if (n != 0)
1008 udelay(50);
1009
1010 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
1011 pr_err("Can't read CTR while initializing i8042\n");
1012 return i8042_probe_defer ? -EPROBE_DEFER : -EIO;
1013 }
1014
1015 } while (n < 2 || ctr[0] != ctr[1]);
1016
1017 i8042_initial_ctr = i8042_ctr = ctr[0];
1018
1019/*
1020 * Disable the keyboard interface and interrupt.
1021 */
1022
1023 i8042_ctr |= I8042_CTR_KBDDIS;
1024 i8042_ctr &= ~I8042_CTR_KBDINT;
1025
1026/*
1027 * Handle keylock.
1028 */
1029
1030 spin_lock_irqsave(&i8042_lock, flags);
1031 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
1032 if (i8042_unlock)
1033 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
1034 else
1035 pr_warn("Warning: Keylock active\n");
1036 }
1037 spin_unlock_irqrestore(&i8042_lock, flags);
1038
1039/*
1040 * If the chip is configured into nontranslated mode by the BIOS, don't
1041 * bother enabling translating and be happy.
1042 */
1043
1044 if (~i8042_ctr & I8042_CTR_XLATE)
1045 i8042_direct = true;
1046
1047/*
1048 * Set nontranslated mode for the kbd interface if requested by an option.
1049 * After this the kbd interface becomes a simple serial in/out, like the aux
1050 * interface is. We don't do this by default, since it can confuse notebook
1051 * BIOSes.
1052 */
1053
1054 if (i8042_direct)
1055 i8042_ctr &= ~I8042_CTR_XLATE;
1056
1057/*
1058 * Write CTR back.
1059 */
1060
1061 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1062 pr_err("Can't write CTR while initializing i8042\n");
1063 return -EIO;
1064 }
1065
1066/*
1067 * Flush whatever accumulated while we were disabling keyboard port.
1068 */
1069
1070 i8042_flush();
1071
1072 return 0;
1073}
1074
1075
1076/*
1077 * Reset the controller and reset CRT to the original value set by BIOS.
1078 */
1079
1080static void i8042_controller_reset(bool s2r_wants_reset)
1081{
1082 i8042_flush();
1083
1084/*
1085 * Disable both KBD and AUX interfaces so they don't get in the way
1086 */
1087
1088 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1089 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1090
1091 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1092 pr_warn("Can't write CTR while resetting\n");
1093
1094/*
1095 * Disable MUX mode if present.
1096 */
1097
1098 if (i8042_mux_present)
1099 i8042_set_mux_mode(false, NULL);
1100
1101/*
1102 * Reset the controller if requested.
1103 */
1104
1105 if (i8042_reset == I8042_RESET_ALWAYS ||
1106 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) {
1107 i8042_controller_selftest();
1108 }
1109
1110/*
1111 * Restore the original control register setting.
1112 */
1113
1114 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1115 pr_warn("Can't restore CTR\n");
1116}
1117
1118
1119/*
1120 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called
1121 * when kernel panics. Flashing LEDs is useful for users running X who may
1122 * not see the console and will help distinguishing panics from "real"
1123 * lockups.
1124 *
1125 * Note that DELAY has a limit of 10ms so we will not get stuck here
1126 * waiting for KBC to free up even if KBD interrupt is off
1127 */
1128
1129#define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1130
1131static long i8042_panic_blink(int state)
1132{
1133 long delay = 0;
1134 char led;
1135
1136 led = (state) ? 0x01 | 0x04 : 0;
1137 while (i8042_read_status() & I8042_STR_IBF)
1138 DELAY;
1139 dbg("%02x -> i8042 (panic blink)\n", 0xed);
1140 i8042_suppress_kbd_ack = 2;
1141 i8042_write_data(0xed); /* set leds */
1142 DELAY;
1143 while (i8042_read_status() & I8042_STR_IBF)
1144 DELAY;
1145 DELAY;
1146 dbg("%02x -> i8042 (panic blink)\n", led);
1147 i8042_write_data(led);
1148 DELAY;
1149 return delay;
1150}
1151
1152#undef DELAY
1153
1154#ifdef CONFIG_X86
1155static void i8042_dritek_enable(void)
1156{
1157 unsigned char param = 0x90;
1158 int error;
1159
1160 error = i8042_command(¶m, 0x1059);
1161 if (error)
1162 pr_warn("Failed to enable DRITEK extension: %d\n", error);
1163}
1164#endif
1165
1166#ifdef CONFIG_PM
1167
1168/*
1169 * Here we try to reset everything back to a state we had
1170 * before suspending.
1171 */
1172
1173static int i8042_controller_resume(bool s2r_wants_reset)
1174{
1175 int error;
1176
1177 error = i8042_controller_check();
1178 if (error)
1179 return error;
1180
1181 if (i8042_reset == I8042_RESET_ALWAYS ||
1182 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) {
1183 error = i8042_controller_selftest();
1184 if (error)
1185 return error;
1186 }
1187
1188/*
1189 * Restore original CTR value and disable all ports
1190 */
1191
1192 i8042_ctr = i8042_initial_ctr;
1193 if (i8042_direct)
1194 i8042_ctr &= ~I8042_CTR_XLATE;
1195 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1196 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1197 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1198 pr_warn("Can't write CTR to resume, retrying...\n");
1199 msleep(50);
1200 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1201 pr_err("CTR write retry failed\n");
1202 return -EIO;
1203 }
1204 }
1205
1206
1207#ifdef CONFIG_X86
1208 if (i8042_dritek)
1209 i8042_dritek_enable();
1210#endif
1211
1212 if (i8042_mux_present) {
1213 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1214 pr_warn("failed to resume active multiplexor, mouse won't work\n");
1215 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1216 i8042_enable_aux_port();
1217
1218 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1219 i8042_enable_kbd_port();
1220
1221 i8042_interrupt(0, NULL);
1222
1223 return 0;
1224}
1225
1226/*
1227 * Here we try to restore the original BIOS settings to avoid
1228 * upsetting it.
1229 */
1230
1231static int i8042_pm_suspend(struct device *dev)
1232{
1233 int i;
1234
1235 if (pm_suspend_via_firmware())
1236 i8042_controller_reset(true);
1237
1238 /* Set up serio interrupts for system wakeup. */
1239 for (i = 0; i < I8042_NUM_PORTS; i++) {
1240 struct serio *serio = i8042_ports[i].serio;
1241
1242 if (serio && device_may_wakeup(&serio->dev))
1243 enable_irq_wake(i8042_ports[i].irq);
1244 }
1245
1246 return 0;
1247}
1248
1249static int i8042_pm_resume_noirq(struct device *dev)
1250{
1251 if (!pm_resume_via_firmware())
1252 i8042_interrupt(0, NULL);
1253
1254 return 0;
1255}
1256
1257static int i8042_pm_resume(struct device *dev)
1258{
1259 bool want_reset;
1260 int i;
1261
1262 for (i = 0; i < I8042_NUM_PORTS; i++) {
1263 struct serio *serio = i8042_ports[i].serio;
1264
1265 if (serio && device_may_wakeup(&serio->dev))
1266 disable_irq_wake(i8042_ports[i].irq);
1267 }
1268
1269 /*
1270 * If platform firmware was not going to be involved in suspend, we did
1271 * not restore the controller state to whatever it had been at boot
1272 * time, so we do not need to do anything.
1273 */
1274 if (!pm_suspend_via_firmware())
1275 return 0;
1276
1277 /*
1278 * We only need to reset the controller if we are resuming after handing
1279 * off control to the platform firmware, otherwise we can simply restore
1280 * the mode.
1281 */
1282 want_reset = pm_resume_via_firmware();
1283
1284 return i8042_controller_resume(want_reset);
1285}
1286
1287static int i8042_pm_thaw(struct device *dev)
1288{
1289 i8042_interrupt(0, NULL);
1290
1291 return 0;
1292}
1293
1294static int i8042_pm_reset(struct device *dev)
1295{
1296 i8042_controller_reset(false);
1297
1298 return 0;
1299}
1300
1301static int i8042_pm_restore(struct device *dev)
1302{
1303 return i8042_controller_resume(false);
1304}
1305
1306static const struct dev_pm_ops i8042_pm_ops = {
1307 .suspend = i8042_pm_suspend,
1308 .resume_noirq = i8042_pm_resume_noirq,
1309 .resume = i8042_pm_resume,
1310 .thaw = i8042_pm_thaw,
1311 .poweroff = i8042_pm_reset,
1312 .restore = i8042_pm_restore,
1313};
1314
1315#endif /* CONFIG_PM */
1316
1317/*
1318 * We need to reset the 8042 back to original mode on system shutdown,
1319 * because otherwise BIOSes will be confused.
1320 */
1321
1322static void i8042_shutdown(struct platform_device *dev)
1323{
1324 i8042_controller_reset(false);
1325}
1326
1327static int i8042_create_kbd_port(void)
1328{
1329 struct serio *serio;
1330 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1331
1332 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1333 if (!serio)
1334 return -ENOMEM;
1335
1336 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1337 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1338 serio->start = i8042_start;
1339 serio->stop = i8042_stop;
1340 serio->close = i8042_port_close;
1341 serio->ps2_cmd_mutex = &i8042_mutex;
1342 serio->port_data = port;
1343 serio->dev.parent = &i8042_platform_device->dev;
1344 strscpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1345 strscpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1346 strscpy(serio->firmware_id, i8042_kbd_firmware_id,
1347 sizeof(serio->firmware_id));
1348 set_primary_fwnode(&serio->dev, i8042_kbd_fwnode);
1349
1350 port->serio = serio;
1351 port->irq = I8042_KBD_IRQ;
1352
1353 return 0;
1354}
1355
1356static int i8042_create_aux_port(int idx)
1357{
1358 struct serio *serio;
1359 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1360 struct i8042_port *port = &i8042_ports[port_no];
1361
1362 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1363 if (!serio)
1364 return -ENOMEM;
1365
1366 serio->id.type = SERIO_8042;
1367 serio->write = i8042_aux_write;
1368 serio->start = i8042_start;
1369 serio->stop = i8042_stop;
1370 serio->ps2_cmd_mutex = &i8042_mutex;
1371 serio->port_data = port;
1372 serio->dev.parent = &i8042_platform_device->dev;
1373 if (idx < 0) {
1374 strscpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1375 strscpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1376 strscpy(serio->firmware_id, i8042_aux_firmware_id,
1377 sizeof(serio->firmware_id));
1378 serio->close = i8042_port_close;
1379 } else {
1380 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1381 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1382 strscpy(serio->firmware_id, i8042_aux_firmware_id,
1383 sizeof(serio->firmware_id));
1384 }
1385
1386 port->serio = serio;
1387 port->mux = idx;
1388 port->irq = I8042_AUX_IRQ;
1389
1390 return 0;
1391}
1392
1393static void i8042_free_kbd_port(void)
1394{
1395 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1396 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1397}
1398
1399static void i8042_free_aux_ports(void)
1400{
1401 int i;
1402
1403 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1404 kfree(i8042_ports[i].serio);
1405 i8042_ports[i].serio = NULL;
1406 }
1407}
1408
1409static void i8042_register_ports(void)
1410{
1411 int i;
1412
1413 for (i = 0; i < I8042_NUM_PORTS; i++) {
1414 struct serio *serio = i8042_ports[i].serio;
1415
1416 if (!serio)
1417 continue;
1418
1419 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1420 serio->name,
1421 (unsigned long) I8042_DATA_REG,
1422 (unsigned long) I8042_COMMAND_REG,
1423 i8042_ports[i].irq);
1424 serio_register_port(serio);
1425 }
1426}
1427
1428static void i8042_unregister_ports(void)
1429{
1430 int i;
1431
1432 for (i = 0; i < I8042_NUM_PORTS; i++) {
1433 if (i8042_ports[i].serio) {
1434 serio_unregister_port(i8042_ports[i].serio);
1435 i8042_ports[i].serio = NULL;
1436 }
1437 }
1438}
1439
1440static void i8042_free_irqs(void)
1441{
1442 if (i8042_aux_irq_registered)
1443 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1444 if (i8042_kbd_irq_registered)
1445 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1446
1447 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1448}
1449
1450static int i8042_setup_aux(void)
1451{
1452 int (*aux_enable)(void);
1453 int error;
1454 int i;
1455
1456 if (i8042_check_aux())
1457 return -ENODEV;
1458
1459 if (i8042_nomux || i8042_check_mux()) {
1460 error = i8042_create_aux_port(-1);
1461 if (error)
1462 goto err_free_ports;
1463 aux_enable = i8042_enable_aux_port;
1464 } else {
1465 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1466 error = i8042_create_aux_port(i);
1467 if (error)
1468 goto err_free_ports;
1469 }
1470 aux_enable = i8042_enable_mux_ports;
1471 }
1472
1473 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1474 "i8042", i8042_platform_device);
1475 if (error)
1476 goto err_free_ports;
1477
1478 error = aux_enable();
1479 if (error)
1480 goto err_free_irq;
1481
1482 i8042_aux_irq_registered = true;
1483 return 0;
1484
1485 err_free_irq:
1486 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1487 err_free_ports:
1488 i8042_free_aux_ports();
1489 return error;
1490}
1491
1492static int i8042_setup_kbd(void)
1493{
1494 int error;
1495
1496 error = i8042_create_kbd_port();
1497 if (error)
1498 return error;
1499
1500 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1501 "i8042", i8042_platform_device);
1502 if (error)
1503 goto err_free_port;
1504
1505 error = i8042_enable_kbd_port();
1506 if (error)
1507 goto err_free_irq;
1508
1509 i8042_kbd_irq_registered = true;
1510 return 0;
1511
1512 err_free_irq:
1513 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1514 err_free_port:
1515 i8042_free_kbd_port();
1516 return error;
1517}
1518
1519static int i8042_kbd_bind_notifier(struct notifier_block *nb,
1520 unsigned long action, void *data)
1521{
1522 struct device *dev = data;
1523 struct serio *serio = to_serio_port(dev);
1524 struct i8042_port *port = serio->port_data;
1525
1526 if (serio != i8042_ports[I8042_KBD_PORT_NO].serio)
1527 return 0;
1528
1529 switch (action) {
1530 case BUS_NOTIFY_BOUND_DRIVER:
1531 port->driver_bound = true;
1532 break;
1533
1534 case BUS_NOTIFY_UNBIND_DRIVER:
1535 port->driver_bound = false;
1536 break;
1537 }
1538
1539 return 0;
1540}
1541
1542static int i8042_probe(struct platform_device *dev)
1543{
1544 int error;
1545
1546 if (i8042_reset == I8042_RESET_ALWAYS) {
1547 error = i8042_controller_selftest();
1548 if (error)
1549 return error;
1550 }
1551
1552 error = i8042_controller_init();
1553 if (error)
1554 return error;
1555
1556#ifdef CONFIG_X86
1557 if (i8042_dritek)
1558 i8042_dritek_enable();
1559#endif
1560
1561 if (!i8042_noaux) {
1562 error = i8042_setup_aux();
1563 if (error && error != -ENODEV && error != -EBUSY)
1564 goto out_fail;
1565 }
1566
1567 if (!i8042_nokbd) {
1568 error = i8042_setup_kbd();
1569 if (error)
1570 goto out_fail;
1571 }
1572/*
1573 * Ok, everything is ready, let's register all serio ports
1574 */
1575 i8042_register_ports();
1576
1577 return 0;
1578
1579 out_fail:
1580 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1581 i8042_free_irqs();
1582 i8042_controller_reset(false);
1583
1584 return error;
1585}
1586
1587static void i8042_remove(struct platform_device *dev)
1588{
1589 i8042_unregister_ports();
1590 i8042_free_irqs();
1591 i8042_controller_reset(false);
1592}
1593
1594static struct platform_driver i8042_driver = {
1595 .driver = {
1596 .name = "i8042",
1597#ifdef CONFIG_PM
1598 .pm = &i8042_pm_ops,
1599#endif
1600 },
1601 .probe = i8042_probe,
1602 .remove_new = i8042_remove,
1603 .shutdown = i8042_shutdown,
1604};
1605
1606static struct notifier_block i8042_kbd_bind_notifier_block = {
1607 .notifier_call = i8042_kbd_bind_notifier,
1608};
1609
1610static int __init i8042_init(void)
1611{
1612 int err;
1613
1614 dbg_init();
1615
1616 err = i8042_platform_init();
1617 if (err)
1618 return (err == -ENODEV) ? 0 : err;
1619
1620 err = i8042_controller_check();
1621 if (err)
1622 goto err_platform_exit;
1623
1624 /* Set this before creating the dev to allow i8042_command to work right away */
1625 i8042_present = true;
1626
1627 err = platform_driver_register(&i8042_driver);
1628 if (err)
1629 goto err_platform_exit;
1630
1631 i8042_platform_device = platform_device_alloc("i8042", -1);
1632 if (!i8042_platform_device) {
1633 err = -ENOMEM;
1634 goto err_unregister_driver;
1635 }
1636
1637 err = platform_device_add(i8042_platform_device);
1638 if (err)
1639 goto err_free_device;
1640
1641 bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
1642 panic_blink = i8042_panic_blink;
1643
1644 return 0;
1645
1646err_free_device:
1647 platform_device_put(i8042_platform_device);
1648err_unregister_driver:
1649 platform_driver_unregister(&i8042_driver);
1650 err_platform_exit:
1651 i8042_platform_exit();
1652 return err;
1653}
1654
1655static void __exit i8042_exit(void)
1656{
1657 if (!i8042_present)
1658 return;
1659
1660 platform_device_unregister(i8042_platform_device);
1661 platform_driver_unregister(&i8042_driver);
1662 i8042_platform_exit();
1663
1664 bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
1665 panic_blink = NULL;
1666}
1667
1668module_init(i8042_init);
1669module_exit(i8042_exit);
1/*
2 * i8042 keyboard and mouse controller driver for Linux
3 *
4 * Copyright (c) 1999-2004 Vojtech Pavlik
5 */
6
7/*
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/types.h>
16#include <linux/delay.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/ioport.h>
20#include <linux/init.h>
21#include <linux/serio.h>
22#include <linux/err.h>
23#include <linux/rcupdate.h>
24#include <linux/platform_device.h>
25#include <linux/i8042.h>
26#include <linux/slab.h>
27#include <linux/suspend.h>
28
29#include <asm/io.h>
30
31MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
32MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
33MODULE_LICENSE("GPL");
34
35static bool i8042_nokbd;
36module_param_named(nokbd, i8042_nokbd, bool, 0);
37MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
38
39static bool i8042_noaux;
40module_param_named(noaux, i8042_noaux, bool, 0);
41MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
42
43static bool i8042_nomux;
44module_param_named(nomux, i8042_nomux, bool, 0);
45MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
46
47static bool i8042_unlock;
48module_param_named(unlock, i8042_unlock, bool, 0);
49MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
50
51static bool i8042_reset;
52module_param_named(reset, i8042_reset, bool, 0);
53MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
54
55static bool i8042_direct;
56module_param_named(direct, i8042_direct, bool, 0);
57MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
58
59static bool i8042_dumbkbd;
60module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
61MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
62
63static bool i8042_noloop;
64module_param_named(noloop, i8042_noloop, bool, 0);
65MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
66
67static bool i8042_notimeout;
68module_param_named(notimeout, i8042_notimeout, bool, 0);
69MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
70
71static bool i8042_kbdreset;
72module_param_named(kbdreset, i8042_kbdreset, bool, 0);
73MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port");
74
75#ifdef CONFIG_X86
76static bool i8042_dritek;
77module_param_named(dritek, i8042_dritek, bool, 0);
78MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
79#endif
80
81#ifdef CONFIG_PNP
82static bool i8042_nopnp;
83module_param_named(nopnp, i8042_nopnp, bool, 0);
84MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
85#endif
86
87#define DEBUG
88#ifdef DEBUG
89static bool i8042_debug;
90module_param_named(debug, i8042_debug, bool, 0600);
91MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
92
93static bool i8042_unmask_kbd_data;
94module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600);
95MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]");
96#endif
97
98static bool i8042_bypass_aux_irq_test;
99static char i8042_kbd_firmware_id[128];
100static char i8042_aux_firmware_id[128];
101
102#include "i8042.h"
103
104/*
105 * i8042_lock protects serialization between i8042_command and
106 * the interrupt handler.
107 */
108static DEFINE_SPINLOCK(i8042_lock);
109
110/*
111 * Writers to AUX and KBD ports as well as users issuing i8042_command
112 * directly should acquire i8042_mutex (by means of calling
113 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that
114 * they do not disturb each other (unfortunately in many i8042
115 * implementations write to one of the ports will immediately abort
116 * command that is being processed by another port).
117 */
118static DEFINE_MUTEX(i8042_mutex);
119
120struct i8042_port {
121 struct serio *serio;
122 int irq;
123 bool exists;
124 bool driver_bound;
125 signed char mux;
126};
127
128#define I8042_KBD_PORT_NO 0
129#define I8042_AUX_PORT_NO 1
130#define I8042_MUX_PORT_NO 2
131#define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
132
133static struct i8042_port i8042_ports[I8042_NUM_PORTS];
134
135static unsigned char i8042_initial_ctr;
136static unsigned char i8042_ctr;
137static bool i8042_mux_present;
138static bool i8042_kbd_irq_registered;
139static bool i8042_aux_irq_registered;
140static unsigned char i8042_suppress_kbd_ack;
141static struct platform_device *i8042_platform_device;
142static struct notifier_block i8042_kbd_bind_notifier_block;
143
144static irqreturn_t i8042_interrupt(int irq, void *dev_id);
145static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
146 struct serio *serio);
147
148void i8042_lock_chip(void)
149{
150 mutex_lock(&i8042_mutex);
151}
152EXPORT_SYMBOL(i8042_lock_chip);
153
154void i8042_unlock_chip(void)
155{
156 mutex_unlock(&i8042_mutex);
157}
158EXPORT_SYMBOL(i8042_unlock_chip);
159
160int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
161 struct serio *serio))
162{
163 unsigned long flags;
164 int ret = 0;
165
166 spin_lock_irqsave(&i8042_lock, flags);
167
168 if (i8042_platform_filter) {
169 ret = -EBUSY;
170 goto out;
171 }
172
173 i8042_platform_filter = filter;
174
175out:
176 spin_unlock_irqrestore(&i8042_lock, flags);
177 return ret;
178}
179EXPORT_SYMBOL(i8042_install_filter);
180
181int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
182 struct serio *port))
183{
184 unsigned long flags;
185 int ret = 0;
186
187 spin_lock_irqsave(&i8042_lock, flags);
188
189 if (i8042_platform_filter != filter) {
190 ret = -EINVAL;
191 goto out;
192 }
193
194 i8042_platform_filter = NULL;
195
196out:
197 spin_unlock_irqrestore(&i8042_lock, flags);
198 return ret;
199}
200EXPORT_SYMBOL(i8042_remove_filter);
201
202/*
203 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
204 * be ready for reading values from it / writing values to it.
205 * Called always with i8042_lock held.
206 */
207
208static int i8042_wait_read(void)
209{
210 int i = 0;
211
212 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
213 udelay(50);
214 i++;
215 }
216 return -(i == I8042_CTL_TIMEOUT);
217}
218
219static int i8042_wait_write(void)
220{
221 int i = 0;
222
223 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
224 udelay(50);
225 i++;
226 }
227 return -(i == I8042_CTL_TIMEOUT);
228}
229
230/*
231 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
232 * of the i8042 down the toilet.
233 */
234
235static int i8042_flush(void)
236{
237 unsigned long flags;
238 unsigned char data, str;
239 int count = 0;
240 int retval = 0;
241
242 spin_lock_irqsave(&i8042_lock, flags);
243
244 while ((str = i8042_read_status()) & I8042_STR_OBF) {
245 if (count++ < I8042_BUFFER_SIZE) {
246 udelay(50);
247 data = i8042_read_data();
248 dbg("%02x <- i8042 (flush, %s)\n",
249 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
250 } else {
251 retval = -EIO;
252 break;
253 }
254 }
255
256 spin_unlock_irqrestore(&i8042_lock, flags);
257
258 return retval;
259}
260
261/*
262 * i8042_command() executes a command on the i8042. It also sends the input
263 * parameter(s) of the commands to it, and receives the output value(s). The
264 * parameters are to be stored in the param array, and the output is placed
265 * into the same array. The number of the parameters and output values is
266 * encoded in bits 8-11 of the command number.
267 */
268
269static int __i8042_command(unsigned char *param, int command)
270{
271 int i, error;
272
273 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
274 return -1;
275
276 error = i8042_wait_write();
277 if (error)
278 return error;
279
280 dbg("%02x -> i8042 (command)\n", command & 0xff);
281 i8042_write_command(command & 0xff);
282
283 for (i = 0; i < ((command >> 12) & 0xf); i++) {
284 error = i8042_wait_write();
285 if (error)
286 return error;
287 dbg("%02x -> i8042 (parameter)\n", param[i]);
288 i8042_write_data(param[i]);
289 }
290
291 for (i = 0; i < ((command >> 8) & 0xf); i++) {
292 error = i8042_wait_read();
293 if (error) {
294 dbg(" -- i8042 (timeout)\n");
295 return error;
296 }
297
298 if (command == I8042_CMD_AUX_LOOP &&
299 !(i8042_read_status() & I8042_STR_AUXDATA)) {
300 dbg(" -- i8042 (auxerr)\n");
301 return -1;
302 }
303
304 param[i] = i8042_read_data();
305 dbg("%02x <- i8042 (return)\n", param[i]);
306 }
307
308 return 0;
309}
310
311int i8042_command(unsigned char *param, int command)
312{
313 unsigned long flags;
314 int retval;
315
316 spin_lock_irqsave(&i8042_lock, flags);
317 retval = __i8042_command(param, command);
318 spin_unlock_irqrestore(&i8042_lock, flags);
319
320 return retval;
321}
322EXPORT_SYMBOL(i8042_command);
323
324/*
325 * i8042_kbd_write() sends a byte out through the keyboard interface.
326 */
327
328static int i8042_kbd_write(struct serio *port, unsigned char c)
329{
330 unsigned long flags;
331 int retval = 0;
332
333 spin_lock_irqsave(&i8042_lock, flags);
334
335 if (!(retval = i8042_wait_write())) {
336 dbg("%02x -> i8042 (kbd-data)\n", c);
337 i8042_write_data(c);
338 }
339
340 spin_unlock_irqrestore(&i8042_lock, flags);
341
342 return retval;
343}
344
345/*
346 * i8042_aux_write() sends a byte out through the aux interface.
347 */
348
349static int i8042_aux_write(struct serio *serio, unsigned char c)
350{
351 struct i8042_port *port = serio->port_data;
352
353 return i8042_command(&c, port->mux == -1 ?
354 I8042_CMD_AUX_SEND :
355 I8042_CMD_MUX_SEND + port->mux);
356}
357
358
359/*
360 * i8042_aux_close attempts to clear AUX or KBD port state by disabling
361 * and then re-enabling it.
362 */
363
364static void i8042_port_close(struct serio *serio)
365{
366 int irq_bit;
367 int disable_bit;
368 const char *port_name;
369
370 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
371 irq_bit = I8042_CTR_AUXINT;
372 disable_bit = I8042_CTR_AUXDIS;
373 port_name = "AUX";
374 } else {
375 irq_bit = I8042_CTR_KBDINT;
376 disable_bit = I8042_CTR_KBDDIS;
377 port_name = "KBD";
378 }
379
380 i8042_ctr &= ~irq_bit;
381 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
382 pr_warn("Can't write CTR while closing %s port\n", port_name);
383
384 udelay(50);
385
386 i8042_ctr &= ~disable_bit;
387 i8042_ctr |= irq_bit;
388 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
389 pr_err("Can't reactivate %s port\n", port_name);
390
391 /*
392 * See if there is any data appeared while we were messing with
393 * port state.
394 */
395 i8042_interrupt(0, NULL);
396}
397
398/*
399 * i8042_start() is called by serio core when port is about to finish
400 * registering. It will mark port as existing so i8042_interrupt can
401 * start sending data through it.
402 */
403static int i8042_start(struct serio *serio)
404{
405 struct i8042_port *port = serio->port_data;
406
407 port->exists = true;
408 mb();
409 return 0;
410}
411
412/*
413 * i8042_stop() marks serio port as non-existing so i8042_interrupt
414 * will not try to send data to the port that is about to go away.
415 * The function is called by serio core as part of unregister procedure.
416 */
417static void i8042_stop(struct serio *serio)
418{
419 struct i8042_port *port = serio->port_data;
420
421 port->exists = false;
422
423 /*
424 * We synchronize with both AUX and KBD IRQs because there is
425 * a (very unlikely) chance that AUX IRQ is raised for KBD port
426 * and vice versa.
427 */
428 synchronize_irq(I8042_AUX_IRQ);
429 synchronize_irq(I8042_KBD_IRQ);
430 port->serio = NULL;
431}
432
433/*
434 * i8042_filter() filters out unwanted bytes from the input data stream.
435 * It is called from i8042_interrupt and thus is running with interrupts
436 * off and i8042_lock held.
437 */
438static bool i8042_filter(unsigned char data, unsigned char str,
439 struct serio *serio)
440{
441 if (unlikely(i8042_suppress_kbd_ack)) {
442 if ((~str & I8042_STR_AUXDATA) &&
443 (data == 0xfa || data == 0xfe)) {
444 i8042_suppress_kbd_ack--;
445 dbg("Extra keyboard ACK - filtered out\n");
446 return true;
447 }
448 }
449
450 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
451 dbg("Filtered out by platform filter\n");
452 return true;
453 }
454
455 return false;
456}
457
458/*
459 * i8042_interrupt() is the most important function in this driver -
460 * it handles the interrupts from the i8042, and sends incoming bytes
461 * to the upper layers.
462 */
463
464static irqreturn_t i8042_interrupt(int irq, void *dev_id)
465{
466 struct i8042_port *port;
467 struct serio *serio;
468 unsigned long flags;
469 unsigned char str, data;
470 unsigned int dfl;
471 unsigned int port_no;
472 bool filtered;
473 int ret = 1;
474
475 spin_lock_irqsave(&i8042_lock, flags);
476
477 str = i8042_read_status();
478 if (unlikely(~str & I8042_STR_OBF)) {
479 spin_unlock_irqrestore(&i8042_lock, flags);
480 if (irq)
481 dbg("Interrupt %d, without any data\n", irq);
482 ret = 0;
483 goto out;
484 }
485
486 data = i8042_read_data();
487
488 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
489 static unsigned long last_transmit;
490 static unsigned char last_str;
491
492 dfl = 0;
493 if (str & I8042_STR_MUXERR) {
494 dbg("MUX error, status is %02x, data is %02x\n",
495 str, data);
496/*
497 * When MUXERR condition is signalled the data register can only contain
498 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
499 * it is not always the case. Some KBCs also report 0xfc when there is
500 * nothing connected to the port while others sometimes get confused which
501 * port the data came from and signal error leaving the data intact. They
502 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
503 * to legacy mode yet, when we see one we'll add proper handling).
504 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
505 * rest assume that the data came from the same serio last byte
506 * was transmitted (if transmission happened not too long ago).
507 */
508
509 switch (data) {
510 default:
511 if (time_before(jiffies, last_transmit + HZ/10)) {
512 str = last_str;
513 break;
514 }
515 /* fall through - report timeout */
516 case 0xfc:
517 case 0xfd:
518 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
519 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
520 }
521 }
522
523 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
524 last_str = str;
525 last_transmit = jiffies;
526 } else {
527
528 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
529 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0);
530
531 port_no = (str & I8042_STR_AUXDATA) ?
532 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
533 }
534
535 port = &i8042_ports[port_no];
536 serio = port->exists ? port->serio : NULL;
537
538 filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n",
539 port_no, irq,
540 dfl & SERIO_PARITY ? ", bad parity" : "",
541 dfl & SERIO_TIMEOUT ? ", timeout" : "");
542
543 filtered = i8042_filter(data, str, serio);
544
545 spin_unlock_irqrestore(&i8042_lock, flags);
546
547 if (likely(port->exists && !filtered))
548 serio_interrupt(serio, data, dfl);
549
550 out:
551 return IRQ_RETVAL(ret);
552}
553
554/*
555 * i8042_enable_kbd_port enables keyboard port on chip
556 */
557
558static int i8042_enable_kbd_port(void)
559{
560 i8042_ctr &= ~I8042_CTR_KBDDIS;
561 i8042_ctr |= I8042_CTR_KBDINT;
562
563 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
564 i8042_ctr &= ~I8042_CTR_KBDINT;
565 i8042_ctr |= I8042_CTR_KBDDIS;
566 pr_err("Failed to enable KBD port\n");
567 return -EIO;
568 }
569
570 return 0;
571}
572
573/*
574 * i8042_enable_aux_port enables AUX (mouse) port on chip
575 */
576
577static int i8042_enable_aux_port(void)
578{
579 i8042_ctr &= ~I8042_CTR_AUXDIS;
580 i8042_ctr |= I8042_CTR_AUXINT;
581
582 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
583 i8042_ctr &= ~I8042_CTR_AUXINT;
584 i8042_ctr |= I8042_CTR_AUXDIS;
585 pr_err("Failed to enable AUX port\n");
586 return -EIO;
587 }
588
589 return 0;
590}
591
592/*
593 * i8042_enable_mux_ports enables 4 individual AUX ports after
594 * the controller has been switched into Multiplexed mode
595 */
596
597static int i8042_enable_mux_ports(void)
598{
599 unsigned char param;
600 int i;
601
602 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
603 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
604 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
605 }
606
607 return i8042_enable_aux_port();
608}
609
610/*
611 * i8042_set_mux_mode checks whether the controller has an
612 * active multiplexor and puts the chip into Multiplexed (true)
613 * or Legacy (false) mode.
614 */
615
616static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
617{
618
619 unsigned char param, val;
620/*
621 * Get rid of bytes in the queue.
622 */
623
624 i8042_flush();
625
626/*
627 * Internal loopback test - send three bytes, they should come back from the
628 * mouse interface, the last should be version.
629 */
630
631 param = val = 0xf0;
632 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
633 return -1;
634 param = val = multiplex ? 0x56 : 0xf6;
635 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
636 return -1;
637 param = val = multiplex ? 0xa4 : 0xa5;
638 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
639 return -1;
640
641/*
642 * Workaround for interference with USB Legacy emulation
643 * that causes a v10.12 MUX to be found.
644 */
645 if (param == 0xac)
646 return -1;
647
648 if (mux_version)
649 *mux_version = param;
650
651 return 0;
652}
653
654/*
655 * i8042_check_mux() checks whether the controller supports the PS/2 Active
656 * Multiplexing specification by Synaptics, Phoenix, Insyde and
657 * LCS/Telegraphics.
658 */
659
660static int __init i8042_check_mux(void)
661{
662 unsigned char mux_version;
663
664 if (i8042_set_mux_mode(true, &mux_version))
665 return -1;
666
667 pr_info("Detected active multiplexing controller, rev %d.%d\n",
668 (mux_version >> 4) & 0xf, mux_version & 0xf);
669
670/*
671 * Disable all muxed ports by disabling AUX.
672 */
673 i8042_ctr |= I8042_CTR_AUXDIS;
674 i8042_ctr &= ~I8042_CTR_AUXINT;
675
676 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
677 pr_err("Failed to disable AUX port, can't use MUX\n");
678 return -EIO;
679 }
680
681 i8042_mux_present = true;
682
683 return 0;
684}
685
686/*
687 * The following is used to test AUX IRQ delivery.
688 */
689static struct completion i8042_aux_irq_delivered __initdata;
690static bool i8042_irq_being_tested __initdata;
691
692static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id)
693{
694 unsigned long flags;
695 unsigned char str, data;
696 int ret = 0;
697
698 spin_lock_irqsave(&i8042_lock, flags);
699 str = i8042_read_status();
700 if (str & I8042_STR_OBF) {
701 data = i8042_read_data();
702 dbg("%02x <- i8042 (aux_test_irq, %s)\n",
703 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
704 if (i8042_irq_being_tested &&
705 data == 0xa5 && (str & I8042_STR_AUXDATA))
706 complete(&i8042_aux_irq_delivered);
707 ret = 1;
708 }
709 spin_unlock_irqrestore(&i8042_lock, flags);
710
711 return IRQ_RETVAL(ret);
712}
713
714/*
715 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
716 * verifies success by readinng CTR. Used when testing for presence of AUX
717 * port.
718 */
719static int __init i8042_toggle_aux(bool on)
720{
721 unsigned char param;
722 int i;
723
724 if (i8042_command(¶m,
725 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
726 return -1;
727
728 /* some chips need some time to set the I8042_CTR_AUXDIS bit */
729 for (i = 0; i < 100; i++) {
730 udelay(50);
731
732 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
733 return -1;
734
735 if (!(param & I8042_CTR_AUXDIS) == on)
736 return 0;
737 }
738
739 return -1;
740}
741
742/*
743 * i8042_check_aux() applies as much paranoia as it can at detecting
744 * the presence of an AUX interface.
745 */
746
747static int __init i8042_check_aux(void)
748{
749 int retval = -1;
750 bool irq_registered = false;
751 bool aux_loop_broken = false;
752 unsigned long flags;
753 unsigned char param;
754
755/*
756 * Get rid of bytes in the queue.
757 */
758
759 i8042_flush();
760
761/*
762 * Internal loopback test - filters out AT-type i8042's. Unfortunately
763 * SiS screwed up and their 5597 doesn't support the LOOP command even
764 * though it has an AUX port.
765 */
766
767 param = 0x5a;
768 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
769 if (retval || param != 0x5a) {
770
771/*
772 * External connection test - filters out AT-soldered PS/2 i8042's
773 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
774 * 0xfa - no error on some notebooks which ignore the spec
775 * Because it's common for chipsets to return error on perfectly functioning
776 * AUX ports, we test for this only when the LOOP command failed.
777 */
778
779 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
780 (param && param != 0xfa && param != 0xff))
781 return -1;
782
783/*
784 * If AUX_LOOP completed without error but returned unexpected data
785 * mark it as broken
786 */
787 if (!retval)
788 aux_loop_broken = true;
789 }
790
791/*
792 * Bit assignment test - filters out PS/2 i8042's in AT mode
793 */
794
795 if (i8042_toggle_aux(false)) {
796 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
797 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
798 }
799
800 if (i8042_toggle_aux(true))
801 return -1;
802
803/*
804 * Reset keyboard (needed on some laptops to successfully detect
805 * touchpad, e.g., some Gigabyte laptop models with Elantech
806 * touchpads).
807 */
808 if (i8042_kbdreset) {
809 pr_warn("Attempting to reset device connected to KBD port\n");
810 i8042_kbd_write(NULL, (unsigned char) 0xff);
811 }
812
813/*
814 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
815 * used it for a PCI card or somethig else.
816 */
817
818 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
819/*
820 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
821 * is working and hope we are right.
822 */
823 retval = 0;
824 goto out;
825 }
826
827 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
828 "i8042", i8042_platform_device))
829 goto out;
830
831 irq_registered = true;
832
833 if (i8042_enable_aux_port())
834 goto out;
835
836 spin_lock_irqsave(&i8042_lock, flags);
837
838 init_completion(&i8042_aux_irq_delivered);
839 i8042_irq_being_tested = true;
840
841 param = 0xa5;
842 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
843
844 spin_unlock_irqrestore(&i8042_lock, flags);
845
846 if (retval)
847 goto out;
848
849 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
850 msecs_to_jiffies(250)) == 0) {
851/*
852 * AUX IRQ was never delivered so we need to flush the controller to
853 * get rid of the byte we put there; otherwise keyboard may not work.
854 */
855 dbg(" -- i8042 (aux irq test timeout)\n");
856 i8042_flush();
857 retval = -1;
858 }
859
860 out:
861
862/*
863 * Disable the interface.
864 */
865
866 i8042_ctr |= I8042_CTR_AUXDIS;
867 i8042_ctr &= ~I8042_CTR_AUXINT;
868
869 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
870 retval = -1;
871
872 if (irq_registered)
873 free_irq(I8042_AUX_IRQ, i8042_platform_device);
874
875 return retval;
876}
877
878static int i8042_controller_check(void)
879{
880 if (i8042_flush()) {
881 pr_info("No controller found\n");
882 return -ENODEV;
883 }
884
885 return 0;
886}
887
888static int i8042_controller_selftest(void)
889{
890 unsigned char param;
891 int i = 0;
892
893 /*
894 * We try this 5 times; on some really fragile systems this does not
895 * take the first time...
896 */
897 do {
898
899 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
900 pr_err("i8042 controller selftest timeout\n");
901 return -ENODEV;
902 }
903
904 if (param == I8042_RET_CTL_TEST)
905 return 0;
906
907 dbg("i8042 controller selftest: %#x != %#x\n",
908 param, I8042_RET_CTL_TEST);
909 msleep(50);
910 } while (i++ < 5);
911
912#ifdef CONFIG_X86
913 /*
914 * On x86, we don't fail entire i8042 initialization if controller
915 * reset fails in hopes that keyboard port will still be functional
916 * and user will still get a working keyboard. This is especially
917 * important on netbooks. On other arches we trust hardware more.
918 */
919 pr_info("giving up on controller selftest, continuing anyway...\n");
920 return 0;
921#else
922 pr_err("i8042 controller selftest failed\n");
923 return -EIO;
924#endif
925}
926
927/*
928 * i8042_controller init initializes the i8042 controller, and,
929 * most importantly, sets it into non-xlated mode if that's
930 * desired.
931 */
932
933static int i8042_controller_init(void)
934{
935 unsigned long flags;
936 int n = 0;
937 unsigned char ctr[2];
938
939/*
940 * Save the CTR for restore on unload / reboot.
941 */
942
943 do {
944 if (n >= 10) {
945 pr_err("Unable to get stable CTR read\n");
946 return -EIO;
947 }
948
949 if (n != 0)
950 udelay(50);
951
952 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
953 pr_err("Can't read CTR while initializing i8042\n");
954 return -EIO;
955 }
956
957 } while (n < 2 || ctr[0] != ctr[1]);
958
959 i8042_initial_ctr = i8042_ctr = ctr[0];
960
961/*
962 * Disable the keyboard interface and interrupt.
963 */
964
965 i8042_ctr |= I8042_CTR_KBDDIS;
966 i8042_ctr &= ~I8042_CTR_KBDINT;
967
968/*
969 * Handle keylock.
970 */
971
972 spin_lock_irqsave(&i8042_lock, flags);
973 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
974 if (i8042_unlock)
975 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
976 else
977 pr_warn("Warning: Keylock active\n");
978 }
979 spin_unlock_irqrestore(&i8042_lock, flags);
980
981/*
982 * If the chip is configured into nontranslated mode by the BIOS, don't
983 * bother enabling translating and be happy.
984 */
985
986 if (~i8042_ctr & I8042_CTR_XLATE)
987 i8042_direct = true;
988
989/*
990 * Set nontranslated mode for the kbd interface if requested by an option.
991 * After this the kbd interface becomes a simple serial in/out, like the aux
992 * interface is. We don't do this by default, since it can confuse notebook
993 * BIOSes.
994 */
995
996 if (i8042_direct)
997 i8042_ctr &= ~I8042_CTR_XLATE;
998
999/*
1000 * Write CTR back.
1001 */
1002
1003 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1004 pr_err("Can't write CTR while initializing i8042\n");
1005 return -EIO;
1006 }
1007
1008/*
1009 * Flush whatever accumulated while we were disabling keyboard port.
1010 */
1011
1012 i8042_flush();
1013
1014 return 0;
1015}
1016
1017
1018/*
1019 * Reset the controller and reset CRT to the original value set by BIOS.
1020 */
1021
1022static void i8042_controller_reset(bool force_reset)
1023{
1024 i8042_flush();
1025
1026/*
1027 * Disable both KBD and AUX interfaces so they don't get in the way
1028 */
1029
1030 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1031 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1032
1033 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1034 pr_warn("Can't write CTR while resetting\n");
1035
1036/*
1037 * Disable MUX mode if present.
1038 */
1039
1040 if (i8042_mux_present)
1041 i8042_set_mux_mode(false, NULL);
1042
1043/*
1044 * Reset the controller if requested.
1045 */
1046
1047 if (i8042_reset || force_reset)
1048 i8042_controller_selftest();
1049
1050/*
1051 * Restore the original control register setting.
1052 */
1053
1054 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1055 pr_warn("Can't restore CTR\n");
1056}
1057
1058
1059/*
1060 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called
1061 * when kernel panics. Flashing LEDs is useful for users running X who may
1062 * not see the console and will help distinguishing panics from "real"
1063 * lockups.
1064 *
1065 * Note that DELAY has a limit of 10ms so we will not get stuck here
1066 * waiting for KBC to free up even if KBD interrupt is off
1067 */
1068
1069#define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1070
1071static long i8042_panic_blink(int state)
1072{
1073 long delay = 0;
1074 char led;
1075
1076 led = (state) ? 0x01 | 0x04 : 0;
1077 while (i8042_read_status() & I8042_STR_IBF)
1078 DELAY;
1079 dbg("%02x -> i8042 (panic blink)\n", 0xed);
1080 i8042_suppress_kbd_ack = 2;
1081 i8042_write_data(0xed); /* set leds */
1082 DELAY;
1083 while (i8042_read_status() & I8042_STR_IBF)
1084 DELAY;
1085 DELAY;
1086 dbg("%02x -> i8042 (panic blink)\n", led);
1087 i8042_write_data(led);
1088 DELAY;
1089 return delay;
1090}
1091
1092#undef DELAY
1093
1094#ifdef CONFIG_X86
1095static void i8042_dritek_enable(void)
1096{
1097 unsigned char param = 0x90;
1098 int error;
1099
1100 error = i8042_command(¶m, 0x1059);
1101 if (error)
1102 pr_warn("Failed to enable DRITEK extension: %d\n", error);
1103}
1104#endif
1105
1106#ifdef CONFIG_PM
1107
1108/*
1109 * Here we try to reset everything back to a state we had
1110 * before suspending.
1111 */
1112
1113static int i8042_controller_resume(bool force_reset)
1114{
1115 int error;
1116
1117 error = i8042_controller_check();
1118 if (error)
1119 return error;
1120
1121 if (i8042_reset || force_reset) {
1122 error = i8042_controller_selftest();
1123 if (error)
1124 return error;
1125 }
1126
1127/*
1128 * Restore original CTR value and disable all ports
1129 */
1130
1131 i8042_ctr = i8042_initial_ctr;
1132 if (i8042_direct)
1133 i8042_ctr &= ~I8042_CTR_XLATE;
1134 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1135 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1136 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1137 pr_warn("Can't write CTR to resume, retrying...\n");
1138 msleep(50);
1139 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1140 pr_err("CTR write retry failed\n");
1141 return -EIO;
1142 }
1143 }
1144
1145
1146#ifdef CONFIG_X86
1147 if (i8042_dritek)
1148 i8042_dritek_enable();
1149#endif
1150
1151 if (i8042_mux_present) {
1152 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1153 pr_warn("failed to resume active multiplexor, mouse won't work\n");
1154 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1155 i8042_enable_aux_port();
1156
1157 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1158 i8042_enable_kbd_port();
1159
1160 i8042_interrupt(0, NULL);
1161
1162 return 0;
1163}
1164
1165/*
1166 * Here we try to restore the original BIOS settings to avoid
1167 * upsetting it.
1168 */
1169
1170static int i8042_pm_suspend(struct device *dev)
1171{
1172 int i;
1173
1174 if (pm_suspend_via_firmware())
1175 i8042_controller_reset(true);
1176
1177 /* Set up serio interrupts for system wakeup. */
1178 for (i = 0; i < I8042_NUM_PORTS; i++) {
1179 struct serio *serio = i8042_ports[i].serio;
1180
1181 if (serio && device_may_wakeup(&serio->dev))
1182 enable_irq_wake(i8042_ports[i].irq);
1183 }
1184
1185 return 0;
1186}
1187
1188static int i8042_pm_resume_noirq(struct device *dev)
1189{
1190 if (!pm_resume_via_firmware())
1191 i8042_interrupt(0, NULL);
1192
1193 return 0;
1194}
1195
1196static int i8042_pm_resume(struct device *dev)
1197{
1198 bool force_reset;
1199 int i;
1200
1201 for (i = 0; i < I8042_NUM_PORTS; i++) {
1202 struct serio *serio = i8042_ports[i].serio;
1203
1204 if (serio && device_may_wakeup(&serio->dev))
1205 disable_irq_wake(i8042_ports[i].irq);
1206 }
1207
1208 /*
1209 * If platform firmware was not going to be involved in suspend, we did
1210 * not restore the controller state to whatever it had been at boot
1211 * time, so we do not need to do anything.
1212 */
1213 if (!pm_suspend_via_firmware())
1214 return 0;
1215
1216 /*
1217 * We only need to reset the controller if we are resuming after handing
1218 * off control to the platform firmware, otherwise we can simply restore
1219 * the mode.
1220 */
1221 force_reset = pm_resume_via_firmware();
1222
1223 return i8042_controller_resume(force_reset);
1224}
1225
1226static int i8042_pm_thaw(struct device *dev)
1227{
1228 i8042_interrupt(0, NULL);
1229
1230 return 0;
1231}
1232
1233static int i8042_pm_reset(struct device *dev)
1234{
1235 i8042_controller_reset(false);
1236
1237 return 0;
1238}
1239
1240static int i8042_pm_restore(struct device *dev)
1241{
1242 return i8042_controller_resume(false);
1243}
1244
1245static const struct dev_pm_ops i8042_pm_ops = {
1246 .suspend = i8042_pm_suspend,
1247 .resume_noirq = i8042_pm_resume_noirq,
1248 .resume = i8042_pm_resume,
1249 .thaw = i8042_pm_thaw,
1250 .poweroff = i8042_pm_reset,
1251 .restore = i8042_pm_restore,
1252};
1253
1254#endif /* CONFIG_PM */
1255
1256/*
1257 * We need to reset the 8042 back to original mode on system shutdown,
1258 * because otherwise BIOSes will be confused.
1259 */
1260
1261static void i8042_shutdown(struct platform_device *dev)
1262{
1263 i8042_controller_reset(false);
1264}
1265
1266static int __init i8042_create_kbd_port(void)
1267{
1268 struct serio *serio;
1269 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1270
1271 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1272 if (!serio)
1273 return -ENOMEM;
1274
1275 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1276 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1277 serio->start = i8042_start;
1278 serio->stop = i8042_stop;
1279 serio->close = i8042_port_close;
1280 serio->port_data = port;
1281 serio->dev.parent = &i8042_platform_device->dev;
1282 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1283 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1284 strlcpy(serio->firmware_id, i8042_kbd_firmware_id,
1285 sizeof(serio->firmware_id));
1286
1287 port->serio = serio;
1288 port->irq = I8042_KBD_IRQ;
1289
1290 return 0;
1291}
1292
1293static int __init i8042_create_aux_port(int idx)
1294{
1295 struct serio *serio;
1296 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1297 struct i8042_port *port = &i8042_ports[port_no];
1298
1299 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1300 if (!serio)
1301 return -ENOMEM;
1302
1303 serio->id.type = SERIO_8042;
1304 serio->write = i8042_aux_write;
1305 serio->start = i8042_start;
1306 serio->stop = i8042_stop;
1307 serio->port_data = port;
1308 serio->dev.parent = &i8042_platform_device->dev;
1309 if (idx < 0) {
1310 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1311 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1312 strlcpy(serio->firmware_id, i8042_aux_firmware_id,
1313 sizeof(serio->firmware_id));
1314 serio->close = i8042_port_close;
1315 } else {
1316 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1317 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1318 strlcpy(serio->firmware_id, i8042_aux_firmware_id,
1319 sizeof(serio->firmware_id));
1320 }
1321
1322 port->serio = serio;
1323 port->mux = idx;
1324 port->irq = I8042_AUX_IRQ;
1325
1326 return 0;
1327}
1328
1329static void __init i8042_free_kbd_port(void)
1330{
1331 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1332 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1333}
1334
1335static void __init i8042_free_aux_ports(void)
1336{
1337 int i;
1338
1339 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1340 kfree(i8042_ports[i].serio);
1341 i8042_ports[i].serio = NULL;
1342 }
1343}
1344
1345static void __init i8042_register_ports(void)
1346{
1347 int i;
1348
1349 for (i = 0; i < I8042_NUM_PORTS; i++) {
1350 struct serio *serio = i8042_ports[i].serio;
1351
1352 if (serio) {
1353 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1354 serio->name,
1355 (unsigned long) I8042_DATA_REG,
1356 (unsigned long) I8042_COMMAND_REG,
1357 i8042_ports[i].irq);
1358 serio_register_port(serio);
1359 device_set_wakeup_capable(&serio->dev, true);
1360 }
1361 }
1362}
1363
1364static void i8042_unregister_ports(void)
1365{
1366 int i;
1367
1368 for (i = 0; i < I8042_NUM_PORTS; i++) {
1369 if (i8042_ports[i].serio) {
1370 serio_unregister_port(i8042_ports[i].serio);
1371 i8042_ports[i].serio = NULL;
1372 }
1373 }
1374}
1375
1376/*
1377 * Checks whether port belongs to i8042 controller.
1378 */
1379bool i8042_check_port_owner(const struct serio *port)
1380{
1381 int i;
1382
1383 for (i = 0; i < I8042_NUM_PORTS; i++)
1384 if (i8042_ports[i].serio == port)
1385 return true;
1386
1387 return false;
1388}
1389EXPORT_SYMBOL(i8042_check_port_owner);
1390
1391static void i8042_free_irqs(void)
1392{
1393 if (i8042_aux_irq_registered)
1394 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1395 if (i8042_kbd_irq_registered)
1396 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1397
1398 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1399}
1400
1401static int __init i8042_setup_aux(void)
1402{
1403 int (*aux_enable)(void);
1404 int error;
1405 int i;
1406
1407 if (i8042_check_aux())
1408 return -ENODEV;
1409
1410 if (i8042_nomux || i8042_check_mux()) {
1411 error = i8042_create_aux_port(-1);
1412 if (error)
1413 goto err_free_ports;
1414 aux_enable = i8042_enable_aux_port;
1415 } else {
1416 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1417 error = i8042_create_aux_port(i);
1418 if (error)
1419 goto err_free_ports;
1420 }
1421 aux_enable = i8042_enable_mux_ports;
1422 }
1423
1424 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1425 "i8042", i8042_platform_device);
1426 if (error)
1427 goto err_free_ports;
1428
1429 if (aux_enable())
1430 goto err_free_irq;
1431
1432 i8042_aux_irq_registered = true;
1433 return 0;
1434
1435 err_free_irq:
1436 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1437 err_free_ports:
1438 i8042_free_aux_ports();
1439 return error;
1440}
1441
1442static int __init i8042_setup_kbd(void)
1443{
1444 int error;
1445
1446 error = i8042_create_kbd_port();
1447 if (error)
1448 return error;
1449
1450 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1451 "i8042", i8042_platform_device);
1452 if (error)
1453 goto err_free_port;
1454
1455 error = i8042_enable_kbd_port();
1456 if (error)
1457 goto err_free_irq;
1458
1459 i8042_kbd_irq_registered = true;
1460 return 0;
1461
1462 err_free_irq:
1463 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1464 err_free_port:
1465 i8042_free_kbd_port();
1466 return error;
1467}
1468
1469static int i8042_kbd_bind_notifier(struct notifier_block *nb,
1470 unsigned long action, void *data)
1471{
1472 struct device *dev = data;
1473 struct serio *serio = to_serio_port(dev);
1474 struct i8042_port *port = serio->port_data;
1475
1476 if (serio != i8042_ports[I8042_KBD_PORT_NO].serio)
1477 return 0;
1478
1479 switch (action) {
1480 case BUS_NOTIFY_BOUND_DRIVER:
1481 port->driver_bound = true;
1482 break;
1483
1484 case BUS_NOTIFY_UNBIND_DRIVER:
1485 port->driver_bound = false;
1486 break;
1487 }
1488
1489 return 0;
1490}
1491
1492static int __init i8042_probe(struct platform_device *dev)
1493{
1494 int error;
1495
1496 i8042_platform_device = dev;
1497
1498 if (i8042_reset) {
1499 error = i8042_controller_selftest();
1500 if (error)
1501 return error;
1502 }
1503
1504 error = i8042_controller_init();
1505 if (error)
1506 return error;
1507
1508#ifdef CONFIG_X86
1509 if (i8042_dritek)
1510 i8042_dritek_enable();
1511#endif
1512
1513 if (!i8042_noaux) {
1514 error = i8042_setup_aux();
1515 if (error && error != -ENODEV && error != -EBUSY)
1516 goto out_fail;
1517 }
1518
1519 if (!i8042_nokbd) {
1520 error = i8042_setup_kbd();
1521 if (error)
1522 goto out_fail;
1523 }
1524/*
1525 * Ok, everything is ready, let's register all serio ports
1526 */
1527 i8042_register_ports();
1528
1529 return 0;
1530
1531 out_fail:
1532 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1533 i8042_free_irqs();
1534 i8042_controller_reset(false);
1535 i8042_platform_device = NULL;
1536
1537 return error;
1538}
1539
1540static int i8042_remove(struct platform_device *dev)
1541{
1542 i8042_unregister_ports();
1543 i8042_free_irqs();
1544 i8042_controller_reset(false);
1545 i8042_platform_device = NULL;
1546
1547 return 0;
1548}
1549
1550static struct platform_driver i8042_driver = {
1551 .driver = {
1552 .name = "i8042",
1553#ifdef CONFIG_PM
1554 .pm = &i8042_pm_ops,
1555#endif
1556 },
1557 .remove = i8042_remove,
1558 .shutdown = i8042_shutdown,
1559};
1560
1561static struct notifier_block i8042_kbd_bind_notifier_block = {
1562 .notifier_call = i8042_kbd_bind_notifier,
1563};
1564
1565static int __init i8042_init(void)
1566{
1567 struct platform_device *pdev;
1568 int err;
1569
1570 dbg_init();
1571
1572 err = i8042_platform_init();
1573 if (err)
1574 return err;
1575
1576 err = i8042_controller_check();
1577 if (err)
1578 goto err_platform_exit;
1579
1580 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0);
1581 if (IS_ERR(pdev)) {
1582 err = PTR_ERR(pdev);
1583 goto err_platform_exit;
1584 }
1585
1586 bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
1587 panic_blink = i8042_panic_blink;
1588
1589 return 0;
1590
1591 err_platform_exit:
1592 i8042_platform_exit();
1593 return err;
1594}
1595
1596static void __exit i8042_exit(void)
1597{
1598 platform_device_unregister(i8042_platform_device);
1599 platform_driver_unregister(&i8042_driver);
1600 i8042_platform_exit();
1601
1602 bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
1603 panic_blink = NULL;
1604}
1605
1606module_init(i8042_init);
1607module_exit(i8042_exit);