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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/clocksource/arm_global_timer.c
4 *
5 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
6 * Author: Stuart Menefy <stuart.menefy@st.com>
7 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
8 */
9
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/clocksource.h>
13#include <linux/clockchips.h>
14#include <linux/cpu.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/of.h>
20#include <linux/of_irq.h>
21#include <linux/of_address.h>
22#include <linux/sched_clock.h>
23
24#include <asm/cputype.h>
25
26#define GT_COUNTER0 0x00
27#define GT_COUNTER1 0x04
28
29#define GT_CONTROL 0x08
30#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
31#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
32#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
33#define GT_CONTROL_AUTO_INC BIT(3) /* banked */
34#define GT_CONTROL_PRESCALER_SHIFT 8
35#define GT_CONTROL_PRESCALER_MAX 0xF
36#define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \
37 GT_CONTROL_PRESCALER_SHIFT)
38
39#define GT_INT_STATUS 0x0c
40#define GT_INT_STATUS_EVENT_FLAG BIT(0)
41
42#define GT_COMP0 0x10
43#define GT_COMP1 0x14
44#define GT_AUTO_INC 0x18
45
46#define MAX_F_ERR 50
47/*
48 * We are expecting to be clocked by the ARM peripheral clock.
49 *
50 * Note: it is assumed we are using a prescaler value of zero, so this is
51 * the units for all operations.
52 */
53static void __iomem *gt_base;
54static struct notifier_block gt_clk_rate_change_nb;
55static u32 gt_psv_new, gt_psv_bck, gt_target_rate;
56static int gt_ppi;
57static struct clock_event_device __percpu *gt_evt;
58
59/*
60 * To get the value from the Global Timer Counter register proceed as follows:
61 * 1. Read the upper 32-bit timer counter register
62 * 2. Read the lower 32-bit timer counter register
63 * 3. Read the upper 32-bit timer counter register again. If the value is
64 * different to the 32-bit upper value read previously, go back to step 2.
65 * Otherwise the 64-bit timer counter value is correct.
66 */
67static u64 notrace _gt_counter_read(void)
68{
69 u64 counter;
70 u32 lower;
71 u32 upper, old_upper;
72
73 upper = readl_relaxed(gt_base + GT_COUNTER1);
74 do {
75 old_upper = upper;
76 lower = readl_relaxed(gt_base + GT_COUNTER0);
77 upper = readl_relaxed(gt_base + GT_COUNTER1);
78 } while (upper != old_upper);
79
80 counter = upper;
81 counter <<= 32;
82 counter |= lower;
83 return counter;
84}
85
86static u64 gt_counter_read(void)
87{
88 return _gt_counter_read();
89}
90
91/**
92 * To ensure that updates to comparator value register do not set the
93 * Interrupt Status Register proceed as follows:
94 * 1. Clear the Comp Enable bit in the Timer Control Register.
95 * 2. Write the lower 32-bit Comparator Value Register.
96 * 3. Write the upper 32-bit Comparator Value Register.
97 * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
98 */
99static void gt_compare_set(unsigned long delta, int periodic)
100{
101 u64 counter = gt_counter_read();
102 unsigned long ctrl;
103
104 counter += delta;
105 ctrl = readl(gt_base + GT_CONTROL);
106 ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
107 GT_CONTROL_AUTO_INC);
108 ctrl |= GT_CONTROL_TIMER_ENABLE;
109 writel_relaxed(ctrl, gt_base + GT_CONTROL);
110 writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
111 writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
112
113 if (periodic) {
114 writel_relaxed(delta, gt_base + GT_AUTO_INC);
115 ctrl |= GT_CONTROL_AUTO_INC;
116 }
117
118 ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
119 writel_relaxed(ctrl, gt_base + GT_CONTROL);
120}
121
122static int gt_clockevent_shutdown(struct clock_event_device *evt)
123{
124 unsigned long ctrl;
125
126 ctrl = readl(gt_base + GT_CONTROL);
127 ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
128 GT_CONTROL_AUTO_INC);
129 writel(ctrl, gt_base + GT_CONTROL);
130 return 0;
131}
132
133static int gt_clockevent_set_periodic(struct clock_event_device *evt)
134{
135 gt_compare_set(DIV_ROUND_CLOSEST(gt_target_rate, HZ), 1);
136 return 0;
137}
138
139static int gt_clockevent_set_next_event(unsigned long evt,
140 struct clock_event_device *unused)
141{
142 gt_compare_set(evt, 0);
143 return 0;
144}
145
146static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
147{
148 struct clock_event_device *evt = dev_id;
149
150 if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
151 GT_INT_STATUS_EVENT_FLAG))
152 return IRQ_NONE;
153
154 /**
155 * ERRATA 740657( Global Timer can send 2 interrupts for
156 * the same event in single-shot mode)
157 * Workaround:
158 * Either disable single-shot mode.
159 * Or
160 * Modify the Interrupt Handler to avoid the
161 * offending sequence. This is achieved by clearing
162 * the Global Timer flag _after_ having incremented
163 * the Comparator register value to a higher value.
164 */
165 if (clockevent_state_oneshot(evt))
166 gt_compare_set(ULONG_MAX, 0);
167
168 writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
169 evt->event_handler(evt);
170
171 return IRQ_HANDLED;
172}
173
174static int gt_starting_cpu(unsigned int cpu)
175{
176 struct clock_event_device *clk = this_cpu_ptr(gt_evt);
177
178 clk->name = "arm_global_timer";
179 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
180 CLOCK_EVT_FEAT_PERCPU;
181 clk->set_state_shutdown = gt_clockevent_shutdown;
182 clk->set_state_periodic = gt_clockevent_set_periodic;
183 clk->set_state_oneshot = gt_clockevent_shutdown;
184 clk->set_state_oneshot_stopped = gt_clockevent_shutdown;
185 clk->set_next_event = gt_clockevent_set_next_event;
186 clk->cpumask = cpumask_of(cpu);
187 clk->rating = 300;
188 clk->irq = gt_ppi;
189 clockevents_config_and_register(clk, gt_target_rate,
190 1, 0xffffffff);
191 enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
192 return 0;
193}
194
195static int gt_dying_cpu(unsigned int cpu)
196{
197 struct clock_event_device *clk = this_cpu_ptr(gt_evt);
198
199 gt_clockevent_shutdown(clk);
200 disable_percpu_irq(clk->irq);
201 return 0;
202}
203
204static u64 gt_clocksource_read(struct clocksource *cs)
205{
206 return gt_counter_read();
207}
208
209static void gt_resume(struct clocksource *cs)
210{
211 unsigned long ctrl;
212
213 ctrl = readl(gt_base + GT_CONTROL);
214 if (!(ctrl & GT_CONTROL_TIMER_ENABLE))
215 /* re-enable timer on resume */
216 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
217}
218
219static struct clocksource gt_clocksource = {
220 .name = "arm_global_timer",
221 .rating = 300,
222 .read = gt_clocksource_read,
223 .mask = CLOCKSOURCE_MASK(64),
224 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
225 .resume = gt_resume,
226};
227
228#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
229static u64 notrace gt_sched_clock_read(void)
230{
231 return _gt_counter_read();
232}
233#endif
234
235static unsigned long gt_read_long(void)
236{
237 return readl_relaxed(gt_base + GT_COUNTER0);
238}
239
240static struct delay_timer gt_delay_timer = {
241 .read_current_timer = gt_read_long,
242};
243
244static void gt_write_presc(u32 psv)
245{
246 u32 reg;
247
248 reg = readl(gt_base + GT_CONTROL);
249 reg &= ~GT_CONTROL_PRESCALER_MASK;
250 reg |= psv << GT_CONTROL_PRESCALER_SHIFT;
251 writel(reg, gt_base + GT_CONTROL);
252}
253
254static u32 gt_read_presc(void)
255{
256 u32 reg;
257
258 reg = readl(gt_base + GT_CONTROL);
259 reg &= GT_CONTROL_PRESCALER_MASK;
260 return reg >> GT_CONTROL_PRESCALER_SHIFT;
261}
262
263static void __init gt_delay_timer_init(void)
264{
265 gt_delay_timer.freq = gt_target_rate;
266 register_current_timer_delay(>_delay_timer);
267}
268
269static int __init gt_clocksource_init(void)
270{
271 writel(0, gt_base + GT_CONTROL);
272 writel(0, gt_base + GT_COUNTER0);
273 writel(0, gt_base + GT_COUNTER1);
274 /* set prescaler and enable timer on all the cores */
275 writel(((CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) <<
276 GT_CONTROL_PRESCALER_SHIFT)
277 | GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
278
279#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
280 sched_clock_register(gt_sched_clock_read, 64, gt_target_rate);
281#endif
282 return clocksource_register_hz(>_clocksource, gt_target_rate);
283}
284
285static int gt_clk_rate_change_cb(struct notifier_block *nb,
286 unsigned long event, void *data)
287{
288 struct clk_notifier_data *ndata = data;
289
290 switch (event) {
291 case PRE_RATE_CHANGE:
292 {
293 int psv;
294
295 psv = DIV_ROUND_CLOSEST(ndata->new_rate,
296 gt_target_rate);
297
298 if (abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR)
299 return NOTIFY_BAD;
300
301 psv--;
302
303 /* prescaler within legal range? */
304 if (psv < 0 || psv > GT_CONTROL_PRESCALER_MAX)
305 return NOTIFY_BAD;
306
307 /*
308 * store timer clock ctrl register so we can restore it in case
309 * of an abort.
310 */
311 gt_psv_bck = gt_read_presc();
312 gt_psv_new = psv;
313 /* scale down: adjust divider in post-change notification */
314 if (ndata->new_rate < ndata->old_rate)
315 return NOTIFY_DONE;
316
317 /* scale up: adjust divider now - before frequency change */
318 gt_write_presc(psv);
319 break;
320 }
321 case POST_RATE_CHANGE:
322 /* scale up: pre-change notification did the adjustment */
323 if (ndata->new_rate > ndata->old_rate)
324 return NOTIFY_OK;
325
326 /* scale down: adjust divider now - after frequency change */
327 gt_write_presc(gt_psv_new);
328 break;
329
330 case ABORT_RATE_CHANGE:
331 /* we have to undo the adjustment in case we scale up */
332 if (ndata->new_rate < ndata->old_rate)
333 return NOTIFY_OK;
334
335 /* restore original register value */
336 gt_write_presc(gt_psv_bck);
337 break;
338 default:
339 return NOTIFY_DONE;
340 }
341
342 return NOTIFY_DONE;
343}
344
345static int __init global_timer_of_register(struct device_node *np)
346{
347 struct clk *gt_clk;
348 static unsigned long gt_clk_rate;
349 int err = 0;
350
351 /*
352 * In A9 r2p0 the comparators for each processor with the global timer
353 * fire when the timer value is greater than or equal to. In previous
354 * revisions the comparators fired when the timer value was equal to.
355 */
356 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
357 && (read_cpuid_id() & 0xf0000f) < 0x200000) {
358 pr_warn("global-timer: non support for this cpu version.\n");
359 return -ENOSYS;
360 }
361
362 gt_ppi = irq_of_parse_and_map(np, 0);
363 if (!gt_ppi) {
364 pr_warn("global-timer: unable to parse irq\n");
365 return -EINVAL;
366 }
367
368 gt_base = of_iomap(np, 0);
369 if (!gt_base) {
370 pr_warn("global-timer: invalid base address\n");
371 return -ENXIO;
372 }
373
374 gt_clk = of_clk_get(np, 0);
375 if (!IS_ERR(gt_clk)) {
376 err = clk_prepare_enable(gt_clk);
377 if (err)
378 goto out_unmap;
379 } else {
380 pr_warn("global-timer: clk not found\n");
381 err = -EINVAL;
382 goto out_unmap;
383 }
384
385 gt_clk_rate = clk_get_rate(gt_clk);
386 gt_target_rate = gt_clk_rate / CONFIG_ARM_GT_INITIAL_PRESCALER_VAL;
387 gt_clk_rate_change_nb.notifier_call =
388 gt_clk_rate_change_cb;
389 err = clk_notifier_register(gt_clk, >_clk_rate_change_nb);
390 if (err) {
391 pr_warn("Unable to register clock notifier\n");
392 goto out_clk;
393 }
394
395 gt_evt = alloc_percpu(struct clock_event_device);
396 if (!gt_evt) {
397 pr_warn("global-timer: can't allocate memory\n");
398 err = -ENOMEM;
399 goto out_clk_nb;
400 }
401
402 err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
403 "gt", gt_evt);
404 if (err) {
405 pr_warn("global-timer: can't register interrupt %d (%d)\n",
406 gt_ppi, err);
407 goto out_free;
408 }
409
410 /* Register and immediately configure the timer on the boot CPU */
411 err = gt_clocksource_init();
412 if (err)
413 goto out_irq;
414
415 err = cpuhp_setup_state(CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
416 "clockevents/arm/global_timer:starting",
417 gt_starting_cpu, gt_dying_cpu);
418 if (err)
419 goto out_irq;
420
421 gt_delay_timer_init();
422
423 return 0;
424
425out_irq:
426 free_percpu_irq(gt_ppi, gt_evt);
427out_free:
428 free_percpu(gt_evt);
429out_clk_nb:
430 clk_notifier_unregister(gt_clk, >_clk_rate_change_nb);
431out_clk:
432 clk_disable_unprepare(gt_clk);
433out_unmap:
434 iounmap(gt_base);
435 WARN(err, "ARM Global timer register failed (%d)\n", err);
436
437 return err;
438}
439
440/* Only tested on r2p2 and r3p0 */
441TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
442 global_timer_of_register);
1/*
2 * drivers/clocksource/arm_global_timer.c
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * Author: Stuart Menefy <stuart.menefy@st.com>
6 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/clocksource.h>
16#include <linux/clockchips.h>
17#include <linux/cpu.h>
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_address.h>
25#include <linux/sched_clock.h>
26
27#include <asm/cputype.h>
28
29#define GT_COUNTER0 0x00
30#define GT_COUNTER1 0x04
31
32#define GT_CONTROL 0x08
33#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
34#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
35#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
36#define GT_CONTROL_AUTO_INC BIT(3) /* banked */
37
38#define GT_INT_STATUS 0x0c
39#define GT_INT_STATUS_EVENT_FLAG BIT(0)
40
41#define GT_COMP0 0x10
42#define GT_COMP1 0x14
43#define GT_AUTO_INC 0x18
44
45/*
46 * We are expecting to be clocked by the ARM peripheral clock.
47 *
48 * Note: it is assumed we are using a prescaler value of zero, so this is
49 * the units for all operations.
50 */
51static void __iomem *gt_base;
52static unsigned long gt_clk_rate;
53static int gt_ppi;
54static struct clock_event_device __percpu *gt_evt;
55
56/*
57 * To get the value from the Global Timer Counter register proceed as follows:
58 * 1. Read the upper 32-bit timer counter register
59 * 2. Read the lower 32-bit timer counter register
60 * 3. Read the upper 32-bit timer counter register again. If the value is
61 * different to the 32-bit upper value read previously, go back to step 2.
62 * Otherwise the 64-bit timer counter value is correct.
63 */
64static u64 notrace _gt_counter_read(void)
65{
66 u64 counter;
67 u32 lower;
68 u32 upper, old_upper;
69
70 upper = readl_relaxed(gt_base + GT_COUNTER1);
71 do {
72 old_upper = upper;
73 lower = readl_relaxed(gt_base + GT_COUNTER0);
74 upper = readl_relaxed(gt_base + GT_COUNTER1);
75 } while (upper != old_upper);
76
77 counter = upper;
78 counter <<= 32;
79 counter |= lower;
80 return counter;
81}
82
83static u64 gt_counter_read(void)
84{
85 return _gt_counter_read();
86}
87
88/**
89 * To ensure that updates to comparator value register do not set the
90 * Interrupt Status Register proceed as follows:
91 * 1. Clear the Comp Enable bit in the Timer Control Register.
92 * 2. Write the lower 32-bit Comparator Value Register.
93 * 3. Write the upper 32-bit Comparator Value Register.
94 * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
95 */
96static void gt_compare_set(unsigned long delta, int periodic)
97{
98 u64 counter = gt_counter_read();
99 unsigned long ctrl;
100
101 counter += delta;
102 ctrl = GT_CONTROL_TIMER_ENABLE;
103 writel_relaxed(ctrl, gt_base + GT_CONTROL);
104 writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
105 writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
106
107 if (periodic) {
108 writel_relaxed(delta, gt_base + GT_AUTO_INC);
109 ctrl |= GT_CONTROL_AUTO_INC;
110 }
111
112 ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
113 writel_relaxed(ctrl, gt_base + GT_CONTROL);
114}
115
116static int gt_clockevent_shutdown(struct clock_event_device *evt)
117{
118 unsigned long ctrl;
119
120 ctrl = readl(gt_base + GT_CONTROL);
121 ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
122 GT_CONTROL_AUTO_INC);
123 writel(ctrl, gt_base + GT_CONTROL);
124 return 0;
125}
126
127static int gt_clockevent_set_periodic(struct clock_event_device *evt)
128{
129 gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
130 return 0;
131}
132
133static int gt_clockevent_set_next_event(unsigned long evt,
134 struct clock_event_device *unused)
135{
136 gt_compare_set(evt, 0);
137 return 0;
138}
139
140static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
141{
142 struct clock_event_device *evt = dev_id;
143
144 if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
145 GT_INT_STATUS_EVENT_FLAG))
146 return IRQ_NONE;
147
148 /**
149 * ERRATA 740657( Global Timer can send 2 interrupts for
150 * the same event in single-shot mode)
151 * Workaround:
152 * Either disable single-shot mode.
153 * Or
154 * Modify the Interrupt Handler to avoid the
155 * offending sequence. This is achieved by clearing
156 * the Global Timer flag _after_ having incremented
157 * the Comparator register value to a higher value.
158 */
159 if (clockevent_state_oneshot(evt))
160 gt_compare_set(ULONG_MAX, 0);
161
162 writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
163 evt->event_handler(evt);
164
165 return IRQ_HANDLED;
166}
167
168static int gt_clockevents_init(struct clock_event_device *clk)
169{
170 int cpu = smp_processor_id();
171
172 clk->name = "arm_global_timer";
173 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
174 CLOCK_EVT_FEAT_PERCPU;
175 clk->set_state_shutdown = gt_clockevent_shutdown;
176 clk->set_state_periodic = gt_clockevent_set_periodic;
177 clk->set_state_oneshot = gt_clockevent_shutdown;
178 clk->set_state_oneshot_stopped = gt_clockevent_shutdown;
179 clk->set_next_event = gt_clockevent_set_next_event;
180 clk->cpumask = cpumask_of(cpu);
181 clk->rating = 300;
182 clk->irq = gt_ppi;
183 clockevents_config_and_register(clk, gt_clk_rate,
184 1, 0xffffffff);
185 enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
186 return 0;
187}
188
189static void gt_clockevents_stop(struct clock_event_device *clk)
190{
191 gt_clockevent_shutdown(clk);
192 disable_percpu_irq(clk->irq);
193}
194
195static cycle_t gt_clocksource_read(struct clocksource *cs)
196{
197 return gt_counter_read();
198}
199
200static void gt_resume(struct clocksource *cs)
201{
202 unsigned long ctrl;
203
204 ctrl = readl(gt_base + GT_CONTROL);
205 if (!(ctrl & GT_CONTROL_TIMER_ENABLE))
206 /* re-enable timer on resume */
207 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
208}
209
210static struct clocksource gt_clocksource = {
211 .name = "arm_global_timer",
212 .rating = 300,
213 .read = gt_clocksource_read,
214 .mask = CLOCKSOURCE_MASK(64),
215 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
216 .resume = gt_resume,
217};
218
219#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
220static u64 notrace gt_sched_clock_read(void)
221{
222 return _gt_counter_read();
223}
224#endif
225
226static unsigned long gt_read_long(void)
227{
228 return readl_relaxed(gt_base + GT_COUNTER0);
229}
230
231static struct delay_timer gt_delay_timer = {
232 .read_current_timer = gt_read_long,
233};
234
235static void __init gt_delay_timer_init(void)
236{
237 gt_delay_timer.freq = gt_clk_rate;
238 register_current_timer_delay(>_delay_timer);
239}
240
241static void __init gt_clocksource_init(void)
242{
243 writel(0, gt_base + GT_CONTROL);
244 writel(0, gt_base + GT_COUNTER0);
245 writel(0, gt_base + GT_COUNTER1);
246 /* enables timer on all the cores */
247 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
248
249#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
250 sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
251#endif
252 clocksource_register_hz(>_clocksource, gt_clk_rate);
253}
254
255static int gt_cpu_notify(struct notifier_block *self, unsigned long action,
256 void *hcpu)
257{
258 switch (action & ~CPU_TASKS_FROZEN) {
259 case CPU_STARTING:
260 gt_clockevents_init(this_cpu_ptr(gt_evt));
261 break;
262 case CPU_DYING:
263 gt_clockevents_stop(this_cpu_ptr(gt_evt));
264 break;
265 }
266
267 return NOTIFY_OK;
268}
269static struct notifier_block gt_cpu_nb = {
270 .notifier_call = gt_cpu_notify,
271};
272
273static void __init global_timer_of_register(struct device_node *np)
274{
275 struct clk *gt_clk;
276 int err = 0;
277
278 /*
279 * In A9 r2p0 the comparators for each processor with the global timer
280 * fire when the timer value is greater than or equal to. In previous
281 * revisions the comparators fired when the timer value was equal to.
282 */
283 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
284 && (read_cpuid_id() & 0xf0000f) < 0x200000) {
285 pr_warn("global-timer: non support for this cpu version.\n");
286 return;
287 }
288
289 gt_ppi = irq_of_parse_and_map(np, 0);
290 if (!gt_ppi) {
291 pr_warn("global-timer: unable to parse irq\n");
292 return;
293 }
294
295 gt_base = of_iomap(np, 0);
296 if (!gt_base) {
297 pr_warn("global-timer: invalid base address\n");
298 return;
299 }
300
301 gt_clk = of_clk_get(np, 0);
302 if (!IS_ERR(gt_clk)) {
303 err = clk_prepare_enable(gt_clk);
304 if (err)
305 goto out_unmap;
306 } else {
307 pr_warn("global-timer: clk not found\n");
308 err = -EINVAL;
309 goto out_unmap;
310 }
311
312 gt_clk_rate = clk_get_rate(gt_clk);
313 gt_evt = alloc_percpu(struct clock_event_device);
314 if (!gt_evt) {
315 pr_warn("global-timer: can't allocate memory\n");
316 err = -ENOMEM;
317 goto out_clk;
318 }
319
320 err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
321 "gt", gt_evt);
322 if (err) {
323 pr_warn("global-timer: can't register interrupt %d (%d)\n",
324 gt_ppi, err);
325 goto out_free;
326 }
327
328 err = register_cpu_notifier(>_cpu_nb);
329 if (err) {
330 pr_warn("global-timer: unable to register cpu notifier.\n");
331 goto out_irq;
332 }
333
334 /* Immediately configure the timer on the boot CPU */
335 gt_clocksource_init();
336 gt_clockevents_init(this_cpu_ptr(gt_evt));
337 gt_delay_timer_init();
338
339 return;
340
341out_irq:
342 free_percpu_irq(gt_ppi, gt_evt);
343out_free:
344 free_percpu(gt_evt);
345out_clk:
346 clk_disable_unprepare(gt_clk);
347out_unmap:
348 iounmap(gt_base);
349 WARN(err, "ARM Global timer register failed (%d)\n", err);
350}
351
352/* Only tested on r2p2 and r3p0 */
353CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
354 global_timer_of_register);