1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __UM_IRQ_H
 3#define __UM_IRQ_H
 4
 5#define TIMER_IRQ		0
 6#define UMN_IRQ			1
 7#define UBD_IRQ			2
 8#define UM_ETH_IRQ		3
 9#define ACCEPT_IRQ		4
10#define MCONSOLE_IRQ		5
11#define WINCH_IRQ		6
12#define SIGIO_WRITE_IRQ 	7
13#define TELNETD_IRQ 		8
14#define XTERM_IRQ 		9
15#define RANDOM_IRQ 		10
 
 
 
 
16
17#ifdef CONFIG_UML_NET_VECTOR
 
18
19#define VECTOR_BASE_IRQ		(RANDOM_IRQ + 1)
20#define VECTOR_IRQ_SPACE	8
21
22#define UM_FIRST_DYN_IRQ (VECTOR_IRQ_SPACE + VECTOR_BASE_IRQ)
23
24#else
25
26#define UM_FIRST_DYN_IRQ (RANDOM_IRQ + 1)
27
28#endif
29
30#define UM_LAST_SIGNAL_IRQ	64
31/* If we have (simulated) PCI MSI, allow 64 more interrupt numbers for it */
32#ifdef CONFIG_PCI_MSI
33#define NR_IRQS			(UM_LAST_SIGNAL_IRQ + 64)
34#else
35#define NR_IRQS			UM_LAST_SIGNAL_IRQ
36#endif /* CONFIG_PCI_MSI */
37
38#include <asm-generic/irq.h>
39#endif

 
 1#ifndef __UM_IRQ_H
 2#define __UM_IRQ_H
 3
 4#define TIMER_IRQ		0
 5#define UMN_IRQ			1
 6#define CONSOLE_IRQ		2
 7#define CONSOLE_WRITE_IRQ	3
 8#define UBD_IRQ			4
 9#define UM_ETH_IRQ		5
10#define SSL_IRQ			6
11#define SSL_WRITE_IRQ		7
12#define ACCEPT_IRQ		8
13#define MCONSOLE_IRQ		9
14#define WINCH_IRQ		10
15#define SIGIO_WRITE_IRQ 	11
16#define TELNETD_IRQ 		12
17#define XTERM_IRQ 		13
18#define RANDOM_IRQ 		14
19
20#define LAST_IRQ RANDOM_IRQ
21#define NR_IRQS (LAST_IRQ + 1)
22
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
23#endif