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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * iommu.c: IOMMU specific routines for memory management.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/slab.h>
15#include <linux/dma-map-ops.h>
16#include <linux/of.h>
17#include <linux/of_platform.h>
18#include <linux/platform_device.h>
19
20#include <asm/io.h>
21#include <asm/mxcc.h>
22#include <asm/mbus.h>
23#include <asm/cacheflush.h>
24#include <asm/tlbflush.h>
25#include <asm/bitext.h>
26#include <asm/iommu.h>
27#include <asm/dma.h>
28
29#include "mm_32.h"
30
31/*
32 * This can be sized dynamically, but we will do this
33 * only when we have a guidance about actual I/O pressures.
34 */
35#define IOMMU_RNGE IOMMU_RNGE_256MB
36#define IOMMU_START 0xF0000000
37#define IOMMU_WINSIZE (256*1024*1024U)
38#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
39#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
40
41static int viking_flush;
42/* viking.S */
43extern void viking_flush_page(unsigned long page);
44extern void viking_mxcc_flush_page(unsigned long page);
45
46/*
47 * Values precomputed according to CPU type.
48 */
49static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
50static pgprot_t dvma_prot; /* Consistent mapping pte flags */
51
52#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
53#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
54
55static const struct dma_map_ops sbus_iommu_dma_gflush_ops;
56static const struct dma_map_ops sbus_iommu_dma_pflush_ops;
57
58static void __init sbus_iommu_init(struct platform_device *op)
59{
60 struct iommu_struct *iommu;
61 unsigned int impl, vers;
62 unsigned long *bitmap;
63 unsigned long control;
64 unsigned long base;
65 unsigned long tmp;
66
67 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
68 if (!iommu) {
69 prom_printf("Unable to allocate iommu structure\n");
70 prom_halt();
71 }
72
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
74 "iommu_regs");
75 if (!iommu->regs) {
76 prom_printf("Cannot map IOMMU registers\n");
77 prom_halt();
78 }
79
80 control = sbus_readl(&iommu->regs->control);
81 impl = (control & IOMMU_CTRL_IMPL) >> 28;
82 vers = (control & IOMMU_CTRL_VERS) >> 24;
83 control &= ~(IOMMU_CTRL_RNGE);
84 control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
85 sbus_writel(control, &iommu->regs->control);
86
87 iommu_invalidate(iommu->regs);
88 iommu->start = IOMMU_START;
89 iommu->end = 0xffffffff;
90
91 /* Allocate IOMMU page table */
92 /* Stupid alignment constraints give me a headache.
93 We need 256K or 512K or 1M or 2M area aligned to
94 its size and current gfp will fortunately give
95 it to us. */
96 tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
97 if (!tmp) {
98 prom_printf("Unable to allocate iommu table [0x%lx]\n",
99 IOMMU_NPTES * sizeof(iopte_t));
100 prom_halt();
101 }
102 iommu->page_table = (iopte_t *)tmp;
103
104 /* Initialize new table. */
105 memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
106 flush_cache_all();
107 flush_tlb_all();
108
109 base = __pa((unsigned long)iommu->page_table) >> 4;
110 sbus_writel(base, &iommu->regs->base);
111 iommu_invalidate(iommu->regs);
112
113 bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
114 if (!bitmap) {
115 prom_printf("Unable to allocate iommu bitmap [%d]\n",
116 (int)(IOMMU_NPTES>>3));
117 prom_halt();
118 }
119 bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
120 /* To be coherent on HyperSparc, the page color of DVMA
121 * and physical addresses must match.
122 */
123 if (srmmu_modtype == HyperSparc)
124 iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
125 else
126 iommu->usemap.num_colors = 1;
127
128 printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
129 impl, vers, iommu->page_table,
130 (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
131
132 op->dev.archdata.iommu = iommu;
133
134 if (flush_page_for_dma_global)
135 op->dev.dma_ops = &sbus_iommu_dma_gflush_ops;
136 else
137 op->dev.dma_ops = &sbus_iommu_dma_pflush_ops;
138}
139
140static int __init iommu_init(void)
141{
142 struct device_node *dp;
143
144 for_each_node_by_name(dp, "iommu") {
145 struct platform_device *op = of_find_device_by_node(dp);
146
147 sbus_iommu_init(op);
148 of_propagate_archdata(op);
149 }
150
151 return 0;
152}
153
154subsys_initcall(iommu_init);
155
156/* Flush the iotlb entries to ram. */
157/* This could be better if we didn't have to flush whole pages. */
158static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
159{
160 unsigned long start;
161 unsigned long end;
162
163 start = (unsigned long)iopte;
164 end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
165 start &= PAGE_MASK;
166 if (viking_mxcc_present) {
167 while(start < end) {
168 viking_mxcc_flush_page(start);
169 start += PAGE_SIZE;
170 }
171 } else if (viking_flush) {
172 while(start < end) {
173 viking_flush_page(start);
174 start += PAGE_SIZE;
175 }
176 } else {
177 while(start < end) {
178 __flush_page_to_ram(start);
179 start += PAGE_SIZE;
180 }
181 }
182}
183
184static dma_addr_t __sbus_iommu_map_page(struct device *dev, struct page *page,
185 unsigned long offset, size_t len, bool per_page_flush)
186{
187 struct iommu_struct *iommu = dev->archdata.iommu;
188 phys_addr_t paddr = page_to_phys(page) + offset;
189 unsigned long off = paddr & ~PAGE_MASK;
190 unsigned long npages = (off + len + PAGE_SIZE - 1) >> PAGE_SHIFT;
191 unsigned long pfn = __phys_to_pfn(paddr);
192 unsigned int busa, busa0;
193 iopte_t *iopte, *iopte0;
194 int ioptex, i;
195
196 /* XXX So what is maxphys for us and how do drivers know it? */
197 if (!len || len > 256 * 1024)
198 return DMA_MAPPING_ERROR;
199
200 /*
201 * We expect unmapped highmem pages to be not in the cache.
202 * XXX Is this a good assumption?
203 * XXX What if someone else unmaps it here and races us?
204 */
205 if (per_page_flush && !PageHighMem(page)) {
206 unsigned long vaddr, p;
207
208 vaddr = (unsigned long)page_address(page) + offset;
209 for (p = vaddr & PAGE_MASK; p < vaddr + len; p += PAGE_SIZE)
210 flush_page_for_dma(p);
211 }
212
213 /* page color = pfn of page */
214 ioptex = bit_map_string_get(&iommu->usemap, npages, pfn);
215 if (ioptex < 0)
216 panic("iommu out");
217 busa0 = iommu->start + (ioptex << PAGE_SHIFT);
218 iopte0 = &iommu->page_table[ioptex];
219
220 busa = busa0;
221 iopte = iopte0;
222 for (i = 0; i < npages; i++) {
223 iopte_val(*iopte) = MKIOPTE(pfn, IOPERM);
224 iommu_invalidate_page(iommu->regs, busa);
225 busa += PAGE_SIZE;
226 iopte++;
227 pfn++;
228 }
229
230 iommu_flush_iotlb(iopte0, npages);
231 return busa0 + off;
232}
233
234static dma_addr_t sbus_iommu_map_page_gflush(struct device *dev,
235 struct page *page, unsigned long offset, size_t len,
236 enum dma_data_direction dir, unsigned long attrs)
237{
238 flush_page_for_dma(0);
239 return __sbus_iommu_map_page(dev, page, offset, len, false);
240}
241
242static dma_addr_t sbus_iommu_map_page_pflush(struct device *dev,
243 struct page *page, unsigned long offset, size_t len,
244 enum dma_data_direction dir, unsigned long attrs)
245{
246 return __sbus_iommu_map_page(dev, page, offset, len, true);
247}
248
249static int __sbus_iommu_map_sg(struct device *dev, struct scatterlist *sgl,
250 int nents, enum dma_data_direction dir, unsigned long attrs,
251 bool per_page_flush)
252{
253 struct scatterlist *sg;
254 int j;
255
256 for_each_sg(sgl, sg, nents, j) {
257 sg->dma_address =__sbus_iommu_map_page(dev, sg_page(sg),
258 sg->offset, sg->length, per_page_flush);
259 if (sg->dma_address == DMA_MAPPING_ERROR)
260 return -EIO;
261 sg->dma_length = sg->length;
262 }
263
264 return nents;
265}
266
267static int sbus_iommu_map_sg_gflush(struct device *dev, struct scatterlist *sgl,
268 int nents, enum dma_data_direction dir, unsigned long attrs)
269{
270 flush_page_for_dma(0);
271 return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, false);
272}
273
274static int sbus_iommu_map_sg_pflush(struct device *dev, struct scatterlist *sgl,
275 int nents, enum dma_data_direction dir, unsigned long attrs)
276{
277 return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, true);
278}
279
280static void sbus_iommu_unmap_page(struct device *dev, dma_addr_t dma_addr,
281 size_t len, enum dma_data_direction dir, unsigned long attrs)
282{
283 struct iommu_struct *iommu = dev->archdata.iommu;
284 unsigned int busa = dma_addr & PAGE_MASK;
285 unsigned long off = dma_addr & ~PAGE_MASK;
286 unsigned int npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
287 unsigned int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
288 unsigned int i;
289
290 BUG_ON(busa < iommu->start);
291 for (i = 0; i < npages; i++) {
292 iopte_val(iommu->page_table[ioptex + i]) = 0;
293 iommu_invalidate_page(iommu->regs, busa);
294 busa += PAGE_SIZE;
295 }
296 bit_map_clear(&iommu->usemap, ioptex, npages);
297}
298
299static void sbus_iommu_unmap_sg(struct device *dev, struct scatterlist *sgl,
300 int nents, enum dma_data_direction dir, unsigned long attrs)
301{
302 struct scatterlist *sg;
303 int i;
304
305 for_each_sg(sgl, sg, nents, i) {
306 sbus_iommu_unmap_page(dev, sg->dma_address, sg->length, dir,
307 attrs);
308 sg->dma_address = 0x21212121;
309 }
310}
311
312#ifdef CONFIG_SBUS
313static void *sbus_iommu_alloc(struct device *dev, size_t len,
314 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
315{
316 struct iommu_struct *iommu = dev->archdata.iommu;
317 unsigned long va, addr, page, end, ret;
318 iopte_t *iopte = iommu->page_table;
319 iopte_t *first;
320 int ioptex;
321
322 /* XXX So what is maxphys for us and how do drivers know it? */
323 if (!len || len > 256 * 1024)
324 return NULL;
325
326 len = PAGE_ALIGN(len);
327 va = __get_free_pages(gfp | __GFP_ZERO, get_order(len));
328 if (va == 0)
329 return NULL;
330
331 addr = ret = sparc_dma_alloc_resource(dev, len);
332 if (!addr)
333 goto out_free_pages;
334
335 BUG_ON((va & ~PAGE_MASK) != 0);
336 BUG_ON((addr & ~PAGE_MASK) != 0);
337 BUG_ON((len & ~PAGE_MASK) != 0);
338
339 /* page color = physical address */
340 ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
341 addr >> PAGE_SHIFT);
342 if (ioptex < 0)
343 panic("iommu out");
344
345 iopte += ioptex;
346 first = iopte;
347 end = addr + len;
348 while(addr < end) {
349 page = va;
350 {
351 pmd_t *pmdp;
352 pte_t *ptep;
353
354 if (viking_mxcc_present)
355 viking_mxcc_flush_page(page);
356 else if (viking_flush)
357 viking_flush_page(page);
358 else
359 __flush_page_to_ram(page);
360
361 pmdp = pmd_off_k(addr);
362 ptep = pte_offset_kernel(pmdp, addr);
363
364 set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
365 }
366 iopte_val(*iopte++) =
367 MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
368 addr += PAGE_SIZE;
369 va += PAGE_SIZE;
370 }
371 /* P3: why do we need this?
372 *
373 * DAVEM: Because there are several aspects, none of which
374 * are handled by a single interface. Some cpus are
375 * completely not I/O DMA coherent, and some have
376 * virtually indexed caches. The driver DMA flushing
377 * methods handle the former case, but here during
378 * IOMMU page table modifications, and usage of non-cacheable
379 * cpu mappings of pages potentially in the cpu caches, we have
380 * to handle the latter case as well.
381 */
382 flush_cache_all();
383 iommu_flush_iotlb(first, len >> PAGE_SHIFT);
384 flush_tlb_all();
385 iommu_invalidate(iommu->regs);
386
387 *dma_handle = iommu->start + (ioptex << PAGE_SHIFT);
388 return (void *)ret;
389
390out_free_pages:
391 free_pages(va, get_order(len));
392 return NULL;
393}
394
395static void sbus_iommu_free(struct device *dev, size_t len, void *cpu_addr,
396 dma_addr_t busa, unsigned long attrs)
397{
398 struct iommu_struct *iommu = dev->archdata.iommu;
399 iopte_t *iopte = iommu->page_table;
400 struct page *page = virt_to_page(cpu_addr);
401 int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
402 unsigned long end;
403
404 if (!sparc_dma_free_resource(cpu_addr, len))
405 return;
406
407 BUG_ON((busa & ~PAGE_MASK) != 0);
408 BUG_ON((len & ~PAGE_MASK) != 0);
409
410 iopte += ioptex;
411 end = busa + len;
412 while (busa < end) {
413 iopte_val(*iopte++) = 0;
414 busa += PAGE_SIZE;
415 }
416 flush_tlb_all();
417 iommu_invalidate(iommu->regs);
418 bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
419
420 __free_pages(page, get_order(len));
421}
422#endif
423
424static const struct dma_map_ops sbus_iommu_dma_gflush_ops = {
425#ifdef CONFIG_SBUS
426 .alloc = sbus_iommu_alloc,
427 .free = sbus_iommu_free,
428#endif
429 .map_page = sbus_iommu_map_page_gflush,
430 .unmap_page = sbus_iommu_unmap_page,
431 .map_sg = sbus_iommu_map_sg_gflush,
432 .unmap_sg = sbus_iommu_unmap_sg,
433};
434
435static const struct dma_map_ops sbus_iommu_dma_pflush_ops = {
436#ifdef CONFIG_SBUS
437 .alloc = sbus_iommu_alloc,
438 .free = sbus_iommu_free,
439#endif
440 .map_page = sbus_iommu_map_page_pflush,
441 .unmap_page = sbus_iommu_unmap_page,
442 .map_sg = sbus_iommu_map_sg_pflush,
443 .unmap_sg = sbus_iommu_unmap_sg,
444};
445
446void __init ld_mmu_iommu(void)
447{
448 if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
449 dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
450 ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
451 } else {
452 dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
453 ioperm_noc = IOPTE_WRITE | IOPTE_VALID;
454 }
455}
1/*
2 * iommu.c: IOMMU specific routines for memory management.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/mm.h>
13#include <linux/slab.h>
14#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */
15#include <linux/scatterlist.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18
19#include <asm/pgalloc.h>
20#include <asm/pgtable.h>
21#include <asm/io.h>
22#include <asm/mxcc.h>
23#include <asm/mbus.h>
24#include <asm/cacheflush.h>
25#include <asm/tlbflush.h>
26#include <asm/bitext.h>
27#include <asm/iommu.h>
28#include <asm/dma.h>
29
30#include "mm_32.h"
31
32/*
33 * This can be sized dynamically, but we will do this
34 * only when we have a guidance about actual I/O pressures.
35 */
36#define IOMMU_RNGE IOMMU_RNGE_256MB
37#define IOMMU_START 0xF0000000
38#define IOMMU_WINSIZE (256*1024*1024U)
39#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
40#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
41
42static int viking_flush;
43/* viking.S */
44extern void viking_flush_page(unsigned long page);
45extern void viking_mxcc_flush_page(unsigned long page);
46
47/*
48 * Values precomputed according to CPU type.
49 */
50static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
51static pgprot_t dvma_prot; /* Consistent mapping pte flags */
52
53#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
54#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
55
56static void __init sbus_iommu_init(struct platform_device *op)
57{
58 struct iommu_struct *iommu;
59 unsigned int impl, vers;
60 unsigned long *bitmap;
61 unsigned long control;
62 unsigned long base;
63 unsigned long tmp;
64
65 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
66 if (!iommu) {
67 prom_printf("Unable to allocate iommu structure\n");
68 prom_halt();
69 }
70
71 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
72 "iommu_regs");
73 if (!iommu->regs) {
74 prom_printf("Cannot map IOMMU registers\n");
75 prom_halt();
76 }
77
78 control = sbus_readl(&iommu->regs->control);
79 impl = (control & IOMMU_CTRL_IMPL) >> 28;
80 vers = (control & IOMMU_CTRL_VERS) >> 24;
81 control &= ~(IOMMU_CTRL_RNGE);
82 control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
83 sbus_writel(control, &iommu->regs->control);
84
85 iommu_invalidate(iommu->regs);
86 iommu->start = IOMMU_START;
87 iommu->end = 0xffffffff;
88
89 /* Allocate IOMMU page table */
90 /* Stupid alignment constraints give me a headache.
91 We need 256K or 512K or 1M or 2M area aligned to
92 its size and current gfp will fortunately give
93 it to us. */
94 tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
95 if (!tmp) {
96 prom_printf("Unable to allocate iommu table [0x%lx]\n",
97 IOMMU_NPTES * sizeof(iopte_t));
98 prom_halt();
99 }
100 iommu->page_table = (iopte_t *)tmp;
101
102 /* Initialize new table. */
103 memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
104 flush_cache_all();
105 flush_tlb_all();
106
107 base = __pa((unsigned long)iommu->page_table) >> 4;
108 sbus_writel(base, &iommu->regs->base);
109 iommu_invalidate(iommu->regs);
110
111 bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
112 if (!bitmap) {
113 prom_printf("Unable to allocate iommu bitmap [%d]\n",
114 (int)(IOMMU_NPTES>>3));
115 prom_halt();
116 }
117 bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
118 /* To be coherent on HyperSparc, the page color of DVMA
119 * and physical addresses must match.
120 */
121 if (srmmu_modtype == HyperSparc)
122 iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
123 else
124 iommu->usemap.num_colors = 1;
125
126 printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
127 impl, vers, iommu->page_table,
128 (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
129
130 op->dev.archdata.iommu = iommu;
131}
132
133static int __init iommu_init(void)
134{
135 struct device_node *dp;
136
137 for_each_node_by_name(dp, "iommu") {
138 struct platform_device *op = of_find_device_by_node(dp);
139
140 sbus_iommu_init(op);
141 of_propagate_archdata(op);
142 }
143
144 return 0;
145}
146
147subsys_initcall(iommu_init);
148
149/* Flush the iotlb entries to ram. */
150/* This could be better if we didn't have to flush whole pages. */
151static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
152{
153 unsigned long start;
154 unsigned long end;
155
156 start = (unsigned long)iopte;
157 end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
158 start &= PAGE_MASK;
159 if (viking_mxcc_present) {
160 while(start < end) {
161 viking_mxcc_flush_page(start);
162 start += PAGE_SIZE;
163 }
164 } else if (viking_flush) {
165 while(start < end) {
166 viking_flush_page(start);
167 start += PAGE_SIZE;
168 }
169 } else {
170 while(start < end) {
171 __flush_page_to_ram(start);
172 start += PAGE_SIZE;
173 }
174 }
175}
176
177static u32 iommu_get_one(struct device *dev, struct page *page, int npages)
178{
179 struct iommu_struct *iommu = dev->archdata.iommu;
180 int ioptex;
181 iopte_t *iopte, *iopte0;
182 unsigned int busa, busa0;
183 int i;
184
185 /* page color = pfn of page */
186 ioptex = bit_map_string_get(&iommu->usemap, npages, page_to_pfn(page));
187 if (ioptex < 0)
188 panic("iommu out");
189 busa0 = iommu->start + (ioptex << PAGE_SHIFT);
190 iopte0 = &iommu->page_table[ioptex];
191
192 busa = busa0;
193 iopte = iopte0;
194 for (i = 0; i < npages; i++) {
195 iopte_val(*iopte) = MKIOPTE(page_to_pfn(page), IOPERM);
196 iommu_invalidate_page(iommu->regs, busa);
197 busa += PAGE_SIZE;
198 iopte++;
199 page++;
200 }
201
202 iommu_flush_iotlb(iopte0, npages);
203
204 return busa0;
205}
206
207static u32 iommu_get_scsi_one(struct device *dev, char *vaddr, unsigned int len)
208{
209 unsigned long off;
210 int npages;
211 struct page *page;
212 u32 busa;
213
214 off = (unsigned long)vaddr & ~PAGE_MASK;
215 npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
216 page = virt_to_page((unsigned long)vaddr & PAGE_MASK);
217 busa = iommu_get_one(dev, page, npages);
218 return busa + off;
219}
220
221static __u32 iommu_get_scsi_one_gflush(struct device *dev, char *vaddr, unsigned long len)
222{
223 flush_page_for_dma(0);
224 return iommu_get_scsi_one(dev, vaddr, len);
225}
226
227static __u32 iommu_get_scsi_one_pflush(struct device *dev, char *vaddr, unsigned long len)
228{
229 unsigned long page = ((unsigned long) vaddr) & PAGE_MASK;
230
231 while(page < ((unsigned long)(vaddr + len))) {
232 flush_page_for_dma(page);
233 page += PAGE_SIZE;
234 }
235 return iommu_get_scsi_one(dev, vaddr, len);
236}
237
238static void iommu_get_scsi_sgl_gflush(struct device *dev, struct scatterlist *sg, int sz)
239{
240 int n;
241
242 flush_page_for_dma(0);
243 while (sz != 0) {
244 --sz;
245 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
246 sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
247 sg->dma_length = sg->length;
248 sg = sg_next(sg);
249 }
250}
251
252static void iommu_get_scsi_sgl_pflush(struct device *dev, struct scatterlist *sg, int sz)
253{
254 unsigned long page, oldpage = 0;
255 int n, i;
256
257 while(sz != 0) {
258 --sz;
259
260 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
261
262 /*
263 * We expect unmapped highmem pages to be not in the cache.
264 * XXX Is this a good assumption?
265 * XXX What if someone else unmaps it here and races us?
266 */
267 if ((page = (unsigned long) page_address(sg_page(sg))) != 0) {
268 for (i = 0; i < n; i++) {
269 if (page != oldpage) { /* Already flushed? */
270 flush_page_for_dma(page);
271 oldpage = page;
272 }
273 page += PAGE_SIZE;
274 }
275 }
276
277 sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
278 sg->dma_length = sg->length;
279 sg = sg_next(sg);
280 }
281}
282
283static void iommu_release_one(struct device *dev, u32 busa, int npages)
284{
285 struct iommu_struct *iommu = dev->archdata.iommu;
286 int ioptex;
287 int i;
288
289 BUG_ON(busa < iommu->start);
290 ioptex = (busa - iommu->start) >> PAGE_SHIFT;
291 for (i = 0; i < npages; i++) {
292 iopte_val(iommu->page_table[ioptex + i]) = 0;
293 iommu_invalidate_page(iommu->regs, busa);
294 busa += PAGE_SIZE;
295 }
296 bit_map_clear(&iommu->usemap, ioptex, npages);
297}
298
299static void iommu_release_scsi_one(struct device *dev, __u32 vaddr, unsigned long len)
300{
301 unsigned long off;
302 int npages;
303
304 off = vaddr & ~PAGE_MASK;
305 npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
306 iommu_release_one(dev, vaddr & PAGE_MASK, npages);
307}
308
309static void iommu_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
310{
311 int n;
312
313 while(sz != 0) {
314 --sz;
315
316 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
317 iommu_release_one(dev, sg->dma_address & PAGE_MASK, n);
318 sg->dma_address = 0x21212121;
319 sg = sg_next(sg);
320 }
321}
322
323#ifdef CONFIG_SBUS
324static int iommu_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va,
325 unsigned long addr, int len)
326{
327 struct iommu_struct *iommu = dev->archdata.iommu;
328 unsigned long page, end;
329 iopte_t *iopte = iommu->page_table;
330 iopte_t *first;
331 int ioptex;
332
333 BUG_ON((va & ~PAGE_MASK) != 0);
334 BUG_ON((addr & ~PAGE_MASK) != 0);
335 BUG_ON((len & ~PAGE_MASK) != 0);
336
337 /* page color = physical address */
338 ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
339 addr >> PAGE_SHIFT);
340 if (ioptex < 0)
341 panic("iommu out");
342
343 iopte += ioptex;
344 first = iopte;
345 end = addr + len;
346 while(addr < end) {
347 page = va;
348 {
349 pgd_t *pgdp;
350 pmd_t *pmdp;
351 pte_t *ptep;
352
353 if (viking_mxcc_present)
354 viking_mxcc_flush_page(page);
355 else if (viking_flush)
356 viking_flush_page(page);
357 else
358 __flush_page_to_ram(page);
359
360 pgdp = pgd_offset(&init_mm, addr);
361 pmdp = pmd_offset(pgdp, addr);
362 ptep = pte_offset_map(pmdp, addr);
363
364 set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
365 }
366 iopte_val(*iopte++) =
367 MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
368 addr += PAGE_SIZE;
369 va += PAGE_SIZE;
370 }
371 /* P3: why do we need this?
372 *
373 * DAVEM: Because there are several aspects, none of which
374 * are handled by a single interface. Some cpus are
375 * completely not I/O DMA coherent, and some have
376 * virtually indexed caches. The driver DMA flushing
377 * methods handle the former case, but here during
378 * IOMMU page table modifications, and usage of non-cacheable
379 * cpu mappings of pages potentially in the cpu caches, we have
380 * to handle the latter case as well.
381 */
382 flush_cache_all();
383 iommu_flush_iotlb(first, len >> PAGE_SHIFT);
384 flush_tlb_all();
385 iommu_invalidate(iommu->regs);
386
387 *pba = iommu->start + (ioptex << PAGE_SHIFT);
388 return 0;
389}
390
391static void iommu_unmap_dma_area(struct device *dev, unsigned long busa, int len)
392{
393 struct iommu_struct *iommu = dev->archdata.iommu;
394 iopte_t *iopte = iommu->page_table;
395 unsigned long end;
396 int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
397
398 BUG_ON((busa & ~PAGE_MASK) != 0);
399 BUG_ON((len & ~PAGE_MASK) != 0);
400
401 iopte += ioptex;
402 end = busa + len;
403 while (busa < end) {
404 iopte_val(*iopte++) = 0;
405 busa += PAGE_SIZE;
406 }
407 flush_tlb_all();
408 iommu_invalidate(iommu->regs);
409 bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
410}
411#endif
412
413static const struct sparc32_dma_ops iommu_dma_gflush_ops = {
414 .get_scsi_one = iommu_get_scsi_one_gflush,
415 .get_scsi_sgl = iommu_get_scsi_sgl_gflush,
416 .release_scsi_one = iommu_release_scsi_one,
417 .release_scsi_sgl = iommu_release_scsi_sgl,
418#ifdef CONFIG_SBUS
419 .map_dma_area = iommu_map_dma_area,
420 .unmap_dma_area = iommu_unmap_dma_area,
421#endif
422};
423
424static const struct sparc32_dma_ops iommu_dma_pflush_ops = {
425 .get_scsi_one = iommu_get_scsi_one_pflush,
426 .get_scsi_sgl = iommu_get_scsi_sgl_pflush,
427 .release_scsi_one = iommu_release_scsi_one,
428 .release_scsi_sgl = iommu_release_scsi_sgl,
429#ifdef CONFIG_SBUS
430 .map_dma_area = iommu_map_dma_area,
431 .unmap_dma_area = iommu_unmap_dma_area,
432#endif
433};
434
435void __init ld_mmu_iommu(void)
436{
437 if (flush_page_for_dma_global) {
438 /* flush_page_for_dma flushes everything, no matter of what page is it */
439 sparc32_dma_ops = &iommu_dma_gflush_ops;
440 } else {
441 sparc32_dma_ops = &iommu_dma_pflush_ops;
442 }
443
444 if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
445 dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
446 ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
447 } else {
448 dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
449 ioperm_noc = IOPTE_WRITE | IOPTE_VALID;
450 }
451}