Loading...
1// SPDX-License-Identifier: GPL-2.0
2/***************************************************************************/
3
4/*
5 * m5249.c -- platform support for ColdFire 5249 based boards
6 *
7 * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
8 */
9
10/***************************************************************************/
11
12#include <linux/clkdev.h>
13#include <linux/kernel.h>
14#include <linux/param.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <asm/machdep.h>
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfclk.h>
22
23/***************************************************************************/
24
25DEFINE_CLK(pll, "pll.0", MCF_CLK);
26DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
27
28struct clk_lookup m5249_clk_lookup[] = {
29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
30 CLKDEV_INIT(NULL, "sys.0", &clk_sys),
31 CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
32 CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
33 CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
34 CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
35 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
36 CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
37 CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
38};
39
40/***************************************************************************/
41
42#ifdef CONFIG_M5249C3
43
44static struct resource m5249_smc91x_resources[] = {
45 {
46 .start = 0xe0000300,
47 .end = 0xe0000300 + 0x100,
48 .flags = IORESOURCE_MEM,
49 },
50 {
51 .start = MCF_IRQ_GPIO6,
52 .end = MCF_IRQ_GPIO6,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct platform_device m5249_smc91x = {
58 .name = "smc91x",
59 .id = 0,
60 .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
61 .resource = m5249_smc91x_resources,
62};
63
64#endif /* CONFIG_M5249C3 */
65
66static struct platform_device *m5249_devices[] __initdata = {
67#ifdef CONFIG_M5249C3
68 &m5249_smc91x,
69#endif
70};
71
72/***************************************************************************/
73
74static void __init m5249_qspi_init(void)
75{
76#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
77 /* QSPI irq setup */
78 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
79 MCFSIM_QSPIICR);
80 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
81#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
82}
83
84/***************************************************************************/
85
86static void __init m5249_i2c_init(void)
87{
88#if IS_ENABLED(CONFIG_I2C_IMX)
89 u32 r;
90
91 /* first I2C controller uses regular irq setup */
92 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
93 MCFSIM_I2CICR);
94 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
95
96 /* second I2C controller is completely different */
97 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
98 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
99 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
100 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
101#endif /* CONFIG_I2C_IMX */
102}
103
104/***************************************************************************/
105
106#ifdef CONFIG_M5249C3
107
108static void __init m5249_smc91x_init(void)
109{
110 u32 gpio;
111
112 /* Set the GPIO line as interrupt source for smc91x device */
113 gpio = readl(MCFSIM2_GPIOINTENABLE);
114 writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
115
116 gpio = readl(MCFINTC2_INTPRI5);
117 writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
118}
119
120#endif /* CONFIG_M5249C3 */
121
122/***************************************************************************/
123
124void __init config_BSP(char *commandp, int size)
125{
126 mach_sched_init = hw_timer_init;
127
128#ifdef CONFIG_M5249C3
129 m5249_smc91x_init();
130#endif
131 m5249_qspi_init();
132 m5249_i2c_init();
133
134 clkdev_add_table(m5249_clk_lookup, ARRAY_SIZE(m5249_clk_lookup));
135}
136
137/***************************************************************************/
138
139static int __init init_BSP(void)
140{
141 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
142 return 0;
143}
144
145arch_initcall(init_BSP);
146
147/***************************************************************************/
1/***************************************************************************/
2
3/*
4 * m5249.c -- platform support for ColdFire 5249 based boards
5 *
6 * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
30
31struct clk *mcf_clks[] = {
32 &clk_pll,
33 &clk_sys,
34 &clk_mcftmr0,
35 &clk_mcftmr1,
36 &clk_mcfuart0,
37 &clk_mcfuart1,
38 &clk_mcfqspi0,
39 NULL
40};
41
42/***************************************************************************/
43
44#ifdef CONFIG_M5249C3
45
46static struct resource m5249_smc91x_resources[] = {
47 {
48 .start = 0xe0000300,
49 .end = 0xe0000300 + 0x100,
50 .flags = IORESOURCE_MEM,
51 },
52 {
53 .start = MCF_IRQ_GPIO6,
54 .end = MCF_IRQ_GPIO6,
55 .flags = IORESOURCE_IRQ,
56 },
57};
58
59static struct platform_device m5249_smc91x = {
60 .name = "smc91x",
61 .id = 0,
62 .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
63 .resource = m5249_smc91x_resources,
64};
65
66#endif /* CONFIG_M5249C3 */
67
68static struct platform_device *m5249_devices[] __initdata = {
69#ifdef CONFIG_M5249C3
70 &m5249_smc91x,
71#endif
72};
73
74/***************************************************************************/
75
76static void __init m5249_qspi_init(void)
77{
78#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
79 /* QSPI irq setup */
80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
81 MCFSIM_QSPIICR);
82 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
83#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
84}
85
86/***************************************************************************/
87
88#ifdef CONFIG_M5249C3
89
90static void __init m5249_smc91x_init(void)
91{
92 u32 gpio;
93
94 /* Set the GPIO line as interrupt source for smc91x device */
95 gpio = readl(MCFSIM2_GPIOINTENABLE);
96 writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
97
98 gpio = readl(MCFINTC2_INTPRI5);
99 writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
100}
101
102#endif /* CONFIG_M5249C3 */
103
104/***************************************************************************/
105
106void __init config_BSP(char *commandp, int size)
107{
108 mach_sched_init = hw_timer_init;
109
110#ifdef CONFIG_M5249C3
111 m5249_smc91x_init();
112#endif
113 m5249_qspi_init();
114}
115
116/***************************************************************************/
117
118static int __init init_BSP(void)
119{
120 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
121 return 0;
122}
123
124arch_initcall(init_BSP);
125
126/***************************************************************************/