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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2018 Intel Corporation. All rights reserved.
7//
8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10// Rander Wang <rander.wang@intel.com>
11// Keyon Jie <yang.jie@linux.intel.com>
12//
13
14/*
15 * Hardware interface for generic Intel audio DSP HDA IP
16 */
17
18#include <sound/hdaudio_ext.h>
19#include <sound/hda_register.h>
20
21#include <linux/acpi.h>
22#include <linux/module.h>
23#include <linux/soundwire/sdw.h>
24#include <linux/soundwire/sdw_intel.h>
25#include <sound/intel-dsp-config.h>
26#include <sound/intel-nhlt.h>
27#include <sound/sof.h>
28#include <sound/sof/xtensa.h>
29#include <sound/hda-mlink.h>
30#include "../sof-audio.h"
31#include "../sof-pci-dev.h"
32#include "../ops.h"
33#include "hda.h"
34#include "telemetry.h"
35
36#define CREATE_TRACE_POINTS
37#include <trace/events/sof_intel.h>
38
39#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
40#include <sound/soc-acpi-intel-match.h>
41#endif
42
43/* platform specific devices */
44#include "shim.h"
45
46#define EXCEPT_MAX_HDR_SIZE 0x400
47#define HDA_EXT_ROM_STATUS_SIZE 8
48
49static u32 hda_get_interface_mask(struct snd_sof_dev *sdev)
50{
51 const struct sof_intel_dsp_desc *chip;
52 u32 interface_mask[2] = { 0 };
53
54 chip = get_chip_info(sdev->pdata);
55 switch (chip->hw_ip_version) {
56 case SOF_INTEL_TANGIER:
57 case SOF_INTEL_BAYTRAIL:
58 case SOF_INTEL_BROADWELL:
59 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP);
60 break;
61 case SOF_INTEL_CAVS_1_5:
62 case SOF_INTEL_CAVS_1_5_PLUS:
63 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
64 BIT(SOF_DAI_INTEL_HDA);
65 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA);
66 break;
67 case SOF_INTEL_CAVS_1_8:
68 case SOF_INTEL_CAVS_2_0:
69 case SOF_INTEL_CAVS_2_5:
70 case SOF_INTEL_ACE_1_0:
71 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
72 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
73 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA);
74 break;
75 case SOF_INTEL_ACE_2_0:
76 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
77 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
78 interface_mask[1] = interface_mask[0]; /* all interfaces accessible without DSP */
79 break;
80 default:
81 break;
82 }
83
84 return interface_mask[sdev->dspless_mode_selected];
85}
86
87#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
88
89/*
90 * The default for SoundWire clock stop quirks is to power gate the IP
91 * and do a Bus Reset, this will need to be modified when the DSP
92 * needs to remain in D0i3 so that the Master does not lose context
93 * and enumeration is not required on clock restart
94 */
95static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET;
96module_param(sdw_clock_stop_quirks, int, 0444);
97MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks");
98
99static int sdw_params_stream(struct device *dev,
100 struct sdw_intel_stream_params_data *params_data)
101{
102 struct snd_soc_dai *d = params_data->dai;
103 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->substream->stream);
104 struct snd_sof_dai_config_data data = { 0 };
105
106 data.dai_index = (params_data->link_id << 8) | d->id;
107 data.dai_data = params_data->alh_stream_id;
108
109 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data);
110}
111
112struct sdw_intel_ops sdw_callback = {
113 .params_stream = sdw_params_stream,
114};
115
116static int sdw_ace2x_params_stream(struct device *dev,
117 struct sdw_intel_stream_params_data *params_data)
118{
119 return sdw_hda_dai_hw_params(params_data->substream,
120 params_data->hw_params,
121 params_data->dai,
122 params_data->link_id);
123}
124
125static int sdw_ace2x_free_stream(struct device *dev,
126 struct sdw_intel_stream_free_data *free_data)
127{
128 return sdw_hda_dai_hw_free(free_data->substream,
129 free_data->dai,
130 free_data->link_id);
131}
132
133static int sdw_ace2x_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
134{
135 return sdw_hda_dai_trigger(substream, cmd, dai);
136}
137
138static struct sdw_intel_ops sdw_ace2x_callback = {
139 .params_stream = sdw_ace2x_params_stream,
140 .free_stream = sdw_ace2x_free_stream,
141 .trigger = sdw_ace2x_trigger,
142};
143
144void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
145{
146 struct sof_intel_hda_dev *hdev;
147
148 hdev = sdev->pdata->hw_pdata;
149
150 if (!hdev->sdw)
151 return;
152
153 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2,
154 HDA_DSP_REG_ADSPIC2_SNDW,
155 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0);
156}
157
158void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
159{
160 u32 interface_mask = hda_get_interface_mask(sdev);
161 const struct sof_intel_dsp_desc *chip;
162
163 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
164 return;
165
166 chip = get_chip_info(sdev->pdata);
167 if (chip && chip->enable_sdw_irq)
168 chip->enable_sdw_irq(sdev, enable);
169}
170
171static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
172{
173 u32 interface_mask = hda_get_interface_mask(sdev);
174 struct sof_intel_hda_dev *hdev;
175 acpi_handle handle;
176 int ret;
177
178 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
179 return -EINVAL;
180
181 handle = ACPI_HANDLE(sdev->dev);
182
183 /* save ACPI info for the probe step */
184 hdev = sdev->pdata->hw_pdata;
185
186 ret = sdw_intel_acpi_scan(handle, &hdev->info);
187 if (ret < 0)
188 return -EINVAL;
189
190 return 0;
191}
192
193static int hda_sdw_probe(struct snd_sof_dev *sdev)
194{
195 const struct sof_intel_dsp_desc *chip;
196 struct sof_intel_hda_dev *hdev;
197 struct sdw_intel_res res;
198 void *sdw;
199
200 hdev = sdev->pdata->hw_pdata;
201
202 memset(&res, 0, sizeof(res));
203
204 chip = get_chip_info(sdev->pdata);
205 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) {
206 res.mmio_base = sdev->bar[HDA_DSP_BAR];
207 res.hw_ops = &sdw_intel_cnl_hw_ops;
208 res.shim_base = hdev->desc->sdw_shim_base;
209 res.alh_base = hdev->desc->sdw_alh_base;
210 res.ext = false;
211 res.ops = &sdw_callback;
212 } else {
213 /*
214 * retrieve eml_lock needed to protect shared registers
215 * in the HDaudio multi-link areas
216 */
217 res.eml_lock = hdac_bus_eml_get_mutex(sof_to_bus(sdev), true,
218 AZX_REG_ML_LEPTR_ID_SDW);
219 if (!res.eml_lock)
220 return -ENODEV;
221
222 res.mmio_base = sdev->bar[HDA_DSP_HDA_BAR];
223 /*
224 * the SHIM and SoundWire register offsets are link-specific
225 * and will be determined when adding auxiliary devices
226 */
227 res.hw_ops = &sdw_intel_lnl_hw_ops;
228 res.ext = true;
229 res.ops = &sdw_ace2x_callback;
230
231 }
232 res.irq = sdev->ipc_irq;
233 res.handle = hdev->info.handle;
234 res.parent = sdev->dev;
235
236 res.dev = sdev->dev;
237 res.clock_stop_quirks = sdw_clock_stop_quirks;
238 res.hbus = sof_to_bus(sdev);
239
240 /*
241 * ops and arg fields are not populated for now,
242 * they will be needed when the DAI callbacks are
243 * provided
244 */
245
246 /* we could filter links here if needed, e.g for quirks */
247 res.count = hdev->info.count;
248 res.link_mask = hdev->info.link_mask;
249
250 sdw = sdw_intel_probe(&res);
251 if (!sdw) {
252 dev_err(sdev->dev, "error: SoundWire probe failed\n");
253 return -EINVAL;
254 }
255
256 /* save context */
257 hdev->sdw = sdw;
258
259 return 0;
260}
261
262int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev)
263{
264 struct sof_intel_hda_dev *hdev;
265 struct sdw_intel_ctx *ctx;
266 u32 caps;
267
268 hdev = sdev->pdata->hw_pdata;
269 ctx = hdev->sdw;
270
271 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP);
272 caps &= SDW_SHIM_LCAP_LCOUNT_MASK;
273
274 /* Check HW supported vs property value */
275 if (caps < ctx->count) {
276 dev_err(sdev->dev,
277 "%s: BIOS master count %d is larger than hardware capabilities %d\n",
278 __func__, ctx->count, caps);
279 return -EINVAL;
280 }
281
282 return 0;
283}
284
285int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev)
286{
287 struct sof_intel_hda_dev *hdev;
288 struct sdw_intel_ctx *ctx;
289 struct hdac_bus *bus;
290 u32 slcount;
291
292 bus = sof_to_bus(sdev);
293
294 hdev = sdev->pdata->hw_pdata;
295 ctx = hdev->sdw;
296
297 slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
298
299 /* Check HW supported vs property value */
300 if (slcount < ctx->count) {
301 dev_err(sdev->dev,
302 "%s: BIOS master count %d is larger than hardware capabilities %d\n",
303 __func__, ctx->count, slcount);
304 return -EINVAL;
305 }
306
307 return 0;
308}
309
310static int hda_sdw_check_lcount(struct snd_sof_dev *sdev)
311{
312 const struct sof_intel_dsp_desc *chip;
313
314 chip = get_chip_info(sdev->pdata);
315 if (chip && chip->read_sdw_lcount)
316 return chip->read_sdw_lcount(sdev);
317
318 return 0;
319}
320
321int hda_sdw_startup(struct snd_sof_dev *sdev)
322{
323 struct sof_intel_hda_dev *hdev;
324 struct snd_sof_pdata *pdata = sdev->pdata;
325 int ret;
326
327 hdev = sdev->pdata->hw_pdata;
328
329 if (!hdev->sdw)
330 return 0;
331
332 if (pdata->machine && !pdata->machine->mach_params.link_mask)
333 return 0;
334
335 ret = hda_sdw_check_lcount(sdev);
336 if (ret < 0)
337 return ret;
338
339 return sdw_intel_startup(hdev->sdw);
340}
341
342static int hda_sdw_exit(struct snd_sof_dev *sdev)
343{
344 struct sof_intel_hda_dev *hdev;
345
346 hdev = sdev->pdata->hw_pdata;
347
348 hda_sdw_int_enable(sdev, false);
349
350 if (hdev->sdw)
351 sdw_intel_exit(hdev->sdw);
352 hdev->sdw = NULL;
353
354 return 0;
355}
356
357bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
358{
359 struct sof_intel_hda_dev *hdev;
360 bool ret = false;
361 u32 irq_status;
362
363 hdev = sdev->pdata->hw_pdata;
364
365 if (!hdev->sdw)
366 return ret;
367
368 /* store status */
369 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2);
370
371 /* invalid message ? */
372 if (irq_status == 0xffffffff)
373 goto out;
374
375 /* SDW message ? */
376 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW)
377 ret = true;
378
379out:
380 return ret;
381}
382
383static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
384{
385 u32 interface_mask = hda_get_interface_mask(sdev);
386 const struct sof_intel_dsp_desc *chip;
387
388 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
389 return false;
390
391 chip = get_chip_info(sdev->pdata);
392 if (chip && chip->check_sdw_irq)
393 return chip->check_sdw_irq(sdev);
394
395 return false;
396}
397
398static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
399{
400 return sdw_intel_thread(irq, context);
401}
402
403bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev)
404{
405 struct sof_intel_hda_dev *hdev;
406
407 hdev = sdev->pdata->hw_pdata;
408 if (hdev->sdw &&
409 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
410 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS))
411 return true;
412
413 return false;
414}
415
416static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
417{
418 u32 interface_mask = hda_get_interface_mask(sdev);
419 const struct sof_intel_dsp_desc *chip;
420
421 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
422 return false;
423
424 chip = get_chip_info(sdev->pdata);
425 if (chip && chip->check_sdw_wakeen_irq)
426 return chip->check_sdw_wakeen_irq(sdev);
427
428 return false;
429}
430
431void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
432{
433 u32 interface_mask = hda_get_interface_mask(sdev);
434 struct sof_intel_hda_dev *hdev;
435
436 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
437 return;
438
439 hdev = sdev->pdata->hw_pdata;
440 if (!hdev->sdw)
441 return;
442
443 sdw_intel_process_wakeen_event(hdev->sdw);
444}
445
446#else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */
447static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
448{
449 return 0;
450}
451
452static inline int hda_sdw_probe(struct snd_sof_dev *sdev)
453{
454 return 0;
455}
456
457static inline int hda_sdw_exit(struct snd_sof_dev *sdev)
458{
459 return 0;
460}
461
462static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
463{
464 return false;
465}
466
467static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
468{
469 return IRQ_HANDLED;
470}
471
472static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
473{
474 return false;
475}
476
477#endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */
478
479/*
480 * Debug
481 */
482
483struct hda_dsp_msg_code {
484 u32 code;
485 const char *text;
486};
487
488#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
489static bool hda_use_msi = true;
490module_param_named(use_msi, hda_use_msi, bool, 0444);
491MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode");
492#else
493#define hda_use_msi (1)
494#endif
495
496int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS;
497module_param_named(position_quirk, sof_hda_position_quirk, int, 0444);
498MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk");
499
500static char *hda_model;
501module_param(hda_model, charp, 0444);
502MODULE_PARM_DESC(hda_model, "Use the given HDA board model.");
503
504static int dmic_num_override = -1;
505module_param_named(dmic_num, dmic_num_override, int, 0444);
506MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number");
507
508static int mclk_id_override = -1;
509module_param_named(mclk_id, mclk_id_override, int, 0444);
510MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id");
511
512static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = {
513 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
514 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
515 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
516 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
517 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
518 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
519 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
520 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
521 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
522 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
523 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
524 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
525 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
526 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
527 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
528 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
529};
530
531#define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state}
532static const struct hda_dsp_msg_code fsr_rom_state_names[] = {
533 FSR_ROM_STATE_ENTRY(INIT),
534 FSR_ROM_STATE_ENTRY(INIT_DONE),
535 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED),
536 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED),
537 FSR_ROM_STATE_ENTRY(FW_FW_LOADED),
538 FSR_ROM_STATE_ENTRY(FW_ENTERED),
539 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK),
540 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET),
541 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT),
542 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE),
543 /* CSE states */
544 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST),
545 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED),
546 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST),
547 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED),
548 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT),
549 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1),
550 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY),
551 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL),
552 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN),
553};
554
555#define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state}
556static const struct hda_dsp_msg_code fsr_bringup_state_names[] = {
557 FSR_BRINGUP_STATE_ENTRY(INIT),
558 FSR_BRINGUP_STATE_ENTRY(INIT_DONE),
559 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD),
560 FSR_BRINGUP_STATE_ENTRY(UNPACK_START),
561 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE),
562 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED),
563};
564
565#define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state}
566static const struct hda_dsp_msg_code fsr_wait_state_names[] = {
567 FSR_WAIT_STATE_ENTRY(IPC_BUSY),
568 FSR_WAIT_STATE_ENTRY(IPC_DONE),
569 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION),
570 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF),
571 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL),
572 FSR_WAIT_STATE_ENTRY(CSE_CSR),
573};
574
575#define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod
576static const char * const fsr_module_names[] = {
577 FSR_MODULE_NAME_ENTRY(ROM),
578 FSR_MODULE_NAME_ENTRY(ROM_BYP),
579 FSR_MODULE_NAME_ENTRY(BASE_FW),
580 FSR_MODULE_NAME_ENTRY(LP_BOOT),
581 FSR_MODULE_NAME_ENTRY(BRNGUP),
582 FSR_MODULE_NAME_ENTRY(ROM_EXT),
583};
584
585static const char *
586hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code,
587 size_t array_size)
588{
589 int i;
590
591 for (i = 0; i < array_size; i++) {
592 if (code == msg_code[i].code)
593 return msg_code[i].text;
594 }
595
596 return NULL;
597}
598
599static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level)
600{
601 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
602 const char *state_text, *error_text, *module_text;
603 u32 fsr, state, wait_state, module, error_code;
604
605 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg);
606 state = FSR_TO_STATE_CODE(fsr);
607 wait_state = FSR_TO_WAIT_STATE_CODE(fsr);
608 module = FSR_TO_MODULE_CODE(fsr);
609
610 if (module > FSR_MOD_ROM_EXT)
611 module_text = "unknown";
612 else
613 module_text = fsr_module_names[module];
614
615 if (module == FSR_MOD_BRNGUP)
616 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names,
617 ARRAY_SIZE(fsr_bringup_state_names));
618 else
619 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names,
620 ARRAY_SIZE(fsr_rom_state_names));
621
622 /* not for us, must be generic sof message */
623 if (!state_text) {
624 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr);
625 return;
626 }
627
628 if (wait_state) {
629 const char *wait_state_text;
630
631 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names,
632 ARRAY_SIZE(fsr_wait_state_names));
633 if (!wait_state_text)
634 wait_state_text = "unknown";
635
636 dev_printk(level, sdev->dev,
637 "%#010x: module: %s, state: %s, waiting for: %s, %s\n",
638 fsr, module_text, state_text, wait_state_text,
639 fsr & FSR_HALTED ? "not running" : "running");
640 } else {
641 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n",
642 fsr, module_text, state_text,
643 fsr & FSR_HALTED ? "not running" : "running");
644 }
645
646 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4);
647 if (!error_code)
648 return;
649
650 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts,
651 ARRAY_SIZE(hda_dsp_rom_fw_error_texts));
652 if (!error_text)
653 error_text = "unknown";
654
655 if (state == FSR_STATE_FW_ENTERED)
656 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code,
657 error_text);
658 else
659 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code,
660 error_text);
661}
662
663static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
664 struct sof_ipc_dsp_oops_xtensa *xoops,
665 struct sof_ipc_panic_info *panic_info,
666 u32 *stack, size_t stack_words)
667{
668 u32 offset = sdev->dsp_oops_offset;
669
670 /* first read registers */
671 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
672
673 /* note: variable AR register array is not read */
674
675 /* then get panic info */
676 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
677 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
678 xoops->arch_hdr.totalsize);
679 return;
680 }
681 offset += xoops->arch_hdr.totalsize;
682 sof_block_read(sdev, sdev->mmio_bar, offset,
683 panic_info, sizeof(*panic_info));
684
685 /* then get the stack */
686 offset += sizeof(*panic_info);
687 sof_block_read(sdev, sdev->mmio_bar, offset, stack,
688 stack_words * sizeof(u32));
689}
690
691/* dump the first 8 dwords representing the extended ROM status */
692static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level,
693 u32 flags)
694{
695 const struct sof_intel_dsp_desc *chip;
696 char msg[128];
697 int len = 0;
698 u32 value;
699 int i;
700
701 chip = get_chip_info(sdev->pdata);
702 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) {
703 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4);
704 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value);
705 }
706
707 dev_printk(level, sdev->dev, "extended rom status: %s", msg);
708
709}
710
711void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
712{
713 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
714 struct sof_ipc_dsp_oops_xtensa xoops;
715 struct sof_ipc_panic_info panic_info;
716 u32 stack[HDA_DSP_STACK_DUMP_SIZE];
717
718 /* print ROM/FW status */
719 hda_dsp_get_state(sdev, level);
720
721 /* The firmware register dump only available with IPC3 */
722 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC_TYPE_3) {
723 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS);
724 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
725
726 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
727 HDA_DSP_STACK_DUMP_SIZE);
728 sof_print_oops_and_stack(sdev, level, status, panic, &xoops,
729 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE);
730 } else {
731 hda_dsp_dump_ext_rom_status(sdev, level, flags);
732 }
733}
734
735void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
736{
737 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
738
739 /* print ROM/FW status */
740 hda_dsp_get_state(sdev, level);
741
742 if (flags & SOF_DBG_DUMP_REGS)
743 sof_ipc4_intel_dump_telemetry_state(sdev, flags);
744 else
745 hda_dsp_dump_ext_rom_status(sdev, level, flags);
746}
747
748static bool hda_check_ipc_irq(struct snd_sof_dev *sdev)
749{
750 const struct sof_intel_dsp_desc *chip;
751
752 chip = get_chip_info(sdev->pdata);
753 if (chip && chip->check_ipc_irq)
754 return chip->check_ipc_irq(sdev);
755
756 return false;
757}
758
759void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
760{
761 u32 adspis;
762 u32 intsts;
763 u32 intctl;
764 u32 ppsts;
765 u8 rirbsts;
766
767 /* read key IRQ stats and config registers */
768 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
769 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
770 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
771 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
772 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS);
773
774 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
775 intsts, intctl, rirbsts);
776 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis);
777}
778
779void hda_ipc_dump(struct snd_sof_dev *sdev)
780{
781 u32 hipcie;
782 u32 hipct;
783 u32 hipcctl;
784
785 hda_ipc_irq_dump(sdev);
786
787 /* read IPC status */
788 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
789 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
790 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
791
792 /* dump the IPC regs */
793 /* TODO: parse the raw msg */
794 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
795 hipcie, hipct, hipcctl);
796}
797
798void hda_ipc4_dump(struct snd_sof_dev *sdev)
799{
800 u32 hipci, hipcie, hipct, hipcte, hipcctl;
801
802 hda_ipc_irq_dump(sdev);
803
804 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
805 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
806 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
807 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
808 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
809
810 /* dump the IPC regs */
811 /* TODO: parse the raw msg */
812 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n",
813 hipci, hipcie, hipct, hipcte, hipcctl);
814}
815
816bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev)
817{
818 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
819 const struct sof_intel_dsp_desc *chip = hda->desc;
820 u32 val;
821
822 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req);
823
824 return !!(val & chip->ipc_req_mask);
825}
826
827static int hda_init(struct snd_sof_dev *sdev)
828{
829 struct hda_bus *hbus;
830 struct hdac_bus *bus;
831 struct pci_dev *pci = to_pci_dev(sdev->dev);
832 int ret;
833
834 hbus = sof_to_hbus(sdev);
835 bus = sof_to_bus(sdev);
836
837 /* HDA bus init */
838 sof_hda_bus_init(sdev, &pci->dev);
839
840 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS)
841 bus->use_posbuf = 0;
842 else
843 bus->use_posbuf = 1;
844 bus->bdl_pos_adj = 0;
845 bus->sync_write = 1;
846
847 mutex_init(&hbus->prepare_mutex);
848 hbus->pci = pci;
849 hbus->mixer_assigned = -1;
850 hbus->modelname = hda_model;
851
852 /* initialise hdac bus */
853 bus->addr = pci_resource_start(pci, 0);
854 bus->remap_addr = pci_ioremap_bar(pci, 0);
855 if (!bus->remap_addr) {
856 dev_err(bus->dev, "error: ioremap error\n");
857 return -ENXIO;
858 }
859
860 /* HDA base */
861 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
862
863 /* init i915 and HDMI codecs */
864 ret = hda_codec_i915_init(sdev);
865 if (ret < 0 && ret != -ENODEV) {
866 dev_err_probe(sdev->dev, ret, "init of i915 and HDMI codec failed\n");
867 goto out;
868 }
869
870 /* get controller capabilities */
871 ret = hda_dsp_ctrl_get_caps(sdev);
872 if (ret < 0) {
873 dev_err(sdev->dev, "error: get caps error\n");
874 hda_codec_i915_exit(sdev);
875 }
876
877out:
878 if (ret < 0)
879 iounmap(sof_to_bus(sdev)->remap_addr);
880
881 return ret;
882}
883
884static int check_dmic_num(struct snd_sof_dev *sdev)
885{
886 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
887 struct nhlt_acpi_table *nhlt;
888 int dmic_num = 0;
889
890 nhlt = hdev->nhlt;
891 if (nhlt)
892 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt);
893
894 /* allow for module parameter override */
895 if (dmic_num_override != -1) {
896 dev_dbg(sdev->dev,
897 "overriding DMICs detected in NHLT tables %d by kernel param %d\n",
898 dmic_num, dmic_num_override);
899 dmic_num = dmic_num_override;
900 }
901
902 if (dmic_num < 0 || dmic_num > 4) {
903 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num);
904 dmic_num = 0;
905 }
906
907 return dmic_num;
908}
909
910static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev)
911{
912 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
913 struct nhlt_acpi_table *nhlt;
914 int ssp_mask = 0;
915
916 nhlt = hdev->nhlt;
917 if (!nhlt)
918 return ssp_mask;
919
920 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) {
921 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S);
922 if (ssp_mask)
923 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask);
924 }
925
926 return ssp_mask;
927}
928
929static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num)
930{
931 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
932 struct nhlt_acpi_table *nhlt;
933
934 nhlt = hdev->nhlt;
935 if (!nhlt)
936 return 0;
937
938 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num);
939}
940
941#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
942
943static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
944 const char *sof_tplg_filename,
945 const char *idisp_str,
946 const char *dmic_str)
947{
948 const char *tplg_filename = NULL;
949 char *filename, *tmp;
950 const char *split_ext;
951
952 filename = kstrdup(sof_tplg_filename, GFP_KERNEL);
953 if (!filename)
954 return NULL;
955
956 /* this assumes a .tplg extension */
957 tmp = filename;
958 split_ext = strsep(&tmp, ".");
959 if (split_ext)
960 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
961 "%s%s%s.tplg",
962 split_ext, idisp_str, dmic_str);
963 kfree(filename);
964
965 return tplg_filename;
966}
967
968static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev,
969 const char **tplg_filename,
970 const char *idisp_str,
971 int *dmic_found,
972 bool tplg_fixup)
973{
974 const char *dmic_str;
975 int dmic_num;
976
977 /* first check for DMICs (using NHLT or module parameter) */
978 dmic_num = check_dmic_num(sdev);
979
980 switch (dmic_num) {
981 case 1:
982 dmic_str = "-1ch";
983 break;
984 case 2:
985 dmic_str = "-2ch";
986 break;
987 case 3:
988 dmic_str = "-3ch";
989 break;
990 case 4:
991 dmic_str = "-4ch";
992 break;
993 default:
994 dmic_num = 0;
995 dmic_str = "";
996 break;
997 }
998
999 if (tplg_fixup) {
1000 const char *default_tplg_filename = *tplg_filename;
1001 const char *fixed_tplg_filename;
1002
1003 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename,
1004 idisp_str, dmic_str);
1005 if (!fixed_tplg_filename)
1006 return -ENOMEM;
1007 *tplg_filename = fixed_tplg_filename;
1008 }
1009
1010 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num);
1011 *dmic_found = dmic_num;
1012
1013 return 0;
1014}
1015#endif
1016
1017static int hda_init_caps(struct snd_sof_dev *sdev)
1018{
1019 u32 interface_mask = hda_get_interface_mask(sdev);
1020 struct hdac_bus *bus = sof_to_bus(sdev);
1021 struct snd_sof_pdata *pdata = sdev->pdata;
1022 struct sof_intel_hda_dev *hdev = pdata->hw_pdata;
1023 u32 link_mask;
1024 int ret = 0;
1025
1026 /* check if dsp is there */
1027 if (bus->ppcap)
1028 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
1029
1030 /* Init HDA controller after i915 init */
1031 ret = hda_dsp_ctrl_init_chip(sdev);
1032 if (ret < 0) {
1033 dev_err(bus->dev, "error: init chip failed with ret: %d\n",
1034 ret);
1035 return ret;
1036 }
1037
1038 hda_bus_ml_init(bus);
1039
1040 /* Skip SoundWire if it is not supported */
1041 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
1042 goto skip_soundwire;
1043
1044 /* scan SoundWire capabilities exposed by DSDT */
1045 ret = hda_sdw_acpi_scan(sdev);
1046 if (ret < 0) {
1047 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n");
1048 goto skip_soundwire;
1049 }
1050
1051 link_mask = hdev->info.link_mask;
1052 if (!link_mask) {
1053 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n");
1054 goto skip_soundwire;
1055 }
1056
1057 /*
1058 * probe/allocate SoundWire resources.
1059 * The hardware configuration takes place in hda_sdw_startup
1060 * after power rails are enabled.
1061 * It's entirely possible to have a mix of I2S/DMIC/SoundWire
1062 * devices, so we allocate the resources in all cases.
1063 */
1064 ret = hda_sdw_probe(sdev);
1065 if (ret < 0) {
1066 dev_err(sdev->dev, "error: SoundWire probe error\n");
1067 return ret;
1068 }
1069
1070skip_soundwire:
1071
1072 /* create codec instances */
1073 hda_codec_probe_bus(sdev);
1074
1075 if (!HDA_IDISP_CODEC(bus->codec_mask))
1076 hda_codec_i915_display_power(sdev, false);
1077
1078 hda_bus_ml_put_all(bus);
1079
1080 return 0;
1081}
1082
1083static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context)
1084{
1085 struct snd_sof_dev *sdev = context;
1086
1087 /*
1088 * Get global interrupt status. It includes all hardware interrupt
1089 * sources in the Intel HD Audio controller.
1090 */
1091 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) &
1092 SOF_HDA_INTSTS_GIS) {
1093
1094 /* disable GIE interrupt */
1095 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
1096 SOF_HDA_INTCTL,
1097 SOF_HDA_INT_GLOBAL_EN,
1098 0);
1099
1100 return IRQ_WAKE_THREAD;
1101 }
1102
1103 return IRQ_NONE;
1104}
1105
1106static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context)
1107{
1108 struct snd_sof_dev *sdev = context;
1109 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
1110
1111 /* deal with streams and controller first */
1112 if (hda_dsp_check_stream_irq(sdev)) {
1113 trace_sof_intel_hda_irq(sdev, "stream");
1114 hda_dsp_stream_threaded_handler(irq, sdev);
1115 }
1116
1117 if (hda_check_ipc_irq(sdev)) {
1118 trace_sof_intel_hda_irq(sdev, "ipc");
1119 sof_ops(sdev)->irq_thread(irq, sdev);
1120 }
1121
1122 if (hda_dsp_check_sdw_irq(sdev)) {
1123 trace_sof_intel_hda_irq(sdev, "sdw");
1124 hda_dsp_sdw_thread(irq, hdev->sdw);
1125 }
1126
1127 if (hda_sdw_check_wakeen_irq(sdev)) {
1128 trace_sof_intel_hda_irq(sdev, "wakeen");
1129 hda_sdw_process_wakeen(sdev);
1130 }
1131
1132 hda_codec_check_for_state_change(sdev);
1133
1134 /* enable GIE interrupt */
1135 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
1136 SOF_HDA_INTCTL,
1137 SOF_HDA_INT_GLOBAL_EN,
1138 SOF_HDA_INT_GLOBAL_EN);
1139
1140 return IRQ_HANDLED;
1141}
1142
1143int hda_dsp_probe_early(struct snd_sof_dev *sdev)
1144{
1145 struct pci_dev *pci = to_pci_dev(sdev->dev);
1146 struct sof_intel_hda_dev *hdev;
1147 const struct sof_intel_dsp_desc *chip;
1148 int ret = 0;
1149
1150 if (!sdev->dspless_mode_selected) {
1151 /*
1152 * detect DSP by checking class/subclass/prog-id information
1153 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
1154 * class=04 subclass 01 prog-if 00: DSP is present
1155 * (and may be required e.g. for DMIC or SSP support)
1156 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
1157 */
1158 if (pci->class == 0x040300) {
1159 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n");
1160 return -ENODEV;
1161 } else if (pci->class != 0x040100 && pci->class != 0x040380) {
1162 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n",
1163 pci->class);
1164 return -ENODEV;
1165 }
1166 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n",
1167 pci->class);
1168 }
1169
1170 chip = get_chip_info(sdev->pdata);
1171 if (!chip) {
1172 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
1173 pci->device);
1174 ret = -EIO;
1175 goto err;
1176 }
1177
1178 sdev->num_cores = chip->cores_num;
1179
1180 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
1181 if (!hdev)
1182 return -ENOMEM;
1183 sdev->pdata->hw_pdata = hdev;
1184 hdev->desc = chip;
1185 ret = hda_init(sdev);
1186
1187err:
1188 return ret;
1189}
1190
1191int hda_dsp_probe(struct snd_sof_dev *sdev)
1192{
1193 struct pci_dev *pci = to_pci_dev(sdev->dev);
1194 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
1195 int ret = 0;
1196
1197 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
1198 PLATFORM_DEVID_NONE,
1199 NULL, 0);
1200 if (IS_ERR(hdev->dmic_dev)) {
1201 dev_err(sdev->dev, "error: failed to create DMIC device\n");
1202 return PTR_ERR(hdev->dmic_dev);
1203 }
1204
1205 /*
1206 * use position update IPC if either it is forced
1207 * or we don't have other choice
1208 */
1209#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
1210 hdev->no_ipc_position = 0;
1211#else
1212 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
1213#endif
1214
1215 if (sdev->dspless_mode_selected)
1216 hdev->no_ipc_position = 1;
1217
1218 if (sdev->dspless_mode_selected)
1219 goto skip_dsp_setup;
1220
1221 /* DSP base */
1222 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
1223 if (!sdev->bar[HDA_DSP_BAR]) {
1224 dev_err(sdev->dev, "error: ioremap error\n");
1225 ret = -ENXIO;
1226 goto hdac_bus_unmap;
1227 }
1228
1229 sdev->mmio_bar = HDA_DSP_BAR;
1230 sdev->mailbox_bar = HDA_DSP_BAR;
1231skip_dsp_setup:
1232
1233 /* allow 64bit DMA address if supported by H/W */
1234 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) {
1235 dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
1236 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1237 }
1238 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1239
1240 /* init streams */
1241 ret = hda_dsp_stream_init(sdev);
1242 if (ret < 0) {
1243 dev_err(sdev->dev, "error: failed to init streams\n");
1244 /*
1245 * not all errors are due to memory issues, but trying
1246 * to free everything does not harm
1247 */
1248 goto free_streams;
1249 }
1250
1251 /*
1252 * register our IRQ
1253 * let's try to enable msi firstly
1254 * if it fails, use legacy interrupt mode
1255 * TODO: support msi multiple vectors
1256 */
1257 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) {
1258 dev_info(sdev->dev, "use msi interrupt mode\n");
1259 sdev->ipc_irq = pci_irq_vector(pci, 0);
1260 /* initialised to "false" by kzalloc() */
1261 sdev->msi_enabled = true;
1262 }
1263
1264 if (!sdev->msi_enabled) {
1265 dev_info(sdev->dev, "use legacy interrupt mode\n");
1266 /*
1267 * in IO-APIC mode, hda->irq and ipc_irq are using the same
1268 * irq number of pci->irq
1269 */
1270 sdev->ipc_irq = pci->irq;
1271 }
1272
1273 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
1274 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler,
1275 hda_dsp_interrupt_thread,
1276 IRQF_SHARED, "AudioDSP", sdev);
1277 if (ret < 0) {
1278 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
1279 sdev->ipc_irq);
1280 goto free_irq_vector;
1281 }
1282
1283 pci_set_master(pci);
1284 synchronize_irq(pci->irq);
1285
1286 /*
1287 * clear TCSEL to clear playback on some HD Audio
1288 * codecs. PCI TCSEL is defined in the Intel manuals.
1289 */
1290 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
1291
1292 /* init HDA capabilities */
1293 ret = hda_init_caps(sdev);
1294 if (ret < 0)
1295 goto free_ipc_irq;
1296
1297 if (!sdev->dspless_mode_selected) {
1298 /* enable ppcap interrupt */
1299 hda_dsp_ctrl_ppcap_enable(sdev, true);
1300 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
1301
1302 /* set default mailbox offset for FW ready message */
1303 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
1304
1305 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work);
1306 }
1307
1308 init_waitqueue_head(&hdev->waitq);
1309
1310 hdev->nhlt = intel_nhlt_init(sdev->dev);
1311
1312 return 0;
1313
1314free_ipc_irq:
1315 free_irq(sdev->ipc_irq, sdev);
1316free_irq_vector:
1317 if (sdev->msi_enabled)
1318 pci_free_irq_vectors(pci);
1319free_streams:
1320 hda_dsp_stream_free(sdev);
1321/* dsp_unmap: not currently used */
1322 if (!sdev->dspless_mode_selected)
1323 iounmap(sdev->bar[HDA_DSP_BAR]);
1324hdac_bus_unmap:
1325 platform_device_unregister(hdev->dmic_dev);
1326
1327 return ret;
1328}
1329
1330void hda_dsp_remove(struct snd_sof_dev *sdev)
1331{
1332 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
1333 const struct sof_intel_dsp_desc *chip = hda->desc;
1334 struct pci_dev *pci = to_pci_dev(sdev->dev);
1335 struct nhlt_acpi_table *nhlt = hda->nhlt;
1336
1337 if (nhlt)
1338 intel_nhlt_free(nhlt);
1339
1340 if (!sdev->dspless_mode_selected)
1341 /* cancel any attempt for DSP D0I3 */
1342 cancel_delayed_work_sync(&hda->d0i3_work);
1343
1344 hda_codec_device_remove(sdev);
1345
1346 hda_sdw_exit(sdev);
1347
1348 if (!IS_ERR_OR_NULL(hda->dmic_dev))
1349 platform_device_unregister(hda->dmic_dev);
1350
1351 if (!sdev->dspless_mode_selected) {
1352 /* disable DSP IRQ */
1353 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
1354 }
1355
1356 /* disable CIE and GIE interrupts */
1357 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
1358 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);
1359
1360 if (sdev->dspless_mode_selected)
1361 goto skip_disable_dsp;
1362
1363 /* no need to check for error as the DSP will be disabled anyway */
1364 if (chip && chip->power_down_dsp)
1365 chip->power_down_dsp(sdev);
1366
1367 /* disable DSP */
1368 hda_dsp_ctrl_ppcap_enable(sdev, false);
1369
1370skip_disable_dsp:
1371 free_irq(sdev->ipc_irq, sdev);
1372 if (sdev->msi_enabled)
1373 pci_free_irq_vectors(pci);
1374
1375 hda_dsp_stream_free(sdev);
1376
1377 hda_bus_ml_free(sof_to_bus(sdev));
1378
1379 if (!sdev->dspless_mode_selected)
1380 iounmap(sdev->bar[HDA_DSP_BAR]);
1381}
1382
1383void hda_dsp_remove_late(struct snd_sof_dev *sdev)
1384{
1385 iounmap(sof_to_bus(sdev)->remap_addr);
1386 sof_hda_bus_exit(sdev);
1387 hda_codec_i915_exit(sdev);
1388}
1389
1390int hda_power_down_dsp(struct snd_sof_dev *sdev)
1391{
1392 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
1393 const struct sof_intel_dsp_desc *chip = hda->desc;
1394
1395 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
1396}
1397
1398#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
1399static void hda_generic_machine_select(struct snd_sof_dev *sdev,
1400 struct snd_soc_acpi_mach **mach)
1401{
1402 struct hdac_bus *bus = sof_to_bus(sdev);
1403 struct snd_soc_acpi_mach_params *mach_params;
1404 struct snd_soc_acpi_mach *hda_mach;
1405 struct snd_sof_pdata *pdata = sdev->pdata;
1406 const char *tplg_filename;
1407 const char *idisp_str;
1408 int dmic_num = 0;
1409 int codec_num = 0;
1410 int ret;
1411 int i;
1412
1413 /* codec detection */
1414 if (!bus->codec_mask) {
1415 dev_info(bus->dev, "no hda codecs found!\n");
1416 } else {
1417 dev_info(bus->dev, "hda codecs found, mask %lx\n",
1418 bus->codec_mask);
1419
1420 for (i = 0; i < HDA_MAX_CODECS; i++) {
1421 if (bus->codec_mask & (1 << i))
1422 codec_num++;
1423 }
1424
1425 /*
1426 * If no machine driver is found, then:
1427 *
1428 * generic hda machine driver can handle:
1429 * - one HDMI codec, and/or
1430 * - one external HDAudio codec
1431 */
1432 if (!*mach && codec_num <= 2) {
1433 bool tplg_fixup;
1434
1435 hda_mach = snd_soc_acpi_intel_hda_machines;
1436
1437 dev_info(bus->dev, "using HDA machine driver %s now\n",
1438 hda_mach->drv_name);
1439
1440 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask))
1441 idisp_str = "-idisp";
1442 else
1443 idisp_str = "";
1444
1445 /* topology: use the info from hda_machines */
1446 if (pdata->tplg_filename) {
1447 tplg_fixup = false;
1448 tplg_filename = pdata->tplg_filename;
1449 } else {
1450 tplg_fixup = true;
1451 tplg_filename = hda_mach->sof_tplg_filename;
1452 }
1453 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num,
1454 tplg_fixup);
1455 if (ret < 0)
1456 return;
1457
1458 hda_mach->mach_params.dmic_num = dmic_num;
1459 pdata->tplg_filename = tplg_filename;
1460
1461 if (codec_num == 2 ||
1462 (codec_num == 1 && !HDA_IDISP_CODEC(bus->codec_mask))) {
1463 /*
1464 * Prevent SoundWire links from starting when an external
1465 * HDaudio codec is used
1466 */
1467 hda_mach->mach_params.link_mask = 0;
1468 } else {
1469 /*
1470 * Allow SoundWire links to start when no external HDaudio codec
1471 * was detected. This will not create a SoundWire card but
1472 * will help detect if any SoundWire codec reports as ATTACHED.
1473 */
1474 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
1475
1476 hda_mach->mach_params.link_mask = hdev->info.link_mask;
1477 }
1478
1479 *mach = hda_mach;
1480 }
1481 }
1482
1483 /* used by hda machine driver to create dai links */
1484 if (*mach) {
1485 mach_params = &(*mach)->mach_params;
1486 mach_params->codec_mask = bus->codec_mask;
1487 mach_params->common_hdmi_codec_drv = true;
1488 }
1489}
1490#else
1491static void hda_generic_machine_select(struct snd_sof_dev *sdev,
1492 struct snd_soc_acpi_mach **mach)
1493{
1494}
1495#endif
1496
1497#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
1498
1499static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev)
1500{
1501 struct snd_sof_pdata *pdata = sdev->pdata;
1502 const struct snd_soc_acpi_link_adr *link;
1503 struct snd_soc_acpi_mach *mach;
1504 struct sof_intel_hda_dev *hdev;
1505 u32 link_mask;
1506 int i;
1507
1508 hdev = pdata->hw_pdata;
1509 link_mask = hdev->info.link_mask;
1510
1511 /*
1512 * Select SoundWire machine driver if needed using the
1513 * alternate tables. This case deals with SoundWire-only
1514 * machines, for mixed cases with I2C/I2S the detection relies
1515 * on the HID list.
1516 */
1517 if (link_mask) {
1518 for (mach = pdata->desc->alt_machines;
1519 mach && mach->link_mask; mach++) {
1520 /*
1521 * On some platforms such as Up Extreme all links
1522 * are enabled but only one link can be used by
1523 * external codec. Instead of exact match of two masks,
1524 * first check whether link_mask of mach is subset of
1525 * link_mask supported by hw and then go on searching
1526 * link_adr
1527 */
1528 if (~link_mask & mach->link_mask)
1529 continue;
1530
1531 /* No need to match adr if there is no links defined */
1532 if (!mach->links)
1533 break;
1534
1535 link = mach->links;
1536 for (i = 0; i < hdev->info.count && link->num_adr;
1537 i++, link++) {
1538 /*
1539 * Try next machine if any expected Slaves
1540 * are not found on this link.
1541 */
1542 if (!snd_soc_acpi_sdw_link_slaves_found(sdev->dev, link,
1543 hdev->sdw->ids,
1544 hdev->sdw->num_slaves))
1545 break;
1546 }
1547 /* Found if all Slaves are checked */
1548 if (i == hdev->info.count || !link->num_adr)
1549 break;
1550 }
1551 if (mach && mach->link_mask) {
1552 int dmic_num = 0;
1553 bool tplg_fixup;
1554 const char *tplg_filename;
1555
1556 mach->mach_params.links = mach->links;
1557 mach->mach_params.link_mask = mach->link_mask;
1558 mach->mach_params.platform = dev_name(sdev->dev);
1559
1560 if (pdata->tplg_filename) {
1561 tplg_fixup = false;
1562 } else {
1563 tplg_fixup = true;
1564 tplg_filename = mach->sof_tplg_filename;
1565 }
1566
1567 /*
1568 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire
1569 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics
1570 * if all conditions are true:
1571 * a) 2 or fewer links are used by SoundWire
1572 * b) the NHLT table reports the presence of microphones
1573 */
1574 if (hweight_long(mach->link_mask) <= 2) {
1575 int ret;
1576
1577 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "",
1578 &dmic_num, tplg_fixup);
1579 if (ret < 0)
1580 return NULL;
1581 }
1582 if (tplg_fixup)
1583 pdata->tplg_filename = tplg_filename;
1584 mach->mach_params.dmic_num = dmic_num;
1585
1586 dev_dbg(sdev->dev,
1587 "SoundWire machine driver %s topology %s\n",
1588 mach->drv_name,
1589 pdata->tplg_filename);
1590
1591 return mach;
1592 }
1593
1594 dev_info(sdev->dev, "No SoundWire machine driver found\n");
1595 }
1596
1597 return NULL;
1598}
1599#else
1600static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev)
1601{
1602 return NULL;
1603}
1604#endif
1605
1606void hda_set_mach_params(struct snd_soc_acpi_mach *mach,
1607 struct snd_sof_dev *sdev)
1608{
1609 struct snd_sof_pdata *pdata = sdev->pdata;
1610 const struct sof_dev_desc *desc = pdata->desc;
1611 struct snd_soc_acpi_mach_params *mach_params;
1612
1613 mach_params = &mach->mach_params;
1614 mach_params->platform = dev_name(sdev->dev);
1615 if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
1616 sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
1617 mach_params->num_dai_drivers = SOF_SKL_NUM_DAIS_NOCODEC;
1618 else
1619 mach_params->num_dai_drivers = desc->ops->num_drv;
1620 mach_params->dai_drivers = desc->ops->drv;
1621}
1622
1623struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev)
1624{
1625 u32 interface_mask = hda_get_interface_mask(sdev);
1626 struct snd_sof_pdata *sof_pdata = sdev->pdata;
1627 const struct sof_dev_desc *desc = sof_pdata->desc;
1628 struct snd_soc_acpi_mach *mach = NULL;
1629 const char *tplg_filename;
1630
1631 /* Try I2S or DMIC if it is supported */
1632 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC)))
1633 mach = snd_soc_acpi_find_machine(desc->machines);
1634
1635 if (mach) {
1636 bool add_extension = false;
1637 bool tplg_fixup = false;
1638
1639 /*
1640 * If tplg file name is overridden, use it instead of
1641 * the one set in mach table
1642 */
1643 if (!sof_pdata->tplg_filename) {
1644 sof_pdata->tplg_filename = mach->sof_tplg_filename;
1645 tplg_fixup = true;
1646 }
1647
1648 /* report to machine driver if any DMICs are found */
1649 mach->mach_params.dmic_num = check_dmic_num(sdev);
1650
1651 if (tplg_fixup &&
1652 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER &&
1653 mach->mach_params.dmic_num) {
1654 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
1655 "%s%s%d%s",
1656 sof_pdata->tplg_filename,
1657 "-dmic",
1658 mach->mach_params.dmic_num,
1659 "ch");
1660 if (!tplg_filename)
1661 return NULL;
1662
1663 sof_pdata->tplg_filename = tplg_filename;
1664 add_extension = true;
1665 }
1666
1667 if (mach->link_mask) {
1668 mach->mach_params.links = mach->links;
1669 mach->mach_params.link_mask = mach->link_mask;
1670 }
1671
1672 /* report SSP link mask to machine driver */
1673 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev);
1674
1675 if (tplg_fixup &&
1676 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER &&
1677 mach->mach_params.i2s_link_mask) {
1678 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
1679 int ssp_num;
1680 int mclk_mask;
1681
1682 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 &&
1683 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB))
1684 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n");
1685
1686 /* fls returns 1-based results, SSPs indices are 0-based */
1687 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1;
1688
1689 if (ssp_num >= chip->ssp_count) {
1690 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n",
1691 ssp_num, chip->ssp_count);
1692 return NULL;
1693 }
1694
1695 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
1696 "%s%s%d",
1697 sof_pdata->tplg_filename,
1698 "-ssp",
1699 ssp_num);
1700 if (!tplg_filename)
1701 return NULL;
1702
1703 sof_pdata->tplg_filename = tplg_filename;
1704 add_extension = true;
1705
1706 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num);
1707
1708 if (mclk_mask < 0) {
1709 dev_err(sdev->dev, "Invalid MCLK configuration\n");
1710 return NULL;
1711 }
1712
1713 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask);
1714
1715 if (mclk_mask) {
1716 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask);
1717 sdev->mclk_id_override = true;
1718 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1;
1719 }
1720 }
1721
1722 if (tplg_fixup && add_extension) {
1723 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
1724 "%s%s",
1725 sof_pdata->tplg_filename,
1726 ".tplg");
1727 if (!tplg_filename)
1728 return NULL;
1729
1730 sof_pdata->tplg_filename = tplg_filename;
1731 }
1732
1733 /* check if mclk_id should be modified from topology defaults */
1734 if (mclk_id_override >= 0) {
1735 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override);
1736 sdev->mclk_id_override = true;
1737 sdev->mclk_id_quirk = mclk_id_override;
1738 }
1739 }
1740
1741 /* If I2S fails, try SoundWire if it is supported */
1742 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH)))
1743 mach = hda_sdw_machine_select(sdev);
1744
1745 /*
1746 * Choose HDA generic machine driver if mach is NULL.
1747 * Otherwise, set certain mach params.
1748 */
1749 hda_generic_machine_select(sdev, &mach);
1750 if (!mach)
1751 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
1752
1753 return mach;
1754}
1755
1756int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1757{
1758 int ret;
1759
1760 ret = snd_intel_dsp_driver_probe(pci);
1761 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
1762 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n");
1763 return -ENODEV;
1764 }
1765
1766 return sof_pci_probe(pci, pci_id);
1767}
1768EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON);
1769
1770int hda_register_clients(struct snd_sof_dev *sdev)
1771{
1772 return hda_probes_register(sdev);
1773}
1774
1775void hda_unregister_clients(struct snd_sof_dev *sdev)
1776{
1777 hda_probes_unregister(sdev);
1778}
1779
1780MODULE_LICENSE("Dual BSD/GPL");
1781MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
1782MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC);
1783MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915);
1784MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
1785MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI);
1786MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT);
1787MODULE_IMPORT_NS(SOUNDWIRE_INTEL);
1788MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK);