1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver core for Samsung SoC onboard UARTs.
   4 *
   5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6 *	http://armlinux.simtec.co.uk/
   7 */
   8
   9/* Note on 2410 error handling
  10 *
  11 * The s3c2410 manual has a love/hate affair with the contents of the
  12 * UERSTAT register in the UART blocks, and keeps marking some of the
  13 * error bits as reserved. Having checked with the s3c2410x01,
  14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15 * feature from the latter versions of the manual.
  16 *
  17 * If it becomes aparrent that latter versions of the 2410 remove these
  18 * bits, then action will have to be taken to differentiate the versions
  19 * and change the policy on BREAK
  20 *
  21 * BJD, 04-Nov-2004
  22 */
  23
  24#include <linux/dmaengine.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/slab.h>
  27#include <linux/math.h>
  28#include <linux/module.h>
  29#include <linux/ioport.h>
  30#include <linux/io.h>
  31#include <linux/platform_device.h>
  32#include <linux/init.h>
  33#include <linux/sysrq.h>
  34#include <linux/console.h>
  35#include <linux/tty.h>
  36#include <linux/tty_flip.h>
  37#include <linux/serial_core.h>
  38#include <linux/serial.h>
  39#include <linux/serial_s3c.h>
  40#include <linux/delay.h>
  41#include <linux/clk.h>
  42#include <linux/cpufreq.h>
  43#include <linux/of.h>
  44#include <asm/irq.h>
  45
  46/* UART name and device definitions */
  47
  48#define S3C24XX_SERIAL_NAME	"ttySAC"
  49#define S3C24XX_SERIAL_MAJOR	204
  50#define S3C24XX_SERIAL_MINOR	64
  51
  52#ifdef CONFIG_ARM64
  53#define UART_NR			12
  54#else
  55#define UART_NR			CONFIG_SERIAL_SAMSUNG_UARTS
  56#endif
  57
  58#define S3C24XX_TX_PIO			1
  59#define S3C24XX_TX_DMA			2
  60#define S3C24XX_RX_PIO			1
  61#define S3C24XX_RX_DMA			2
  62
  63/* flag to ignore all characters coming in */
  64#define RXSTAT_DUMMY_READ (0x10000000)
  65
  66enum s3c24xx_port_type {
  67	TYPE_S3C6400,
  68	TYPE_APPLE_S5L,
  69};
  70
  71struct s3c24xx_uart_info {
  72	const char		*name;
  73	enum s3c24xx_port_type	type;
  74	unsigned int		port_type;
  75	unsigned int		fifosize;
  76	unsigned long		rx_fifomask;
  77	unsigned long		rx_fifoshift;
  78	unsigned long		rx_fifofull;
  79	unsigned long		tx_fifomask;
  80	unsigned long		tx_fifoshift;
  81	unsigned long		tx_fifofull;
  82	unsigned int		def_clk_sel;
  83	unsigned long		num_clks;
  84	unsigned long		clksel_mask;
  85	unsigned long		clksel_shift;
  86	unsigned long		ucon_mask;
  87
  88	/* uart port features */
  89
  90	unsigned int		has_divslot:1;
  91};
  92
  93struct s3c24xx_serial_drv_data {
  94	const struct s3c24xx_uart_info	info;
  95	const struct s3c2410_uartcfg	def_cfg;
  96	const unsigned int		fifosize[UART_NR];
  97};
  98
  99struct s3c24xx_uart_dma {
 100	unsigned int			rx_chan_id;
 101	unsigned int			tx_chan_id;
 102
 103	struct dma_slave_config		rx_conf;
 104	struct dma_slave_config		tx_conf;
 105
 106	struct dma_chan			*rx_chan;
 107	struct dma_chan			*tx_chan;
 108
 109	dma_addr_t			rx_addr;
 110	dma_addr_t			tx_addr;
 111
 112	dma_cookie_t			rx_cookie;
 113	dma_cookie_t			tx_cookie;
 114
 115	char				*rx_buf;
 116
 117	dma_addr_t			tx_transfer_addr;
 118
 119	size_t				rx_size;
 120	size_t				tx_size;
 121
 122	struct dma_async_tx_descriptor	*tx_desc;
 123	struct dma_async_tx_descriptor	*rx_desc;
 124
 125	int				tx_bytes_requested;
 126	int				rx_bytes_requested;
 127};
 128
 129struct s3c24xx_uart_port {
 130	unsigned char			rx_enabled;
 131	unsigned char			tx_enabled;
 132	unsigned int			pm_level;
 133	unsigned long			baudclk_rate;
 134	unsigned int			min_dma_size;
 135
 136	unsigned int			rx_irq;
 137	unsigned int			tx_irq;
 138
 139	unsigned int			tx_in_progress;
 140	unsigned int			tx_mode;
 141	unsigned int			rx_mode;
 142
 143	const struct s3c24xx_uart_info	*info;
 144	struct clk			*clk;
 145	struct clk			*baudclk;
 146	struct uart_port		port;
 147	const struct s3c24xx_serial_drv_data	*drv_data;
 148
 149	/* reference to platform data */
 150	const struct s3c2410_uartcfg	*cfg;
 151
 152	struct s3c24xx_uart_dma		*dma;
 153};
 154
 155static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
 156
 157/* conversion functions */
 158
 159#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 160
 161/* register access controls */
 162
 163#define portaddr(port, reg) ((port)->membase + (reg))
 164#define portaddrl(port, reg) \
 165	((unsigned long *)(unsigned long)((port)->membase + (reg)))
 166
 167static u32 rd_reg(const struct uart_port *port, u32 reg)
 168{
 169	switch (port->iotype) {
 170	case UPIO_MEM:
 171		return readb_relaxed(portaddr(port, reg));
 172	case UPIO_MEM32:
 173		return readl_relaxed(portaddr(port, reg));
 174	default:
 175		return 0;
 176	}
 177	return 0;
 178}
 179
 180#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 181
 182static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
 183{
 184	switch (port->iotype) {
 185	case UPIO_MEM:
 186		writeb_relaxed(val, portaddr(port, reg));
 187		break;
 188	case UPIO_MEM32:
 189		writel_relaxed(val, portaddr(port, reg));
 190		break;
 191	}
 192}
 193
 194#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 195
 196/* Byte-order aware bit setting/clearing functions. */
 197
 198static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
 199				   unsigned int reg)
 200{
 201	unsigned long flags;
 202	u32 val;
 203
 204	local_irq_save(flags);
 205	val = rd_regl(port, reg);
 206	val |= (1 << idx);
 207	wr_regl(port, reg, val);
 208	local_irq_restore(flags);
 209}
 210
 211static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
 212				     unsigned int reg)
 213{
 214	unsigned long flags;
 215	u32 val;
 216
 217	local_irq_save(flags);
 218	val = rd_regl(port, reg);
 219	val &= ~(1 << idx);
 220	wr_regl(port, reg, val);
 221	local_irq_restore(flags);
 222}
 223
 224static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 225{
 226	return container_of(port, struct s3c24xx_uart_port, port);
 227}
 228
 229/* translate a port to the device name */
 230
 231static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
 232{
 233	return to_platform_device(port->dev)->name;
 234}
 235
 236static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
 237{
 238	return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 239}
 240
 241static void s3c24xx_serial_rx_enable(struct uart_port *port)
 242{
 243	struct s3c24xx_uart_port *ourport = to_ourport(port);
 244	unsigned long flags;
 245	unsigned int ucon, ufcon;
 246	int count = 10000;
 247
 248	uart_port_lock_irqsave(port, &flags);
 249
 250	while (--count && !s3c24xx_serial_txempty_nofifo(port))
 251		udelay(100);
 252
 253	ufcon = rd_regl(port, S3C2410_UFCON);
 254	ufcon |= S3C2410_UFCON_RESETRX;
 255	wr_regl(port, S3C2410_UFCON, ufcon);
 256
 257	ucon = rd_regl(port, S3C2410_UCON);
 258	ucon |= S3C2410_UCON_RXIRQMODE;
 259	wr_regl(port, S3C2410_UCON, ucon);
 260
 261	ourport->rx_enabled = 1;
 262	uart_port_unlock_irqrestore(port, flags);
 263}
 264
 265static void s3c24xx_serial_rx_disable(struct uart_port *port)
 266{
 267	struct s3c24xx_uart_port *ourport = to_ourport(port);
 268	unsigned long flags;
 269	unsigned int ucon;
 270
 271	uart_port_lock_irqsave(port, &flags);
 272
 273	ucon = rd_regl(port, S3C2410_UCON);
 274	ucon &= ~S3C2410_UCON_RXIRQMODE;
 275	wr_regl(port, S3C2410_UCON, ucon);
 276
 277	ourport->rx_enabled = 0;
 278	uart_port_unlock_irqrestore(port, flags);
 279}
 280
 281static void s3c24xx_serial_stop_tx(struct uart_port *port)
 282{
 283	struct s3c24xx_uart_port *ourport = to_ourport(port);
 284	struct s3c24xx_uart_dma *dma = ourport->dma;
 285	struct dma_tx_state state;
 286	int count;
 287
 288	if (!ourport->tx_enabled)
 289		return;
 290
 291	switch (ourport->info->type) {
 292	case TYPE_S3C6400:
 293		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 294		break;
 295	case TYPE_APPLE_S5L:
 296		s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
 297		break;
 298	default:
 299		disable_irq_nosync(ourport->tx_irq);
 300		break;
 301	}
 302
 303	if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 304		dmaengine_pause(dma->tx_chan);
 305		dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 306		dmaengine_terminate_all(dma->tx_chan);
 307		dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 308					dma->tx_transfer_addr, dma->tx_size,
 309					DMA_TO_DEVICE);
 310		async_tx_ack(dma->tx_desc);
 311		count = dma->tx_bytes_requested - state.residue;
 312		uart_xmit_advance(port, count);
 313	}
 314
 315	ourport->tx_enabled = 0;
 316	ourport->tx_in_progress = 0;
 317
 318	if (port->flags & UPF_CONS_FLOW)
 319		s3c24xx_serial_rx_enable(port);
 320
 321	ourport->tx_mode = 0;
 322}
 323
 324static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 325
 326static void s3c24xx_serial_tx_dma_complete(void *args)
 327{
 328	struct s3c24xx_uart_port *ourport = args;
 329	struct uart_port *port = &ourport->port;
 330	struct circ_buf *xmit = &port->state->xmit;
 331	struct s3c24xx_uart_dma *dma = ourport->dma;
 332	struct dma_tx_state state;
 333	unsigned long flags;
 334	int count;
 335
 336	dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 337	count = dma->tx_bytes_requested - state.residue;
 338	async_tx_ack(dma->tx_desc);
 339
 340	dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 341				dma->tx_transfer_addr, dma->tx_size,
 342				DMA_TO_DEVICE);
 343
 344	uart_port_lock_irqsave(port, &flags);
 345
 346	uart_xmit_advance(port, count);
 347	ourport->tx_in_progress = 0;
 348
 349	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 350		uart_write_wakeup(port);
 351
 352	s3c24xx_serial_start_next_tx(ourport);
 353	uart_port_unlock_irqrestore(port, flags);
 354}
 355
 356static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 357{
 358	const struct uart_port *port = &ourport->port;
 359	u32 ucon;
 360
 361	/* Mask Tx interrupt */
 362	switch (ourport->info->type) {
 363	case TYPE_S3C6400:
 364		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 365		break;
 366	case TYPE_APPLE_S5L:
 367		WARN_ON(1); // No DMA
 368		break;
 369	default:
 370		disable_irq_nosync(ourport->tx_irq);
 371		break;
 372	}
 373
 374	/* Enable tx dma mode */
 375	ucon = rd_regl(port, S3C2410_UCON);
 376	ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 377	ucon |= S3C64XX_UCON_TXBURST_1;
 378	ucon |= S3C64XX_UCON_TXMODE_DMA;
 379	wr_regl(port,  S3C2410_UCON, ucon);
 380
 381	ourport->tx_mode = S3C24XX_TX_DMA;
 382}
 383
 384static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 385{
 386	const struct uart_port *port = &ourport->port;
 387	u32 ucon, ufcon;
 388
 389	/* Set ufcon txtrig */
 390	ourport->tx_in_progress = S3C24XX_TX_PIO;
 391	ufcon = rd_regl(port, S3C2410_UFCON);
 392	wr_regl(port,  S3C2410_UFCON, ufcon);
 393
 394	/* Enable tx pio mode */
 395	ucon = rd_regl(port, S3C2410_UCON);
 396	ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 397	ucon |= S3C64XX_UCON_TXMODE_CPU;
 398	wr_regl(port,  S3C2410_UCON, ucon);
 399
 400	/* Unmask Tx interrupt */
 401	switch (ourport->info->type) {
 402	case TYPE_S3C6400:
 403		s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 404				  S3C64XX_UINTM);
 405		break;
 406	case TYPE_APPLE_S5L:
 407		ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
 408		wr_regl(port, S3C2410_UCON, ucon);
 409		break;
 410	default:
 411		enable_irq(ourport->tx_irq);
 412		break;
 413	}
 414
 415	ourport->tx_mode = S3C24XX_TX_PIO;
 416
 417	/*
 418	 * The Apple version only has edge triggered TX IRQs, so we need
 419	 * to kick off the process by sending some characters here.
 420	 */
 421	if (ourport->info->type == TYPE_APPLE_S5L)
 422		s3c24xx_serial_tx_chars(ourport);
 423}
 424
 425static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 426{
 427	if (ourport->tx_mode != S3C24XX_TX_PIO)
 428		enable_tx_pio(ourport);
 429}
 430
 431static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 432				      unsigned int count)
 433{
 434	struct uart_port *port = &ourport->port;
 435	struct circ_buf *xmit = &port->state->xmit;
 436	struct s3c24xx_uart_dma *dma = ourport->dma;
 437
 438	if (ourport->tx_mode != S3C24XX_TX_DMA)
 439		enable_tx_dma(ourport);
 440
 441	dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 442	dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 443
 444	dma_sync_single_for_device(dma->tx_chan->device->dev,
 445				   dma->tx_transfer_addr, dma->tx_size,
 446				   DMA_TO_DEVICE);
 447
 448	dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 449				dma->tx_transfer_addr, dma->tx_size,
 450				DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 451	if (!dma->tx_desc) {
 452		dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 453		return -EIO;
 454	}
 455
 456	dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 457	dma->tx_desc->callback_param = ourport;
 458	dma->tx_bytes_requested = dma->tx_size;
 459
 460	ourport->tx_in_progress = S3C24XX_TX_DMA;
 461	dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 462	dma_async_issue_pending(dma->tx_chan);
 463	return 0;
 464}
 465
 466static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 467{
 468	struct uart_port *port = &ourport->port;
 469	struct circ_buf *xmit = &port->state->xmit;
 470	unsigned long count;
 471
 472	/* Get data size up to the end of buffer */
 473	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 474
 475	if (!count) {
 476		s3c24xx_serial_stop_tx(port);
 477		return;
 478	}
 479
 480	if (!ourport->dma || !ourport->dma->tx_chan ||
 481	    count < ourport->min_dma_size ||
 482	    xmit->tail & (dma_get_cache_alignment() - 1))
 483		s3c24xx_serial_start_tx_pio(ourport);
 484	else
 485		s3c24xx_serial_start_tx_dma(ourport, count);
 486}
 487
 488static void s3c24xx_serial_start_tx(struct uart_port *port)
 489{
 490	struct s3c24xx_uart_port *ourport = to_ourport(port);
 491	struct circ_buf *xmit = &port->state->xmit;
 492
 493	if (!ourport->tx_enabled) {
 494		if (port->flags & UPF_CONS_FLOW)
 495			s3c24xx_serial_rx_disable(port);
 496
 497		ourport->tx_enabled = 1;
 498		if (!ourport->dma || !ourport->dma->tx_chan)
 499			s3c24xx_serial_start_tx_pio(ourport);
 500	}
 501
 502	if (ourport->dma && ourport->dma->tx_chan) {
 503		if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 504			s3c24xx_serial_start_next_tx(ourport);
 505	}
 506}
 507
 508static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 509		struct tty_port *tty, int count)
 510{
 511	struct s3c24xx_uart_dma *dma = ourport->dma;
 512	int copied;
 513
 514	if (!count)
 515		return;
 516
 517	dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
 518				dma->rx_size, DMA_FROM_DEVICE);
 519
 520	ourport->port.icount.rx += count;
 521	if (!tty) {
 522		dev_err(ourport->port.dev, "No tty port\n");
 523		return;
 524	}
 525	copied = tty_insert_flip_string(tty,
 526			((unsigned char *)(ourport->dma->rx_buf)), count);
 527	if (copied != count) {
 528		WARN_ON(1);
 529		dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 530	}
 531}
 532
 533static void s3c24xx_serial_stop_rx(struct uart_port *port)
 534{
 535	struct s3c24xx_uart_port *ourport = to_ourport(port);
 536	struct s3c24xx_uart_dma *dma = ourport->dma;
 537	struct tty_port *t = &port->state->port;
 538	struct dma_tx_state state;
 539	enum dma_status dma_status;
 540	unsigned int received;
 541
 542	if (ourport->rx_enabled) {
 543		dev_dbg(port->dev, "stopping rx\n");
 544		switch (ourport->info->type) {
 545		case TYPE_S3C6400:
 546			s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 547					S3C64XX_UINTM);
 548			break;
 549		case TYPE_APPLE_S5L:
 550			s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
 551			s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
 552			break;
 553		default:
 554			disable_irq_nosync(ourport->rx_irq);
 555			break;
 556		}
 557		ourport->rx_enabled = 0;
 558	}
 559	if (dma && dma->rx_chan) {
 560		dmaengine_pause(dma->tx_chan);
 561		dma_status = dmaengine_tx_status(dma->rx_chan,
 562				dma->rx_cookie, &state);
 563		if (dma_status == DMA_IN_PROGRESS ||
 564			dma_status == DMA_PAUSED) {
 565			received = dma->rx_bytes_requested - state.residue;
 566			dmaengine_terminate_all(dma->rx_chan);
 567			s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 568		}
 569	}
 570}
 571
 572static inline const struct s3c24xx_uart_info
 573	*s3c24xx_port_to_info(struct uart_port *port)
 574{
 575	return to_ourport(port)->info;
 576}
 577
 578static inline const struct s3c2410_uartcfg
 579	*s3c24xx_port_to_cfg(const struct uart_port *port)
 580{
 581	const struct s3c24xx_uart_port *ourport;
 582
 583	if (port->dev == NULL)
 584		return NULL;
 585
 586	ourport = container_of(port, struct s3c24xx_uart_port, port);
 587	return ourport->cfg;
 588}
 589
 590static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
 591				     unsigned long ufstat)
 592{
 593	const struct s3c24xx_uart_info *info = ourport->info;
 594
 595	if (ufstat & info->rx_fifofull)
 596		return ourport->port.fifosize;
 597
 598	return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 599}
 600
 601static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 602static void s3c24xx_serial_rx_dma_complete(void *args)
 603{
 604	struct s3c24xx_uart_port *ourport = args;
 605	struct uart_port *port = &ourport->port;
 606
 607	struct s3c24xx_uart_dma *dma = ourport->dma;
 608	struct tty_port *t = &port->state->port;
 609	struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 610
 611	struct dma_tx_state state;
 612	unsigned long flags;
 613	int received;
 614
 615	dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 616	received  = dma->rx_bytes_requested - state.residue;
 617	async_tx_ack(dma->rx_desc);
 618
 619	uart_port_lock_irqsave(port, &flags);
 620
 621	if (received)
 622		s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 623
 624	if (tty) {
 625		tty_flip_buffer_push(t);
 626		tty_kref_put(tty);
 627	}
 628
 629	s3c64xx_start_rx_dma(ourport);
 630
 631	uart_port_unlock_irqrestore(port, flags);
 632}
 633
 634static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 635{
 636	struct s3c24xx_uart_dma *dma = ourport->dma;
 637
 638	dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
 639				   dma->rx_size, DMA_FROM_DEVICE);
 640
 641	dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 642				dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 643				DMA_PREP_INTERRUPT);
 644	if (!dma->rx_desc) {
 645		dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 646		return;
 647	}
 648
 649	dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 650	dma->rx_desc->callback_param = ourport;
 651	dma->rx_bytes_requested = dma->rx_size;
 652
 653	dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 654	dma_async_issue_pending(dma->rx_chan);
 655}
 656
 657/* ? - where has parity gone?? */
 658#define S3C2410_UERSTAT_PARITY (0x1000)
 659
 660static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 661{
 662	struct uart_port *port = &ourport->port;
 663	unsigned int ucon;
 664
 665	/* set Rx mode to DMA mode */
 666	ucon = rd_regl(port, S3C2410_UCON);
 667	ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 668			S3C64XX_UCON_TIMEOUT_MASK |
 669			S3C64XX_UCON_EMPTYINT_EN |
 670			S3C64XX_UCON_DMASUS_EN |
 671			S3C64XX_UCON_TIMEOUT_EN |
 672			S3C64XX_UCON_RXMODE_MASK);
 673	ucon |= S3C64XX_UCON_RXBURST_1 |
 674			0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 675			S3C64XX_UCON_EMPTYINT_EN |
 676			S3C64XX_UCON_TIMEOUT_EN |
 677			S3C64XX_UCON_RXMODE_DMA;
 678	wr_regl(port, S3C2410_UCON, ucon);
 679
 680	ourport->rx_mode = S3C24XX_RX_DMA;
 681}
 682
 683static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 684{
 685	struct uart_port *port = &ourport->port;
 686	unsigned int ucon;
 687
 688	/* set Rx mode to DMA mode */
 689	ucon = rd_regl(port, S3C2410_UCON);
 690	ucon &= ~S3C64XX_UCON_RXMODE_MASK;
 691	ucon |= S3C64XX_UCON_RXMODE_CPU;
 692
 693	/* Apple types use these bits for IRQ masks */
 694	if (ourport->info->type != TYPE_APPLE_S5L) {
 695		ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 696				S3C64XX_UCON_EMPTYINT_EN |
 697				S3C64XX_UCON_DMASUS_EN |
 698				S3C64XX_UCON_TIMEOUT_EN);
 699		ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 700				S3C64XX_UCON_TIMEOUT_EN;
 701	}
 702	wr_regl(port, S3C2410_UCON, ucon);
 703
 704	ourport->rx_mode = S3C24XX_RX_PIO;
 705}
 706
 707static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 708
 709static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 710{
 711	unsigned int utrstat, received;
 712	struct s3c24xx_uart_port *ourport = dev_id;
 713	struct uart_port *port = &ourport->port;
 714	struct s3c24xx_uart_dma *dma = ourport->dma;
 715	struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 716	struct tty_port *t = &port->state->port;
 717	struct dma_tx_state state;
 718
 719	utrstat = rd_regl(port, S3C2410_UTRSTAT);
 720	rd_regl(port, S3C2410_UFSTAT);
 721
 722	uart_port_lock(port);
 723
 724	if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 725		s3c64xx_start_rx_dma(ourport);
 726		if (ourport->rx_mode == S3C24XX_RX_PIO)
 727			enable_rx_dma(ourport);
 728		goto finish;
 729	}
 730
 731	if (ourport->rx_mode == S3C24XX_RX_DMA) {
 732		dmaengine_pause(dma->rx_chan);
 733		dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 734		dmaengine_terminate_all(dma->rx_chan);
 735		received = dma->rx_bytes_requested - state.residue;
 736		s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 737
 738		enable_rx_pio(ourport);
 739	}
 740
 741	s3c24xx_serial_rx_drain_fifo(ourport);
 742
 743	if (tty) {
 744		tty_flip_buffer_push(t);
 745		tty_kref_put(tty);
 746	}
 747
 748	wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 749
 750finish:
 751	uart_port_unlock(port);
 752
 753	return IRQ_HANDLED;
 754}
 755
 756static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 757{
 758	struct uart_port *port = &ourport->port;
 759	unsigned int ufcon, ufstat, uerstat;
 760	unsigned int fifocnt = 0;
 761	int max_count = port->fifosize;
 762	u8 ch, flag;
 763
 764	while (max_count-- > 0) {
 765		/*
 766		 * Receive all characters known to be in FIFO
 767		 * before reading FIFO level again
 768		 */
 769		if (fifocnt == 0) {
 770			ufstat = rd_regl(port, S3C2410_UFSTAT);
 771			fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 772			if (fifocnt == 0)
 773				break;
 774		}
 775		fifocnt--;
 776
 777		uerstat = rd_regl(port, S3C2410_UERSTAT);
 778		ch = rd_reg(port, S3C2410_URXH);
 779
 780		if (port->flags & UPF_CONS_FLOW) {
 781			int txe = s3c24xx_serial_txempty_nofifo(port);
 782
 783			if (ourport->rx_enabled) {
 784				if (!txe) {
 785					ourport->rx_enabled = 0;
 786					continue;
 787				}
 788			} else {
 789				if (txe) {
 790					ufcon = rd_regl(port, S3C2410_UFCON);
 791					ufcon |= S3C2410_UFCON_RESETRX;
 792					wr_regl(port, S3C2410_UFCON, ufcon);
 793					ourport->rx_enabled = 1;
 794					return;
 795				}
 796				continue;
 797			}
 798		}
 799
 800		/* insert the character into the buffer */
 801
 802		flag = TTY_NORMAL;
 803		port->icount.rx++;
 804
 805		if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 806			dev_dbg(port->dev,
 807				"rxerr: port ch=0x%02x, rxs=0x%08x\n",
 808				ch, uerstat);
 809
 810			/* check for break */
 811			if (uerstat & S3C2410_UERSTAT_BREAK) {
 812				dev_dbg(port->dev, "break!\n");
 813				port->icount.brk++;
 814				if (uart_handle_break(port))
 815					continue; /* Ignore character */
 816			}
 817
 818			if (uerstat & S3C2410_UERSTAT_FRAME)
 819				port->icount.frame++;
 820			if (uerstat & S3C2410_UERSTAT_OVERRUN)
 821				port->icount.overrun++;
 822
 823			uerstat &= port->read_status_mask;
 824
 825			if (uerstat & S3C2410_UERSTAT_BREAK)
 826				flag = TTY_BREAK;
 827			else if (uerstat & S3C2410_UERSTAT_PARITY)
 828				flag = TTY_PARITY;
 829			else if (uerstat & (S3C2410_UERSTAT_FRAME |
 830					    S3C2410_UERSTAT_OVERRUN))
 831				flag = TTY_FRAME;
 832		}
 833
 834		if (uart_handle_sysrq_char(port, ch))
 835			continue; /* Ignore character */
 836
 837		uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 838				 ch, flag);
 839	}
 840
 841	tty_flip_buffer_push(&port->state->port);
 842}
 843
 844static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 845{
 846	struct s3c24xx_uart_port *ourport = dev_id;
 847	struct uart_port *port = &ourport->port;
 848
 849	uart_port_lock(port);
 850	s3c24xx_serial_rx_drain_fifo(ourport);
 851	uart_port_unlock(port);
 852
 853	return IRQ_HANDLED;
 854}
 855
 856static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
 857{
 858	struct s3c24xx_uart_port *ourport = dev_id;
 859
 860	if (ourport->dma && ourport->dma->rx_chan)
 861		return s3c24xx_serial_rx_chars_dma(dev_id);
 862	return s3c24xx_serial_rx_chars_pio(dev_id);
 863}
 864
 865static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
 866{
 867	struct uart_port *port = &ourport->port;
 868	struct circ_buf *xmit = &port->state->xmit;
 869	int count, dma_count = 0;
 870
 871	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 872
 873	if (ourport->dma && ourport->dma->tx_chan &&
 874	    count >= ourport->min_dma_size) {
 875		int align = dma_get_cache_alignment() -
 876			(xmit->tail & (dma_get_cache_alignment() - 1));
 877		if (count - align >= ourport->min_dma_size) {
 878			dma_count = count - align;
 879			count = align;
 880		}
 881	}
 882
 883	if (port->x_char) {
 884		wr_reg(port, S3C2410_UTXH, port->x_char);
 885		port->icount.tx++;
 886		port->x_char = 0;
 887		return;
 888	}
 889
 890	/* if there isn't anything more to transmit, or the uart is now
 891	 * stopped, disable the uart and exit
 892	 */
 893
 894	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 895		s3c24xx_serial_stop_tx(port);
 896		return;
 897	}
 898
 899	/* try and drain the buffer... */
 900
 901	if (count > port->fifosize) {
 902		count = port->fifosize;
 903		dma_count = 0;
 904	}
 905
 906	while (!uart_circ_empty(xmit) && count > 0) {
 907		if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 908			break;
 909
 910		wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 911		uart_xmit_advance(port, 1);
 912		count--;
 913	}
 914
 915	if (!count && dma_count) {
 916		s3c24xx_serial_start_tx_dma(ourport, dma_count);
 917		return;
 918	}
 919
 920	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 921		uart_write_wakeup(port);
 922
 923	if (uart_circ_empty(xmit))
 924		s3c24xx_serial_stop_tx(port);
 925}
 926
 927static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
 928{
 929	struct s3c24xx_uart_port *ourport = id;
 930	struct uart_port *port = &ourport->port;
 931
 932	uart_port_lock(port);
 933
 934	s3c24xx_serial_tx_chars(ourport);
 935
 936	uart_port_unlock(port);
 937	return IRQ_HANDLED;
 938}
 939
 940/* interrupt handler for s3c64xx and later SoC's.*/
 941static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 942{
 943	const struct s3c24xx_uart_port *ourport = id;
 944	const struct uart_port *port = &ourport->port;
 945	unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 946	irqreturn_t ret = IRQ_HANDLED;
 947
 948	if (pend & S3C64XX_UINTM_RXD_MSK) {
 949		ret = s3c24xx_serial_rx_irq(irq, id);
 950		wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 951	}
 952	if (pend & S3C64XX_UINTM_TXD_MSK) {
 953		ret = s3c24xx_serial_tx_irq(irq, id);
 954		wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 955	}
 956	return ret;
 957}
 958
 959/* interrupt handler for Apple SoC's.*/
 960static irqreturn_t apple_serial_handle_irq(int irq, void *id)
 961{
 962	const struct s3c24xx_uart_port *ourport = id;
 963	const struct uart_port *port = &ourport->port;
 964	unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
 965	irqreturn_t ret = IRQ_NONE;
 966
 967	if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
 968		wr_regl(port, S3C2410_UTRSTAT,
 969			APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
 970		ret = s3c24xx_serial_rx_irq(irq, id);
 971	}
 972	if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
 973		wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
 974		ret = s3c24xx_serial_tx_irq(irq, id);
 975	}
 976
 977	return ret;
 978}
 979
 980static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 981{
 982	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 983	unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 984	unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 985
 986	if (ufcon & S3C2410_UFCON_FIFOMODE) {
 987		if ((ufstat & info->tx_fifomask) != 0 ||
 988		    (ufstat & info->tx_fifofull))
 989			return 0;
 990
 991		return 1;
 992	}
 993
 994	return s3c24xx_serial_txempty_nofifo(port);
 995}
 996
 997/* no modem control lines */
 998static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 999{
1000	unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1001
1002	if (umstat & S3C2410_UMSTAT_CTS)
1003		return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1004	else
1005		return TIOCM_CAR | TIOCM_DSR;
1006}
1007
1008static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1009{
1010	unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1011	unsigned int ucon = rd_regl(port, S3C2410_UCON);
1012
1013	if (mctrl & TIOCM_RTS)
1014		umcon |= S3C2410_UMCOM_RTS_LOW;
1015	else
1016		umcon &= ~S3C2410_UMCOM_RTS_LOW;
1017
1018	wr_regl(port, S3C2410_UMCON, umcon);
1019
1020	if (mctrl & TIOCM_LOOP)
1021		ucon |= S3C2410_UCON_LOOPBACK;
1022	else
1023		ucon &= ~S3C2410_UCON_LOOPBACK;
1024
1025	wr_regl(port, S3C2410_UCON, ucon);
1026}
1027
1028static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1029{
1030	unsigned long flags;
1031	unsigned int ucon;
1032
1033	uart_port_lock_irqsave(port, &flags);
1034
1035	ucon = rd_regl(port, S3C2410_UCON);
1036
1037	if (break_state)
1038		ucon |= S3C2410_UCON_SBREAK;
1039	else
1040		ucon &= ~S3C2410_UCON_SBREAK;
1041
1042	wr_regl(port, S3C2410_UCON, ucon);
1043
1044	uart_port_unlock_irqrestore(port, flags);
1045}
1046
1047static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1048{
1049	struct s3c24xx_uart_dma	*dma = p->dma;
1050	struct dma_slave_caps dma_caps;
1051	const char *reason = NULL;
1052	int ret;
1053
1054	/* Default slave configuration parameters */
1055	dma->rx_conf.direction		= DMA_DEV_TO_MEM;
1056	dma->rx_conf.src_addr_width	= DMA_SLAVE_BUSWIDTH_1_BYTE;
1057	dma->rx_conf.src_addr		= p->port.mapbase + S3C2410_URXH;
1058	dma->rx_conf.src_maxburst	= 1;
1059
1060	dma->tx_conf.direction		= DMA_MEM_TO_DEV;
1061	dma->tx_conf.dst_addr_width	= DMA_SLAVE_BUSWIDTH_1_BYTE;
1062	dma->tx_conf.dst_addr		= p->port.mapbase + S3C2410_UTXH;
1063	dma->tx_conf.dst_maxburst	= 1;
1064
1065	dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1066
1067	if (IS_ERR(dma->rx_chan)) {
1068		reason = "DMA RX channel request failed";
1069		ret = PTR_ERR(dma->rx_chan);
1070		goto err_warn;
1071	}
1072
1073	ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1074	if (ret < 0 ||
1075	    dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1076		reason = "insufficient DMA RX engine capabilities";
1077		ret = -EOPNOTSUPP;
1078		goto err_release_rx;
1079	}
1080
1081	dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1082
1083	dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1084	if (IS_ERR(dma->tx_chan)) {
1085		reason = "DMA TX channel request failed";
1086		ret = PTR_ERR(dma->tx_chan);
1087		goto err_release_rx;
1088	}
1089
1090	ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1091	if (ret < 0 ||
1092	    dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1093		reason = "insufficient DMA TX engine capabilities";
1094		ret = -EOPNOTSUPP;
1095		goto err_release_tx;
1096	}
1097
1098	dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1099
1100	/* RX buffer */
1101	dma->rx_size = PAGE_SIZE;
1102
1103	dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1104	if (!dma->rx_buf) {
1105		ret = -ENOMEM;
1106		goto err_release_tx;
1107	}
1108
1109	dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1110				      dma->rx_size, DMA_FROM_DEVICE);
1111	if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1112		reason = "DMA mapping error for RX buffer";
1113		ret = -EIO;
1114		goto err_free_rx;
1115	}
1116
1117	/* TX buffer */
1118	dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1119				      p->port.state->xmit.buf, UART_XMIT_SIZE,
1120				      DMA_TO_DEVICE);
1121	if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1122		reason = "DMA mapping error for TX buffer";
1123		ret = -EIO;
1124		goto err_unmap_rx;
1125	}
1126
1127	return 0;
1128
1129err_unmap_rx:
1130	dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1131			 dma->rx_size, DMA_FROM_DEVICE);
1132err_free_rx:
1133	kfree(dma->rx_buf);
1134err_release_tx:
1135	dma_release_channel(dma->tx_chan);
1136err_release_rx:
1137	dma_release_channel(dma->rx_chan);
1138err_warn:
1139	if (reason)
1140		dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1141	return ret;
1142}
1143
1144static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1145{
1146	struct s3c24xx_uart_dma	*dma = p->dma;
1147
1148	if (dma->rx_chan) {
1149		dmaengine_terminate_all(dma->rx_chan);
1150		dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1151				 dma->rx_size, DMA_FROM_DEVICE);
1152		kfree(dma->rx_buf);
1153		dma_release_channel(dma->rx_chan);
1154		dma->rx_chan = NULL;
1155	}
1156
1157	if (dma->tx_chan) {
1158		dmaengine_terminate_all(dma->tx_chan);
1159		dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1160				 UART_XMIT_SIZE, DMA_TO_DEVICE);
1161		dma_release_channel(dma->tx_chan);
1162		dma->tx_chan = NULL;
1163	}
1164}
1165
1166static void s3c64xx_serial_shutdown(struct uart_port *port)
1167{
1168	struct s3c24xx_uart_port *ourport = to_ourport(port);
1169
1170	ourport->tx_enabled = 0;
1171	ourport->tx_mode = 0;
1172	ourport->rx_enabled = 0;
1173
1174	free_irq(port->irq, ourport);
1175
1176	wr_regl(port, S3C64XX_UINTP, 0xf);
1177	wr_regl(port, S3C64XX_UINTM, 0xf);
1178
1179	if (ourport->dma)
1180		s3c24xx_serial_release_dma(ourport);
1181
1182	ourport->tx_in_progress = 0;
1183}
1184
1185static void apple_s5l_serial_shutdown(struct uart_port *port)
1186{
1187	struct s3c24xx_uart_port *ourport = to_ourport(port);
1188
1189	unsigned int ucon;
1190
1191	ucon = rd_regl(port, S3C2410_UCON);
1192	ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1193		  APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1194		  APPLE_S5L_UCON_RXTO_ENA_MSK);
1195	wr_regl(port, S3C2410_UCON, ucon);
1196
1197	wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1198
1199	free_irq(port->irq, ourport);
1200
1201	ourport->tx_enabled = 0;
1202	ourport->tx_mode = 0;
1203	ourport->rx_enabled = 0;
1204
1205	if (ourport->dma)
1206		s3c24xx_serial_release_dma(ourport);
1207
1208	ourport->tx_in_progress = 0;
1209}
1210
1211static int s3c64xx_serial_startup(struct uart_port *port)
1212{
1213	struct s3c24xx_uart_port *ourport = to_ourport(port);
1214	unsigned long flags;
1215	unsigned int ufcon;
1216	int ret;
1217
1218	wr_regl(port, S3C64XX_UINTM, 0xf);
1219	if (ourport->dma) {
1220		ret = s3c24xx_serial_request_dma(ourport);
1221		if (ret < 0) {
1222			devm_kfree(port->dev, ourport->dma);
1223			ourport->dma = NULL;
1224		}
1225	}
1226
1227	ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1228			  s3c24xx_serial_portname(port), ourport);
1229	if (ret) {
1230		dev_err(port->dev, "cannot get irq %d\n", port->irq);
1231		return ret;
1232	}
1233
1234	/* For compatibility with s3c24xx Soc's */
1235	ourport->rx_enabled = 1;
1236	ourport->tx_enabled = 0;
1237
1238	uart_port_lock_irqsave(port, &flags);
1239
1240	ufcon = rd_regl(port, S3C2410_UFCON);
1241	ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1242	if (!uart_console(port))
1243		ufcon |= S3C2410_UFCON_RESETTX;
1244	wr_regl(port, S3C2410_UFCON, ufcon);
1245
1246	enable_rx_pio(ourport);
1247
1248	uart_port_unlock_irqrestore(port, flags);
1249
1250	/* Enable Rx Interrupt */
1251	s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1252
1253	return ret;
1254}
1255
1256static int apple_s5l_serial_startup(struct uart_port *port)
1257{
1258	struct s3c24xx_uart_port *ourport = to_ourport(port);
1259	unsigned long flags;
1260	unsigned int ufcon;
1261	int ret;
1262
1263	wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1264
1265	ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1266			  s3c24xx_serial_portname(port), ourport);
1267	if (ret) {
1268		dev_err(port->dev, "cannot get irq %d\n", port->irq);
1269		return ret;
1270	}
1271
1272	/* For compatibility with s3c24xx Soc's */
1273	ourport->rx_enabled = 1;
1274	ourport->tx_enabled = 0;
1275
1276	uart_port_lock_irqsave(port, &flags);
1277
1278	ufcon = rd_regl(port, S3C2410_UFCON);
1279	ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1280	if (!uart_console(port))
1281		ufcon |= S3C2410_UFCON_RESETTX;
1282	wr_regl(port, S3C2410_UFCON, ufcon);
1283
1284	enable_rx_pio(ourport);
1285
1286	uart_port_unlock_irqrestore(port, flags);
1287
1288	/* Enable Rx Interrupt */
1289	s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1290	s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1291
1292	return ret;
1293}
1294
1295/* power power management control */
1296
1297static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1298			      unsigned int old)
1299{
1300	struct s3c24xx_uart_port *ourport = to_ourport(port);
1301	int timeout = 10000;
1302
1303	ourport->pm_level = level;
1304
1305	switch (level) {
1306	case 3:
1307		while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1308			udelay(100);
1309
1310		if (!IS_ERR(ourport->baudclk))
1311			clk_disable_unprepare(ourport->baudclk);
1312
1313		clk_disable_unprepare(ourport->clk);
1314		break;
1315
1316	case 0:
1317		clk_prepare_enable(ourport->clk);
1318
1319		if (!IS_ERR(ourport->baudclk))
1320			clk_prepare_enable(ourport->baudclk);
1321		break;
1322	default:
1323		dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1324	}
1325}
1326
1327/* baud rate calculation
1328 *
1329 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1330 * of different sources, including the peripheral clock ("pclk") and an
1331 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1332 * with a programmable extra divisor.
1333 *
1334 * The following code goes through the clock sources, and calculates the
1335 * baud clocks (and the resultant actual baud rates) and then tries to
1336 * pick the closest one and select that.
1337 *
1338 */
1339
1340#define MAX_CLK_NAME_LENGTH 15
1341
1342static inline int s3c24xx_serial_getsource(struct uart_port *port)
1343{
1344	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1345	unsigned int ucon;
1346
1347	if (info->num_clks == 1)
1348		return 0;
1349
1350	ucon = rd_regl(port, S3C2410_UCON);
1351	ucon &= info->clksel_mask;
1352	return ucon >> info->clksel_shift;
1353}
1354
1355static void s3c24xx_serial_setsource(struct uart_port *port,
1356			unsigned int clk_sel)
1357{
1358	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1359	unsigned int ucon;
1360
1361	if (info->num_clks == 1)
1362		return;
1363
1364	ucon = rd_regl(port, S3C2410_UCON);
1365	if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1366		return;
1367
1368	ucon &= ~info->clksel_mask;
1369	ucon |= clk_sel << info->clksel_shift;
1370	wr_regl(port, S3C2410_UCON, ucon);
1371}
1372
1373static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1374			unsigned int req_baud, struct clk **best_clk,
1375			unsigned int *clk_num)
1376{
1377	const struct s3c24xx_uart_info *info = ourport->info;
1378	struct clk *clk;
1379	unsigned long rate;
1380	unsigned int cnt, baud, quot, best_quot = 0;
1381	char clkname[MAX_CLK_NAME_LENGTH];
1382	int calc_deviation, deviation = (1 << 30) - 1;
1383
1384	for (cnt = 0; cnt < info->num_clks; cnt++) {
1385		/* Keep selected clock if provided */
1386		if (ourport->cfg->clk_sel &&
1387			!(ourport->cfg->clk_sel & (1 << cnt)))
1388			continue;
1389
1390		sprintf(clkname, "clk_uart_baud%d", cnt);
1391		clk = clk_get(ourport->port.dev, clkname);
1392		if (IS_ERR(clk))
1393			continue;
1394
1395		rate = clk_get_rate(clk);
1396		if (!rate) {
1397			dev_err(ourport->port.dev,
1398				"Failed to get clock rate for %s.\n", clkname);
1399			clk_put(clk);
1400			continue;
1401		}
1402
1403		if (ourport->info->has_divslot) {
1404			unsigned long div = rate / req_baud;
1405
1406			/* The UDIVSLOT register on the newer UARTs allows us to
1407			 * get a divisor adjustment of 1/16th on the baud clock.
1408			 *
1409			 * We don't keep the UDIVSLOT value (the 16ths we
1410			 * calculated by not multiplying the baud by 16) as it
1411			 * is easy enough to recalculate.
1412			 */
1413
1414			quot = div / 16;
1415			baud = rate / div;
1416		} else {
1417			quot = (rate + (8 * req_baud)) / (16 * req_baud);
1418			baud = rate / (quot * 16);
1419		}
1420		quot--;
1421
1422		calc_deviation = abs(req_baud - baud);
1423
1424		if (calc_deviation < deviation) {
1425			/*
1426			 * If we find a better clk, release the previous one, if
1427			 * any.
1428			 */
1429			if (!IS_ERR(*best_clk))
1430				clk_put(*best_clk);
1431			*best_clk = clk;
1432			best_quot = quot;
1433			*clk_num = cnt;
1434			deviation = calc_deviation;
1435		} else {
1436			clk_put(clk);
1437		}
1438	}
1439
1440	return best_quot;
1441}
1442
1443/* udivslot_table[]
1444 *
1445 * This table takes the fractional value of the baud divisor and gives
1446 * the recommended setting for the UDIVSLOT register.
1447 */
1448static const u16 udivslot_table[16] = {
1449	[0] = 0x0000,
1450	[1] = 0x0080,
1451	[2] = 0x0808,
1452	[3] = 0x0888,
1453	[4] = 0x2222,
1454	[5] = 0x4924,
1455	[6] = 0x4A52,
1456	[7] = 0x54AA,
1457	[8] = 0x5555,
1458	[9] = 0xD555,
1459	[10] = 0xD5D5,
1460	[11] = 0xDDD5,
1461	[12] = 0xDDDD,
1462	[13] = 0xDFDD,
1463	[14] = 0xDFDF,
1464	[15] = 0xFFDF,
1465};
1466
1467static void s3c24xx_serial_set_termios(struct uart_port *port,
1468				       struct ktermios *termios,
1469				       const struct ktermios *old)
1470{
1471	const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1472	struct s3c24xx_uart_port *ourport = to_ourport(port);
1473	struct clk *clk = ERR_PTR(-EINVAL);
1474	unsigned long flags;
1475	unsigned int baud, quot, clk_sel = 0;
1476	unsigned int ulcon;
1477	unsigned int umcon;
1478	unsigned int udivslot = 0;
1479
1480	/*
1481	 * We don't support modem control lines.
1482	 */
1483	termios->c_cflag &= ~(HUPCL | CMSPAR);
1484	termios->c_cflag |= CLOCAL;
1485
1486	/*
1487	 * Ask the core to calculate the divisor for us.
1488	 */
1489
1490	baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1491	quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1492	if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1493		quot = port->custom_divisor;
1494	if (IS_ERR(clk))
1495		return;
1496
1497	/* check to see if we need  to change clock source */
1498
1499	if (ourport->baudclk != clk) {
1500		clk_prepare_enable(clk);
1501
1502		s3c24xx_serial_setsource(port, clk_sel);
1503
1504		if (!IS_ERR(ourport->baudclk)) {
1505			clk_disable_unprepare(ourport->baudclk);
1506			ourport->baudclk = ERR_PTR(-EINVAL);
1507		}
1508
1509		ourport->baudclk = clk;
1510		ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1511	}
1512
1513	if (ourport->info->has_divslot) {
1514		unsigned int div = ourport->baudclk_rate / baud;
1515
1516		if (cfg->has_fracval) {
1517			udivslot = (div & 15);
1518			dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1519		} else {
1520			udivslot = udivslot_table[div & 15];
1521			dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1522				udivslot, div & 15);
1523		}
1524	}
1525
1526	switch (termios->c_cflag & CSIZE) {
1527	case CS5:
1528		dev_dbg(port->dev, "config: 5bits/char\n");
1529		ulcon = S3C2410_LCON_CS5;
1530		break;
1531	case CS6:
1532		dev_dbg(port->dev, "config: 6bits/char\n");
1533		ulcon = S3C2410_LCON_CS6;
1534		break;
1535	case CS7:
1536		dev_dbg(port->dev, "config: 7bits/char\n");
1537		ulcon = S3C2410_LCON_CS7;
1538		break;
1539	case CS8:
1540	default:
1541		dev_dbg(port->dev, "config: 8bits/char\n");
1542		ulcon = S3C2410_LCON_CS8;
1543		break;
1544	}
1545
1546	/* preserve original lcon IR settings */
1547	ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1548
1549	if (termios->c_cflag & CSTOPB)
1550		ulcon |= S3C2410_LCON_STOPB;
1551
1552	if (termios->c_cflag & PARENB) {
1553		if (termios->c_cflag & PARODD)
1554			ulcon |= S3C2410_LCON_PODD;
1555		else
1556			ulcon |= S3C2410_LCON_PEVEN;
1557	} else {
1558		ulcon |= S3C2410_LCON_PNONE;
1559	}
1560
1561	uart_port_lock_irqsave(port, &flags);
1562
1563	dev_dbg(port->dev,
1564		"setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1565		ulcon, quot, udivslot);
1566
1567	wr_regl(port, S3C2410_ULCON, ulcon);
1568	wr_regl(port, S3C2410_UBRDIV, quot);
1569
1570	port->status &= ~UPSTAT_AUTOCTS;
1571
1572	umcon = rd_regl(port, S3C2410_UMCON);
1573	if (termios->c_cflag & CRTSCTS) {
1574		umcon |= S3C2410_UMCOM_AFC;
1575		/* Disable RTS when RX FIFO contains 63 bytes */
1576		umcon &= ~S3C2412_UMCON_AFC_8;
1577		port->status = UPSTAT_AUTOCTS;
1578	} else {
1579		umcon &= ~S3C2410_UMCOM_AFC;
1580	}
1581	wr_regl(port, S3C2410_UMCON, umcon);
1582
1583	if (ourport->info->has_divslot)
1584		wr_regl(port, S3C2443_DIVSLOT, udivslot);
1585
1586	dev_dbg(port->dev,
1587		"uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1588		rd_regl(port, S3C2410_ULCON),
1589		rd_regl(port, S3C2410_UCON),
1590		rd_regl(port, S3C2410_UFCON));
1591
1592	/*
1593	 * Update the per-port timeout.
1594	 */
1595	uart_update_timeout(port, termios->c_cflag, baud);
1596
1597	/*
1598	 * Which character status flags are we interested in?
1599	 */
1600	port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1601	if (termios->c_iflag & INPCK)
1602		port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1603			S3C2410_UERSTAT_PARITY;
1604	/*
1605	 * Which character status flags should we ignore?
1606	 */
1607	port->ignore_status_mask = 0;
1608	if (termios->c_iflag & IGNPAR)
1609		port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1610	if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1611		port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1612
1613	/*
1614	 * Ignore all characters if CREAD is not set.
1615	 */
1616	if ((termios->c_cflag & CREAD) == 0)
1617		port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1618
1619	uart_port_unlock_irqrestore(port, flags);
1620}
1621
1622static const char *s3c24xx_serial_type(struct uart_port *port)
1623{
1624	const struct s3c24xx_uart_port *ourport = to_ourport(port);
1625
1626	switch (ourport->info->type) {
1627	case TYPE_S3C6400:
1628		return "S3C6400/10";
1629	case TYPE_APPLE_S5L:
1630		return "APPLE S5L";
1631	default:
1632		return NULL;
1633	}
1634}
1635
1636static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1637{
1638	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1639
1640	if (flags & UART_CONFIG_TYPE)
1641		port->type = info->port_type;
1642}
1643
1644/*
1645 * verify the new serial_struct (for TIOCSSERIAL).
1646 */
1647static int
1648s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1649{
1650	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1651
1652	if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1653		return -EINVAL;
1654
1655	return 0;
1656}
1657
1658#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1659
1660static struct console s3c24xx_serial_console;
1661
1662static void __init s3c24xx_serial_register_console(void)
1663{
1664	register_console(&s3c24xx_serial_console);
1665}
1666
1667static void s3c24xx_serial_unregister_console(void)
1668{
1669	if (console_is_registered(&s3c24xx_serial_console))
1670		unregister_console(&s3c24xx_serial_console);
1671}
1672
1673#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1674#else
1675static inline void s3c24xx_serial_register_console(void) { }
1676static inline void s3c24xx_serial_unregister_console(void) { }
1677#define S3C24XX_SERIAL_CONSOLE NULL
1678#endif
1679
1680#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1681static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1682static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1683			 unsigned char c);
1684#endif
1685
1686static const struct uart_ops s3c64xx_serial_ops = {
1687	.pm		= s3c24xx_serial_pm,
1688	.tx_empty	= s3c24xx_serial_tx_empty,
1689	.get_mctrl	= s3c24xx_serial_get_mctrl,
1690	.set_mctrl	= s3c24xx_serial_set_mctrl,
1691	.stop_tx	= s3c24xx_serial_stop_tx,
1692	.start_tx	= s3c24xx_serial_start_tx,
1693	.stop_rx	= s3c24xx_serial_stop_rx,
1694	.break_ctl	= s3c24xx_serial_break_ctl,
1695	.startup	= s3c64xx_serial_startup,
1696	.shutdown	= s3c64xx_serial_shutdown,
1697	.set_termios	= s3c24xx_serial_set_termios,
1698	.type		= s3c24xx_serial_type,
1699	.config_port	= s3c24xx_serial_config_port,
1700	.verify_port	= s3c24xx_serial_verify_port,
1701#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1702	.poll_get_char = s3c24xx_serial_get_poll_char,
1703	.poll_put_char = s3c24xx_serial_put_poll_char,
1704#endif
1705};
1706
1707static const struct uart_ops apple_s5l_serial_ops = {
1708	.pm		= s3c24xx_serial_pm,
1709	.tx_empty	= s3c24xx_serial_tx_empty,
1710	.get_mctrl	= s3c24xx_serial_get_mctrl,
1711	.set_mctrl	= s3c24xx_serial_set_mctrl,
1712	.stop_tx	= s3c24xx_serial_stop_tx,
1713	.start_tx	= s3c24xx_serial_start_tx,
1714	.stop_rx	= s3c24xx_serial_stop_rx,
1715	.break_ctl	= s3c24xx_serial_break_ctl,
1716	.startup	= apple_s5l_serial_startup,
1717	.shutdown	= apple_s5l_serial_shutdown,
1718	.set_termios	= s3c24xx_serial_set_termios,
1719	.type		= s3c24xx_serial_type,
1720	.config_port	= s3c24xx_serial_config_port,
1721	.verify_port	= s3c24xx_serial_verify_port,
1722#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1723	.poll_get_char = s3c24xx_serial_get_poll_char,
1724	.poll_put_char = s3c24xx_serial_put_poll_char,
1725#endif
1726};
1727
1728static struct uart_driver s3c24xx_uart_drv = {
1729	.owner		= THIS_MODULE,
1730	.driver_name	= "s3c2410_serial",
1731	.nr		= UART_NR,
1732	.cons		= S3C24XX_SERIAL_CONSOLE,
1733	.dev_name	= S3C24XX_SERIAL_NAME,
1734	.major		= S3C24XX_SERIAL_MAJOR,
1735	.minor		= S3C24XX_SERIAL_MINOR,
1736};
1737
1738static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1739
1740static void s3c24xx_serial_init_port_default(int index) {
1741	struct uart_port *port = &s3c24xx_serial_ports[index].port;
1742
1743	spin_lock_init(&port->lock);
1744
1745	port->iotype = UPIO_MEM;
1746	port->uartclk = 0;
1747	port->fifosize = 16;
1748	port->flags = UPF_BOOT_AUTOCONF;
1749	port->line = index;
1750}
1751
1752/* s3c24xx_serial_resetport
1753 *
1754 * reset the fifos and other the settings.
1755 */
1756
1757static void s3c24xx_serial_resetport(struct uart_port *port,
1758				     const struct s3c2410_uartcfg *cfg)
1759{
1760	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1761	unsigned long ucon = rd_regl(port, S3C2410_UCON);
1762
1763	ucon &= (info->clksel_mask | info->ucon_mask);
1764	wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1765
1766	/* reset both fifos */
1767	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1768	wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1769
1770	/* some delay is required after fifo reset */
1771	udelay(1);
1772}
1773
1774static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1775{
1776	struct device *dev = ourport->port.dev;
1777	const struct s3c24xx_uart_info *info = ourport->info;
1778	char clk_name[MAX_CLK_NAME_LENGTH];
1779	unsigned int clk_sel;
1780	struct clk *clk;
1781	int clk_num;
1782	int ret;
1783
1784	clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1785	for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1786		if (!(clk_sel & (1 << clk_num)))
1787			continue;
1788
1789		sprintf(clk_name, "clk_uart_baud%d", clk_num);
1790		clk = clk_get(dev, clk_name);
1791		if (IS_ERR(clk))
1792			continue;
1793
1794		ret = clk_prepare_enable(clk);
1795		if (ret) {
1796			clk_put(clk);
1797			continue;
1798		}
1799
1800		ourport->baudclk = clk;
1801		ourport->baudclk_rate = clk_get_rate(clk);
1802		s3c24xx_serial_setsource(&ourport->port, clk_num);
1803
1804		return 0;
1805	}
1806
1807	return -EINVAL;
1808}
1809
1810/* s3c24xx_serial_init_port
1811 *
1812 * initialise a single serial port from the platform device given
1813 */
1814
1815static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1816				    struct platform_device *platdev)
1817{
1818	struct uart_port *port = &ourport->port;
1819	const struct s3c2410_uartcfg *cfg = ourport->cfg;
1820	struct resource *res;
1821	int ret;
1822
1823	if (platdev == NULL)
1824		return -ENODEV;
1825
1826	if (port->mapbase != 0)
1827		return -EINVAL;
1828
1829	/* setup info for port */
1830	port->dev	= &platdev->dev;
1831
1832	port->uartclk = 1;
1833
1834	if (cfg->uart_flags & UPF_CONS_FLOW) {
1835		dev_dbg(port->dev, "enabling flow control\n");
1836		port->flags |= UPF_CONS_FLOW;
1837	}
1838
1839	/* sort our the physical and virtual addresses for each UART */
1840
1841	res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1842	if (res == NULL) {
1843		dev_err(port->dev, "failed to find memory resource for uart\n");
1844		return -EINVAL;
1845	}
1846
1847	dev_dbg(port->dev, "resource %pR)\n", res);
1848
1849	port->membase = devm_ioremap_resource(port->dev, res);
1850	if (IS_ERR(port->membase)) {
1851		dev_err(port->dev, "failed to remap controller address\n");
1852		return -EBUSY;
1853	}
1854
1855	port->mapbase = res->start;
1856	ret = platform_get_irq(platdev, 0);
1857	if (ret < 0) {
1858		port->irq = 0;
1859	} else {
1860		port->irq = ret;
1861		ourport->rx_irq = ret;
1862		ourport->tx_irq = ret + 1;
1863	}
1864
1865	/*
1866	 * DMA is currently supported only on DT platforms, if DMA properties
1867	 * are specified.
1868	 */
1869	if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1870						     "dmas", NULL)) {
1871		ourport->dma = devm_kzalloc(port->dev,
1872					    sizeof(*ourport->dma),
1873					    GFP_KERNEL);
1874		if (!ourport->dma) {
1875			ret = -ENOMEM;
1876			goto err;
1877		}
1878	}
1879
1880	ourport->clk	= clk_get(&platdev->dev, "uart");
1881	if (IS_ERR(ourport->clk)) {
1882		pr_err("%s: Controller clock not found\n",
1883				dev_name(&platdev->dev));
1884		ret = PTR_ERR(ourport->clk);
1885		goto err;
1886	}
1887
1888	ret = clk_prepare_enable(ourport->clk);
1889	if (ret) {
1890		pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1891		clk_put(ourport->clk);
1892		goto err;
1893	}
1894
1895	ret = s3c24xx_serial_enable_baudclk(ourport);
1896	if (ret)
1897		pr_warn("uart: failed to enable baudclk\n");
1898
1899	/* Keep all interrupts masked and cleared */
1900	switch (ourport->info->type) {
1901	case TYPE_S3C6400:
1902		wr_regl(port, S3C64XX_UINTM, 0xf);
1903		wr_regl(port, S3C64XX_UINTP, 0xf);
1904		wr_regl(port, S3C64XX_UINTSP, 0xf);
1905		break;
1906	case TYPE_APPLE_S5L: {
1907		unsigned int ucon;
1908
1909		ucon = rd_regl(port, S3C2410_UCON);
1910		ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1911			APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1912			APPLE_S5L_UCON_RXTO_ENA_MSK);
1913		wr_regl(port, S3C2410_UCON, ucon);
1914
1915		wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1916		break;
1917	}
1918	default:
1919		break;
1920	}
1921
1922	dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1923		&port->mapbase, port->membase, port->irq,
1924		ourport->rx_irq, ourport->tx_irq, port->uartclk);
1925
1926	/* reset the fifos (and setup the uart) */
1927	s3c24xx_serial_resetport(port, cfg);
1928
1929	return 0;
1930
1931err:
1932	port->mapbase = 0;
1933	return ret;
1934}
1935
1936/* Device driver serial port probe */
1937
1938static int probe_index;
1939
1940static inline const struct s3c24xx_serial_drv_data *
1941s3c24xx_get_driver_data(struct platform_device *pdev)
1942{
1943	if (dev_of_node(&pdev->dev))
1944		return of_device_get_match_data(&pdev->dev);
1945
1946	return (struct s3c24xx_serial_drv_data *)
1947			platform_get_device_id(pdev)->driver_data;
1948}
1949
1950static int s3c24xx_serial_probe(struct platform_device *pdev)
1951{
1952	struct device_node *np = pdev->dev.of_node;
1953	struct s3c24xx_uart_port *ourport;
1954	int index = probe_index;
1955	int ret, prop = 0;
1956
1957	if (np) {
1958		ret = of_alias_get_id(np, "serial");
1959		if (ret >= 0)
1960			index = ret;
1961	}
1962
1963	if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1964		dev_err(&pdev->dev, "serial%d out of range\n", index);
1965		return -EINVAL;
1966	}
1967	ourport = &s3c24xx_serial_ports[index];
1968
1969	s3c24xx_serial_init_port_default(index);
1970
1971	ourport->drv_data = s3c24xx_get_driver_data(pdev);
1972	if (!ourport->drv_data) {
1973		dev_err(&pdev->dev, "could not find driver data\n");
1974		return -ENODEV;
1975	}
1976
1977	ourport->baudclk = ERR_PTR(-EINVAL);
1978	ourport->info = &ourport->drv_data->info;
1979	ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1980			dev_get_platdata(&pdev->dev) :
1981			&ourport->drv_data->def_cfg;
1982
1983	switch (ourport->info->type) {
1984	case TYPE_S3C6400:
1985		ourport->port.ops = &s3c64xx_serial_ops;
1986		break;
1987	case TYPE_APPLE_S5L:
1988		ourport->port.ops = &apple_s5l_serial_ops;
1989		break;
1990	}
1991
1992	if (np) {
1993		of_property_read_u32(np,
1994			"samsung,uart-fifosize", &ourport->port.fifosize);
1995
1996		if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
1997			switch (prop) {
1998			case 1:
1999				ourport->port.iotype = UPIO_MEM;
2000				break;
2001			case 4:
2002				ourport->port.iotype = UPIO_MEM32;
2003				break;
2004			default:
2005				dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2006						prop);
2007				return -EINVAL;
2008			}
2009		}
2010	}
2011
2012	if (ourport->drv_data->fifosize[index])
2013		ourport->port.fifosize = ourport->drv_data->fifosize[index];
2014	else if (ourport->info->fifosize)
2015		ourport->port.fifosize = ourport->info->fifosize;
2016	ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2017
2018	/*
2019	 * DMA transfers must be aligned at least to cache line size,
2020	 * so find minimal transfer size suitable for DMA mode
2021	 */
2022	ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2023				    dma_get_cache_alignment());
2024
2025	dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2026
2027	ret = s3c24xx_serial_init_port(ourport, pdev);
2028	if (ret < 0)
2029		return ret;
2030
2031	if (!s3c24xx_uart_drv.state) {
2032		ret = uart_register_driver(&s3c24xx_uart_drv);
2033		if (ret < 0) {
2034			pr_err("Failed to register Samsung UART driver\n");
2035			return ret;
2036		}
2037	}
2038
2039	dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2040	uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2041	platform_set_drvdata(pdev, &ourport->port);
2042
2043	/*
2044	 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2045	 * so that a potential re-enablement through the pm-callback overlaps
2046	 * and keeps the clock enabled in this case.
2047	 */
2048	clk_disable_unprepare(ourport->clk);
2049	if (!IS_ERR(ourport->baudclk))
2050		clk_disable_unprepare(ourport->baudclk);
2051
2052	probe_index++;
2053
2054	return 0;
2055}
2056
2057static void s3c24xx_serial_remove(struct platform_device *dev)
2058{
2059	struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2060
2061	if (port) {
2062		uart_remove_one_port(&s3c24xx_uart_drv, port);
2063	}
2064
2065	uart_unregister_driver(&s3c24xx_uart_drv);
2066}
2067
2068/* UART power management code */
2069#ifdef CONFIG_PM_SLEEP
2070static int s3c24xx_serial_suspend(struct device *dev)
2071{
2072	struct uart_port *port = s3c24xx_dev_to_port(dev);
2073
2074	if (port)
2075		uart_suspend_port(&s3c24xx_uart_drv, port);
2076
2077	return 0;
2078}
2079
2080static int s3c24xx_serial_resume(struct device *dev)
2081{
2082	struct uart_port *port = s3c24xx_dev_to_port(dev);
2083	struct s3c24xx_uart_port *ourport = to_ourport(port);
2084
2085	if (port) {
2086		clk_prepare_enable(ourport->clk);
2087		if (!IS_ERR(ourport->baudclk))
2088			clk_prepare_enable(ourport->baudclk);
2089		s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2090		if (!IS_ERR(ourport->baudclk))
2091			clk_disable_unprepare(ourport->baudclk);
2092		clk_disable_unprepare(ourport->clk);
2093
2094		uart_resume_port(&s3c24xx_uart_drv, port);
2095	}
2096
2097	return 0;
2098}
2099
2100static int s3c24xx_serial_resume_noirq(struct device *dev)
2101{
2102	struct uart_port *port = s3c24xx_dev_to_port(dev);
2103	struct s3c24xx_uart_port *ourport = to_ourport(port);
2104
2105	if (port) {
2106		/* restore IRQ mask */
2107		switch (ourport->info->type) {
2108		case TYPE_S3C6400: {
2109			unsigned int uintm = 0xf;
2110
2111			if (ourport->tx_enabled)
2112				uintm &= ~S3C64XX_UINTM_TXD_MSK;
2113			if (ourport->rx_enabled)
2114				uintm &= ~S3C64XX_UINTM_RXD_MSK;
2115			clk_prepare_enable(ourport->clk);
2116			if (!IS_ERR(ourport->baudclk))
2117				clk_prepare_enable(ourport->baudclk);
2118			wr_regl(port, S3C64XX_UINTM, uintm);
2119			if (!IS_ERR(ourport->baudclk))
2120				clk_disable_unprepare(ourport->baudclk);
2121			clk_disable_unprepare(ourport->clk);
2122			break;
2123		}
2124		case TYPE_APPLE_S5L: {
2125			unsigned int ucon;
2126			int ret;
2127
2128			ret = clk_prepare_enable(ourport->clk);
2129			if (ret) {
2130				dev_err(dev, "clk_enable clk failed: %d\n", ret);
2131				return ret;
2132			}
2133			if (!IS_ERR(ourport->baudclk)) {
2134				ret = clk_prepare_enable(ourport->baudclk);
2135				if (ret) {
2136					dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2137					clk_disable_unprepare(ourport->clk);
2138					return ret;
2139				}
2140			}
2141
2142			ucon = rd_regl(port, S3C2410_UCON);
2143
2144			ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2145				  APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2146				  APPLE_S5L_UCON_RXTO_ENA_MSK);
2147
2148			if (ourport->tx_enabled)
2149				ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2150			if (ourport->rx_enabled)
2151				ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2152					APPLE_S5L_UCON_RXTO_ENA_MSK;
2153
2154			wr_regl(port, S3C2410_UCON, ucon);
2155
2156			if (!IS_ERR(ourport->baudclk))
2157				clk_disable_unprepare(ourport->baudclk);
2158			clk_disable_unprepare(ourport->clk);
2159			break;
2160		}
2161		default:
2162			break;
2163		}
2164	}
2165
2166	return 0;
2167}
2168
2169static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2170	SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume)
2171	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq)
2172};
2173#define SERIAL_SAMSUNG_PM_OPS	(&s3c24xx_serial_pm_ops)
2174
2175#else /* !CONFIG_PM_SLEEP */
2176
2177#define SERIAL_SAMSUNG_PM_OPS	NULL
2178#endif /* CONFIG_PM_SLEEP */
2179
2180/* Console code */
2181
2182#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2183
2184static struct uart_port *cons_uart;
2185
2186static int
2187s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2188{
2189	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2190	unsigned long ufstat, utrstat;
2191
2192	if (ufcon & S3C2410_UFCON_FIFOMODE) {
2193		/* fifo mode - check amount of data in fifo registers... */
2194
2195		ufstat = rd_regl(port, S3C2410_UFSTAT);
2196		return (ufstat & info->tx_fifofull) ? 0 : 1;
2197	}
2198
2199	/* in non-fifo mode, we go and use the tx buffer empty */
2200
2201	utrstat = rd_regl(port, S3C2410_UTRSTAT);
2202	return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2203}
2204
2205static bool
2206s3c24xx_port_configured(unsigned int ucon)
2207{
2208	/* consider the serial port configured if the tx/rx mode set */
2209	return (ucon & 0xf) != 0;
2210}
2211
2212#ifdef CONFIG_CONSOLE_POLL
2213/*
2214 * Console polling routines for writing and reading from the uart while
2215 * in an interrupt or debug context.
2216 */
2217
2218static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2219{
2220	const struct s3c24xx_uart_port *ourport = to_ourport(port);
2221	unsigned int ufstat;
2222
2223	ufstat = rd_regl(port, S3C2410_UFSTAT);
2224	if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2225		return NO_POLL_CHAR;
2226
2227	return rd_reg(port, S3C2410_URXH);
2228}
2229
2230static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2231		unsigned char c)
2232{
2233	unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2234	unsigned int ucon = rd_regl(port, S3C2410_UCON);
2235
2236	/* not possible to xmit on unconfigured port */
2237	if (!s3c24xx_port_configured(ucon))
2238		return;
2239
2240	while (!s3c24xx_serial_console_txrdy(port, ufcon))
2241		cpu_relax();
2242	wr_reg(port, S3C2410_UTXH, c);
2243}
2244
2245#endif /* CONFIG_CONSOLE_POLL */
2246
2247static void
2248s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2249{
2250	unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2251
2252	while (!s3c24xx_serial_console_txrdy(port, ufcon))
2253		cpu_relax();
2254	wr_reg(port, S3C2410_UTXH, ch);
2255}
2256
2257static void
2258s3c24xx_serial_console_write(struct console *co, const char *s,
2259			     unsigned int count)
2260{
2261	unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2262	unsigned long flags;
2263	bool locked = true;
2264
2265	/* not possible to xmit on unconfigured port */
2266	if (!s3c24xx_port_configured(ucon))
2267		return;
2268
2269	if (cons_uart->sysrq)
2270		locked = false;
2271	else if (oops_in_progress)
2272		locked = uart_port_trylock_irqsave(cons_uart, &flags);
2273	else
2274		uart_port_lock_irqsave(cons_uart, &flags);
2275
2276	uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2277
2278	if (locked)
2279		uart_port_unlock_irqrestore(cons_uart, flags);
2280}
2281
2282/* Shouldn't be __init, as it can be instantiated from other module */
2283static void
2284s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2285			   int *parity, int *bits)
2286{
2287	struct clk *clk;
2288	unsigned int ulcon;
2289	unsigned int ucon;
2290	unsigned int ubrdiv;
2291	unsigned long rate;
2292	unsigned int clk_sel;
2293	char clk_name[MAX_CLK_NAME_LENGTH];
2294
2295	ulcon  = rd_regl(port, S3C2410_ULCON);
2296	ucon   = rd_regl(port, S3C2410_UCON);
2297	ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2298
2299	if (s3c24xx_port_configured(ucon)) {
2300		switch (ulcon & S3C2410_LCON_CSMASK) {
2301		case S3C2410_LCON_CS5:
2302			*bits = 5;
2303			break;
2304		case S3C2410_LCON_CS6:
2305			*bits = 6;
2306			break;
2307		case S3C2410_LCON_CS7:
2308			*bits = 7;
2309			break;
2310		case S3C2410_LCON_CS8:
2311		default:
2312			*bits = 8;
2313			break;
2314		}
2315
2316		switch (ulcon & S3C2410_LCON_PMASK) {
2317		case S3C2410_LCON_PEVEN:
2318			*parity = 'e';
2319			break;
2320
2321		case S3C2410_LCON_PODD:
2322			*parity = 'o';
2323			break;
2324
2325		case S3C2410_LCON_PNONE:
2326		default:
2327			*parity = 'n';
2328		}
2329
2330		/* now calculate the baud rate */
2331
2332		clk_sel = s3c24xx_serial_getsource(port);
2333		sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2334
2335		clk = clk_get(port->dev, clk_name);
2336		if (!IS_ERR(clk))
2337			rate = clk_get_rate(clk);
2338		else
2339			rate = 1;
2340
2341		*baud = rate / (16 * (ubrdiv + 1));
2342		dev_dbg(port->dev, "calculated baud %d\n", *baud);
2343	}
2344}
2345
2346/* Shouldn't be __init, as it can be instantiated from other module */
2347static int
2348s3c24xx_serial_console_setup(struct console *co, char *options)
2349{
2350	struct uart_port *port;
2351	int baud = 9600;
2352	int bits = 8;
2353	int parity = 'n';
2354	int flow = 'n';
2355
2356	/* is this a valid port */
2357
2358	if (co->index == -1 || co->index >= UART_NR)
2359		co->index = 0;
2360
2361	port = &s3c24xx_serial_ports[co->index].port;
2362
2363	/* is the port configured? */
2364
2365	if (port->mapbase == 0x0)
2366		return -ENODEV;
2367
2368	cons_uart = port;
2369
2370	/*
2371	 * Check whether an invalid uart number has been specified, and
2372	 * if so, search for the first available port that does have
2373	 * console support.
2374	 */
2375	if (options)
2376		uart_parse_options(options, &baud, &parity, &bits, &flow);
2377	else
2378		s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2379
2380	dev_dbg(port->dev, "baud %d\n", baud);
2381
2382	return uart_set_options(port, co, baud, parity, bits, flow);
2383}
2384
2385static struct console s3c24xx_serial_console = {
2386	.name		= S3C24XX_SERIAL_NAME,
2387	.device		= uart_console_device,
2388	.flags		= CON_PRINTBUFFER,
2389	.index		= -1,
2390	.write		= s3c24xx_serial_console_write,
2391	.setup		= s3c24xx_serial_console_setup,
2392	.data		= &s3c24xx_uart_drv,
2393};
2394#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2395
2396#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2397static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2398	.info = {
2399		.name		= "Samsung S3C6400 UART",
2400		.type		= TYPE_S3C6400,
2401		.port_type	= PORT_S3C6400,
2402		.fifosize	= 64,
2403		.has_divslot	= 1,
2404		.rx_fifomask	= S3C2440_UFSTAT_RXMASK,
2405		.rx_fifoshift	= S3C2440_UFSTAT_RXSHIFT,
2406		.rx_fifofull	= S3C2440_UFSTAT_RXFULL,
2407		.tx_fifofull	= S3C2440_UFSTAT_TXFULL,
2408		.tx_fifomask	= S3C2440_UFSTAT_TXMASK,
2409		.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,
2410		.def_clk_sel	= S3C2410_UCON_CLKSEL2,
2411		.num_clks	= 4,
2412		.clksel_mask	= S3C6400_UCON_CLKMASK,
2413		.clksel_shift	= S3C6400_UCON_CLKSHIFT,
2414	},
2415	.def_cfg = {
2416		.ucon		= S3C2410_UCON_DEFAULT,
2417		.ufcon		= S3C2410_UFCON_DEFAULT,
2418	},
2419};
2420#define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2421#else
2422#define S3C6400_SERIAL_DRV_DATA NULL
2423#endif
2424
2425#ifdef CONFIG_CPU_S5PV210
2426static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2427	.info = {
2428		.name		= "Samsung S5PV210 UART",
2429		.type		= TYPE_S3C6400,
2430		.port_type	= PORT_S3C6400,
2431		.has_divslot	= 1,
2432		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,
2433		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,
2434		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,
2435		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,
2436		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,
2437		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,
2438		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2439		.num_clks	= 2,
2440		.clksel_mask	= S5PV210_UCON_CLKMASK,
2441		.clksel_shift	= S5PV210_UCON_CLKSHIFT,
2442	},
2443	.def_cfg = {
2444		.ucon		= S5PV210_UCON_DEFAULT,
2445		.ufcon		= S5PV210_UFCON_DEFAULT,
2446	},
2447	.fifosize = { 256, 64, 16, 16 },
2448};
2449#define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2450#else
2451#define S5PV210_SERIAL_DRV_DATA	NULL
2452#endif
2453
2454#if defined(CONFIG_ARCH_EXYNOS)
2455#define EXYNOS_COMMON_SERIAL_DRV_DATA()				\
2456	.info = {						\
2457		.name		= "Samsung Exynos UART",	\
2458		.type		= TYPE_S3C6400,			\
2459		.port_type	= PORT_S3C6400,			\
2460		.has_divslot	= 1,				\
2461		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,	\
2462		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,	\
2463		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,	\
2464		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,	\
2465		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,	\
2466		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,	\
2467		.def_clk_sel	= S3C2410_UCON_CLKSEL0,		\
2468		.num_clks	= 1,				\
2469		.clksel_mask	= 0,				\
2470		.clksel_shift	= 0,				\
2471	},							\
2472	.def_cfg = {						\
2473		.ucon		= S5PV210_UCON_DEFAULT,		\
2474		.ufcon		= S5PV210_UFCON_DEFAULT,	\
2475		.has_fracval	= 1,				\
2476	}							\
2477
2478static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2479	EXYNOS_COMMON_SERIAL_DRV_DATA(),
2480	.fifosize = { 256, 64, 16, 16 },
2481};
2482
2483static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2484	EXYNOS_COMMON_SERIAL_DRV_DATA(),
2485	.fifosize = { 64, 256, 16, 256 },
2486};
2487
2488static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2489	EXYNOS_COMMON_SERIAL_DRV_DATA(),
2490	.fifosize = { 256, 64, 64, 64 },
2491};
2492
2493/*
2494 * Common drv_data struct for platforms that specify samsung,uart-fifosize in
2495 * device tree.
2496 */
2497static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = {
2498	EXYNOS_COMMON_SERIAL_DRV_DATA(),
2499	.fifosize = { 0 },
2500};
2501
2502#define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2503#define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2504#define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2505#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data)
2506
2507#else
2508#define EXYNOS4210_SERIAL_DRV_DATA NULL
2509#define EXYNOS5433_SERIAL_DRV_DATA NULL
2510#define EXYNOS850_SERIAL_DRV_DATA NULL
2511#define EXYNOS_FIFOSZDT_DRV_DATA NULL
2512#endif
2513
2514#ifdef CONFIG_ARCH_APPLE
2515static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2516	.info = {
2517		.name		= "Apple S5L UART",
2518		.type		= TYPE_APPLE_S5L,
2519		.port_type	= PORT_8250,
2520		.fifosize	= 16,
2521		.rx_fifomask	= S3C2410_UFSTAT_RXMASK,
2522		.rx_fifoshift	= S3C2410_UFSTAT_RXSHIFT,
2523		.rx_fifofull	= S3C2410_UFSTAT_RXFULL,
2524		.tx_fifofull	= S3C2410_UFSTAT_TXFULL,
2525		.tx_fifomask	= S3C2410_UFSTAT_TXMASK,
2526		.tx_fifoshift	= S3C2410_UFSTAT_TXSHIFT,
2527		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2528		.num_clks	= 1,
2529		.clksel_mask	= 0,
2530		.clksel_shift	= 0,
2531		.ucon_mask	= APPLE_S5L_UCON_MASK,
2532	},
2533	.def_cfg = {
2534		.ucon		= APPLE_S5L_UCON_DEFAULT,
2535		.ufcon		= S3C2410_UFCON_DEFAULT,
2536	},
2537};
2538#define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2539#else
2540#define S5L_SERIAL_DRV_DATA NULL
2541#endif
2542
2543#if defined(CONFIG_ARCH_ARTPEC)
2544static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2545	.info = {
2546		.name		= "Axis ARTPEC-8 UART",
2547		.type		= TYPE_S3C6400,
2548		.port_type	= PORT_S3C6400,
2549		.fifosize	= 64,
2550		.has_divslot	= 1,
2551		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,
2552		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,
2553		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,
2554		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,
2555		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,
2556		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,
2557		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2558		.num_clks	= 1,
2559		.clksel_mask	= 0,
2560		.clksel_shift	= 0,
2561	},
2562	.def_cfg = {
2563		.ucon		= S5PV210_UCON_DEFAULT,
2564		.ufcon		= S5PV210_UFCON_DEFAULT,
2565		.has_fracval	= 1,
2566	}
2567};
2568#define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2569#else
2570#define ARTPEC8_SERIAL_DRV_DATA (NULL)
2571#endif
2572
2573static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2574	{
2575		.name		= "s3c6400-uart",
2576		.driver_data	= (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2577	}, {
2578		.name		= "s5pv210-uart",
2579		.driver_data	= (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2580	}, {
2581		.name		= "exynos4210-uart",
2582		.driver_data	= (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2583	}, {
2584		.name		= "exynos5433-uart",
2585		.driver_data	= (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2586	}, {
2587		.name		= "s5l-uart",
2588		.driver_data	= (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2589	}, {
2590		.name		= "exynos850-uart",
2591		.driver_data	= (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2592	}, {
2593		.name		= "artpec8-uart",
2594		.driver_data	= (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2595	}, {
2596		.name		= "gs101-uart",
2597		.driver_data	= (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA,
2598	},
2599	{ },
2600};
2601MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2602
2603#ifdef CONFIG_OF
2604static const struct of_device_id s3c24xx_uart_dt_match[] = {
2605	{ .compatible = "samsung,s3c6400-uart",
2606		.data = S3C6400_SERIAL_DRV_DATA },
2607	{ .compatible = "samsung,s5pv210-uart",
2608		.data = S5PV210_SERIAL_DRV_DATA },
2609	{ .compatible = "samsung,exynos4210-uart",
2610		.data = EXYNOS4210_SERIAL_DRV_DATA },
2611	{ .compatible = "samsung,exynos5433-uart",
2612		.data = EXYNOS5433_SERIAL_DRV_DATA },
2613	{ .compatible = "apple,s5l-uart",
2614		.data = S5L_SERIAL_DRV_DATA },
2615	{ .compatible = "samsung,exynos850-uart",
2616		.data = EXYNOS850_SERIAL_DRV_DATA },
2617	{ .compatible = "axis,artpec8-uart",
2618		.data = ARTPEC8_SERIAL_DRV_DATA },
2619	{ .compatible = "google,gs101-uart",
2620		.data = EXYNOS_FIFOSZDT_DRV_DATA },
2621	{},
2622};
2623MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2624#endif
2625
2626static struct platform_driver samsung_serial_driver = {
2627	.probe		= s3c24xx_serial_probe,
2628	.remove_new	= s3c24xx_serial_remove,
2629	.id_table	= s3c24xx_serial_driver_ids,
2630	.driver		= {
2631		.name	= "samsung-uart",
2632		.pm	= SERIAL_SAMSUNG_PM_OPS,
2633		.of_match_table	= of_match_ptr(s3c24xx_uart_dt_match),
2634	},
2635};
2636
2637static int __init samsung_serial_init(void)
2638{
2639	int ret;
2640
2641	s3c24xx_serial_register_console();
2642
2643	ret = platform_driver_register(&samsung_serial_driver);
2644	if (ret) {
2645		s3c24xx_serial_unregister_console();
2646		return ret;
2647	}
2648
2649	return 0;
2650}
2651
2652static void __exit samsung_serial_exit(void)
2653{
2654	platform_driver_unregister(&samsung_serial_driver);
2655	s3c24xx_serial_unregister_console();
2656}
2657
2658module_init(samsung_serial_init);
2659module_exit(samsung_serial_exit);
2660
2661#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2662/*
2663 * Early console.
2664 */
2665
2666static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2667{
2668	switch (port->iotype) {
2669	case UPIO_MEM:
2670		writeb(val, portaddr(port, reg));
2671		break;
2672	case UPIO_MEM32:
2673		writel(val, portaddr(port, reg));
2674		break;
2675	}
2676}
2677
2678struct samsung_early_console_data {
2679	u32 txfull_mask;
2680	u32 rxfifo_mask;
2681};
2682
2683static void samsung_early_busyuart(const struct uart_port *port)
2684{
2685	while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2686		;
2687}
2688
2689static void samsung_early_busyuart_fifo(const struct uart_port *port)
2690{
2691	const struct samsung_early_console_data *data = port->private_data;
2692
2693	while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2694		;
2695}
2696
2697static void samsung_early_putc(struct uart_port *port, unsigned char c)
2698{
2699	if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2700		samsung_early_busyuart_fifo(port);
2701	else
2702		samsung_early_busyuart(port);
2703
2704	wr_reg_barrier(port, S3C2410_UTXH, c);
2705}
2706
2707static void samsung_early_write(struct console *con, const char *s,
2708				unsigned int n)
2709{
2710	struct earlycon_device *dev = con->data;
2711
2712	uart_console_write(&dev->port, s, n, samsung_early_putc);
2713}
2714
2715static int samsung_early_read(struct console *con, char *s, unsigned int n)
2716{
2717	struct earlycon_device *dev = con->data;
2718	const struct samsung_early_console_data *data = dev->port.private_data;
2719	int ch, ufstat, num_read = 0;
2720
2721	while (num_read < n) {
2722		ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
2723		if (!(ufstat & data->rxfifo_mask))
2724			break;
2725		ch = rd_reg(&dev->port, S3C2410_URXH);
2726		if (ch == NO_POLL_CHAR)
2727			break;
2728
2729		s[num_read++] = ch;
2730	}
2731
2732	return num_read;
2733}
2734
2735static int __init samsung_early_console_setup(struct earlycon_device *device,
2736					      const char *opt)
2737{
2738	if (!device->port.membase)
2739		return -ENODEV;
2740
2741	device->con->write = samsung_early_write;
2742	device->con->read = samsung_early_read;
2743	return 0;
2744}
2745
2746/* S3C2410 */
2747static struct samsung_early_console_data s3c2410_early_console_data = {
2748	.txfull_mask = S3C2410_UFSTAT_TXFULL,
2749	.rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
2750};
2751
2752/* S3C64xx */
2753static struct samsung_early_console_data s3c2440_early_console_data = {
2754	.txfull_mask = S3C2440_UFSTAT_TXFULL,
2755	.rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
2756};
2757
2758static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2759					      const char *opt)
2760{
2761	device->port.private_data = &s3c2440_early_console_data;
2762	return samsung_early_console_setup(device, opt);
2763}
2764
2765OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2766			s3c2440_early_console_setup);
2767
2768/* S5PV210, Exynos */
2769static struct samsung_early_console_data s5pv210_early_console_data = {
2770	.txfull_mask = S5PV210_UFSTAT_TXFULL,
2771	.rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
2772};
2773
2774static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2775					      const char *opt)
2776{
2777	device->port.private_data = &s5pv210_early_console_data;
2778	return samsung_early_console_setup(device, opt);
2779}
2780
2781OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2782			s5pv210_early_console_setup);
2783OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2784			s5pv210_early_console_setup);
2785OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
2786			s5pv210_early_console_setup);
2787
2788/* Apple S5L */
2789static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
2790						const char *opt)
2791{
2792	/* Close enough to S3C2410 for earlycon... */
2793	device->port.private_data = &s3c2410_early_console_data;
2794
2795#ifdef CONFIG_ARM64
2796	/* ... but we need to override the existing fixmap entry as nGnRnE */
2797	__set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
2798		     __pgprot(PROT_DEVICE_nGnRnE));
2799#endif
2800	return samsung_early_console_setup(device, opt);
2801}
2802
2803OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
2804#endif
2805
2806MODULE_ALIAS("platform:samsung-uart");
2807MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2808MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2809MODULE_LICENSE("GPL v2");