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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4/* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
5#define __DISABLE_TRACE_MMIO__
6
7#include <linux/clk.h>
8#include <linux/console.h>
9#include <linux/io.h>
10#include <linux/iopoll.h>
11#include <linux/irq.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/pm_opp.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/pm_wakeirq.h>
18#include <linux/soc/qcom/geni-se.h>
19#include <linux/serial.h>
20#include <linux/serial_core.h>
21#include <linux/slab.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <dt-bindings/interconnect/qcom,icc.h>
25
26/* UART specific GENI registers */
27#define SE_UART_LOOPBACK_CFG 0x22c
28#define SE_UART_IO_MACRO_CTRL 0x240
29#define SE_UART_TX_TRANS_CFG 0x25c
30#define SE_UART_TX_WORD_LEN 0x268
31#define SE_UART_TX_STOP_BIT_LEN 0x26c
32#define SE_UART_TX_TRANS_LEN 0x270
33#define SE_UART_RX_TRANS_CFG 0x280
34#define SE_UART_RX_WORD_LEN 0x28c
35#define SE_UART_RX_STALE_CNT 0x294
36#define SE_UART_TX_PARITY_CFG 0x2a4
37#define SE_UART_RX_PARITY_CFG 0x2a8
38#define SE_UART_MANUAL_RFR 0x2ac
39
40/* SE_UART_TRANS_CFG */
41#define UART_TX_PAR_EN BIT(0)
42#define UART_CTS_MASK BIT(1)
43
44/* SE_UART_TX_STOP_BIT_LEN */
45#define TX_STOP_BIT_LEN_1 0
46#define TX_STOP_BIT_LEN_2 2
47
48/* SE_UART_RX_TRANS_CFG */
49#define UART_RX_PAR_EN BIT(3)
50
51/* SE_UART_RX_WORD_LEN */
52#define RX_WORD_LEN_MASK GENMASK(9, 0)
53
54/* SE_UART_RX_STALE_CNT */
55#define RX_STALE_CNT GENMASK(23, 0)
56
57/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
58#define PAR_CALC_EN BIT(0)
59#define PAR_EVEN 0x00
60#define PAR_ODD 0x01
61#define PAR_SPACE 0x10
62
63/* SE_UART_MANUAL_RFR register fields */
64#define UART_MANUAL_RFR_EN BIT(31)
65#define UART_RFR_NOT_READY BIT(1)
66#define UART_RFR_READY BIT(0)
67
68/* UART M_CMD OP codes */
69#define UART_START_TX 0x1
70/* UART S_CMD OP codes */
71#define UART_START_READ 0x1
72#define UART_PARAM 0x1
73#define UART_PARAM_RFR_OPEN BIT(7)
74
75#define UART_OVERSAMPLING 32
76#define STALE_TIMEOUT 16
77#define DEFAULT_BITS_PER_CHAR 10
78#define GENI_UART_CONS_PORTS 1
79#define GENI_UART_PORTS 3
80#define DEF_FIFO_DEPTH_WORDS 16
81#define DEF_TX_WM 2
82#define DEF_FIFO_WIDTH_BITS 32
83#define UART_RX_WM 2
84
85/* SE_UART_LOOPBACK_CFG */
86#define RX_TX_SORTED BIT(0)
87#define CTS_RTS_SORTED BIT(1)
88#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
89
90/* UART pin swap value */
91#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
92#define IO_MACRO_IO0_SEL 0x3
93#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
94#define IO_MACRO_IO2_IO3_SWAP 0x4640
95
96/* We always configure 4 bytes per FIFO word */
97#define BYTES_PER_FIFO_WORD 4U
98
99#define DMA_RX_BUF_SIZE 2048
100
101struct qcom_geni_device_data {
102 bool console;
103 enum geni_se_xfer_mode mode;
104};
105
106struct qcom_geni_private_data {
107 /* NOTE: earlycon port will have NULL here */
108 struct uart_driver *drv;
109
110 u32 poll_cached_bytes;
111 unsigned int poll_cached_bytes_cnt;
112
113 u32 write_cached_bytes;
114 unsigned int write_cached_bytes_cnt;
115};
116
117struct qcom_geni_serial_port {
118 struct uart_port uport;
119 struct geni_se se;
120 const char *name;
121 u32 tx_fifo_depth;
122 u32 tx_fifo_width;
123 u32 rx_fifo_depth;
124 dma_addr_t tx_dma_addr;
125 dma_addr_t rx_dma_addr;
126 bool setup;
127 unsigned int baud;
128 unsigned long clk_rate;
129 void *rx_buf;
130 u32 loopback;
131 bool brk;
132
133 unsigned int tx_remaining;
134 int wakeup_irq;
135 bool rx_tx_swap;
136 bool cts_rts_swap;
137
138 struct qcom_geni_private_data private_data;
139 const struct qcom_geni_device_data *dev_data;
140};
141
142static const struct uart_ops qcom_geni_console_pops;
143static const struct uart_ops qcom_geni_uart_pops;
144static struct uart_driver qcom_geni_console_driver;
145static struct uart_driver qcom_geni_uart_driver;
146
147static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport)
148{
149 return container_of(uport, struct qcom_geni_serial_port, uport);
150}
151
152static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
153 [0] = {
154 .uport = {
155 .iotype = UPIO_MEM,
156 .ops = &qcom_geni_uart_pops,
157 .flags = UPF_BOOT_AUTOCONF,
158 .line = 0,
159 },
160 },
161 [1] = {
162 .uport = {
163 .iotype = UPIO_MEM,
164 .ops = &qcom_geni_uart_pops,
165 .flags = UPF_BOOT_AUTOCONF,
166 .line = 1,
167 },
168 },
169 [2] = {
170 .uport = {
171 .iotype = UPIO_MEM,
172 .ops = &qcom_geni_uart_pops,
173 .flags = UPF_BOOT_AUTOCONF,
174 .line = 2,
175 },
176 },
177};
178
179static struct qcom_geni_serial_port qcom_geni_console_port = {
180 .uport = {
181 .iotype = UPIO_MEM,
182 .ops = &qcom_geni_console_pops,
183 .flags = UPF_BOOT_AUTOCONF,
184 .line = 0,
185 },
186};
187
188static int qcom_geni_serial_request_port(struct uart_port *uport)
189{
190 struct platform_device *pdev = to_platform_device(uport->dev);
191 struct qcom_geni_serial_port *port = to_dev_port(uport);
192
193 uport->membase = devm_platform_ioremap_resource(pdev, 0);
194 if (IS_ERR(uport->membase))
195 return PTR_ERR(uport->membase);
196 port->se.base = uport->membase;
197 return 0;
198}
199
200static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
201{
202 if (cfg_flags & UART_CONFIG_TYPE) {
203 uport->type = PORT_MSM;
204 qcom_geni_serial_request_port(uport);
205 }
206}
207
208static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
209{
210 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
211 u32 geni_ios;
212
213 if (uart_console(uport)) {
214 mctrl |= TIOCM_CTS;
215 } else {
216 geni_ios = readl(uport->membase + SE_GENI_IOS);
217 if (!(geni_ios & IO2_DATA_IN))
218 mctrl |= TIOCM_CTS;
219 }
220
221 return mctrl;
222}
223
224static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
225 unsigned int mctrl)
226{
227 u32 uart_manual_rfr = 0;
228 struct qcom_geni_serial_port *port = to_dev_port(uport);
229
230 if (uart_console(uport))
231 return;
232
233 if (mctrl & TIOCM_LOOP)
234 port->loopback = RX_TX_CTS_RTS_SORTED;
235
236 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
237 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
239}
240
241static const char *qcom_geni_serial_get_type(struct uart_port *uport)
242{
243 return "MSM";
244}
245
246static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
247{
248 struct qcom_geni_serial_port *port;
249 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
250
251 if (line < 0 || line >= nr_ports)
252 return ERR_PTR(-ENXIO);
253
254 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
255 return port;
256}
257
258static bool qcom_geni_serial_main_active(struct uart_port *uport)
259{
260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE;
261}
262
263static bool qcom_geni_serial_secondary_active(struct uart_port *uport)
264{
265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE;
266}
267
268static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
269 int offset, int field, bool set)
270{
271 u32 reg;
272 struct qcom_geni_serial_port *port;
273 unsigned int baud;
274 unsigned int fifo_bits;
275 unsigned long timeout_us = 20000;
276 struct qcom_geni_private_data *private_data = uport->private_data;
277
278 if (private_data->drv) {
279 port = to_dev_port(uport);
280 baud = port->baud;
281 if (!baud)
282 baud = 115200;
283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
284 /*
285 * Total polling iterations based on FIFO worth of bytes to be
286 * sent at current baud. Add a little fluff to the wait.
287 */
288 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
289 }
290
291 /*
292 * Use custom implementation instead of readl_poll_atomic since ktimer
293 * is not ready at the time of early console.
294 */
295 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
296 while (timeout_us) {
297 reg = readl(uport->membase + offset);
298 if ((bool)(reg & field) == set)
299 return true;
300 udelay(10);
301 timeout_us -= 10;
302 }
303 return false;
304}
305
306static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
307{
308 u32 m_cmd;
309
310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
311 m_cmd = UART_START_TX << M_OPCODE_SHFT;
312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
313}
314
315static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
316{
317 int done;
318 u32 irq_clear = M_CMD_DONE_EN;
319
320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
321 M_CMD_DONE_EN, true);
322 if (!done) {
323 writel(M_GENI_CMD_ABORT, uport->membase +
324 SE_GENI_M_CMD_CTRL_REG);
325 irq_clear |= M_CMD_ABORT_EN;
326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
327 M_CMD_ABORT_EN, true);
328 }
329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
330}
331
332static void qcom_geni_serial_abort_rx(struct uart_port *uport)
333{
334 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
335
336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
338 S_GENI_CMD_ABORT, false);
339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
341}
342
343#ifdef CONFIG_CONSOLE_POLL
344static int qcom_geni_serial_get_char(struct uart_port *uport)
345{
346 struct qcom_geni_private_data *private_data = uport->private_data;
347 u32 status;
348 u32 word_cnt;
349 int ret;
350
351 if (!private_data->poll_cached_bytes_cnt) {
352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
354
355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
357
358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
359 word_cnt = status & RX_FIFO_WC_MSK;
360 if (!word_cnt)
361 return NO_POLL_CHAR;
362
363 if (word_cnt == 1 && (status & RX_LAST))
364 /*
365 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
366 * treated as if it was BYTES_PER_FIFO_WORD.
367 */
368 private_data->poll_cached_bytes_cnt =
369 (status & RX_LAST_BYTE_VALID_MSK) >>
370 RX_LAST_BYTE_VALID_SHFT;
371
372 if (private_data->poll_cached_bytes_cnt == 0)
373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
374
375 private_data->poll_cached_bytes =
376 readl(uport->membase + SE_GENI_RX_FIFOn);
377 }
378
379 private_data->poll_cached_bytes_cnt--;
380 ret = private_data->poll_cached_bytes & 0xff;
381 private_data->poll_cached_bytes >>= 8;
382
383 return ret;
384}
385
386static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
387 unsigned char c)
388{
389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
390 qcom_geni_serial_setup_tx(uport, 1);
391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
392 M_TX_FIFO_WATERMARK_EN, true));
393 writel(c, uport->membase + SE_GENI_TX_FIFOn);
394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
395 qcom_geni_serial_poll_tx_done(uport);
396}
397#endif
398
399#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
400static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
401{
402 struct qcom_geni_private_data *private_data = uport->private_data;
403
404 private_data->write_cached_bytes =
405 (private_data->write_cached_bytes >> 8) | (ch << 24);
406 private_data->write_cached_bytes_cnt++;
407
408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
409 writel(private_data->write_cached_bytes,
410 uport->membase + SE_GENI_TX_FIFOn);
411 private_data->write_cached_bytes_cnt = 0;
412 }
413}
414
415static void
416__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
417 unsigned int count)
418{
419 struct qcom_geni_private_data *private_data = uport->private_data;
420
421 int i;
422 u32 bytes_to_send = count;
423
424 for (i = 0; i < count; i++) {
425 /*
426 * uart_console_write() adds a carriage return for each newline.
427 * Account for additional bytes to be written.
428 */
429 if (s[i] == '\n')
430 bytes_to_send++;
431 }
432
433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
434 qcom_geni_serial_setup_tx(uport, bytes_to_send);
435 for (i = 0; i < count; ) {
436 size_t chars_to_write = 0;
437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
438
439 /*
440 * If the WM bit never set, then the Tx state machine is not
441 * in a valid state, so break, cancel/abort any existing
442 * command. Unfortunately the current data being written is
443 * lost.
444 */
445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
446 M_TX_FIFO_WATERMARK_EN, true))
447 break;
448 chars_to_write = min_t(size_t, count - i, avail / 2);
449 uart_console_write(uport, s + i, chars_to_write,
450 qcom_geni_serial_wr_char);
451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
452 SE_GENI_M_IRQ_CLEAR);
453 i += chars_to_write;
454 }
455
456 if (private_data->write_cached_bytes_cnt) {
457 private_data->write_cached_bytes >>= BITS_PER_BYTE *
458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
459 writel(private_data->write_cached_bytes,
460 uport->membase + SE_GENI_TX_FIFOn);
461 private_data->write_cached_bytes_cnt = 0;
462 }
463
464 qcom_geni_serial_poll_tx_done(uport);
465}
466
467static void qcom_geni_serial_console_write(struct console *co, const char *s,
468 unsigned int count)
469{
470 struct uart_port *uport;
471 struct qcom_geni_serial_port *port;
472 bool locked = true;
473 unsigned long flags;
474 u32 geni_status;
475 u32 irq_en;
476
477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
478
479 port = get_port_from_line(co->index, true);
480 if (IS_ERR(port))
481 return;
482
483 uport = &port->uport;
484 if (oops_in_progress)
485 locked = uart_port_trylock_irqsave(uport, &flags);
486 else
487 uart_port_lock_irqsave(uport, &flags);
488
489 geni_status = readl(uport->membase + SE_GENI_STATUS);
490
491 /* Cancel the current write to log the fault */
492 if (!locked) {
493 geni_se_cancel_m_cmd(&port->se);
494 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
495 M_CMD_CANCEL_EN, true)) {
496 geni_se_abort_m_cmd(&port->se);
497 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
498 M_CMD_ABORT_EN, true);
499 writel(M_CMD_ABORT_EN, uport->membase +
500 SE_GENI_M_IRQ_CLEAR);
501 }
502 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
503 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
504 /*
505 * It seems we can't interrupt existing transfers if all data
506 * has been sent, in which case we need to look for done first.
507 */
508 qcom_geni_serial_poll_tx_done(uport);
509
510 if (!uart_circ_empty(&uport->state->xmit)) {
511 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
512 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
513 uport->membase + SE_GENI_M_IRQ_EN);
514 }
515 }
516
517 __qcom_geni_serial_console_write(uport, s, count);
518
519 if (port->tx_remaining)
520 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
521
522 if (locked)
523 uart_port_unlock_irqrestore(uport, flags);
524}
525
526static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
527{
528 u32 i;
529 unsigned char buf[sizeof(u32)];
530 struct tty_port *tport;
531 struct qcom_geni_serial_port *port = to_dev_port(uport);
532
533 tport = &uport->state->port;
534 for (i = 0; i < bytes; ) {
535 int c;
536 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
537
538 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
539 i += chunk;
540 if (drop)
541 continue;
542
543 for (c = 0; c < chunk; c++) {
544 int sysrq;
545
546 uport->icount.rx++;
547 if (port->brk && buf[c] == 0) {
548 port->brk = false;
549 if (uart_handle_break(uport))
550 continue;
551 }
552
553 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
554
555 if (!sysrq)
556 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
557 }
558 }
559 if (!drop)
560 tty_flip_buffer_push(tport);
561}
562#else
563static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
564{
565
566}
567#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
568
569static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
570{
571 struct qcom_geni_serial_port *port = to_dev_port(uport);
572 struct tty_port *tport = &uport->state->port;
573 int ret;
574
575 ret = tty_insert_flip_string(tport, port->rx_buf, bytes);
576 if (ret != bytes) {
577 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
578 __func__, ret, bytes);
579 WARN_ON_ONCE(1);
580 }
581 uport->icount.rx += ret;
582 tty_flip_buffer_push(tport);
583}
584
585static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
586{
587 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
588}
589
590static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport)
591{
592 struct qcom_geni_serial_port *port = to_dev_port(uport);
593 bool done;
594
595 if (!qcom_geni_serial_main_active(uport))
596 return;
597
598 if (port->tx_dma_addr) {
599 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr,
600 port->tx_remaining);
601 port->tx_dma_addr = 0;
602 port->tx_remaining = 0;
603 }
604
605 geni_se_cancel_m_cmd(&port->se);
606
607 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
608 M_CMD_CANCEL_EN, true);
609 if (!done) {
610 geni_se_abort_m_cmd(&port->se);
611 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
612 M_CMD_ABORT_EN, true);
613 if (!done)
614 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set");
615 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
616 }
617
618 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
619}
620
621static void qcom_geni_serial_start_tx_dma(struct uart_port *uport)
622{
623 struct qcom_geni_serial_port *port = to_dev_port(uport);
624 struct circ_buf *xmit = &uport->state->xmit;
625 unsigned int xmit_size;
626 int ret;
627
628 if (port->tx_dma_addr)
629 return;
630
631 if (uart_circ_empty(xmit))
632 return;
633
634 xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
635
636 qcom_geni_serial_setup_tx(uport, xmit_size);
637
638 ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail],
639 xmit_size, &port->tx_dma_addr);
640 if (ret) {
641 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret);
642 qcom_geni_serial_stop_tx_dma(uport);
643 return;
644 }
645
646 port->tx_remaining = xmit_size;
647}
648
649static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport)
650{
651 u32 irq_en;
652
653 if (qcom_geni_serial_main_active(uport) ||
654 !qcom_geni_serial_tx_empty(uport))
655 return;
656
657 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
658 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
659
660 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
661 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
662}
663
664static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport)
665{
666 u32 irq_en;
667 struct qcom_geni_serial_port *port = to_dev_port(uport);
668
669 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
670 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
671 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
672 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
673 /* Possible stop tx is called multiple times. */
674 if (!qcom_geni_serial_main_active(uport))
675 return;
676
677 geni_se_cancel_m_cmd(&port->se);
678 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
679 M_CMD_CANCEL_EN, true)) {
680 geni_se_abort_m_cmd(&port->se);
681 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
682 M_CMD_ABORT_EN, true);
683 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
684 }
685 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
686}
687
688static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop)
689{
690 u32 status;
691 u32 word_cnt;
692 u32 last_word_byte_cnt;
693 u32 last_word_partial;
694 u32 total_bytes;
695
696 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
697 word_cnt = status & RX_FIFO_WC_MSK;
698 last_word_partial = status & RX_LAST;
699 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
700 RX_LAST_BYTE_VALID_SHFT;
701
702 if (!word_cnt)
703 return;
704 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
705 if (last_word_partial && last_word_byte_cnt)
706 total_bytes += last_word_byte_cnt;
707 else
708 total_bytes += BYTES_PER_FIFO_WORD;
709 handle_rx_console(uport, total_bytes, drop);
710}
711
712static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport)
713{
714 u32 irq_en;
715 struct qcom_geni_serial_port *port = to_dev_port(uport);
716 u32 s_irq_status;
717
718 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
719 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
720 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
721
722 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
723 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
724 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
725
726 if (!qcom_geni_serial_secondary_active(uport))
727 return;
728
729 geni_se_cancel_s_cmd(&port->se);
730 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
731 S_CMD_CANCEL_EN, true);
732 /*
733 * If timeout occurs secondary engine remains active
734 * and Abort sequence is executed.
735 */
736 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
737 /* Flush the Rx buffer */
738 if (s_irq_status & S_RX_FIFO_LAST_EN)
739 qcom_geni_serial_handle_rx_fifo(uport, true);
740 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
741
742 if (qcom_geni_serial_secondary_active(uport))
743 qcom_geni_serial_abort_rx(uport);
744}
745
746static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport)
747{
748 u32 irq_en;
749 struct qcom_geni_serial_port *port = to_dev_port(uport);
750
751 if (qcom_geni_serial_secondary_active(uport))
752 qcom_geni_serial_stop_rx_fifo(uport);
753
754 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
755
756 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
757 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
758 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
759
760 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
761 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
762 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
763}
764
765static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport)
766{
767 struct qcom_geni_serial_port *port = to_dev_port(uport);
768
769 if (!qcom_geni_serial_secondary_active(uport))
770 return;
771
772 geni_se_cancel_s_cmd(&port->se);
773 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
774 S_CMD_CANCEL_EN, true);
775
776 if (qcom_geni_serial_secondary_active(uport))
777 qcom_geni_serial_abort_rx(uport);
778
779 if (port->rx_dma_addr) {
780 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr,
781 DMA_RX_BUF_SIZE);
782 port->rx_dma_addr = 0;
783 }
784}
785
786static void qcom_geni_serial_start_rx_dma(struct uart_port *uport)
787{
788 struct qcom_geni_serial_port *port = to_dev_port(uport);
789 int ret;
790
791 if (qcom_geni_serial_secondary_active(uport))
792 qcom_geni_serial_stop_rx_dma(uport);
793
794 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN);
795
796 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,
797 DMA_RX_BUF_SIZE,
798 &port->rx_dma_addr);
799 if (ret) {
800 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);
801 qcom_geni_serial_stop_rx_dma(uport);
802 }
803}
804
805static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop)
806{
807 struct qcom_geni_serial_port *port = to_dev_port(uport);
808 u32 rx_in;
809 int ret;
810
811 if (!qcom_geni_serial_secondary_active(uport))
812 return;
813
814 if (!port->rx_dma_addr)
815 return;
816
817 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE);
818 port->rx_dma_addr = 0;
819
820 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN);
821 if (!rx_in) {
822 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n");
823 return;
824 }
825
826 if (!drop)
827 handle_rx_uart(uport, rx_in, drop);
828
829 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,
830 DMA_RX_BUF_SIZE,
831 &port->rx_dma_addr);
832 if (ret) {
833 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);
834 qcom_geni_serial_stop_rx_dma(uport);
835 }
836}
837
838static void qcom_geni_serial_start_rx(struct uart_port *uport)
839{
840 uport->ops->start_rx(uport);
841}
842
843static void qcom_geni_serial_stop_rx(struct uart_port *uport)
844{
845 uport->ops->stop_rx(uport);
846}
847
848static void qcom_geni_serial_stop_tx(struct uart_port *uport)
849{
850 uport->ops->stop_tx(uport);
851}
852
853static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport,
854 unsigned int chunk)
855{
856 struct qcom_geni_serial_port *port = to_dev_port(uport);
857 struct circ_buf *xmit = &uport->state->xmit;
858 unsigned int tx_bytes, c, remaining = chunk;
859 u8 buf[BYTES_PER_FIFO_WORD];
860
861 while (remaining) {
862 memset(buf, 0, sizeof(buf));
863 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD);
864
865 for (c = 0; c < tx_bytes ; c++) {
866 buf[c] = xmit->buf[xmit->tail];
867 uart_xmit_advance(uport, 1);
868 }
869
870 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
871
872 remaining -= tx_bytes;
873 port->tx_remaining -= tx_bytes;
874 }
875}
876
877static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport,
878 bool done, bool active)
879{
880 struct qcom_geni_serial_port *port = to_dev_port(uport);
881 struct circ_buf *xmit = &uport->state->xmit;
882 size_t avail;
883 size_t pending;
884 u32 status;
885 u32 irq_en;
886 unsigned int chunk;
887
888 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
889
890 /* Complete the current tx command before taking newly added data */
891 if (active)
892 pending = port->tx_remaining;
893 else
894 pending = uart_circ_chars_pending(xmit);
895
896 /* All data has been transmitted and acknowledged as received */
897 if (!pending && !status && done) {
898 qcom_geni_serial_stop_tx_fifo(uport);
899 goto out_write_wakeup;
900 }
901
902 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
903 avail *= BYTES_PER_FIFO_WORD;
904
905 chunk = min(avail, pending);
906 if (!chunk)
907 goto out_write_wakeup;
908
909 if (!port->tx_remaining) {
910 qcom_geni_serial_setup_tx(uport, pending);
911 port->tx_remaining = pending;
912
913 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
914 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
915 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
916 uport->membase + SE_GENI_M_IRQ_EN);
917 }
918
919 qcom_geni_serial_send_chunk_fifo(uport, chunk);
920
921 /*
922 * The tx fifo watermark is level triggered and latched. Though we had
923 * cleared it in qcom_geni_serial_isr it will have already reasserted
924 * so we must clear it again here after our writes.
925 */
926 writel(M_TX_FIFO_WATERMARK_EN,
927 uport->membase + SE_GENI_M_IRQ_CLEAR);
928
929out_write_wakeup:
930 if (!port->tx_remaining) {
931 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
932 if (irq_en & M_TX_FIFO_WATERMARK_EN)
933 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
934 uport->membase + SE_GENI_M_IRQ_EN);
935 }
936
937 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
938 uart_write_wakeup(uport);
939}
940
941static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport)
942{
943 struct qcom_geni_serial_port *port = to_dev_port(uport);
944 struct circ_buf *xmit = &uport->state->xmit;
945
946 uart_xmit_advance(uport, port->tx_remaining);
947 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining);
948 port->tx_dma_addr = 0;
949 port->tx_remaining = 0;
950
951 if (!uart_circ_empty(xmit))
952 qcom_geni_serial_start_tx_dma(uport);
953
954 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
955 uart_write_wakeup(uport);
956}
957
958static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
959{
960 u32 m_irq_en;
961 u32 m_irq_status;
962 u32 s_irq_status;
963 u32 geni_status;
964 u32 dma;
965 u32 dma_tx_status;
966 u32 dma_rx_status;
967 struct uart_port *uport = dev;
968 bool drop_rx = false;
969 struct tty_port *tport = &uport->state->port;
970 struct qcom_geni_serial_port *port = to_dev_port(uport);
971
972 if (uport->suspended)
973 return IRQ_NONE;
974
975 uart_port_lock(uport);
976
977 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
978 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
979 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT);
980 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT);
981 geni_status = readl(uport->membase + SE_GENI_STATUS);
982 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN);
983 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
984 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
985 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
986 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR);
987 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR);
988
989 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
990 goto out_unlock;
991
992 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
993 uport->icount.overrun++;
994 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
995 }
996
997 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) {
998 if (s_irq_status & S_GP_IRQ_0_EN)
999 uport->icount.parity++;
1000 drop_rx = true;
1001 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) {
1002 uport->icount.brk++;
1003 port->brk = true;
1004 }
1005
1006 if (dma) {
1007 if (dma_tx_status & TX_DMA_DONE)
1008 qcom_geni_serial_handle_tx_dma(uport);
1009
1010 if (dma_rx_status) {
1011 if (dma_rx_status & RX_RESET_DONE)
1012 goto out_unlock;
1013
1014 if (dma_rx_status & RX_DMA_PARITY_ERR) {
1015 uport->icount.parity++;
1016 drop_rx = true;
1017 }
1018
1019 if (dma_rx_status & RX_DMA_BREAK)
1020 uport->icount.brk++;
1021
1022 if (dma_rx_status & (RX_DMA_DONE | RX_EOT))
1023 qcom_geni_serial_handle_rx_dma(uport, drop_rx);
1024 }
1025 } else {
1026 if (m_irq_status & m_irq_en &
1027 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
1028 qcom_geni_serial_handle_tx_fifo(uport,
1029 m_irq_status & M_CMD_DONE_EN,
1030 geni_status & M_GENI_CMD_ACTIVE);
1031
1032 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN))
1033 qcom_geni_serial_handle_rx_fifo(uport, drop_rx);
1034 }
1035
1036out_unlock:
1037 uart_unlock_and_check_sysrq(uport);
1038
1039 return IRQ_HANDLED;
1040}
1041
1042static int setup_fifos(struct qcom_geni_serial_port *port)
1043{
1044 struct uart_port *uport;
1045 u32 old_rx_fifo_depth = port->rx_fifo_depth;
1046
1047 uport = &port->uport;
1048 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
1049 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
1050 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
1051 uport->fifosize =
1052 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
1053
1054 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) {
1055 /*
1056 * Use krealloc rather than krealloc_array because rx_buf is
1057 * accessed as 1 byte entries as well as 4 byte entries so it's
1058 * not necessarily an array.
1059 */
1060 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf,
1061 port->rx_fifo_depth * sizeof(u32),
1062 GFP_KERNEL);
1063 if (!port->rx_buf)
1064 return -ENOMEM;
1065 }
1066
1067 return 0;
1068}
1069
1070
1071static void qcom_geni_serial_shutdown(struct uart_port *uport)
1072{
1073 disable_irq(uport->irq);
1074
1075 if (uart_console(uport))
1076 return;
1077
1078 qcom_geni_serial_stop_tx(uport);
1079 qcom_geni_serial_stop_rx(uport);
1080}
1081
1082static int qcom_geni_serial_port_setup(struct uart_port *uport)
1083{
1084 struct qcom_geni_serial_port *port = to_dev_port(uport);
1085 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
1086 u32 proto;
1087 u32 pin_swap;
1088 int ret;
1089
1090 proto = geni_se_read_proto(&port->se);
1091 if (proto != GENI_SE_UART) {
1092 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
1093 return -ENXIO;
1094 }
1095
1096 qcom_geni_serial_stop_rx(uport);
1097
1098 ret = setup_fifos(port);
1099 if (ret)
1100 return ret;
1101
1102 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
1103
1104 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
1105 if (port->rx_tx_swap) {
1106 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
1107 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
1108 }
1109 if (port->cts_rts_swap) {
1110 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
1111 pin_swap |= IO_MACRO_IO0_SEL;
1112 }
1113 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
1114 if (port->rx_tx_swap || port->cts_rts_swap)
1115 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
1116
1117 /*
1118 * Make an unconditional cancel on the main sequencer to reset
1119 * it else we could end up in data loss scenarios.
1120 */
1121 if (uart_console(uport))
1122 qcom_geni_serial_poll_tx_done(uport);
1123 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1124 false, true, true);
1125 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
1126 geni_se_select_mode(&port->se, port->dev_data->mode);
1127 qcom_geni_serial_start_rx(uport);
1128 port->setup = true;
1129
1130 return 0;
1131}
1132
1133static int qcom_geni_serial_startup(struct uart_port *uport)
1134{
1135 int ret;
1136 struct qcom_geni_serial_port *port = to_dev_port(uport);
1137
1138 if (!port->setup) {
1139 ret = qcom_geni_serial_port_setup(uport);
1140 if (ret)
1141 return ret;
1142 }
1143 enable_irq(uport->irq);
1144
1145 return 0;
1146}
1147
1148static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
1149 unsigned int *clk_div, unsigned int percent_tol)
1150{
1151 unsigned long freq;
1152 unsigned long div, maxdiv;
1153 u64 mult;
1154 unsigned long offset, abs_tol, achieved;
1155
1156 abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
1157 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
1158 div = 1;
1159 while (div <= maxdiv) {
1160 mult = (u64)div * desired_clk;
1161 if (mult != (unsigned long)mult)
1162 break;
1163
1164 offset = div * abs_tol;
1165 freq = clk_round_rate(clk, mult - offset);
1166
1167 /* Can only get lower if we're done */
1168 if (freq < mult - offset)
1169 break;
1170
1171 /*
1172 * Re-calculate div in case rounding skipped rates but we
1173 * ended up at a good one, then check for a match.
1174 */
1175 div = DIV_ROUND_CLOSEST(freq, desired_clk);
1176 achieved = DIV_ROUND_CLOSEST(freq, div);
1177 if (achieved <= desired_clk + abs_tol &&
1178 achieved >= desired_clk - abs_tol) {
1179 *clk_div = div;
1180 return freq;
1181 }
1182
1183 div = DIV_ROUND_UP(freq, desired_clk);
1184 }
1185
1186 return 0;
1187}
1188
1189static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
1190 unsigned int sampling_rate, unsigned int *clk_div)
1191{
1192 unsigned long ser_clk;
1193 unsigned long desired_clk;
1194
1195 desired_clk = baud * sampling_rate;
1196 if (!desired_clk)
1197 return 0;
1198
1199 /*
1200 * try to find a clock rate within 2% tolerance, then within 5%
1201 */
1202 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2);
1203 if (!ser_clk)
1204 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5);
1205
1206 return ser_clk;
1207}
1208
1209static void qcom_geni_serial_set_termios(struct uart_port *uport,
1210 struct ktermios *termios,
1211 const struct ktermios *old)
1212{
1213 unsigned int baud;
1214 u32 bits_per_char;
1215 u32 tx_trans_cfg;
1216 u32 tx_parity_cfg;
1217 u32 rx_trans_cfg;
1218 u32 rx_parity_cfg;
1219 u32 stop_bit_len;
1220 unsigned int clk_div;
1221 u32 ser_clk_cfg;
1222 struct qcom_geni_serial_port *port = to_dev_port(uport);
1223 unsigned long clk_rate;
1224 u32 ver, sampling_rate;
1225 unsigned int avg_bw_core;
1226
1227 qcom_geni_serial_stop_rx(uport);
1228 /* baud rate */
1229 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1230 port->baud = baud;
1231
1232 sampling_rate = UART_OVERSAMPLING;
1233 /* Sampling rate is halved for IP versions >= 2.5 */
1234 ver = geni_se_get_qup_hw_version(&port->se);
1235 if (ver >= QUP_SE_VERSION_2_5)
1236 sampling_rate /= 2;
1237
1238 clk_rate = get_clk_div_rate(port->se.clk, baud,
1239 sampling_rate, &clk_div);
1240 if (!clk_rate) {
1241 dev_err(port->se.dev,
1242 "Couldn't find suitable clock rate for %u\n",
1243 baud * sampling_rate);
1244 goto out_restart_rx;
1245 }
1246
1247 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",
1248 baud * sampling_rate, clk_rate, clk_div);
1249
1250 uport->uartclk = clk_rate;
1251 port->clk_rate = clk_rate;
1252 dev_pm_opp_set_rate(uport->dev, clk_rate);
1253 ser_clk_cfg = SER_CLK_EN;
1254 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1255
1256 /*
1257 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1258 * only.
1259 */
1260 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1261 : GENI_DEFAULT_BW;
1262 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1263 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1264 geni_icc_set_bw(&port->se);
1265
1266 /* parity */
1267 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1268 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1269 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1270 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1271 if (termios->c_cflag & PARENB) {
1272 tx_trans_cfg |= UART_TX_PAR_EN;
1273 rx_trans_cfg |= UART_RX_PAR_EN;
1274 tx_parity_cfg |= PAR_CALC_EN;
1275 rx_parity_cfg |= PAR_CALC_EN;
1276 if (termios->c_cflag & PARODD) {
1277 tx_parity_cfg |= PAR_ODD;
1278 rx_parity_cfg |= PAR_ODD;
1279 } else if (termios->c_cflag & CMSPAR) {
1280 tx_parity_cfg |= PAR_SPACE;
1281 rx_parity_cfg |= PAR_SPACE;
1282 } else {
1283 tx_parity_cfg |= PAR_EVEN;
1284 rx_parity_cfg |= PAR_EVEN;
1285 }
1286 } else {
1287 tx_trans_cfg &= ~UART_TX_PAR_EN;
1288 rx_trans_cfg &= ~UART_RX_PAR_EN;
1289 tx_parity_cfg &= ~PAR_CALC_EN;
1290 rx_parity_cfg &= ~PAR_CALC_EN;
1291 }
1292
1293 /* bits per char */
1294 bits_per_char = tty_get_char_size(termios->c_cflag);
1295
1296 /* stop bits */
1297 if (termios->c_cflag & CSTOPB)
1298 stop_bit_len = TX_STOP_BIT_LEN_2;
1299 else
1300 stop_bit_len = TX_STOP_BIT_LEN_1;
1301
1302 /* flow control, clear the CTS_MASK bit if using flow control. */
1303 if (termios->c_cflag & CRTSCTS)
1304 tx_trans_cfg &= ~UART_CTS_MASK;
1305 else
1306 tx_trans_cfg |= UART_CTS_MASK;
1307
1308 if (baud)
1309 uart_update_timeout(uport, termios->c_cflag, baud);
1310
1311 if (!uart_console(uport))
1312 writel(port->loopback,
1313 uport->membase + SE_UART_LOOPBACK_CFG);
1314 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1315 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1316 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1317 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1318 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1319 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1320 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1321 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1322 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1323out_restart_rx:
1324 qcom_geni_serial_start_rx(uport);
1325}
1326
1327#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1328static int qcom_geni_console_setup(struct console *co, char *options)
1329{
1330 struct uart_port *uport;
1331 struct qcom_geni_serial_port *port;
1332 int baud = 115200;
1333 int bits = 8;
1334 int parity = 'n';
1335 int flow = 'n';
1336 int ret;
1337
1338 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1339 return -ENXIO;
1340
1341 port = get_port_from_line(co->index, true);
1342 if (IS_ERR(port)) {
1343 pr_err("Invalid line %d\n", co->index);
1344 return PTR_ERR(port);
1345 }
1346
1347 uport = &port->uport;
1348
1349 if (unlikely(!uport->membase))
1350 return -ENXIO;
1351
1352 if (!port->setup) {
1353 ret = qcom_geni_serial_port_setup(uport);
1354 if (ret)
1355 return ret;
1356 }
1357
1358 if (options)
1359 uart_parse_options(options, &baud, &parity, &bits, &flow);
1360
1361 return uart_set_options(uport, co, baud, parity, bits, flow);
1362}
1363
1364static void qcom_geni_serial_earlycon_write(struct console *con,
1365 const char *s, unsigned int n)
1366{
1367 struct earlycon_device *dev = con->data;
1368
1369 __qcom_geni_serial_console_write(&dev->port, s, n);
1370}
1371
1372#ifdef CONFIG_CONSOLE_POLL
1373static int qcom_geni_serial_earlycon_read(struct console *con,
1374 char *s, unsigned int n)
1375{
1376 struct earlycon_device *dev = con->data;
1377 struct uart_port *uport = &dev->port;
1378 int num_read = 0;
1379 int ch;
1380
1381 while (num_read < n) {
1382 ch = qcom_geni_serial_get_char(uport);
1383 if (ch == NO_POLL_CHAR)
1384 break;
1385 s[num_read++] = ch;
1386 }
1387
1388 return num_read;
1389}
1390
1391static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1392 struct console *con)
1393{
1394 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1395 con->read = qcom_geni_serial_earlycon_read;
1396}
1397#else
1398static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1399 struct console *con) { }
1400#endif
1401
1402static struct qcom_geni_private_data earlycon_private_data;
1403
1404static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1405 const char *opt)
1406{
1407 struct uart_port *uport = &dev->port;
1408 u32 tx_trans_cfg;
1409 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1410 u32 rx_trans_cfg = 0;
1411 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1412 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1413 u32 bits_per_char;
1414 struct geni_se se;
1415
1416 if (!uport->membase)
1417 return -EINVAL;
1418
1419 uport->private_data = &earlycon_private_data;
1420
1421 memset(&se, 0, sizeof(se));
1422 se.base = uport->membase;
1423 if (geni_se_read_proto(&se) != GENI_SE_UART)
1424 return -ENXIO;
1425 /*
1426 * Ignore Flow control.
1427 * n = 8.
1428 */
1429 tx_trans_cfg = UART_CTS_MASK;
1430 bits_per_char = BITS_PER_BYTE;
1431
1432 /*
1433 * Make an unconditional cancel on the main sequencer to reset
1434 * it else we could end up in data loss scenarios.
1435 */
1436 qcom_geni_serial_poll_tx_done(uport);
1437 qcom_geni_serial_abort_rx(uport);
1438 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1439 false, true, true);
1440 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1441 geni_se_select_mode(&se, GENI_SE_FIFO);
1442
1443 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1444 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1445 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1446 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1447 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1448 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1449 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1450
1451 dev->con->write = qcom_geni_serial_earlycon_write;
1452 dev->con->setup = NULL;
1453 qcom_geni_serial_enable_early_read(&se, dev->con);
1454
1455 return 0;
1456}
1457OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1458 qcom_geni_serial_earlycon_setup);
1459
1460static int __init console_register(struct uart_driver *drv)
1461{
1462 return uart_register_driver(drv);
1463}
1464
1465static void console_unregister(struct uart_driver *drv)
1466{
1467 uart_unregister_driver(drv);
1468}
1469
1470static struct console cons_ops = {
1471 .name = "ttyMSM",
1472 .write = qcom_geni_serial_console_write,
1473 .device = uart_console_device,
1474 .setup = qcom_geni_console_setup,
1475 .flags = CON_PRINTBUFFER,
1476 .index = -1,
1477 .data = &qcom_geni_console_driver,
1478};
1479
1480static struct uart_driver qcom_geni_console_driver = {
1481 .owner = THIS_MODULE,
1482 .driver_name = "qcom_geni_console",
1483 .dev_name = "ttyMSM",
1484 .nr = GENI_UART_CONS_PORTS,
1485 .cons = &cons_ops,
1486};
1487#else
1488static int console_register(struct uart_driver *drv)
1489{
1490 return 0;
1491}
1492
1493static void console_unregister(struct uart_driver *drv)
1494{
1495}
1496#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1497
1498static struct uart_driver qcom_geni_uart_driver = {
1499 .owner = THIS_MODULE,
1500 .driver_name = "qcom_geni_uart",
1501 .dev_name = "ttyHS",
1502 .nr = GENI_UART_PORTS,
1503};
1504
1505static void qcom_geni_serial_pm(struct uart_port *uport,
1506 unsigned int new_state, unsigned int old_state)
1507{
1508 struct qcom_geni_serial_port *port = to_dev_port(uport);
1509
1510 /* If we've never been called, treat it as off */
1511 if (old_state == UART_PM_STATE_UNDEFINED)
1512 old_state = UART_PM_STATE_OFF;
1513
1514 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1515 geni_icc_enable(&port->se);
1516 if (port->clk_rate)
1517 dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1518 geni_se_resources_on(&port->se);
1519 } else if (new_state == UART_PM_STATE_OFF &&
1520 old_state == UART_PM_STATE_ON) {
1521 geni_se_resources_off(&port->se);
1522 dev_pm_opp_set_rate(uport->dev, 0);
1523 geni_icc_disable(&port->se);
1524 }
1525}
1526
1527static const struct uart_ops qcom_geni_console_pops = {
1528 .tx_empty = qcom_geni_serial_tx_empty,
1529 .stop_tx = qcom_geni_serial_stop_tx_fifo,
1530 .start_tx = qcom_geni_serial_start_tx_fifo,
1531 .stop_rx = qcom_geni_serial_stop_rx_fifo,
1532 .start_rx = qcom_geni_serial_start_rx_fifo,
1533 .set_termios = qcom_geni_serial_set_termios,
1534 .startup = qcom_geni_serial_startup,
1535 .request_port = qcom_geni_serial_request_port,
1536 .config_port = qcom_geni_serial_config_port,
1537 .shutdown = qcom_geni_serial_shutdown,
1538 .type = qcom_geni_serial_get_type,
1539 .set_mctrl = qcom_geni_serial_set_mctrl,
1540 .get_mctrl = qcom_geni_serial_get_mctrl,
1541#ifdef CONFIG_CONSOLE_POLL
1542 .poll_get_char = qcom_geni_serial_get_char,
1543 .poll_put_char = qcom_geni_serial_poll_put_char,
1544 .poll_init = qcom_geni_serial_port_setup,
1545#endif
1546 .pm = qcom_geni_serial_pm,
1547};
1548
1549static const struct uart_ops qcom_geni_uart_pops = {
1550 .tx_empty = qcom_geni_serial_tx_empty,
1551 .stop_tx = qcom_geni_serial_stop_tx_dma,
1552 .start_tx = qcom_geni_serial_start_tx_dma,
1553 .start_rx = qcom_geni_serial_start_rx_dma,
1554 .stop_rx = qcom_geni_serial_stop_rx_dma,
1555 .set_termios = qcom_geni_serial_set_termios,
1556 .startup = qcom_geni_serial_startup,
1557 .request_port = qcom_geni_serial_request_port,
1558 .config_port = qcom_geni_serial_config_port,
1559 .shutdown = qcom_geni_serial_shutdown,
1560 .type = qcom_geni_serial_get_type,
1561 .set_mctrl = qcom_geni_serial_set_mctrl,
1562 .get_mctrl = qcom_geni_serial_get_mctrl,
1563 .pm = qcom_geni_serial_pm,
1564};
1565
1566static int qcom_geni_serial_probe(struct platform_device *pdev)
1567{
1568 int ret = 0;
1569 int line;
1570 struct qcom_geni_serial_port *port;
1571 struct uart_port *uport;
1572 struct resource *res;
1573 int irq;
1574 struct uart_driver *drv;
1575 const struct qcom_geni_device_data *data;
1576
1577 data = of_device_get_match_data(&pdev->dev);
1578 if (!data)
1579 return -EINVAL;
1580
1581 if (data->console) {
1582 drv = &qcom_geni_console_driver;
1583 line = of_alias_get_id(pdev->dev.of_node, "serial");
1584 } else {
1585 drv = &qcom_geni_uart_driver;
1586 line = of_alias_get_id(pdev->dev.of_node, "serial");
1587 if (line == -ENODEV) /* compat with non-standard aliases */
1588 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1589 }
1590
1591 port = get_port_from_line(line, data->console);
1592 if (IS_ERR(port)) {
1593 dev_err(&pdev->dev, "Invalid line %d\n", line);
1594 return PTR_ERR(port);
1595 }
1596
1597 uport = &port->uport;
1598 /* Don't allow 2 drivers to access the same port */
1599 if (uport->private_data)
1600 return -ENODEV;
1601
1602 uport->dev = &pdev->dev;
1603 port->dev_data = data;
1604 port->se.dev = &pdev->dev;
1605 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1606 port->se.clk = devm_clk_get(&pdev->dev, "se");
1607 if (IS_ERR(port->se.clk)) {
1608 ret = PTR_ERR(port->se.clk);
1609 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1610 return ret;
1611 }
1612
1613 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1614 if (!res)
1615 return -EINVAL;
1616 uport->mapbase = res->start;
1617
1618 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1619 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1620 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1621
1622 if (!data->console) {
1623 port->rx_buf = devm_kzalloc(uport->dev,
1624 DMA_RX_BUF_SIZE, GFP_KERNEL);
1625 if (!port->rx_buf)
1626 return -ENOMEM;
1627 }
1628
1629 ret = geni_icc_get(&port->se, NULL);
1630 if (ret)
1631 return ret;
1632 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1633 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1634
1635 /* Set BW for register access */
1636 ret = geni_icc_set_bw(&port->se);
1637 if (ret)
1638 return ret;
1639
1640 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1641 "qcom_geni_serial_%s%d",
1642 uart_console(uport) ? "console" : "uart", uport->line);
1643 if (!port->name)
1644 return -ENOMEM;
1645
1646 irq = platform_get_irq(pdev, 0);
1647 if (irq < 0)
1648 return irq;
1649 uport->irq = irq;
1650 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1651
1652 if (!data->console)
1653 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1654
1655 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1656 port->rx_tx_swap = true;
1657
1658 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1659 port->cts_rts_swap = true;
1660
1661 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1662 if (ret)
1663 return ret;
1664 /* OPP table is optional */
1665 ret = devm_pm_opp_of_add_table(&pdev->dev);
1666 if (ret && ret != -ENODEV) {
1667 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1668 return ret;
1669 }
1670
1671 port->private_data.drv = drv;
1672 uport->private_data = &port->private_data;
1673 platform_set_drvdata(pdev, port);
1674
1675 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1676 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1677 IRQF_TRIGGER_HIGH, port->name, uport);
1678 if (ret) {
1679 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1680 return ret;
1681 }
1682
1683 ret = uart_add_one_port(drv, uport);
1684 if (ret)
1685 return ret;
1686
1687 if (port->wakeup_irq > 0) {
1688 device_init_wakeup(&pdev->dev, true);
1689 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1690 port->wakeup_irq);
1691 if (ret) {
1692 device_init_wakeup(&pdev->dev, false);
1693 uart_remove_one_port(drv, uport);
1694 return ret;
1695 }
1696 }
1697
1698 return 0;
1699}
1700
1701static void qcom_geni_serial_remove(struct platform_device *pdev)
1702{
1703 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1704 struct uart_driver *drv = port->private_data.drv;
1705
1706 dev_pm_clear_wake_irq(&pdev->dev);
1707 device_init_wakeup(&pdev->dev, false);
1708 uart_remove_one_port(drv, &port->uport);
1709}
1710
1711static int qcom_geni_serial_sys_suspend(struct device *dev)
1712{
1713 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1714 struct uart_port *uport = &port->uport;
1715 struct qcom_geni_private_data *private_data = uport->private_data;
1716
1717 /*
1718 * This is done so we can hit the lowest possible state in suspend
1719 * even with no_console_suspend
1720 */
1721 if (uart_console(uport)) {
1722 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);
1723 geni_icc_set_bw(&port->se);
1724 }
1725 return uart_suspend_port(private_data->drv, uport);
1726}
1727
1728static int qcom_geni_serial_sys_resume(struct device *dev)
1729{
1730 int ret;
1731 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1732 struct uart_port *uport = &port->uport;
1733 struct qcom_geni_private_data *private_data = uport->private_data;
1734
1735 ret = uart_resume_port(private_data->drv, uport);
1736 if (uart_console(uport)) {
1737 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1738 geni_icc_set_bw(&port->se);
1739 }
1740 return ret;
1741}
1742
1743static int qcom_geni_serial_sys_hib_resume(struct device *dev)
1744{
1745 int ret = 0;
1746 struct uart_port *uport;
1747 struct qcom_geni_private_data *private_data;
1748 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1749
1750 uport = &port->uport;
1751 private_data = uport->private_data;
1752
1753 if (uart_console(uport)) {
1754 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1755 geni_icc_set_bw(&port->se);
1756 ret = uart_resume_port(private_data->drv, uport);
1757 /*
1758 * For hibernation usecase clients for
1759 * console UART won't call port setup during restore,
1760 * hence call port setup for console uart.
1761 */
1762 qcom_geni_serial_port_setup(uport);
1763 } else {
1764 /*
1765 * Peripheral register settings are lost during hibernation.
1766 * Update setup flag such that port setup happens again
1767 * during next session. Clients of HS-UART will close and
1768 * open the port during hibernation.
1769 */
1770 port->setup = false;
1771 }
1772 return ret;
1773}
1774
1775static const struct qcom_geni_device_data qcom_geni_console_data = {
1776 .console = true,
1777 .mode = GENI_SE_FIFO,
1778};
1779
1780static const struct qcom_geni_device_data qcom_geni_uart_data = {
1781 .console = false,
1782 .mode = GENI_SE_DMA,
1783};
1784
1785static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1786 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1787 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume),
1788 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1789 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1790 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume),
1791 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume),
1792};
1793
1794static const struct of_device_id qcom_geni_serial_match_table[] = {
1795 {
1796 .compatible = "qcom,geni-debug-uart",
1797 .data = &qcom_geni_console_data,
1798 },
1799 {
1800 .compatible = "qcom,geni-uart",
1801 .data = &qcom_geni_uart_data,
1802 },
1803 {}
1804};
1805MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1806
1807static struct platform_driver qcom_geni_serial_platform_driver = {
1808 .remove_new = qcom_geni_serial_remove,
1809 .probe = qcom_geni_serial_probe,
1810 .driver = {
1811 .name = "qcom_geni_serial",
1812 .of_match_table = qcom_geni_serial_match_table,
1813 .pm = &qcom_geni_serial_pm_ops,
1814 },
1815};
1816
1817static int __init qcom_geni_serial_init(void)
1818{
1819 int ret;
1820
1821 ret = console_register(&qcom_geni_console_driver);
1822 if (ret)
1823 return ret;
1824
1825 ret = uart_register_driver(&qcom_geni_uart_driver);
1826 if (ret) {
1827 console_unregister(&qcom_geni_console_driver);
1828 return ret;
1829 }
1830
1831 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1832 if (ret) {
1833 console_unregister(&qcom_geni_console_driver);
1834 uart_unregister_driver(&qcom_geni_uart_driver);
1835 }
1836 return ret;
1837}
1838module_init(qcom_geni_serial_init);
1839
1840static void __exit qcom_geni_serial_exit(void)
1841{
1842 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1843 console_unregister(&qcom_geni_console_driver);
1844 uart_unregister_driver(&qcom_geni_uart_driver);
1845}
1846module_exit(qcom_geni_serial_exit);
1847
1848MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1849MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#include <linux/clk.h>
5#include <linux/console.h>
6#include <linux/io.h>
7#include <linux/iopoll.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12#include <linux/qcom-geni-se.h>
13#include <linux/serial.h>
14#include <linux/serial_core.h>
15#include <linux/slab.h>
16#include <linux/tty.h>
17#include <linux/tty_flip.h>
18
19/* UART specific GENI registers */
20#define SE_UART_TX_TRANS_CFG 0x25c
21#define SE_UART_TX_WORD_LEN 0x268
22#define SE_UART_TX_STOP_BIT_LEN 0x26c
23#define SE_UART_TX_TRANS_LEN 0x270
24#define SE_UART_RX_TRANS_CFG 0x280
25#define SE_UART_RX_WORD_LEN 0x28c
26#define SE_UART_RX_STALE_CNT 0x294
27#define SE_UART_TX_PARITY_CFG 0x2a4
28#define SE_UART_RX_PARITY_CFG 0x2a8
29
30/* SE_UART_TRANS_CFG */
31#define UART_TX_PAR_EN BIT(0)
32#define UART_CTS_MASK BIT(1)
33
34/* SE_UART_TX_WORD_LEN */
35#define TX_WORD_LEN_MSK GENMASK(9, 0)
36
37/* SE_UART_TX_STOP_BIT_LEN */
38#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
39#define TX_STOP_BIT_LEN_1 0
40#define TX_STOP_BIT_LEN_1_5 1
41#define TX_STOP_BIT_LEN_2 2
42
43/* SE_UART_TX_TRANS_LEN */
44#define TX_TRANS_LEN_MSK GENMASK(23, 0)
45
46/* SE_UART_RX_TRANS_CFG */
47#define UART_RX_INS_STATUS_BIT BIT(2)
48#define UART_RX_PAR_EN BIT(3)
49
50/* SE_UART_RX_WORD_LEN */
51#define RX_WORD_LEN_MASK GENMASK(9, 0)
52
53/* SE_UART_RX_STALE_CNT */
54#define RX_STALE_CNT GENMASK(23, 0)
55
56/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
57#define PAR_CALC_EN BIT(0)
58#define PAR_MODE_MSK GENMASK(2, 1)
59#define PAR_MODE_SHFT 1
60#define PAR_EVEN 0x00
61#define PAR_ODD 0x01
62#define PAR_SPACE 0x10
63#define PAR_MARK 0x11
64
65/* UART M_CMD OP codes */
66#define UART_START_TX 0x1
67#define UART_START_BREAK 0x4
68#define UART_STOP_BREAK 0x5
69/* UART S_CMD OP codes */
70#define UART_START_READ 0x1
71#define UART_PARAM 0x1
72
73#define UART_OVERSAMPLING 32
74#define STALE_TIMEOUT 16
75#define DEFAULT_BITS_PER_CHAR 10
76#define GENI_UART_CONS_PORTS 1
77#define DEF_FIFO_DEPTH_WORDS 16
78#define DEF_TX_WM 2
79#define DEF_FIFO_WIDTH_BITS 32
80#define UART_CONSOLE_RX_WM 2
81
82#ifdef CONFIG_CONSOLE_POLL
83#define RX_BYTES_PW 1
84#else
85#define RX_BYTES_PW 4
86#endif
87
88struct qcom_geni_serial_port {
89 struct uart_port uport;
90 struct geni_se se;
91 char name[20];
92 u32 tx_fifo_depth;
93 u32 tx_fifo_width;
94 u32 rx_fifo_depth;
95 u32 tx_wm;
96 u32 rx_wm;
97 u32 rx_rfr;
98 enum geni_se_xfer_mode xfer_mode;
99 bool setup;
100 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
101 unsigned int xmit_size;
102 unsigned int baud;
103 unsigned int tx_bytes_pw;
104 unsigned int rx_bytes_pw;
105 bool brk;
106};
107
108static const struct uart_ops qcom_geni_serial_pops;
109static struct uart_driver qcom_geni_console_driver;
110static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
111static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
112static void qcom_geni_serial_stop_rx(struct uart_port *uport);
113
114static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
115 32000000, 48000000, 64000000, 80000000,
116 96000000, 100000000};
117
118#define to_dev_port(ptr, member) \
119 container_of(ptr, struct qcom_geni_serial_port, member)
120
121static struct qcom_geni_serial_port qcom_geni_console_port;
122
123static int qcom_geni_serial_request_port(struct uart_port *uport)
124{
125 struct platform_device *pdev = to_platform_device(uport->dev);
126 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
127 struct resource *res;
128
129 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130 uport->membase = devm_ioremap_resource(&pdev->dev, res);
131 if (IS_ERR(uport->membase))
132 return PTR_ERR(uport->membase);
133 port->se.base = uport->membase;
134 return 0;
135}
136
137static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
138{
139 if (cfg_flags & UART_CONFIG_TYPE) {
140 uport->type = PORT_MSM;
141 qcom_geni_serial_request_port(uport);
142 }
143}
144
145static unsigned int qcom_geni_cons_get_mctrl(struct uart_port *uport)
146{
147 return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
148}
149
150static void qcom_geni_cons_set_mctrl(struct uart_port *uport,
151 unsigned int mctrl)
152{
153}
154
155static const char *qcom_geni_serial_get_type(struct uart_port *uport)
156{
157 return "MSM";
158}
159
160static struct qcom_geni_serial_port *get_port_from_line(int line)
161{
162 if (line < 0 || line >= GENI_UART_CONS_PORTS)
163 return ERR_PTR(-ENXIO);
164 return &qcom_geni_console_port;
165}
166
167static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
168 int offset, int field, bool set)
169{
170 u32 reg;
171 struct qcom_geni_serial_port *port;
172 unsigned int baud;
173 unsigned int fifo_bits;
174 unsigned long timeout_us = 20000;
175
176 /* Ensure polling is not re-ordered before the prior writes/reads */
177 mb();
178
179 if (uport->private_data) {
180 port = to_dev_port(uport, uport);
181 baud = port->baud;
182 if (!baud)
183 baud = 115200;
184 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
185 /*
186 * Total polling iterations based on FIFO worth of bytes to be
187 * sent at current baud. Add a little fluff to the wait.
188 */
189 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
190 }
191
192 return !readl_poll_timeout_atomic(uport->membase + offset, reg,
193 (bool)(reg & field) == set, 10, timeout_us);
194}
195
196static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
197{
198 u32 m_cmd;
199
200 writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
201 m_cmd = UART_START_TX << M_OPCODE_SHFT;
202 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
203}
204
205static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
206{
207 int done;
208 u32 irq_clear = M_CMD_DONE_EN;
209
210 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
211 M_CMD_DONE_EN, true);
212 if (!done) {
213 writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
214 SE_GENI_M_CMD_CTRL_REG);
215 irq_clear |= M_CMD_ABORT_EN;
216 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
217 M_CMD_ABORT_EN, true);
218 }
219 writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
220}
221
222static void qcom_geni_serial_abort_rx(struct uart_port *uport)
223{
224 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
225
226 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
227 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
228 S_GENI_CMD_ABORT, false);
229 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
230 writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
231}
232
233#ifdef CONFIG_CONSOLE_POLL
234static int qcom_geni_serial_get_char(struct uart_port *uport)
235{
236 u32 rx_fifo;
237 u32 status;
238
239 status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
240 writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
241
242 status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
243 writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
244
245 /*
246 * Ensure the writes to clear interrupts is not re-ordered after
247 * reading the data.
248 */
249 mb();
250
251 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
252 if (!(status & RX_FIFO_WC_MSK))
253 return NO_POLL_CHAR;
254
255 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
256 return rx_fifo & 0xff;
257}
258
259static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
260 unsigned char c)
261{
262 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
263
264 writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
265 qcom_geni_serial_setup_tx(uport, 1);
266 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
267 M_TX_FIFO_WATERMARK_EN, true));
268 writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
269 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
270 SE_GENI_M_IRQ_CLEAR);
271 qcom_geni_serial_poll_tx_done(uport);
272}
273#endif
274
275#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
276static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
277{
278 writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
279}
280
281static void
282__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
283 unsigned int count)
284{
285 int i;
286 u32 bytes_to_send = count;
287
288 for (i = 0; i < count; i++) {
289 if (s[i] == '\n')
290 bytes_to_send++;
291 }
292
293 writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
294 qcom_geni_serial_setup_tx(uport, bytes_to_send);
295 for (i = 0; i < count; ) {
296 size_t chars_to_write = 0;
297 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
298
299 /*
300 * If the WM bit never set, then the Tx state machine is not
301 * in a valid state, so break, cancel/abort any existing
302 * command. Unfortunately the current data being written is
303 * lost.
304 */
305 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
306 M_TX_FIFO_WATERMARK_EN, true))
307 break;
308 chars_to_write = min_t(size_t, (size_t)(count - i), avail / 2);
309 uart_console_write(uport, s + i, chars_to_write,
310 qcom_geni_serial_wr_char);
311 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
312 SE_GENI_M_IRQ_CLEAR);
313 i += chars_to_write;
314 }
315 qcom_geni_serial_poll_tx_done(uport);
316}
317
318static void qcom_geni_serial_console_write(struct console *co, const char *s,
319 unsigned int count)
320{
321 struct uart_port *uport;
322 struct qcom_geni_serial_port *port;
323 bool locked = true;
324 unsigned long flags;
325
326 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
327
328 port = get_port_from_line(co->index);
329 if (IS_ERR(port))
330 return;
331
332 uport = &port->uport;
333 if (oops_in_progress)
334 locked = spin_trylock_irqsave(&uport->lock, flags);
335 else
336 spin_lock_irqsave(&uport->lock, flags);
337
338 /* Cancel the current write to log the fault */
339 if (!locked) {
340 geni_se_cancel_m_cmd(&port->se);
341 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
342 M_CMD_CANCEL_EN, true)) {
343 geni_se_abort_m_cmd(&port->se);
344 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
345 M_CMD_ABORT_EN, true);
346 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
347 SE_GENI_M_IRQ_CLEAR);
348 }
349 writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
350 SE_GENI_M_IRQ_CLEAR);
351 }
352
353 __qcom_geni_serial_console_write(uport, s, count);
354 if (locked)
355 spin_unlock_irqrestore(&uport->lock, flags);
356}
357
358static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
359{
360 u32 i;
361 unsigned char buf[sizeof(u32)];
362 struct tty_port *tport;
363 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
364
365 tport = &uport->state->port;
366 for (i = 0; i < bytes; ) {
367 int c;
368 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
369
370 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
371 i += chunk;
372 if (drop)
373 continue;
374
375 for (c = 0; c < chunk; c++) {
376 int sysrq;
377
378 uport->icount.rx++;
379 if (port->brk && buf[c] == 0) {
380 port->brk = false;
381 if (uart_handle_break(uport))
382 continue;
383 }
384
385 sysrq = uart_handle_sysrq_char(uport, buf[c]);
386 if (!sysrq)
387 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
388 }
389 }
390 if (!drop)
391 tty_flip_buffer_push(tport);
392 return 0;
393}
394#else
395static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
396{
397 return -EPERM;
398}
399
400#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
401
402static void qcom_geni_serial_start_tx(struct uart_port *uport)
403{
404 u32 irq_en;
405 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
406 u32 status;
407
408 if (port->xfer_mode == GENI_SE_FIFO) {
409 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
410 if (status & M_GENI_CMD_ACTIVE)
411 return;
412
413 if (!qcom_geni_serial_tx_empty(uport))
414 return;
415
416 /*
417 * Ensure writing to IRQ_EN & watermark registers are not
418 * re-ordered before checking the status of the Serial
419 * Engine and TX FIFO
420 */
421 mb();
422
423 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
424 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
425
426 writel_relaxed(port->tx_wm, uport->membase +
427 SE_GENI_TX_WATERMARK_REG);
428 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
429 }
430}
431
432static void qcom_geni_serial_stop_tx(struct uart_port *uport)
433{
434 u32 irq_en;
435 u32 status;
436 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
437
438 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
439 irq_en &= ~M_CMD_DONE_EN;
440 if (port->xfer_mode == GENI_SE_FIFO) {
441 irq_en &= ~M_TX_FIFO_WATERMARK_EN;
442 writel_relaxed(0, uport->membase +
443 SE_GENI_TX_WATERMARK_REG);
444 }
445 port->xmit_size = 0;
446 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
447 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
448 /* Possible stop tx is called multiple times. */
449 if (!(status & M_GENI_CMD_ACTIVE))
450 return;
451
452 /*
453 * Ensure cancel command write is not re-ordered before checking
454 * the status of the Primary Sequencer.
455 */
456 mb();
457
458 geni_se_cancel_m_cmd(&port->se);
459 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
460 M_CMD_CANCEL_EN, true)) {
461 geni_se_abort_m_cmd(&port->se);
462 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
463 M_CMD_ABORT_EN, true);
464 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
465 SE_GENI_M_IRQ_CLEAR);
466 }
467 writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
468}
469
470static void qcom_geni_serial_start_rx(struct uart_port *uport)
471{
472 u32 irq_en;
473 u32 status;
474 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
475
476 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
477 if (status & S_GENI_CMD_ACTIVE)
478 qcom_geni_serial_stop_rx(uport);
479
480 /*
481 * Ensure setup command write is not re-ordered before checking
482 * the status of the Secondary Sequencer.
483 */
484 mb();
485
486 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
487
488 if (port->xfer_mode == GENI_SE_FIFO) {
489 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
490 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
491 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
492
493 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
494 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
495 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
496 }
497}
498
499static void qcom_geni_serial_stop_rx(struct uart_port *uport)
500{
501 u32 irq_en;
502 u32 status;
503 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
504 u32 irq_clear = S_CMD_DONE_EN;
505
506 if (port->xfer_mode == GENI_SE_FIFO) {
507 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
508 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
509 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
510
511 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
512 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
513 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
514 }
515
516 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
517 /* Possible stop rx is called multiple times. */
518 if (!(status & S_GENI_CMD_ACTIVE))
519 return;
520
521 /*
522 * Ensure cancel command write is not re-ordered before checking
523 * the status of the Secondary Sequencer.
524 */
525 mb();
526
527 geni_se_cancel_s_cmd(&port->se);
528 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
529 S_GENI_CMD_CANCEL, false);
530 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
531 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
532 if (status & S_GENI_CMD_ACTIVE)
533 qcom_geni_serial_abort_rx(uport);
534}
535
536static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
537{
538 u32 status;
539 u32 word_cnt;
540 u32 last_word_byte_cnt;
541 u32 last_word_partial;
542 u32 total_bytes;
543 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
544
545 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
546 word_cnt = status & RX_FIFO_WC_MSK;
547 last_word_partial = status & RX_LAST;
548 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
549 RX_LAST_BYTE_VALID_SHFT;
550
551 if (!word_cnt)
552 return;
553 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
554 if (last_word_partial && last_word_byte_cnt)
555 total_bytes += last_word_byte_cnt;
556 else
557 total_bytes += port->rx_bytes_pw;
558 port->handle_rx(uport, total_bytes, drop);
559}
560
561static void qcom_geni_serial_handle_tx(struct uart_port *uport)
562{
563 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
564 struct circ_buf *xmit = &uport->state->xmit;
565 size_t avail;
566 size_t remaining;
567 int i;
568 u32 status;
569 unsigned int chunk;
570 int tail;
571
572 chunk = uart_circ_chars_pending(xmit);
573 status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
574 /* Both FIFO and framework buffer are drained */
575 if (chunk == port->xmit_size && !status) {
576 port->xmit_size = 0;
577 uart_circ_clear(xmit);
578 qcom_geni_serial_stop_tx(uport);
579 goto out_write_wakeup;
580 }
581 chunk -= port->xmit_size;
582
583 avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw;
584 tail = (xmit->tail + port->xmit_size) & (UART_XMIT_SIZE - 1);
585 if (chunk > (UART_XMIT_SIZE - tail))
586 chunk = UART_XMIT_SIZE - tail;
587 if (chunk > avail)
588 chunk = avail;
589
590 if (!chunk)
591 goto out_write_wakeup;
592
593 qcom_geni_serial_setup_tx(uport, chunk);
594
595 remaining = chunk;
596 for (i = 0; i < chunk; ) {
597 unsigned int tx_bytes;
598 unsigned int buf = 0;
599 int c;
600
601 tx_bytes = min_t(size_t, remaining, (size_t)port->tx_bytes_pw);
602 for (c = 0; c < tx_bytes ; c++)
603 buf |= (xmit->buf[tail + c] << (c * BITS_PER_BYTE));
604
605 writel_relaxed(buf, uport->membase + SE_GENI_TX_FIFOn);
606
607 i += tx_bytes;
608 tail = (tail + tx_bytes) & (UART_XMIT_SIZE - 1);
609 uport->icount.tx += tx_bytes;
610 remaining -= tx_bytes;
611 }
612 qcom_geni_serial_poll_tx_done(uport);
613 port->xmit_size += chunk;
614out_write_wakeup:
615 uart_write_wakeup(uport);
616}
617
618static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
619{
620 unsigned int m_irq_status;
621 unsigned int s_irq_status;
622 struct uart_port *uport = dev;
623 unsigned long flags;
624 unsigned int m_irq_en;
625 bool drop_rx = false;
626 struct tty_port *tport = &uport->state->port;
627 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
628
629 if (uport->suspended)
630 return IRQ_HANDLED;
631
632 spin_lock_irqsave(&uport->lock, flags);
633 m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
634 s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
635 m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
636 writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
637 writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
638
639 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
640 goto out_unlock;
641
642 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
643 uport->icount.overrun++;
644 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
645 }
646
647 if (m_irq_status & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN) &&
648 m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
649 qcom_geni_serial_handle_tx(uport);
650
651 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
652 if (s_irq_status & S_GP_IRQ_0_EN)
653 uport->icount.parity++;
654 drop_rx = true;
655 } else if (s_irq_status & S_GP_IRQ_2_EN ||
656 s_irq_status & S_GP_IRQ_3_EN) {
657 uport->icount.brk++;
658 port->brk = true;
659 }
660
661 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
662 s_irq_status & S_RX_FIFO_LAST_EN)
663 qcom_geni_serial_handle_rx(uport, drop_rx);
664
665out_unlock:
666 spin_unlock_irqrestore(&uport->lock, flags);
667 return IRQ_HANDLED;
668}
669
670static int get_tx_fifo_size(struct qcom_geni_serial_port *port)
671{
672 struct uart_port *uport;
673
674 if (!port)
675 return -ENODEV;
676
677 uport = &port->uport;
678 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
679 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
680 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
681 uport->fifosize =
682 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
683 return 0;
684}
685
686static void set_rfr_wm(struct qcom_geni_serial_port *port)
687{
688 /*
689 * Set RFR (Flow off) to FIFO_DEPTH - 2.
690 * RX WM level at 10% RX_FIFO_DEPTH.
691 * TX WM level at 10% TX_FIFO_DEPTH.
692 */
693 port->rx_rfr = port->rx_fifo_depth - 2;
694 port->rx_wm = UART_CONSOLE_RX_WM;
695 port->tx_wm = DEF_TX_WM;
696}
697
698static void qcom_geni_serial_shutdown(struct uart_port *uport)
699{
700 unsigned long flags;
701
702 /* Stop the console before stopping the current tx */
703 console_stop(uport->cons);
704
705 disable_irq(uport->irq);
706 free_irq(uport->irq, uport);
707 spin_lock_irqsave(&uport->lock, flags);
708 qcom_geni_serial_stop_tx(uport);
709 qcom_geni_serial_stop_rx(uport);
710 spin_unlock_irqrestore(&uport->lock, flags);
711}
712
713static int qcom_geni_serial_port_setup(struct uart_port *uport)
714{
715 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
716 unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
717
718 set_rfr_wm(port);
719 writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
720 /*
721 * Make an unconditional cancel on the main sequencer to reset
722 * it else we could end up in data loss scenarios.
723 */
724 port->xfer_mode = GENI_SE_FIFO;
725 qcom_geni_serial_poll_tx_done(uport);
726 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
727 false, true, false);
728 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
729 false, false, true);
730 geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
731 geni_se_select_mode(&port->se, port->xfer_mode);
732 port->setup = true;
733 return 0;
734}
735
736static int qcom_geni_serial_startup(struct uart_port *uport)
737{
738 int ret;
739 u32 proto;
740 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
741
742 scnprintf(port->name, sizeof(port->name),
743 "qcom_serial_geni%d", uport->line);
744
745 proto = geni_se_read_proto(&port->se);
746 if (proto != GENI_SE_UART) {
747 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
748 return -ENXIO;
749 }
750
751 get_tx_fifo_size(port);
752 if (!port->setup) {
753 ret = qcom_geni_serial_port_setup(uport);
754 if (ret)
755 return ret;
756 }
757
758 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
759 port->name, uport);
760 if (ret)
761 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
762 return ret;
763}
764
765static unsigned long get_clk_cfg(unsigned long clk_freq)
766{
767 int i;
768
769 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
770 if (!(root_freq[i] % clk_freq))
771 return root_freq[i];
772 }
773 return 0;
774}
775
776static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
777{
778 unsigned long ser_clk;
779 unsigned long desired_clk;
780
781 desired_clk = baud * UART_OVERSAMPLING;
782 ser_clk = get_clk_cfg(desired_clk);
783 if (!ser_clk) {
784 pr_err("%s: Can't find matching DFS entry for baud %d\n",
785 __func__, baud);
786 return ser_clk;
787 }
788
789 *clk_div = ser_clk / desired_clk;
790 return ser_clk;
791}
792
793static void qcom_geni_serial_set_termios(struct uart_port *uport,
794 struct ktermios *termios, struct ktermios *old)
795{
796 unsigned int baud;
797 unsigned int bits_per_char;
798 unsigned int tx_trans_cfg;
799 unsigned int tx_parity_cfg;
800 unsigned int rx_trans_cfg;
801 unsigned int rx_parity_cfg;
802 unsigned int stop_bit_len;
803 unsigned int clk_div;
804 unsigned long ser_clk_cfg;
805 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
806 unsigned long clk_rate;
807
808 qcom_geni_serial_stop_rx(uport);
809 /* baud rate */
810 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
811 port->baud = baud;
812 clk_rate = get_clk_div_rate(baud, &clk_div);
813 if (!clk_rate)
814 goto out_restart_rx;
815
816 uport->uartclk = clk_rate;
817 clk_set_rate(port->se.clk, clk_rate);
818 ser_clk_cfg = SER_CLK_EN;
819 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
820
821 /* parity */
822 tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
823 tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
824 rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
825 rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
826 if (termios->c_cflag & PARENB) {
827 tx_trans_cfg |= UART_TX_PAR_EN;
828 rx_trans_cfg |= UART_RX_PAR_EN;
829 tx_parity_cfg |= PAR_CALC_EN;
830 rx_parity_cfg |= PAR_CALC_EN;
831 if (termios->c_cflag & PARODD) {
832 tx_parity_cfg |= PAR_ODD;
833 rx_parity_cfg |= PAR_ODD;
834 } else if (termios->c_cflag & CMSPAR) {
835 tx_parity_cfg |= PAR_SPACE;
836 rx_parity_cfg |= PAR_SPACE;
837 } else {
838 tx_parity_cfg |= PAR_EVEN;
839 rx_parity_cfg |= PAR_EVEN;
840 }
841 } else {
842 tx_trans_cfg &= ~UART_TX_PAR_EN;
843 rx_trans_cfg &= ~UART_RX_PAR_EN;
844 tx_parity_cfg &= ~PAR_CALC_EN;
845 rx_parity_cfg &= ~PAR_CALC_EN;
846 }
847
848 /* bits per char */
849 switch (termios->c_cflag & CSIZE) {
850 case CS5:
851 bits_per_char = 5;
852 break;
853 case CS6:
854 bits_per_char = 6;
855 break;
856 case CS7:
857 bits_per_char = 7;
858 break;
859 case CS8:
860 default:
861 bits_per_char = 8;
862 break;
863 }
864
865 /* stop bits */
866 if (termios->c_cflag & CSTOPB)
867 stop_bit_len = TX_STOP_BIT_LEN_2;
868 else
869 stop_bit_len = TX_STOP_BIT_LEN_1;
870
871 /* flow control, clear the CTS_MASK bit if using flow control. */
872 if (termios->c_cflag & CRTSCTS)
873 tx_trans_cfg &= ~UART_CTS_MASK;
874 else
875 tx_trans_cfg |= UART_CTS_MASK;
876
877 if (baud)
878 uart_update_timeout(uport, termios->c_cflag, baud);
879
880 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
881 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
882 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
883 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
884 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
885 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
886 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
887 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
888 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
889out_restart_rx:
890 qcom_geni_serial_start_rx(uport);
891}
892
893static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
894{
895 return !readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
896}
897
898#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
899static int __init qcom_geni_console_setup(struct console *co, char *options)
900{
901 struct uart_port *uport;
902 struct qcom_geni_serial_port *port;
903 int baud;
904 int bits = 8;
905 int parity = 'n';
906 int flow = 'n';
907
908 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
909 return -ENXIO;
910
911 port = get_port_from_line(co->index);
912 if (IS_ERR(port)) {
913 pr_err("Invalid line %d(%d)\n", co->index, (int)PTR_ERR(port));
914 return PTR_ERR(port);
915 }
916
917 uport = &port->uport;
918
919 if (unlikely(!uport->membase))
920 return -ENXIO;
921
922 if (geni_se_resources_on(&port->se)) {
923 dev_err(port->se.dev, "Error turning on resources\n");
924 return -ENXIO;
925 }
926
927 if (unlikely(geni_se_read_proto(&port->se) != GENI_SE_UART)) {
928 geni_se_resources_off(&port->se);
929 return -ENXIO;
930 }
931
932 if (!port->setup) {
933 port->tx_bytes_pw = 1;
934 port->rx_bytes_pw = RX_BYTES_PW;
935 qcom_geni_serial_stop_rx(uport);
936 qcom_geni_serial_port_setup(uport);
937 }
938
939 if (options)
940 uart_parse_options(options, &baud, &parity, &bits, &flow);
941
942 return uart_set_options(uport, co, baud, parity, bits, flow);
943}
944
945static int __init console_register(struct uart_driver *drv)
946{
947 return uart_register_driver(drv);
948}
949
950static void console_unregister(struct uart_driver *drv)
951{
952 uart_unregister_driver(drv);
953}
954
955static struct console cons_ops = {
956 .name = "ttyMSM",
957 .write = qcom_geni_serial_console_write,
958 .device = uart_console_device,
959 .setup = qcom_geni_console_setup,
960 .flags = CON_PRINTBUFFER,
961 .index = -1,
962 .data = &qcom_geni_console_driver,
963};
964
965static struct uart_driver qcom_geni_console_driver = {
966 .owner = THIS_MODULE,
967 .driver_name = "qcom_geni_console",
968 .dev_name = "ttyMSM",
969 .nr = GENI_UART_CONS_PORTS,
970 .cons = &cons_ops,
971};
972#else
973static int console_register(struct uart_driver *drv)
974{
975 return 0;
976}
977
978static void console_unregister(struct uart_driver *drv)
979{
980}
981#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
982
983static void qcom_geni_serial_cons_pm(struct uart_port *uport,
984 unsigned int new_state, unsigned int old_state)
985{
986 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
987
988 if (unlikely(!uart_console(uport)))
989 return;
990
991 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
992 geni_se_resources_on(&port->se);
993 else if (new_state == UART_PM_STATE_OFF &&
994 old_state == UART_PM_STATE_ON)
995 geni_se_resources_off(&port->se);
996}
997
998static const struct uart_ops qcom_geni_console_pops = {
999 .tx_empty = qcom_geni_serial_tx_empty,
1000 .stop_tx = qcom_geni_serial_stop_tx,
1001 .start_tx = qcom_geni_serial_start_tx,
1002 .stop_rx = qcom_geni_serial_stop_rx,
1003 .set_termios = qcom_geni_serial_set_termios,
1004 .startup = qcom_geni_serial_startup,
1005 .request_port = qcom_geni_serial_request_port,
1006 .config_port = qcom_geni_serial_config_port,
1007 .shutdown = qcom_geni_serial_shutdown,
1008 .type = qcom_geni_serial_get_type,
1009 .set_mctrl = qcom_geni_cons_set_mctrl,
1010 .get_mctrl = qcom_geni_cons_get_mctrl,
1011#ifdef CONFIG_CONSOLE_POLL
1012 .poll_get_char = qcom_geni_serial_get_char,
1013 .poll_put_char = qcom_geni_serial_poll_put_char,
1014#endif
1015 .pm = qcom_geni_serial_cons_pm,
1016};
1017
1018static int qcom_geni_serial_probe(struct platform_device *pdev)
1019{
1020 int ret = 0;
1021 int line = -1;
1022 struct qcom_geni_serial_port *port;
1023 struct uart_port *uport;
1024 struct resource *res;
1025 int irq;
1026
1027 if (pdev->dev.of_node)
1028 line = of_alias_get_id(pdev->dev.of_node, "serial");
1029 else
1030 line = pdev->id;
1031
1032 if (line < 0 || line >= GENI_UART_CONS_PORTS)
1033 return -ENXIO;
1034 port = get_port_from_line(line);
1035 if (IS_ERR(port)) {
1036 ret = PTR_ERR(port);
1037 dev_err(&pdev->dev, "Invalid line %d(%d)\n", line, ret);
1038 return ret;
1039 }
1040
1041 uport = &port->uport;
1042 /* Don't allow 2 drivers to access the same port */
1043 if (uport->private_data)
1044 return -ENODEV;
1045
1046 uport->dev = &pdev->dev;
1047 port->se.dev = &pdev->dev;
1048 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1049 port->se.clk = devm_clk_get(&pdev->dev, "se");
1050 if (IS_ERR(port->se.clk)) {
1051 ret = PTR_ERR(port->se.clk);
1052 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1053 return ret;
1054 }
1055
1056 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1057 if (!res)
1058 return -EINVAL;
1059 uport->mapbase = res->start;
1060
1061 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1062 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1063 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1064
1065 irq = platform_get_irq(pdev, 0);
1066 if (irq < 0) {
1067 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1068 return irq;
1069 }
1070 uport->irq = irq;
1071
1072 uport->private_data = &qcom_geni_console_driver;
1073 platform_set_drvdata(pdev, port);
1074 port->handle_rx = handle_rx_console;
1075 port->setup = false;
1076 return uart_add_one_port(&qcom_geni_console_driver, uport);
1077}
1078
1079static int qcom_geni_serial_remove(struct platform_device *pdev)
1080{
1081 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1082 struct uart_driver *drv = port->uport.private_data;
1083
1084 uart_remove_one_port(drv, &port->uport);
1085 return 0;
1086}
1087
1088static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
1089{
1090 struct platform_device *pdev = to_platform_device(dev);
1091 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1092 struct uart_port *uport = &port->uport;
1093
1094 uart_suspend_port(uport->private_data, uport);
1095 return 0;
1096}
1097
1098static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
1099{
1100 struct platform_device *pdev = to_platform_device(dev);
1101 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1102 struct uart_port *uport = &port->uport;
1103
1104 if (console_suspend_enabled && uport->suspended) {
1105 uart_resume_port(uport->private_data, uport);
1106 disable_irq(uport->irq);
1107 }
1108 return 0;
1109}
1110
1111static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1112 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
1113 qcom_geni_serial_sys_resume_noirq)
1114};
1115
1116static const struct of_device_id qcom_geni_serial_match_table[] = {
1117 { .compatible = "qcom,geni-debug-uart", },
1118 {}
1119};
1120MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1121
1122static struct platform_driver qcom_geni_serial_platform_driver = {
1123 .remove = qcom_geni_serial_remove,
1124 .probe = qcom_geni_serial_probe,
1125 .driver = {
1126 .name = "qcom_geni_serial",
1127 .of_match_table = qcom_geni_serial_match_table,
1128 .pm = &qcom_geni_serial_pm_ops,
1129 },
1130};
1131
1132static int __init qcom_geni_serial_init(void)
1133{
1134 int ret;
1135
1136 qcom_geni_console_port.uport.iotype = UPIO_MEM;
1137 qcom_geni_console_port.uport.ops = &qcom_geni_console_pops;
1138 qcom_geni_console_port.uport.flags = UPF_BOOT_AUTOCONF;
1139 qcom_geni_console_port.uport.line = 0;
1140
1141 ret = console_register(&qcom_geni_console_driver);
1142 if (ret)
1143 return ret;
1144
1145 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1146 if (ret)
1147 console_unregister(&qcom_geni_console_driver);
1148 return ret;
1149}
1150module_init(qcom_geni_serial_init);
1151
1152static void __exit qcom_geni_serial_exit(void)
1153{
1154 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1155 console_unregister(&qcom_geni_console_driver);
1156}
1157module_exit(qcom_geni_serial_exit);
1158
1159MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1160MODULE_LICENSE("GPL v2");