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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MPS2 UART driver
4 *
5 * Copyright (C) 2015 ARM Limited
6 *
7 * Author: Vladimir Murzin <vladimir.murzin@arm.com>
8 *
9 * TODO: support for SysRq
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/console.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/serial_core.h>
22#include <linux/tty_flip.h>
23#include <linux/types.h>
24#include <linux/idr.h>
25
26#define SERIAL_NAME "ttyMPS"
27#define DRIVER_NAME "mps2-uart"
28#define MAKE_NAME(x) (DRIVER_NAME # x)
29
30#define UARTn_DATA 0x00
31
32#define UARTn_STATE 0x04
33#define UARTn_STATE_TX_FULL BIT(0)
34#define UARTn_STATE_RX_FULL BIT(1)
35#define UARTn_STATE_TX_OVERRUN BIT(2)
36#define UARTn_STATE_RX_OVERRUN BIT(3)
37
38#define UARTn_CTRL 0x08
39#define UARTn_CTRL_TX_ENABLE BIT(0)
40#define UARTn_CTRL_RX_ENABLE BIT(1)
41#define UARTn_CTRL_TX_INT_ENABLE BIT(2)
42#define UARTn_CTRL_RX_INT_ENABLE BIT(3)
43#define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
44#define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
45
46#define UARTn_INT 0x0c
47#define UARTn_INT_TX BIT(0)
48#define UARTn_INT_RX BIT(1)
49#define UARTn_INT_TX_OVERRUN BIT(2)
50#define UARTn_INT_RX_OVERRUN BIT(3)
51
52#define UARTn_BAUDDIV 0x10
53#define UARTn_BAUDDIV_MASK GENMASK(20, 0)
54
55/*
56 * Helpers to make typical enable/disable operations more readable.
57 */
58#define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
59 UARTn_CTRL_TX_INT_ENABLE |\
60 UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
61
62#define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
63 UARTn_CTRL_RX_INT_ENABLE |\
64 UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
65
66#define MPS2_MAX_PORTS 3
67
68#define UART_PORT_COMBINED_IRQ BIT(0)
69
70struct mps2_uart_port {
71 struct uart_port port;
72 struct clk *clk;
73 unsigned int tx_irq;
74 unsigned int rx_irq;
75 unsigned int flags;
76};
77
78static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
79{
80 return container_of(port, struct mps2_uart_port, port);
81}
82
83static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off)
84{
85 struct mps2_uart_port *mps_port = to_mps2_port(port);
86
87 writeb(val, mps_port->port.membase + off);
88}
89
90static u8 mps2_uart_read8(struct uart_port *port, unsigned int off)
91{
92 struct mps2_uart_port *mps_port = to_mps2_port(port);
93
94 return readb(mps_port->port.membase + off);
95}
96
97static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off)
98{
99 struct mps2_uart_port *mps_port = to_mps2_port(port);
100
101 writel_relaxed(val, mps_port->port.membase + off);
102}
103
104static unsigned int mps2_uart_tx_empty(struct uart_port *port)
105{
106 u8 status = mps2_uart_read8(port, UARTn_STATE);
107
108 return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
109}
110
111static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
112{
113}
114
115static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
116{
117 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
118}
119
120static void mps2_uart_stop_tx(struct uart_port *port)
121{
122 u8 control = mps2_uart_read8(port, UARTn_CTRL);
123
124 control &= ~UARTn_CTRL_TX_INT_ENABLE;
125
126 mps2_uart_write8(port, control, UARTn_CTRL);
127}
128
129static void mps2_uart_tx_chars(struct uart_port *port)
130{
131 u8 ch;
132
133 uart_port_tx(port, ch,
134 mps2_uart_tx_empty(port),
135 mps2_uart_write8(port, ch, UARTn_DATA));
136}
137
138static void mps2_uart_start_tx(struct uart_port *port)
139{
140 u8 control = mps2_uart_read8(port, UARTn_CTRL);
141
142 control |= UARTn_CTRL_TX_INT_ENABLE;
143
144 mps2_uart_write8(port, control, UARTn_CTRL);
145
146 /*
147 * We've just unmasked the TX IRQ and now slow-starting via
148 * polling; if there is enough data to fill up the internal
149 * write buffer in one go, the TX IRQ should assert, at which
150 * point we switch to fully interrupt-driven TX.
151 */
152
153 mps2_uart_tx_chars(port);
154}
155
156static void mps2_uart_stop_rx(struct uart_port *port)
157{
158 u8 control = mps2_uart_read8(port, UARTn_CTRL);
159
160 control &= ~UARTn_CTRL_RX_GRP;
161
162 mps2_uart_write8(port, control, UARTn_CTRL);
163}
164
165static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
166{
167}
168
169static void mps2_uart_rx_chars(struct uart_port *port)
170{
171 struct tty_port *tport = &port->state->port;
172
173 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
174 u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
175
176 port->icount.rx++;
177 tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
178 }
179
180 tty_flip_buffer_push(tport);
181}
182
183static irqreturn_t mps2_uart_rxirq(int irq, void *data)
184{
185 struct uart_port *port = data;
186 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
187
188 if (unlikely(!(irqflag & UARTn_INT_RX)))
189 return IRQ_NONE;
190
191 uart_port_lock(port);
192
193 mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
194 mps2_uart_rx_chars(port);
195
196 uart_port_unlock(port);
197
198 return IRQ_HANDLED;
199}
200
201static irqreturn_t mps2_uart_txirq(int irq, void *data)
202{
203 struct uart_port *port = data;
204 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
205
206 if (unlikely(!(irqflag & UARTn_INT_TX)))
207 return IRQ_NONE;
208
209 uart_port_lock(port);
210
211 mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
212 mps2_uart_tx_chars(port);
213
214 uart_port_unlock(port);
215
216 return IRQ_HANDLED;
217}
218
219static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
220{
221 irqreturn_t handled = IRQ_NONE;
222 struct uart_port *port = data;
223 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
224
225 uart_port_lock(port);
226
227 if (irqflag & UARTn_INT_RX_OVERRUN) {
228 struct tty_port *tport = &port->state->port;
229
230 mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
231 port->icount.overrun++;
232 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
233 tty_flip_buffer_push(tport);
234 handled = IRQ_HANDLED;
235 }
236
237 /*
238 * It's never been seen in practice and it never *should* happen since
239 * we check if there is enough room in TX buffer before sending data.
240 * So we keep this check in case something suspicious has happened.
241 */
242 if (irqflag & UARTn_INT_TX_OVERRUN) {
243 mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
244 handled = IRQ_HANDLED;
245 }
246
247 uart_port_unlock(port);
248
249 return handled;
250}
251
252static irqreturn_t mps2_uart_combinedirq(int irq, void *data)
253{
254 if (mps2_uart_rxirq(irq, data) == IRQ_HANDLED)
255 return IRQ_HANDLED;
256
257 if (mps2_uart_txirq(irq, data) == IRQ_HANDLED)
258 return IRQ_HANDLED;
259
260 if (mps2_uart_oerrirq(irq, data) == IRQ_HANDLED)
261 return IRQ_HANDLED;
262
263 return IRQ_NONE;
264}
265
266static int mps2_uart_startup(struct uart_port *port)
267{
268 struct mps2_uart_port *mps_port = to_mps2_port(port);
269 u8 control = mps2_uart_read8(port, UARTn_CTRL);
270 int ret;
271
272 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
273
274 mps2_uart_write8(port, control, UARTn_CTRL);
275
276 if (mps_port->flags & UART_PORT_COMBINED_IRQ) {
277 ret = request_irq(port->irq, mps2_uart_combinedirq, 0,
278 MAKE_NAME(-combined), mps_port);
279
280 if (ret) {
281 dev_err(port->dev, "failed to register combinedirq (%d)\n", ret);
282 return ret;
283 }
284 } else {
285 ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
286 MAKE_NAME(-overrun), mps_port);
287
288 if (ret) {
289 dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
290 return ret;
291 }
292
293 ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
294 MAKE_NAME(-rx), mps_port);
295 if (ret) {
296 dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
297 goto err_free_oerrirq;
298 }
299
300 ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
301 MAKE_NAME(-tx), mps_port);
302 if (ret) {
303 dev_err(port->dev, "failed to register txirq (%d)\n", ret);
304 goto err_free_rxirq;
305 }
306
307 }
308
309 control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
310
311 mps2_uart_write8(port, control, UARTn_CTRL);
312
313 return 0;
314
315err_free_rxirq:
316 free_irq(mps_port->rx_irq, mps_port);
317err_free_oerrirq:
318 free_irq(port->irq, mps_port);
319
320 return ret;
321}
322
323static void mps2_uart_shutdown(struct uart_port *port)
324{
325 struct mps2_uart_port *mps_port = to_mps2_port(port);
326 u8 control = mps2_uart_read8(port, UARTn_CTRL);
327
328 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
329
330 mps2_uart_write8(port, control, UARTn_CTRL);
331
332 if (!(mps_port->flags & UART_PORT_COMBINED_IRQ)) {
333 free_irq(mps_port->rx_irq, mps_port);
334 free_irq(mps_port->tx_irq, mps_port);
335 }
336
337 free_irq(port->irq, mps_port);
338}
339
340static void
341mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios,
342 const struct ktermios *old)
343{
344 unsigned long flags;
345 unsigned int baud, bauddiv;
346
347 termios->c_cflag &= ~(CRTSCTS | CMSPAR);
348 termios->c_cflag &= ~CSIZE;
349 termios->c_cflag |= CS8;
350 termios->c_cflag &= ~PARENB;
351 termios->c_cflag &= ~CSTOPB;
352
353 baud = uart_get_baud_rate(port, termios, old,
354 DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
355 DIV_ROUND_CLOSEST(port->uartclk, 16));
356
357 bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
358
359 uart_port_lock_irqsave(port, &flags);
360
361 uart_update_timeout(port, termios->c_cflag, baud);
362 mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
363
364 uart_port_unlock_irqrestore(port, flags);
365
366 if (tty_termios_baud_rate(termios))
367 tty_termios_encode_baud_rate(termios, baud, baud);
368}
369
370static const char *mps2_uart_type(struct uart_port *port)
371{
372 return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
373}
374
375static void mps2_uart_release_port(struct uart_port *port)
376{
377}
378
379static int mps2_uart_request_port(struct uart_port *port)
380{
381 return 0;
382}
383
384static void mps2_uart_config_port(struct uart_port *port, int type)
385{
386 if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
387 port->type = PORT_MPS2UART;
388}
389
390static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
391{
392 return -EINVAL;
393}
394
395static const struct uart_ops mps2_uart_pops = {
396 .tx_empty = mps2_uart_tx_empty,
397 .set_mctrl = mps2_uart_set_mctrl,
398 .get_mctrl = mps2_uart_get_mctrl,
399 .stop_tx = mps2_uart_stop_tx,
400 .start_tx = mps2_uart_start_tx,
401 .stop_rx = mps2_uart_stop_rx,
402 .break_ctl = mps2_uart_break_ctl,
403 .startup = mps2_uart_startup,
404 .shutdown = mps2_uart_shutdown,
405 .set_termios = mps2_uart_set_termios,
406 .type = mps2_uart_type,
407 .release_port = mps2_uart_release_port,
408 .request_port = mps2_uart_request_port,
409 .config_port = mps2_uart_config_port,
410 .verify_port = mps2_uart_verify_port,
411};
412
413static DEFINE_IDR(ports_idr);
414
415#ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
416static void mps2_uart_console_putchar(struct uart_port *port, unsigned char ch)
417{
418 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
419 cpu_relax();
420
421 mps2_uart_write8(port, ch, UARTn_DATA);
422}
423
424static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
425{
426 struct mps2_uart_port *mps_port = idr_find(&ports_idr, co->index);
427 struct uart_port *port = &mps_port->port;
428
429 uart_console_write(port, s, cnt, mps2_uart_console_putchar);
430}
431
432static int mps2_uart_console_setup(struct console *co, char *options)
433{
434 struct mps2_uart_port *mps_port;
435 int baud = 9600;
436 int bits = 8;
437 int parity = 'n';
438 int flow = 'n';
439
440 if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
441 return -ENODEV;
442
443 mps_port = idr_find(&ports_idr, co->index);
444
445 if (!mps_port)
446 return -ENODEV;
447
448 if (options)
449 uart_parse_options(options, &baud, &parity, &bits, &flow);
450
451 return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
452}
453
454static struct uart_driver mps2_uart_driver;
455
456static struct console mps2_uart_console = {
457 .name = SERIAL_NAME,
458 .device = uart_console_device,
459 .write = mps2_uart_console_write,
460 .setup = mps2_uart_console_setup,
461 .flags = CON_PRINTBUFFER,
462 .index = -1,
463 .data = &mps2_uart_driver,
464};
465
466#define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
467
468static void mps2_early_putchar(struct uart_port *port, unsigned char ch)
469{
470 while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL)
471 cpu_relax();
472
473 writeb((unsigned char)ch, port->membase + UARTn_DATA);
474}
475
476static void mps2_early_write(struct console *con, const char *s, unsigned int n)
477{
478 struct earlycon_device *dev = con->data;
479
480 uart_console_write(&dev->port, s, n, mps2_early_putchar);
481}
482
483static int __init mps2_early_console_setup(struct earlycon_device *device,
484 const char *opt)
485{
486 if (!device->port.membase)
487 return -ENODEV;
488
489 device->con->write = mps2_early_write;
490
491 return 0;
492}
493
494OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup);
495
496#else
497#define MPS2_SERIAL_CONSOLE NULL
498#endif
499
500static struct uart_driver mps2_uart_driver = {
501 .driver_name = DRIVER_NAME,
502 .dev_name = SERIAL_NAME,
503 .nr = MPS2_MAX_PORTS,
504 .cons = MPS2_SERIAL_CONSOLE,
505};
506
507static int mps2_of_get_port(struct platform_device *pdev,
508 struct mps2_uart_port *mps_port)
509{
510 struct device_node *np = pdev->dev.of_node;
511 int id;
512
513 if (!np)
514 return -ENODEV;
515
516 id = of_alias_get_id(np, "serial");
517
518 if (id < 0)
519 id = idr_alloc_cyclic(&ports_idr, (void *)mps_port, 0, MPS2_MAX_PORTS, GFP_KERNEL);
520 else
521 id = idr_alloc(&ports_idr, (void *)mps_port, id, MPS2_MAX_PORTS, GFP_KERNEL);
522
523 if (id < 0)
524 return id;
525
526 /* Only combined irq is presesnt */
527 if (platform_irq_count(pdev) == 1)
528 mps_port->flags |= UART_PORT_COMBINED_IRQ;
529
530 mps_port->port.line = id;
531
532 return 0;
533}
534
535static int mps2_init_port(struct platform_device *pdev,
536 struct mps2_uart_port *mps_port)
537{
538 struct resource *res;
539 int ret;
540
541 mps_port->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
542 if (IS_ERR(mps_port->port.membase))
543 return PTR_ERR(mps_port->port.membase);
544
545 mps_port->port.mapbase = res->start;
546 mps_port->port.mapsize = resource_size(res);
547 mps_port->port.iotype = UPIO_MEM;
548 mps_port->port.flags = UPF_BOOT_AUTOCONF;
549 mps_port->port.fifosize = 1;
550 mps_port->port.ops = &mps2_uart_pops;
551 mps_port->port.dev = &pdev->dev;
552
553 mps_port->clk = devm_clk_get(&pdev->dev, NULL);
554 if (IS_ERR(mps_port->clk))
555 return PTR_ERR(mps_port->clk);
556
557 ret = clk_prepare_enable(mps_port->clk);
558 if (ret)
559 return ret;
560
561 mps_port->port.uartclk = clk_get_rate(mps_port->clk);
562
563 clk_disable_unprepare(mps_port->clk);
564
565
566 if (mps_port->flags & UART_PORT_COMBINED_IRQ) {
567 mps_port->port.irq = platform_get_irq(pdev, 0);
568 } else {
569 mps_port->rx_irq = platform_get_irq(pdev, 0);
570 mps_port->tx_irq = platform_get_irq(pdev, 1);
571 mps_port->port.irq = platform_get_irq(pdev, 2);
572 }
573
574 return ret;
575}
576
577static int mps2_serial_probe(struct platform_device *pdev)
578{
579 struct mps2_uart_port *mps_port;
580 int ret;
581
582 mps_port = devm_kzalloc(&pdev->dev, sizeof(struct mps2_uart_port), GFP_KERNEL);
583
584 if (!mps_port)
585 return -ENOMEM;
586
587 ret = mps2_of_get_port(pdev, mps_port);
588 if (ret)
589 return ret;
590
591 ret = mps2_init_port(pdev, mps_port);
592 if (ret)
593 return ret;
594
595 ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
596 if (ret)
597 return ret;
598
599 platform_set_drvdata(pdev, mps_port);
600
601 return 0;
602}
603
604#ifdef CONFIG_OF
605static const struct of_device_id mps2_match[] = {
606 { .compatible = "arm,mps2-uart", },
607 {},
608};
609#endif
610
611static struct platform_driver mps2_serial_driver = {
612 .probe = mps2_serial_probe,
613
614 .driver = {
615 .name = DRIVER_NAME,
616 .of_match_table = of_match_ptr(mps2_match),
617 .suppress_bind_attrs = true,
618 },
619};
620
621static int __init mps2_uart_init(void)
622{
623 int ret;
624
625 ret = uart_register_driver(&mps2_uart_driver);
626 if (ret)
627 return ret;
628
629 ret = platform_driver_register(&mps2_serial_driver);
630 if (ret)
631 uart_unregister_driver(&mps2_uart_driver);
632
633 return ret;
634}
635arch_initcall(mps2_uart_init);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MPS2 UART driver
4 *
5 * Copyright (C) 2015 ARM Limited
6 *
7 * Author: Vladimir Murzin <vladimir.murzin@arm.com>
8 *
9 * TODO: support for SysRq
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/console.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/of_device.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/serial_core.h>
23#include <linux/tty_flip.h>
24#include <linux/types.h>
25
26#define SERIAL_NAME "ttyMPS"
27#define DRIVER_NAME "mps2-uart"
28#define MAKE_NAME(x) (DRIVER_NAME # x)
29
30#define UARTn_DATA 0x00
31
32#define UARTn_STATE 0x04
33#define UARTn_STATE_TX_FULL BIT(0)
34#define UARTn_STATE_RX_FULL BIT(1)
35#define UARTn_STATE_TX_OVERRUN BIT(2)
36#define UARTn_STATE_RX_OVERRUN BIT(3)
37
38#define UARTn_CTRL 0x08
39#define UARTn_CTRL_TX_ENABLE BIT(0)
40#define UARTn_CTRL_RX_ENABLE BIT(1)
41#define UARTn_CTRL_TX_INT_ENABLE BIT(2)
42#define UARTn_CTRL_RX_INT_ENABLE BIT(3)
43#define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
44#define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
45
46#define UARTn_INT 0x0c
47#define UARTn_INT_TX BIT(0)
48#define UARTn_INT_RX BIT(1)
49#define UARTn_INT_TX_OVERRUN BIT(2)
50#define UARTn_INT_RX_OVERRUN BIT(3)
51
52#define UARTn_BAUDDIV 0x10
53#define UARTn_BAUDDIV_MASK GENMASK(20, 0)
54
55/*
56 * Helpers to make typical enable/disable operations more readable.
57 */
58#define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
59 UARTn_CTRL_TX_INT_ENABLE |\
60 UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
61
62#define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
63 UARTn_CTRL_RX_INT_ENABLE |\
64 UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
65
66#define MPS2_MAX_PORTS 3
67
68struct mps2_uart_port {
69 struct uart_port port;
70 struct clk *clk;
71 unsigned int tx_irq;
72 unsigned int rx_irq;
73};
74
75static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
76{
77 return container_of(port, struct mps2_uart_port, port);
78}
79
80static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off)
81{
82 struct mps2_uart_port *mps_port = to_mps2_port(port);
83
84 writeb(val, mps_port->port.membase + off);
85}
86
87static u8 mps2_uart_read8(struct uart_port *port, unsigned int off)
88{
89 struct mps2_uart_port *mps_port = to_mps2_port(port);
90
91 return readb(mps_port->port.membase + off);
92}
93
94static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off)
95{
96 struct mps2_uart_port *mps_port = to_mps2_port(port);
97
98 writel_relaxed(val, mps_port->port.membase + off);
99}
100
101static unsigned int mps2_uart_tx_empty(struct uart_port *port)
102{
103 u8 status = mps2_uart_read8(port, UARTn_STATE);
104
105 return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
106}
107
108static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
109{
110}
111
112static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
113{
114 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
115}
116
117static void mps2_uart_stop_tx(struct uart_port *port)
118{
119 u8 control = mps2_uart_read8(port, UARTn_CTRL);
120
121 control &= ~UARTn_CTRL_TX_INT_ENABLE;
122
123 mps2_uart_write8(port, control, UARTn_CTRL);
124}
125
126static void mps2_uart_tx_chars(struct uart_port *port)
127{
128 struct circ_buf *xmit = &port->state->xmit;
129
130 while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
131 if (port->x_char) {
132 mps2_uart_write8(port, port->x_char, UARTn_DATA);
133 port->x_char = 0;
134 port->icount.tx++;
135 continue;
136 }
137
138 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
139 break;
140
141 mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
142 xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
143 port->icount.tx++;
144 }
145
146 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
147 uart_write_wakeup(port);
148
149 if (uart_circ_empty(xmit))
150 mps2_uart_stop_tx(port);
151}
152
153static void mps2_uart_start_tx(struct uart_port *port)
154{
155 u8 control = mps2_uart_read8(port, UARTn_CTRL);
156
157 control |= UARTn_CTRL_TX_INT_ENABLE;
158
159 mps2_uart_write8(port, control, UARTn_CTRL);
160
161 /*
162 * We've just unmasked the TX IRQ and now slow-starting via
163 * polling; if there is enough data to fill up the internal
164 * write buffer in one go, the TX IRQ should assert, at which
165 * point we switch to fully interrupt-driven TX.
166 */
167
168 mps2_uart_tx_chars(port);
169}
170
171static void mps2_uart_stop_rx(struct uart_port *port)
172{
173 u8 control = mps2_uart_read8(port, UARTn_CTRL);
174
175 control &= ~UARTn_CTRL_RX_GRP;
176
177 mps2_uart_write8(port, control, UARTn_CTRL);
178}
179
180static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
181{
182}
183
184static void mps2_uart_rx_chars(struct uart_port *port)
185{
186 struct tty_port *tport = &port->state->port;
187
188 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
189 u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
190
191 port->icount.rx++;
192 tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
193 }
194
195 tty_flip_buffer_push(tport);
196}
197
198static irqreturn_t mps2_uart_rxirq(int irq, void *data)
199{
200 struct uart_port *port = data;
201 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
202
203 if (unlikely(!(irqflag & UARTn_INT_RX)))
204 return IRQ_NONE;
205
206 spin_lock(&port->lock);
207
208 mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
209 mps2_uart_rx_chars(port);
210
211 spin_unlock(&port->lock);
212
213 return IRQ_HANDLED;
214}
215
216static irqreturn_t mps2_uart_txirq(int irq, void *data)
217{
218 struct uart_port *port = data;
219 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
220
221 if (unlikely(!(irqflag & UARTn_INT_TX)))
222 return IRQ_NONE;
223
224 spin_lock(&port->lock);
225
226 mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
227 mps2_uart_tx_chars(port);
228
229 spin_unlock(&port->lock);
230
231 return IRQ_HANDLED;
232}
233
234static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
235{
236 irqreturn_t handled = IRQ_NONE;
237 struct uart_port *port = data;
238 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
239
240 spin_lock(&port->lock);
241
242 if (irqflag & UARTn_INT_RX_OVERRUN) {
243 struct tty_port *tport = &port->state->port;
244
245 mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
246 port->icount.overrun++;
247 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
248 tty_flip_buffer_push(tport);
249 handled = IRQ_HANDLED;
250 }
251
252 /*
253 * It's never been seen in practice and it never *should* happen since
254 * we check if there is enough room in TX buffer before sending data.
255 * So we keep this check in case something suspicious has happened.
256 */
257 if (irqflag & UARTn_INT_TX_OVERRUN) {
258 mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
259 handled = IRQ_HANDLED;
260 }
261
262 spin_unlock(&port->lock);
263
264 return handled;
265}
266
267static int mps2_uart_startup(struct uart_port *port)
268{
269 struct mps2_uart_port *mps_port = to_mps2_port(port);
270 u8 control = mps2_uart_read8(port, UARTn_CTRL);
271 int ret;
272
273 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
274
275 mps2_uart_write8(port, control, UARTn_CTRL);
276
277 ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
278 MAKE_NAME(-rx), mps_port);
279 if (ret) {
280 dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
281 return ret;
282 }
283
284 ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
285 MAKE_NAME(-tx), mps_port);
286 if (ret) {
287 dev_err(port->dev, "failed to register txirq (%d)\n", ret);
288 goto err_free_rxirq;
289 }
290
291 ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
292 MAKE_NAME(-overrun), mps_port);
293
294 if (ret) {
295 dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
296 goto err_free_txirq;
297 }
298
299 control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
300
301 mps2_uart_write8(port, control, UARTn_CTRL);
302
303 return 0;
304
305err_free_txirq:
306 free_irq(mps_port->tx_irq, mps_port);
307err_free_rxirq:
308 free_irq(mps_port->rx_irq, mps_port);
309
310 return ret;
311}
312
313static void mps2_uart_shutdown(struct uart_port *port)
314{
315 struct mps2_uart_port *mps_port = to_mps2_port(port);
316 u8 control = mps2_uart_read8(port, UARTn_CTRL);
317
318 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
319
320 mps2_uart_write8(port, control, UARTn_CTRL);
321
322 free_irq(mps_port->rx_irq, mps_port);
323 free_irq(mps_port->tx_irq, mps_port);
324 free_irq(port->irq, mps_port);
325}
326
327static void
328mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios,
329 struct ktermios *old)
330{
331 unsigned long flags;
332 unsigned int baud, bauddiv;
333
334 termios->c_cflag &= ~(CRTSCTS | CMSPAR);
335 termios->c_cflag &= ~CSIZE;
336 termios->c_cflag |= CS8;
337 termios->c_cflag &= ~PARENB;
338 termios->c_cflag &= ~CSTOPB;
339
340 baud = uart_get_baud_rate(port, termios, old,
341 DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
342 DIV_ROUND_CLOSEST(port->uartclk, 16));
343
344 bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
345
346 spin_lock_irqsave(&port->lock, flags);
347
348 uart_update_timeout(port, termios->c_cflag, baud);
349 mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
350
351 spin_unlock_irqrestore(&port->lock, flags);
352
353 if (tty_termios_baud_rate(termios))
354 tty_termios_encode_baud_rate(termios, baud, baud);
355}
356
357static const char *mps2_uart_type(struct uart_port *port)
358{
359 return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
360}
361
362static void mps2_uart_release_port(struct uart_port *port)
363{
364}
365
366static int mps2_uart_request_port(struct uart_port *port)
367{
368 return 0;
369}
370
371static void mps2_uart_config_port(struct uart_port *port, int type)
372{
373 if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
374 port->type = PORT_MPS2UART;
375}
376
377static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
378{
379 return -EINVAL;
380}
381
382static const struct uart_ops mps2_uart_pops = {
383 .tx_empty = mps2_uart_tx_empty,
384 .set_mctrl = mps2_uart_set_mctrl,
385 .get_mctrl = mps2_uart_get_mctrl,
386 .stop_tx = mps2_uart_stop_tx,
387 .start_tx = mps2_uart_start_tx,
388 .stop_rx = mps2_uart_stop_rx,
389 .break_ctl = mps2_uart_break_ctl,
390 .startup = mps2_uart_startup,
391 .shutdown = mps2_uart_shutdown,
392 .set_termios = mps2_uart_set_termios,
393 .type = mps2_uart_type,
394 .release_port = mps2_uart_release_port,
395 .request_port = mps2_uart_request_port,
396 .config_port = mps2_uart_config_port,
397 .verify_port = mps2_uart_verify_port,
398};
399
400static struct mps2_uart_port mps2_uart_ports[MPS2_MAX_PORTS];
401
402#ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
403static void mps2_uart_console_putchar(struct uart_port *port, int ch)
404{
405 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
406 cpu_relax();
407
408 mps2_uart_write8(port, ch, UARTn_DATA);
409}
410
411static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
412{
413 struct uart_port *port = &mps2_uart_ports[co->index].port;
414
415 uart_console_write(port, s, cnt, mps2_uart_console_putchar);
416}
417
418static int mps2_uart_console_setup(struct console *co, char *options)
419{
420 struct mps2_uart_port *mps_port;
421 int baud = 9600;
422 int bits = 8;
423 int parity = 'n';
424 int flow = 'n';
425
426 if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
427 return -ENODEV;
428
429 mps_port = &mps2_uart_ports[co->index];
430
431 if (options)
432 uart_parse_options(options, &baud, &parity, &bits, &flow);
433
434 return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
435}
436
437static struct uart_driver mps2_uart_driver;
438
439static struct console mps2_uart_console = {
440 .name = SERIAL_NAME,
441 .device = uart_console_device,
442 .write = mps2_uart_console_write,
443 .setup = mps2_uart_console_setup,
444 .flags = CON_PRINTBUFFER,
445 .index = -1,
446 .data = &mps2_uart_driver,
447};
448
449#define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
450
451static void mps2_early_putchar(struct uart_port *port, int ch)
452{
453 while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL)
454 cpu_relax();
455
456 writeb((unsigned char)ch, port->membase + UARTn_DATA);
457}
458
459static void mps2_early_write(struct console *con, const char *s, unsigned int n)
460{
461 struct earlycon_device *dev = con->data;
462
463 uart_console_write(&dev->port, s, n, mps2_early_putchar);
464}
465
466static int __init mps2_early_console_setup(struct earlycon_device *device,
467 const char *opt)
468{
469 if (!device->port.membase)
470 return -ENODEV;
471
472 device->con->write = mps2_early_write;
473
474 return 0;
475}
476
477OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup);
478
479#else
480#define MPS2_SERIAL_CONSOLE NULL
481#endif
482
483static struct uart_driver mps2_uart_driver = {
484 .driver_name = DRIVER_NAME,
485 .dev_name = SERIAL_NAME,
486 .nr = MPS2_MAX_PORTS,
487 .cons = MPS2_SERIAL_CONSOLE,
488};
489
490static struct mps2_uart_port *mps2_of_get_port(struct platform_device *pdev)
491{
492 struct device_node *np = pdev->dev.of_node;
493 int id;
494
495 if (!np)
496 return NULL;
497
498 id = of_alias_get_id(np, "serial");
499 if (id < 0)
500 id = 0;
501
502 if (WARN_ON(id >= MPS2_MAX_PORTS))
503 return NULL;
504
505 mps2_uart_ports[id].port.line = id;
506 return &mps2_uart_ports[id];
507}
508
509static int mps2_init_port(struct mps2_uart_port *mps_port,
510 struct platform_device *pdev)
511{
512 struct resource *res;
513 int ret;
514
515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
516 mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res);
517 if (IS_ERR(mps_port->port.membase))
518 return PTR_ERR(mps_port->port.membase);
519
520 mps_port->port.mapbase = res->start;
521 mps_port->port.mapsize = resource_size(res);
522
523 mps_port->rx_irq = platform_get_irq(pdev, 0);
524 mps_port->tx_irq = platform_get_irq(pdev, 1);
525 mps_port->port.irq = platform_get_irq(pdev, 2);
526
527 mps_port->port.iotype = UPIO_MEM;
528 mps_port->port.flags = UPF_BOOT_AUTOCONF;
529 mps_port->port.fifosize = 1;
530 mps_port->port.ops = &mps2_uart_pops;
531 mps_port->port.dev = &pdev->dev;
532
533 mps_port->clk = devm_clk_get(&pdev->dev, NULL);
534 if (IS_ERR(mps_port->clk))
535 return PTR_ERR(mps_port->clk);
536
537 ret = clk_prepare_enable(mps_port->clk);
538 if (ret)
539 return ret;
540
541 mps_port->port.uartclk = clk_get_rate(mps_port->clk);
542
543 clk_disable_unprepare(mps_port->clk);
544
545 return ret;
546}
547
548static int mps2_serial_probe(struct platform_device *pdev)
549{
550 struct mps2_uart_port *mps_port;
551 int ret;
552
553 mps_port = mps2_of_get_port(pdev);
554 if (!mps_port)
555 return -ENODEV;
556
557 ret = mps2_init_port(mps_port, pdev);
558 if (ret)
559 return ret;
560
561 ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
562 if (ret)
563 return ret;
564
565 platform_set_drvdata(pdev, mps_port);
566
567 return 0;
568}
569
570#ifdef CONFIG_OF
571static const struct of_device_id mps2_match[] = {
572 { .compatible = "arm,mps2-uart", },
573 {},
574};
575#endif
576
577static struct platform_driver mps2_serial_driver = {
578 .probe = mps2_serial_probe,
579
580 .driver = {
581 .name = DRIVER_NAME,
582 .of_match_table = of_match_ptr(mps2_match),
583 .suppress_bind_attrs = true,
584 },
585};
586
587static int __init mps2_uart_init(void)
588{
589 int ret;
590
591 ret = uart_register_driver(&mps2_uart_driver);
592 if (ret)
593 return ret;
594
595 ret = platform_driver_register(&mps2_serial_driver);
596 if (ret)
597 uart_unregister_driver(&mps2_uart_driver);
598
599 return ret;
600}
601arch_initcall(mps2_uart_init);