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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * OMAP2 McSPI controller driver
4 *
5 * Copyright (C) 2005, 2006 Nokia Corporation
6 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
7 * Juha Yrjola <juha.yrjola@nokia.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/interrupt.h>
12#include <linux/module.h>
13#include <linux/device.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/platform_device.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/gcd.h>
27
28#include <linux/spi/spi.h>
29
30#include <linux/platform_data/spi-omap2-mcspi.h>
31
32#define OMAP2_MCSPI_MAX_FREQ 48000000
33#define OMAP2_MCSPI_MAX_DIVIDER 4096
34#define OMAP2_MCSPI_MAX_FIFODEPTH 64
35#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
36#define SPI_AUTOSUSPEND_TIMEOUT 2000
37
38#define OMAP2_MCSPI_REVISION 0x00
39#define OMAP2_MCSPI_SYSSTATUS 0x14
40#define OMAP2_MCSPI_IRQSTATUS 0x18
41#define OMAP2_MCSPI_IRQENABLE 0x1c
42#define OMAP2_MCSPI_WAKEUPENABLE 0x20
43#define OMAP2_MCSPI_SYST 0x24
44#define OMAP2_MCSPI_MODULCTRL 0x28
45#define OMAP2_MCSPI_XFERLEVEL 0x7c
46
47/* per-channel banks, 0x14 bytes each, first is: */
48#define OMAP2_MCSPI_CHCONF0 0x2c
49#define OMAP2_MCSPI_CHSTAT0 0x30
50#define OMAP2_MCSPI_CHCTRL0 0x34
51#define OMAP2_MCSPI_TX0 0x38
52#define OMAP2_MCSPI_RX0 0x3c
53
54/* per-register bitmasks: */
55#define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
56
57#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
58#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
59#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
60
61#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
62#define OMAP2_MCSPI_CHCONF_POL BIT(1)
63#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
64#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
65#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
66#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
67#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
68#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
69#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
70#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
71#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
72#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
73#define OMAP2_MCSPI_CHCONF_IS BIT(18)
74#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
75#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
76#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
77#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
78#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
79
80#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
81#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
82#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
83#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
84
85#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
86#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
87
88#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
89
90/* We have 2 DMA channels per CS, one for RX and one for TX */
91struct omap2_mcspi_dma {
92 struct dma_chan *dma_tx;
93 struct dma_chan *dma_rx;
94
95 struct completion dma_tx_completion;
96 struct completion dma_rx_completion;
97
98 char dma_rx_ch_name[14];
99 char dma_tx_ch_name[14];
100};
101
102/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
103 * cache operations; better heuristics consider wordsize and bitrate.
104 */
105#define DMA_MIN_BYTES 160
106
107
108/*
109 * Used for context save and restore, structure members to be updated whenever
110 * corresponding registers are modified.
111 */
112struct omap2_mcspi_regs {
113 u32 modulctrl;
114 u32 wakeupenable;
115 struct list_head cs;
116};
117
118struct omap2_mcspi {
119 struct completion txdone;
120 struct spi_controller *ctlr;
121 /* Virtual base address of the controller */
122 void __iomem *base;
123 unsigned long phys;
124 /* SPI1 has 4 channels, while SPI2 has 2 */
125 struct omap2_mcspi_dma *dma_channels;
126 struct device *dev;
127 struct omap2_mcspi_regs ctx;
128 struct clk *ref_clk;
129 int fifo_depth;
130 bool target_aborted;
131 unsigned int pin_dir:1;
132 size_t max_xfer_len;
133 u32 ref_clk_hz;
134};
135
136struct omap2_mcspi_cs {
137 void __iomem *base;
138 unsigned long phys;
139 int word_len;
140 u16 mode;
141 struct list_head node;
142 /* Context save and restore shadow register */
143 u32 chconf0, chctrl0;
144};
145
146static inline void mcspi_write_reg(struct spi_controller *ctlr,
147 int idx, u32 val)
148{
149 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
150
151 writel_relaxed(val, mcspi->base + idx);
152}
153
154static inline u32 mcspi_read_reg(struct spi_controller *ctlr, int idx)
155{
156 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
157
158 return readl_relaxed(mcspi->base + idx);
159}
160
161static inline void mcspi_write_cs_reg(const struct spi_device *spi,
162 int idx, u32 val)
163{
164 struct omap2_mcspi_cs *cs = spi->controller_state;
165
166 writel_relaxed(val, cs->base + idx);
167}
168
169static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
170{
171 struct omap2_mcspi_cs *cs = spi->controller_state;
172
173 return readl_relaxed(cs->base + idx);
174}
175
176static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
177{
178 struct omap2_mcspi_cs *cs = spi->controller_state;
179
180 return cs->chconf0;
181}
182
183static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
184{
185 struct omap2_mcspi_cs *cs = spi->controller_state;
186
187 cs->chconf0 = val;
188 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
189 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
190}
191
192static inline int mcspi_bytes_per_word(int word_len)
193{
194 if (word_len <= 8)
195 return 1;
196 else if (word_len <= 16)
197 return 2;
198 else /* word_len <= 32 */
199 return 4;
200}
201
202static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
203 int is_read, int enable)
204{
205 u32 l, rw;
206
207 l = mcspi_cached_chconf0(spi);
208
209 if (is_read) /* 1 is read, 0 write */
210 rw = OMAP2_MCSPI_CHCONF_DMAR;
211 else
212 rw = OMAP2_MCSPI_CHCONF_DMAW;
213
214 if (enable)
215 l |= rw;
216 else
217 l &= ~rw;
218
219 mcspi_write_chconf0(spi, l);
220}
221
222static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
223{
224 struct omap2_mcspi_cs *cs = spi->controller_state;
225 u32 l;
226
227 l = cs->chctrl0;
228 if (enable)
229 l |= OMAP2_MCSPI_CHCTRL_EN;
230 else
231 l &= ~OMAP2_MCSPI_CHCTRL_EN;
232 cs->chctrl0 = l;
233 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
234 /* Flash post-writes */
235 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
236}
237
238static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
239{
240 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
241 u32 l;
242
243 /* The controller handles the inverted chip selects
244 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
245 * the inversion from the core spi_set_cs function.
246 */
247 if (spi->mode & SPI_CS_HIGH)
248 enable = !enable;
249
250 if (spi->controller_state) {
251 int err = pm_runtime_resume_and_get(mcspi->dev);
252 if (err < 0) {
253 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
254 return;
255 }
256
257 l = mcspi_cached_chconf0(spi);
258
259 if (enable)
260 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
261 else
262 l |= OMAP2_MCSPI_CHCONF_FORCE;
263
264 mcspi_write_chconf0(spi, l);
265
266 pm_runtime_mark_last_busy(mcspi->dev);
267 pm_runtime_put_autosuspend(mcspi->dev);
268 }
269}
270
271static void omap2_mcspi_set_mode(struct spi_controller *ctlr)
272{
273 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
274 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
275 u32 l;
276
277 /*
278 * Choose host or target mode
279 */
280 l = mcspi_read_reg(ctlr, OMAP2_MCSPI_MODULCTRL);
281 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
282 if (spi_controller_is_target(ctlr)) {
283 l |= (OMAP2_MCSPI_MODULCTRL_MS);
284 } else {
285 l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
286 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
287 }
288 mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, l);
289
290 ctx->modulctrl = l;
291}
292
293static void omap2_mcspi_set_fifo(const struct spi_device *spi,
294 struct spi_transfer *t, int enable)
295{
296 struct spi_controller *ctlr = spi->controller;
297 struct omap2_mcspi_cs *cs = spi->controller_state;
298 struct omap2_mcspi *mcspi;
299 unsigned int wcnt;
300 int max_fifo_depth, bytes_per_word;
301 u32 chconf, xferlevel;
302
303 mcspi = spi_controller_get_devdata(ctlr);
304
305 chconf = mcspi_cached_chconf0(spi);
306 if (enable) {
307 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
308 if (t->len % bytes_per_word != 0)
309 goto disable_fifo;
310
311 if (t->rx_buf != NULL && t->tx_buf != NULL)
312 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
313 else
314 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
315
316 wcnt = t->len / bytes_per_word;
317 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
318 goto disable_fifo;
319
320 xferlevel = wcnt << 16;
321 if (t->rx_buf != NULL) {
322 chconf |= OMAP2_MCSPI_CHCONF_FFER;
323 xferlevel |= (bytes_per_word - 1) << 8;
324 }
325
326 if (t->tx_buf != NULL) {
327 chconf |= OMAP2_MCSPI_CHCONF_FFET;
328 xferlevel |= bytes_per_word - 1;
329 }
330
331 mcspi_write_reg(ctlr, OMAP2_MCSPI_XFERLEVEL, xferlevel);
332 mcspi_write_chconf0(spi, chconf);
333 mcspi->fifo_depth = max_fifo_depth;
334
335 return;
336 }
337
338disable_fifo:
339 if (t->rx_buf != NULL)
340 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
341
342 if (t->tx_buf != NULL)
343 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
344
345 mcspi_write_chconf0(spi, chconf);
346 mcspi->fifo_depth = 0;
347}
348
349static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
350{
351 unsigned long timeout;
352
353 timeout = jiffies + msecs_to_jiffies(1000);
354 while (!(readl_relaxed(reg) & bit)) {
355 if (time_after(jiffies, timeout)) {
356 if (!(readl_relaxed(reg) & bit))
357 return -ETIMEDOUT;
358 else
359 return 0;
360 }
361 cpu_relax();
362 }
363 return 0;
364}
365
366static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi,
367 struct completion *x)
368{
369 if (spi_controller_is_target(mcspi->ctlr)) {
370 if (wait_for_completion_interruptible(x) ||
371 mcspi->target_aborted)
372 return -EINTR;
373 } else {
374 wait_for_completion(x);
375 }
376
377 return 0;
378}
379
380static void omap2_mcspi_rx_callback(void *data)
381{
382 struct spi_device *spi = data;
383 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
384 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
385
386 /* We must disable the DMA RX request */
387 omap2_mcspi_set_dma_req(spi, 1, 0);
388
389 complete(&mcspi_dma->dma_rx_completion);
390}
391
392static void omap2_mcspi_tx_callback(void *data)
393{
394 struct spi_device *spi = data;
395 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
396 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
397
398 /* We must disable the DMA TX request */
399 omap2_mcspi_set_dma_req(spi, 0, 0);
400
401 complete(&mcspi_dma->dma_tx_completion);
402}
403
404static void omap2_mcspi_tx_dma(struct spi_device *spi,
405 struct spi_transfer *xfer,
406 struct dma_slave_config cfg)
407{
408 struct omap2_mcspi *mcspi;
409 struct omap2_mcspi_dma *mcspi_dma;
410 struct dma_async_tx_descriptor *tx;
411
412 mcspi = spi_controller_get_devdata(spi->controller);
413 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
414
415 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
416
417 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
418 xfer->tx_sg.nents,
419 DMA_MEM_TO_DEV,
420 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
421 if (tx) {
422 tx->callback = omap2_mcspi_tx_callback;
423 tx->callback_param = spi;
424 dmaengine_submit(tx);
425 } else {
426 /* FIXME: fall back to PIO? */
427 }
428 dma_async_issue_pending(mcspi_dma->dma_tx);
429 omap2_mcspi_set_dma_req(spi, 0, 1);
430}
431
432static unsigned
433omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
434 struct dma_slave_config cfg,
435 unsigned es)
436{
437 struct omap2_mcspi *mcspi;
438 struct omap2_mcspi_dma *mcspi_dma;
439 unsigned int count, transfer_reduction = 0;
440 struct scatterlist *sg_out[2];
441 int nb_sizes = 0, out_mapped_nents[2], ret, x;
442 size_t sizes[2];
443 u32 l;
444 int elements = 0;
445 int word_len, element_count;
446 struct omap2_mcspi_cs *cs = spi->controller_state;
447 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
448 struct dma_async_tx_descriptor *tx;
449
450 mcspi = spi_controller_get_devdata(spi->controller);
451 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
452 count = xfer->len;
453
454 /*
455 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
456 * it mentions reducing DMA transfer length by one element in host
457 * normal mode.
458 */
459 if (mcspi->fifo_depth == 0)
460 transfer_reduction = es;
461
462 word_len = cs->word_len;
463 l = mcspi_cached_chconf0(spi);
464
465 if (word_len <= 8)
466 element_count = count;
467 else if (word_len <= 16)
468 element_count = count >> 1;
469 else /* word_len <= 32 */
470 element_count = count >> 2;
471
472
473 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
474
475 /*
476 * Reduce DMA transfer length by one more if McSPI is
477 * configured in turbo mode.
478 */
479 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
480 transfer_reduction += es;
481
482 if (transfer_reduction) {
483 /* Split sgl into two. The second sgl won't be used. */
484 sizes[0] = count - transfer_reduction;
485 sizes[1] = transfer_reduction;
486 nb_sizes = 2;
487 } else {
488 /*
489 * Don't bother splitting the sgl. This essentially
490 * clones the original sgl.
491 */
492 sizes[0] = count;
493 nb_sizes = 1;
494 }
495
496 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes,
497 sizes, sg_out, out_mapped_nents, GFP_KERNEL);
498
499 if (ret < 0) {
500 dev_err(&spi->dev, "sg_split failed\n");
501 return 0;
502 }
503
504 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0],
505 out_mapped_nents[0], DMA_DEV_TO_MEM,
506 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
507 if (tx) {
508 tx->callback = omap2_mcspi_rx_callback;
509 tx->callback_param = spi;
510 dmaengine_submit(tx);
511 } else {
512 /* FIXME: fall back to PIO? */
513 }
514
515 dma_async_issue_pending(mcspi_dma->dma_rx);
516 omap2_mcspi_set_dma_req(spi, 1, 1);
517
518 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
519 if (ret || mcspi->target_aborted) {
520 dmaengine_terminate_sync(mcspi_dma->dma_rx);
521 omap2_mcspi_set_dma_req(spi, 1, 0);
522 return 0;
523 }
524
525 for (x = 0; x < nb_sizes; x++)
526 kfree(sg_out[x]);
527
528 if (mcspi->fifo_depth > 0)
529 return count;
530
531 /*
532 * Due to the DMA transfer length reduction the missing bytes must
533 * be read manually to receive all of the expected data.
534 */
535 omap2_mcspi_set_enable(spi, 0);
536
537 elements = element_count - 1;
538
539 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
540 elements--;
541
542 if (!mcspi_wait_for_reg_bit(chstat_reg,
543 OMAP2_MCSPI_CHSTAT_RXS)) {
544 u32 w;
545
546 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
547 if (word_len <= 8)
548 ((u8 *)xfer->rx_buf)[elements++] = w;
549 else if (word_len <= 16)
550 ((u16 *)xfer->rx_buf)[elements++] = w;
551 else /* word_len <= 32 */
552 ((u32 *)xfer->rx_buf)[elements++] = w;
553 } else {
554 int bytes_per_word = mcspi_bytes_per_word(word_len);
555 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
556 count -= (bytes_per_word << 1);
557 omap2_mcspi_set_enable(spi, 1);
558 return count;
559 }
560 }
561 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
562 u32 w;
563
564 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
565 if (word_len <= 8)
566 ((u8 *)xfer->rx_buf)[elements] = w;
567 else if (word_len <= 16)
568 ((u16 *)xfer->rx_buf)[elements] = w;
569 else /* word_len <= 32 */
570 ((u32 *)xfer->rx_buf)[elements] = w;
571 } else {
572 dev_err(&spi->dev, "DMA RX last word empty\n");
573 count -= mcspi_bytes_per_word(word_len);
574 }
575 omap2_mcspi_set_enable(spi, 1);
576 return count;
577}
578
579static unsigned
580omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
581{
582 struct omap2_mcspi *mcspi;
583 struct omap2_mcspi_cs *cs = spi->controller_state;
584 struct omap2_mcspi_dma *mcspi_dma;
585 unsigned int count;
586 u8 *rx;
587 const u8 *tx;
588 struct dma_slave_config cfg;
589 enum dma_slave_buswidth width;
590 unsigned es;
591 void __iomem *chstat_reg;
592 void __iomem *irqstat_reg;
593 int wait_res;
594
595 mcspi = spi_controller_get_devdata(spi->controller);
596 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
597
598 if (cs->word_len <= 8) {
599 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
600 es = 1;
601 } else if (cs->word_len <= 16) {
602 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
603 es = 2;
604 } else {
605 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
606 es = 4;
607 }
608
609 count = xfer->len;
610
611 memset(&cfg, 0, sizeof(cfg));
612 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
613 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
614 cfg.src_addr_width = width;
615 cfg.dst_addr_width = width;
616 cfg.src_maxburst = 1;
617 cfg.dst_maxburst = 1;
618
619 rx = xfer->rx_buf;
620 tx = xfer->tx_buf;
621
622 mcspi->target_aborted = false;
623 reinit_completion(&mcspi_dma->dma_tx_completion);
624 reinit_completion(&mcspi_dma->dma_rx_completion);
625 reinit_completion(&mcspi->txdone);
626 if (tx) {
627 /* Enable EOW IRQ to know end of tx in target mode */
628 if (spi_controller_is_target(spi->controller))
629 mcspi_write_reg(spi->controller,
630 OMAP2_MCSPI_IRQENABLE,
631 OMAP2_MCSPI_IRQSTATUS_EOW);
632 omap2_mcspi_tx_dma(spi, xfer, cfg);
633 }
634
635 if (rx != NULL)
636 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
637
638 if (tx != NULL) {
639 int ret;
640
641 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
642 if (ret || mcspi->target_aborted) {
643 dmaengine_terminate_sync(mcspi_dma->dma_tx);
644 omap2_mcspi_set_dma_req(spi, 0, 0);
645 return 0;
646 }
647
648 if (spi_controller_is_target(mcspi->ctlr)) {
649 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
650 if (ret || mcspi->target_aborted)
651 return 0;
652 }
653
654 if (mcspi->fifo_depth > 0) {
655 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
656
657 if (mcspi_wait_for_reg_bit(irqstat_reg,
658 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
659 dev_err(&spi->dev, "EOW timed out\n");
660
661 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS,
662 OMAP2_MCSPI_IRQSTATUS_EOW);
663 }
664
665 /* for TX_ONLY mode, be sure all words have shifted out */
666 if (rx == NULL) {
667 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
668 if (mcspi->fifo_depth > 0) {
669 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
670 OMAP2_MCSPI_CHSTAT_TXFFE);
671 if (wait_res < 0)
672 dev_err(&spi->dev, "TXFFE timed out\n");
673 } else {
674 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
675 OMAP2_MCSPI_CHSTAT_TXS);
676 if (wait_res < 0)
677 dev_err(&spi->dev, "TXS timed out\n");
678 }
679 if (wait_res >= 0 &&
680 (mcspi_wait_for_reg_bit(chstat_reg,
681 OMAP2_MCSPI_CHSTAT_EOT) < 0))
682 dev_err(&spi->dev, "EOT timed out\n");
683 }
684 }
685 return count;
686}
687
688static unsigned
689omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
690{
691 struct omap2_mcspi_cs *cs = spi->controller_state;
692 unsigned int count, c;
693 u32 l;
694 void __iomem *base = cs->base;
695 void __iomem *tx_reg;
696 void __iomem *rx_reg;
697 void __iomem *chstat_reg;
698 int word_len;
699
700 count = xfer->len;
701 c = count;
702 word_len = cs->word_len;
703
704 l = mcspi_cached_chconf0(spi);
705
706 /* We store the pre-calculated register addresses on stack to speed
707 * up the transfer loop. */
708 tx_reg = base + OMAP2_MCSPI_TX0;
709 rx_reg = base + OMAP2_MCSPI_RX0;
710 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
711
712 if (c < (word_len>>3))
713 return 0;
714
715 if (word_len <= 8) {
716 u8 *rx;
717 const u8 *tx;
718
719 rx = xfer->rx_buf;
720 tx = xfer->tx_buf;
721
722 do {
723 c -= 1;
724 if (tx != NULL) {
725 if (mcspi_wait_for_reg_bit(chstat_reg,
726 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
727 dev_err(&spi->dev, "TXS timed out\n");
728 goto out;
729 }
730 dev_vdbg(&spi->dev, "write-%d %02x\n",
731 word_len, *tx);
732 writel_relaxed(*tx++, tx_reg);
733 }
734 if (rx != NULL) {
735 if (mcspi_wait_for_reg_bit(chstat_reg,
736 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
737 dev_err(&spi->dev, "RXS timed out\n");
738 goto out;
739 }
740
741 if (c == 1 && tx == NULL &&
742 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
743 omap2_mcspi_set_enable(spi, 0);
744 *rx++ = readl_relaxed(rx_reg);
745 dev_vdbg(&spi->dev, "read-%d %02x\n",
746 word_len, *(rx - 1));
747 if (mcspi_wait_for_reg_bit(chstat_reg,
748 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
749 dev_err(&spi->dev,
750 "RXS timed out\n");
751 goto out;
752 }
753 c = 0;
754 } else if (c == 0 && tx == NULL) {
755 omap2_mcspi_set_enable(spi, 0);
756 }
757
758 *rx++ = readl_relaxed(rx_reg);
759 dev_vdbg(&spi->dev, "read-%d %02x\n",
760 word_len, *(rx - 1));
761 }
762 /* Add word delay between each word */
763 spi_delay_exec(&xfer->word_delay, xfer);
764 } while (c);
765 } else if (word_len <= 16) {
766 u16 *rx;
767 const u16 *tx;
768
769 rx = xfer->rx_buf;
770 tx = xfer->tx_buf;
771 do {
772 c -= 2;
773 if (tx != NULL) {
774 if (mcspi_wait_for_reg_bit(chstat_reg,
775 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
776 dev_err(&spi->dev, "TXS timed out\n");
777 goto out;
778 }
779 dev_vdbg(&spi->dev, "write-%d %04x\n",
780 word_len, *tx);
781 writel_relaxed(*tx++, tx_reg);
782 }
783 if (rx != NULL) {
784 if (mcspi_wait_for_reg_bit(chstat_reg,
785 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
786 dev_err(&spi->dev, "RXS timed out\n");
787 goto out;
788 }
789
790 if (c == 2 && tx == NULL &&
791 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
792 omap2_mcspi_set_enable(spi, 0);
793 *rx++ = readl_relaxed(rx_reg);
794 dev_vdbg(&spi->dev, "read-%d %04x\n",
795 word_len, *(rx - 1));
796 if (mcspi_wait_for_reg_bit(chstat_reg,
797 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
798 dev_err(&spi->dev,
799 "RXS timed out\n");
800 goto out;
801 }
802 c = 0;
803 } else if (c == 0 && tx == NULL) {
804 omap2_mcspi_set_enable(spi, 0);
805 }
806
807 *rx++ = readl_relaxed(rx_reg);
808 dev_vdbg(&spi->dev, "read-%d %04x\n",
809 word_len, *(rx - 1));
810 }
811 /* Add word delay between each word */
812 spi_delay_exec(&xfer->word_delay, xfer);
813 } while (c >= 2);
814 } else if (word_len <= 32) {
815 u32 *rx;
816 const u32 *tx;
817
818 rx = xfer->rx_buf;
819 tx = xfer->tx_buf;
820 do {
821 c -= 4;
822 if (tx != NULL) {
823 if (mcspi_wait_for_reg_bit(chstat_reg,
824 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
825 dev_err(&spi->dev, "TXS timed out\n");
826 goto out;
827 }
828 dev_vdbg(&spi->dev, "write-%d %08x\n",
829 word_len, *tx);
830 writel_relaxed(*tx++, tx_reg);
831 }
832 if (rx != NULL) {
833 if (mcspi_wait_for_reg_bit(chstat_reg,
834 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
835 dev_err(&spi->dev, "RXS timed out\n");
836 goto out;
837 }
838
839 if (c == 4 && tx == NULL &&
840 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
841 omap2_mcspi_set_enable(spi, 0);
842 *rx++ = readl_relaxed(rx_reg);
843 dev_vdbg(&spi->dev, "read-%d %08x\n",
844 word_len, *(rx - 1));
845 if (mcspi_wait_for_reg_bit(chstat_reg,
846 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
847 dev_err(&spi->dev,
848 "RXS timed out\n");
849 goto out;
850 }
851 c = 0;
852 } else if (c == 0 && tx == NULL) {
853 omap2_mcspi_set_enable(spi, 0);
854 }
855
856 *rx++ = readl_relaxed(rx_reg);
857 dev_vdbg(&spi->dev, "read-%d %08x\n",
858 word_len, *(rx - 1));
859 }
860 /* Add word delay between each word */
861 spi_delay_exec(&xfer->word_delay, xfer);
862 } while (c >= 4);
863 }
864
865 /* for TX_ONLY mode, be sure all words have shifted out */
866 if (xfer->rx_buf == NULL) {
867 if (mcspi_wait_for_reg_bit(chstat_reg,
868 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
869 dev_err(&spi->dev, "TXS timed out\n");
870 } else if (mcspi_wait_for_reg_bit(chstat_reg,
871 OMAP2_MCSPI_CHSTAT_EOT) < 0)
872 dev_err(&spi->dev, "EOT timed out\n");
873
874 /* disable chan to purge rx datas received in TX_ONLY transfer,
875 * otherwise these rx datas will affect the direct following
876 * RX_ONLY transfer.
877 */
878 omap2_mcspi_set_enable(spi, 0);
879 }
880out:
881 omap2_mcspi_set_enable(spi, 1);
882 return count - c;
883}
884
885static u32 omap2_mcspi_calc_divisor(u32 speed_hz, u32 ref_clk_hz)
886{
887 u32 div;
888
889 for (div = 0; div < 15; div++)
890 if (speed_hz >= (ref_clk_hz >> div))
891 return div;
892
893 return 15;
894}
895
896/* called only when no transfer is active to this device */
897static int omap2_mcspi_setup_transfer(struct spi_device *spi,
898 struct spi_transfer *t)
899{
900 struct omap2_mcspi_cs *cs = spi->controller_state;
901 struct omap2_mcspi *mcspi;
902 u32 ref_clk_hz, l = 0, clkd = 0, div, extclk = 0, clkg = 0;
903 u8 word_len = spi->bits_per_word;
904 u32 speed_hz = spi->max_speed_hz;
905
906 mcspi = spi_controller_get_devdata(spi->controller);
907
908 if (t != NULL && t->bits_per_word)
909 word_len = t->bits_per_word;
910
911 cs->word_len = word_len;
912
913 if (t && t->speed_hz)
914 speed_hz = t->speed_hz;
915
916 ref_clk_hz = mcspi->ref_clk_hz;
917 speed_hz = min_t(u32, speed_hz, ref_clk_hz);
918 if (speed_hz < (ref_clk_hz / OMAP2_MCSPI_MAX_DIVIDER)) {
919 clkd = omap2_mcspi_calc_divisor(speed_hz, ref_clk_hz);
920 speed_hz = ref_clk_hz >> clkd;
921 clkg = 0;
922 } else {
923 div = (ref_clk_hz + speed_hz - 1) / speed_hz;
924 speed_hz = ref_clk_hz / div;
925 clkd = (div - 1) & 0xf;
926 extclk = (div - 1) >> 4;
927 clkg = OMAP2_MCSPI_CHCONF_CLKG;
928 }
929
930 l = mcspi_cached_chconf0(spi);
931
932 /* standard 4-wire host mode: SCK, MOSI/out, MISO/in, nCS
933 * REVISIT: this controller could support SPI_3WIRE mode.
934 */
935 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
936 l &= ~OMAP2_MCSPI_CHCONF_IS;
937 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
938 l |= OMAP2_MCSPI_CHCONF_DPE0;
939 } else {
940 l |= OMAP2_MCSPI_CHCONF_IS;
941 l |= OMAP2_MCSPI_CHCONF_DPE1;
942 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
943 }
944
945 /* wordlength */
946 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
947 l |= (word_len - 1) << 7;
948
949 /* set chipselect polarity; manage with FORCE */
950 if (!(spi->mode & SPI_CS_HIGH))
951 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
952 else
953 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
954
955 /* set clock divisor */
956 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
957 l |= clkd << 2;
958
959 /* set clock granularity */
960 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
961 l |= clkg;
962 if (clkg) {
963 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
964 cs->chctrl0 |= extclk << 8;
965 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
966 }
967
968 /* set SPI mode 0..3 */
969 if (spi->mode & SPI_CPOL)
970 l |= OMAP2_MCSPI_CHCONF_POL;
971 else
972 l &= ~OMAP2_MCSPI_CHCONF_POL;
973 if (spi->mode & SPI_CPHA)
974 l |= OMAP2_MCSPI_CHCONF_PHA;
975 else
976 l &= ~OMAP2_MCSPI_CHCONF_PHA;
977
978 mcspi_write_chconf0(spi, l);
979
980 cs->mode = spi->mode;
981
982 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
983 speed_hz,
984 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
985 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
986
987 return 0;
988}
989
990/*
991 * Note that we currently allow DMA only if we get a channel
992 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
993 */
994static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
995 struct omap2_mcspi_dma *mcspi_dma)
996{
997 int ret = 0;
998
999 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
1000 mcspi_dma->dma_rx_ch_name);
1001 if (IS_ERR(mcspi_dma->dma_rx)) {
1002 ret = PTR_ERR(mcspi_dma->dma_rx);
1003 mcspi_dma->dma_rx = NULL;
1004 goto no_dma;
1005 }
1006
1007 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
1008 mcspi_dma->dma_tx_ch_name);
1009 if (IS_ERR(mcspi_dma->dma_tx)) {
1010 ret = PTR_ERR(mcspi_dma->dma_tx);
1011 mcspi_dma->dma_tx = NULL;
1012 dma_release_channel(mcspi_dma->dma_rx);
1013 mcspi_dma->dma_rx = NULL;
1014 }
1015
1016 init_completion(&mcspi_dma->dma_rx_completion);
1017 init_completion(&mcspi_dma->dma_tx_completion);
1018
1019no_dma:
1020 return ret;
1021}
1022
1023static void omap2_mcspi_release_dma(struct spi_controller *ctlr)
1024{
1025 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1026 struct omap2_mcspi_dma *mcspi_dma;
1027 int i;
1028
1029 for (i = 0; i < ctlr->num_chipselect; i++) {
1030 mcspi_dma = &mcspi->dma_channels[i];
1031
1032 if (mcspi_dma->dma_rx) {
1033 dma_release_channel(mcspi_dma->dma_rx);
1034 mcspi_dma->dma_rx = NULL;
1035 }
1036 if (mcspi_dma->dma_tx) {
1037 dma_release_channel(mcspi_dma->dma_tx);
1038 mcspi_dma->dma_tx = NULL;
1039 }
1040 }
1041}
1042
1043static void omap2_mcspi_cleanup(struct spi_device *spi)
1044{
1045 struct omap2_mcspi_cs *cs;
1046
1047 if (spi->controller_state) {
1048 /* Unlink controller state from context save list */
1049 cs = spi->controller_state;
1050 list_del(&cs->node);
1051
1052 kfree(cs);
1053 }
1054}
1055
1056static int omap2_mcspi_setup(struct spi_device *spi)
1057{
1058 bool initial_setup = false;
1059 int ret;
1060 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1061 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1062 struct omap2_mcspi_cs *cs = spi->controller_state;
1063
1064 if (!cs) {
1065 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
1066 if (!cs)
1067 return -ENOMEM;
1068 cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14;
1069 cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14;
1070 cs->mode = 0;
1071 cs->chconf0 = 0;
1072 cs->chctrl0 = 0;
1073 spi->controller_state = cs;
1074 /* Link this to context save list */
1075 list_add_tail(&cs->node, &ctx->cs);
1076 initial_setup = true;
1077 }
1078
1079 ret = pm_runtime_resume_and_get(mcspi->dev);
1080 if (ret < 0) {
1081 if (initial_setup)
1082 omap2_mcspi_cleanup(spi);
1083
1084 return ret;
1085 }
1086
1087 ret = omap2_mcspi_setup_transfer(spi, NULL);
1088 if (ret && initial_setup)
1089 omap2_mcspi_cleanup(spi);
1090
1091 pm_runtime_mark_last_busy(mcspi->dev);
1092 pm_runtime_put_autosuspend(mcspi->dev);
1093
1094 return ret;
1095}
1096
1097static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
1098{
1099 struct omap2_mcspi *mcspi = data;
1100 u32 irqstat;
1101
1102 irqstat = mcspi_read_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS);
1103 if (!irqstat)
1104 return IRQ_NONE;
1105
1106 /* Disable IRQ and wakeup target xfer task */
1107 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQENABLE, 0);
1108 if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
1109 complete(&mcspi->txdone);
1110
1111 return IRQ_HANDLED;
1112}
1113
1114static int omap2_mcspi_target_abort(struct spi_controller *ctlr)
1115{
1116 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1117 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
1118
1119 mcspi->target_aborted = true;
1120 complete(&mcspi_dma->dma_rx_completion);
1121 complete(&mcspi_dma->dma_tx_completion);
1122 complete(&mcspi->txdone);
1123
1124 return 0;
1125}
1126
1127static int omap2_mcspi_transfer_one(struct spi_controller *ctlr,
1128 struct spi_device *spi,
1129 struct spi_transfer *t)
1130{
1131
1132 /* We only enable one channel at a time -- the one whose message is
1133 * -- although this controller would gladly
1134 * arbitrate among multiple channels. This corresponds to "single
1135 * channel" host mode. As a side effect, we need to manage the
1136 * chipselect with the FORCE bit ... CS != channel enable.
1137 */
1138
1139 struct omap2_mcspi *mcspi;
1140 struct omap2_mcspi_dma *mcspi_dma;
1141 struct omap2_mcspi_cs *cs;
1142 struct omap2_mcspi_device_config *cd;
1143 int par_override = 0;
1144 int status = 0;
1145 u32 chconf;
1146
1147 mcspi = spi_controller_get_devdata(ctlr);
1148 mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0);
1149 cs = spi->controller_state;
1150 cd = spi->controller_data;
1151
1152 /*
1153 * The target driver could have changed spi->mode in which case
1154 * it will be different from cs->mode (the current hardware setup).
1155 * If so, set par_override (even though its not a parity issue) so
1156 * omap2_mcspi_setup_transfer will be called to configure the hardware
1157 * with the correct mode on the first iteration of the loop below.
1158 */
1159 if (spi->mode != cs->mode)
1160 par_override = 1;
1161
1162 omap2_mcspi_set_enable(spi, 0);
1163
1164 if (spi_get_csgpiod(spi, 0))
1165 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1166
1167 if (par_override ||
1168 (t->speed_hz != spi->max_speed_hz) ||
1169 (t->bits_per_word != spi->bits_per_word)) {
1170 par_override = 1;
1171 status = omap2_mcspi_setup_transfer(spi, t);
1172 if (status < 0)
1173 goto out;
1174 if (t->speed_hz == spi->max_speed_hz &&
1175 t->bits_per_word == spi->bits_per_word)
1176 par_override = 0;
1177 }
1178 if (cd && cd->cs_per_word) {
1179 chconf = mcspi->ctx.modulctrl;
1180 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1181 mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, chconf);
1182 mcspi->ctx.modulctrl =
1183 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1184 }
1185
1186 chconf = mcspi_cached_chconf0(spi);
1187 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1188 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1189
1190 if (t->tx_buf == NULL)
1191 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1192 else if (t->rx_buf == NULL)
1193 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1194
1195 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1196 /* Turbo mode is for more than one word */
1197 if (t->len > ((cs->word_len + 7) >> 3))
1198 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1199 }
1200
1201 mcspi_write_chconf0(spi, chconf);
1202
1203 if (t->len) {
1204 unsigned count;
1205
1206 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1207 ctlr->cur_msg_mapped &&
1208 ctlr->can_dma(ctlr, spi, t))
1209 omap2_mcspi_set_fifo(spi, t, 1);
1210
1211 omap2_mcspi_set_enable(spi, 1);
1212
1213 /* RX_ONLY mode needs dummy data in TX reg */
1214 if (t->tx_buf == NULL)
1215 writel_relaxed(0, cs->base
1216 + OMAP2_MCSPI_TX0);
1217
1218 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1219 ctlr->cur_msg_mapped &&
1220 ctlr->can_dma(ctlr, spi, t))
1221 count = omap2_mcspi_txrx_dma(spi, t);
1222 else
1223 count = omap2_mcspi_txrx_pio(spi, t);
1224
1225 if (count != t->len) {
1226 status = -EIO;
1227 goto out;
1228 }
1229 }
1230
1231 omap2_mcspi_set_enable(spi, 0);
1232
1233 if (mcspi->fifo_depth > 0)
1234 omap2_mcspi_set_fifo(spi, t, 0);
1235
1236out:
1237 /* Restore defaults if they were overriden */
1238 if (par_override) {
1239 par_override = 0;
1240 status = omap2_mcspi_setup_transfer(spi, NULL);
1241 }
1242
1243 if (cd && cd->cs_per_word) {
1244 chconf = mcspi->ctx.modulctrl;
1245 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1246 mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, chconf);
1247 mcspi->ctx.modulctrl =
1248 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1249 }
1250
1251 omap2_mcspi_set_enable(spi, 0);
1252
1253 if (spi_get_csgpiod(spi, 0))
1254 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1255
1256 if (mcspi->fifo_depth > 0 && t)
1257 omap2_mcspi_set_fifo(spi, t, 0);
1258
1259 return status;
1260}
1261
1262static int omap2_mcspi_prepare_message(struct spi_controller *ctlr,
1263 struct spi_message *msg)
1264{
1265 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1266 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1267 struct omap2_mcspi_cs *cs;
1268
1269 /* Only a single channel can have the FORCE bit enabled
1270 * in its chconf0 register.
1271 * Scan all channels and disable them except the current one.
1272 * A FORCE can remain from a last transfer having cs_change enabled
1273 */
1274 list_for_each_entry(cs, &ctx->cs, node) {
1275 if (msg->spi->controller_state == cs)
1276 continue;
1277
1278 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1279 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1280 writel_relaxed(cs->chconf0,
1281 cs->base + OMAP2_MCSPI_CHCONF0);
1282 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1283 }
1284 }
1285
1286 return 0;
1287}
1288
1289static bool omap2_mcspi_can_dma(struct spi_controller *ctlr,
1290 struct spi_device *spi,
1291 struct spi_transfer *xfer)
1292{
1293 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1294 struct omap2_mcspi_dma *mcspi_dma =
1295 &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
1296
1297 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
1298 return false;
1299
1300 if (spi_controller_is_target(ctlr))
1301 return true;
1302
1303 ctlr->dma_rx = mcspi_dma->dma_rx;
1304 ctlr->dma_tx = mcspi_dma->dma_tx;
1305
1306 return (xfer->len >= DMA_MIN_BYTES);
1307}
1308
1309static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
1310{
1311 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1312 struct omap2_mcspi_dma *mcspi_dma =
1313 &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
1314
1315 if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
1316 return mcspi->max_xfer_len;
1317
1318 return SIZE_MAX;
1319}
1320
1321static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
1322{
1323 struct spi_controller *ctlr = mcspi->ctlr;
1324 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1325 int ret = 0;
1326
1327 ret = pm_runtime_resume_and_get(mcspi->dev);
1328 if (ret < 0)
1329 return ret;
1330
1331 mcspi_write_reg(ctlr, OMAP2_MCSPI_WAKEUPENABLE,
1332 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1333 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1334
1335 omap2_mcspi_set_mode(ctlr);
1336 pm_runtime_mark_last_busy(mcspi->dev);
1337 pm_runtime_put_autosuspend(mcspi->dev);
1338 return 0;
1339}
1340
1341static int omap_mcspi_runtime_suspend(struct device *dev)
1342{
1343 int error;
1344
1345 error = pinctrl_pm_select_idle_state(dev);
1346 if (error)
1347 dev_warn(dev, "%s: failed to set pins: %i\n", __func__, error);
1348
1349 return 0;
1350}
1351
1352/*
1353 * When SPI wake up from off-mode, CS is in activate state. If it was in
1354 * inactive state when driver was suspend, then force it to inactive state at
1355 * wake up.
1356 */
1357static int omap_mcspi_runtime_resume(struct device *dev)
1358{
1359 struct spi_controller *ctlr = dev_get_drvdata(dev);
1360 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1361 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1362 struct omap2_mcspi_cs *cs;
1363 int error;
1364
1365 error = pinctrl_pm_select_default_state(dev);
1366 if (error)
1367 dev_warn(dev, "%s: failed to set pins: %i\n", __func__, error);
1368
1369 /* McSPI: context restore */
1370 mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1371 mcspi_write_reg(ctlr, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1372
1373 list_for_each_entry(cs, &ctx->cs, node) {
1374 /*
1375 * We need to toggle CS state for OMAP take this
1376 * change in account.
1377 */
1378 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1379 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1380 writel_relaxed(cs->chconf0,
1381 cs->base + OMAP2_MCSPI_CHCONF0);
1382 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1383 writel_relaxed(cs->chconf0,
1384 cs->base + OMAP2_MCSPI_CHCONF0);
1385 } else {
1386 writel_relaxed(cs->chconf0,
1387 cs->base + OMAP2_MCSPI_CHCONF0);
1388 }
1389 }
1390
1391 return 0;
1392}
1393
1394static struct omap2_mcspi_platform_config omap2_pdata = {
1395 .regs_offset = 0,
1396};
1397
1398static struct omap2_mcspi_platform_config omap4_pdata = {
1399 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1400};
1401
1402static struct omap2_mcspi_platform_config am654_pdata = {
1403 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1404 .max_xfer_len = SZ_4K - 1,
1405};
1406
1407static const struct of_device_id omap_mcspi_of_match[] = {
1408 {
1409 .compatible = "ti,omap2-mcspi",
1410 .data = &omap2_pdata,
1411 },
1412 {
1413 .compatible = "ti,omap4-mcspi",
1414 .data = &omap4_pdata,
1415 },
1416 {
1417 .compatible = "ti,am654-mcspi",
1418 .data = &am654_pdata,
1419 },
1420 { },
1421};
1422MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1423
1424static int omap2_mcspi_probe(struct platform_device *pdev)
1425{
1426 struct spi_controller *ctlr;
1427 const struct omap2_mcspi_platform_config *pdata;
1428 struct omap2_mcspi *mcspi;
1429 struct resource *r;
1430 int status = 0, i;
1431 u32 regs_offset = 0;
1432 struct device_node *node = pdev->dev.of_node;
1433 const struct of_device_id *match;
1434
1435 if (of_property_read_bool(node, "spi-slave"))
1436 ctlr = spi_alloc_target(&pdev->dev, sizeof(*mcspi));
1437 else
1438 ctlr = spi_alloc_host(&pdev->dev, sizeof(*mcspi));
1439 if (!ctlr)
1440 return -ENOMEM;
1441
1442 /* the spi->mode bits understood by this driver: */
1443 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1444 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1445 ctlr->setup = omap2_mcspi_setup;
1446 ctlr->auto_runtime_pm = true;
1447 ctlr->prepare_message = omap2_mcspi_prepare_message;
1448 ctlr->can_dma = omap2_mcspi_can_dma;
1449 ctlr->transfer_one = omap2_mcspi_transfer_one;
1450 ctlr->set_cs = omap2_mcspi_set_cs;
1451 ctlr->cleanup = omap2_mcspi_cleanup;
1452 ctlr->target_abort = omap2_mcspi_target_abort;
1453 ctlr->dev.of_node = node;
1454 ctlr->use_gpio_descriptors = true;
1455
1456 platform_set_drvdata(pdev, ctlr);
1457
1458 mcspi = spi_controller_get_devdata(ctlr);
1459 mcspi->ctlr = ctlr;
1460
1461 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1462 if (match) {
1463 u32 num_cs = 1; /* default number of chipselect */
1464 pdata = match->data;
1465
1466 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1467 ctlr->num_chipselect = num_cs;
1468 if (of_property_read_bool(node, "ti,pindir-d0-out-d1-in"))
1469 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1470 } else {
1471 pdata = dev_get_platdata(&pdev->dev);
1472 ctlr->num_chipselect = pdata->num_cs;
1473 mcspi->pin_dir = pdata->pin_dir;
1474 }
1475 regs_offset = pdata->regs_offset;
1476 if (pdata->max_xfer_len) {
1477 mcspi->max_xfer_len = pdata->max_xfer_len;
1478 ctlr->max_transfer_size = omap2_mcspi_max_xfer_size;
1479 }
1480
1481 mcspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
1482 if (IS_ERR(mcspi->base)) {
1483 status = PTR_ERR(mcspi->base);
1484 goto free_ctlr;
1485 }
1486 mcspi->phys = r->start + regs_offset;
1487 mcspi->base += regs_offset;
1488
1489 mcspi->dev = &pdev->dev;
1490
1491 INIT_LIST_HEAD(&mcspi->ctx.cs);
1492
1493 mcspi->dma_channels = devm_kcalloc(&pdev->dev, ctlr->num_chipselect,
1494 sizeof(struct omap2_mcspi_dma),
1495 GFP_KERNEL);
1496 if (mcspi->dma_channels == NULL) {
1497 status = -ENOMEM;
1498 goto free_ctlr;
1499 }
1500
1501 for (i = 0; i < ctlr->num_chipselect; i++) {
1502 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1503 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1504
1505 status = omap2_mcspi_request_dma(mcspi,
1506 &mcspi->dma_channels[i]);
1507 if (status == -EPROBE_DEFER)
1508 goto free_ctlr;
1509 }
1510
1511 status = platform_get_irq(pdev, 0);
1512 if (status < 0)
1513 goto free_ctlr;
1514 init_completion(&mcspi->txdone);
1515 status = devm_request_irq(&pdev->dev, status,
1516 omap2_mcspi_irq_handler, 0, pdev->name,
1517 mcspi);
1518 if (status) {
1519 dev_err(&pdev->dev, "Cannot request IRQ");
1520 goto free_ctlr;
1521 }
1522
1523 mcspi->ref_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
1524 if (mcspi->ref_clk)
1525 mcspi->ref_clk_hz = clk_get_rate(mcspi->ref_clk);
1526 else
1527 mcspi->ref_clk_hz = OMAP2_MCSPI_MAX_FREQ;
1528 ctlr->max_speed_hz = mcspi->ref_clk_hz;
1529 ctlr->min_speed_hz = mcspi->ref_clk_hz >> 15;
1530
1531 pm_runtime_use_autosuspend(&pdev->dev);
1532 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1533 pm_runtime_enable(&pdev->dev);
1534
1535 status = omap2_mcspi_controller_setup(mcspi);
1536 if (status < 0)
1537 goto disable_pm;
1538
1539 status = devm_spi_register_controller(&pdev->dev, ctlr);
1540 if (status < 0)
1541 goto disable_pm;
1542
1543 return status;
1544
1545disable_pm:
1546 pm_runtime_dont_use_autosuspend(&pdev->dev);
1547 pm_runtime_put_sync(&pdev->dev);
1548 pm_runtime_disable(&pdev->dev);
1549free_ctlr:
1550 omap2_mcspi_release_dma(ctlr);
1551 spi_controller_put(ctlr);
1552 return status;
1553}
1554
1555static void omap2_mcspi_remove(struct platform_device *pdev)
1556{
1557 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1558 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1559
1560 omap2_mcspi_release_dma(ctlr);
1561
1562 pm_runtime_dont_use_autosuspend(mcspi->dev);
1563 pm_runtime_put_sync(mcspi->dev);
1564 pm_runtime_disable(&pdev->dev);
1565}
1566
1567/* work with hotplug and coldplug */
1568MODULE_ALIAS("platform:omap2_mcspi");
1569
1570static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
1571{
1572 struct spi_controller *ctlr = dev_get_drvdata(dev);
1573 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1574 int error;
1575
1576 error = pinctrl_pm_select_sleep_state(dev);
1577 if (error)
1578 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1579 __func__, error);
1580
1581 error = spi_controller_suspend(ctlr);
1582 if (error)
1583 dev_warn(mcspi->dev, "%s: controller suspend failed: %i\n",
1584 __func__, error);
1585
1586 return pm_runtime_force_suspend(dev);
1587}
1588
1589static int __maybe_unused omap2_mcspi_resume(struct device *dev)
1590{
1591 struct spi_controller *ctlr = dev_get_drvdata(dev);
1592 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1593 int error;
1594
1595 error = spi_controller_resume(ctlr);
1596 if (error)
1597 dev_warn(mcspi->dev, "%s: controller resume failed: %i\n",
1598 __func__, error);
1599
1600 return pm_runtime_force_resume(dev);
1601}
1602
1603static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1604 SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
1605 omap2_mcspi_resume)
1606 .runtime_suspend = omap_mcspi_runtime_suspend,
1607 .runtime_resume = omap_mcspi_runtime_resume,
1608};
1609
1610static struct platform_driver omap2_mcspi_driver = {
1611 .driver = {
1612 .name = "omap2_mcspi",
1613 .pm = &omap2_mcspi_pm_ops,
1614 .of_match_table = omap_mcspi_of_match,
1615 },
1616 .probe = omap2_mcspi_probe,
1617 .remove_new = omap2_mcspi_remove,
1618};
1619
1620module_platform_driver(omap2_mcspi_driver);
1621MODULE_LICENSE("GPL");
1/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/device.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/platform_device.h>
28#include <linux/err.h>
29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/slab.h>
32#include <linux/pm_runtime.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/gcd.h>
36
37#include <linux/spi/spi.h>
38#include <linux/gpio.h>
39
40#include <linux/platform_data/spi-omap2-mcspi.h>
41
42#define OMAP2_MCSPI_MAX_FREQ 48000000
43#define OMAP2_MCSPI_MAX_DIVIDER 4096
44#define OMAP2_MCSPI_MAX_FIFODEPTH 64
45#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
46#define SPI_AUTOSUSPEND_TIMEOUT 2000
47
48#define OMAP2_MCSPI_REVISION 0x00
49#define OMAP2_MCSPI_SYSSTATUS 0x14
50#define OMAP2_MCSPI_IRQSTATUS 0x18
51#define OMAP2_MCSPI_IRQENABLE 0x1c
52#define OMAP2_MCSPI_WAKEUPENABLE 0x20
53#define OMAP2_MCSPI_SYST 0x24
54#define OMAP2_MCSPI_MODULCTRL 0x28
55#define OMAP2_MCSPI_XFERLEVEL 0x7c
56
57/* per-channel banks, 0x14 bytes each, first is: */
58#define OMAP2_MCSPI_CHCONF0 0x2c
59#define OMAP2_MCSPI_CHSTAT0 0x30
60#define OMAP2_MCSPI_CHCTRL0 0x34
61#define OMAP2_MCSPI_TX0 0x38
62#define OMAP2_MCSPI_RX0 0x3c
63
64/* per-register bitmasks: */
65#define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
66
67#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
70
71#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72#define OMAP2_MCSPI_CHCONF_POL BIT(1)
73#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
75#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
78#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83#define OMAP2_MCSPI_CHCONF_IS BIT(18)
84#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
86#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
87#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
88#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
89
90#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
91#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
93#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
94
95#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
96#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
97
98#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
99
100/* We have 2 DMA channels per CS, one for RX and one for TX */
101struct omap2_mcspi_dma {
102 struct dma_chan *dma_tx;
103 struct dma_chan *dma_rx;
104
105 struct completion dma_tx_completion;
106 struct completion dma_rx_completion;
107
108 char dma_rx_ch_name[14];
109 char dma_tx_ch_name[14];
110};
111
112/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113 * cache operations; better heuristics consider wordsize and bitrate.
114 */
115#define DMA_MIN_BYTES 160
116
117
118/*
119 * Used for context save and restore, structure members to be updated whenever
120 * corresponding registers are modified.
121 */
122struct omap2_mcspi_regs {
123 u32 modulctrl;
124 u32 wakeupenable;
125 struct list_head cs;
126};
127
128struct omap2_mcspi {
129 struct spi_master *master;
130 /* Virtual base address of the controller */
131 void __iomem *base;
132 unsigned long phys;
133 /* SPI1 has 4 channels, while SPI2 has 2 */
134 struct omap2_mcspi_dma *dma_channels;
135 struct device *dev;
136 struct omap2_mcspi_regs ctx;
137 int fifo_depth;
138 unsigned int pin_dir:1;
139};
140
141struct omap2_mcspi_cs {
142 void __iomem *base;
143 unsigned long phys;
144 int word_len;
145 u16 mode;
146 struct list_head node;
147 /* Context save and restore shadow register */
148 u32 chconf0, chctrl0;
149};
150
151static inline void mcspi_write_reg(struct spi_master *master,
152 int idx, u32 val)
153{
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155
156 writel_relaxed(val, mcspi->base + idx);
157}
158
159static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
160{
161 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
162
163 return readl_relaxed(mcspi->base + idx);
164}
165
166static inline void mcspi_write_cs_reg(const struct spi_device *spi,
167 int idx, u32 val)
168{
169 struct omap2_mcspi_cs *cs = spi->controller_state;
170
171 writel_relaxed(val, cs->base + idx);
172}
173
174static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
175{
176 struct omap2_mcspi_cs *cs = spi->controller_state;
177
178 return readl_relaxed(cs->base + idx);
179}
180
181static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
182{
183 struct omap2_mcspi_cs *cs = spi->controller_state;
184
185 return cs->chconf0;
186}
187
188static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
189{
190 struct omap2_mcspi_cs *cs = spi->controller_state;
191
192 cs->chconf0 = val;
193 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
194 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
195}
196
197static inline int mcspi_bytes_per_word(int word_len)
198{
199 if (word_len <= 8)
200 return 1;
201 else if (word_len <= 16)
202 return 2;
203 else /* word_len <= 32 */
204 return 4;
205}
206
207static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
208 int is_read, int enable)
209{
210 u32 l, rw;
211
212 l = mcspi_cached_chconf0(spi);
213
214 if (is_read) /* 1 is read, 0 write */
215 rw = OMAP2_MCSPI_CHCONF_DMAR;
216 else
217 rw = OMAP2_MCSPI_CHCONF_DMAW;
218
219 if (enable)
220 l |= rw;
221 else
222 l &= ~rw;
223
224 mcspi_write_chconf0(spi, l);
225}
226
227static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
228{
229 struct omap2_mcspi_cs *cs = spi->controller_state;
230 u32 l;
231
232 l = cs->chctrl0;
233 if (enable)
234 l |= OMAP2_MCSPI_CHCTRL_EN;
235 else
236 l &= ~OMAP2_MCSPI_CHCTRL_EN;
237 cs->chctrl0 = l;
238 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
239 /* Flash post-writes */
240 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
241}
242
243static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
244{
245 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
246 u32 l;
247
248 /* The controller handles the inverted chip selects
249 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
250 * the inversion from the core spi_set_cs function.
251 */
252 if (spi->mode & SPI_CS_HIGH)
253 enable = !enable;
254
255 if (spi->controller_state) {
256 int err = pm_runtime_get_sync(mcspi->dev);
257 if (err < 0) {
258 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
259 return;
260 }
261
262 l = mcspi_cached_chconf0(spi);
263
264 if (enable)
265 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
266 else
267 l |= OMAP2_MCSPI_CHCONF_FORCE;
268
269 mcspi_write_chconf0(spi, l);
270
271 pm_runtime_mark_last_busy(mcspi->dev);
272 pm_runtime_put_autosuspend(mcspi->dev);
273 }
274}
275
276static void omap2_mcspi_set_master_mode(struct spi_master *master)
277{
278 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
279 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
280 u32 l;
281
282 /*
283 * Setup when switching from (reset default) slave mode
284 * to single-channel master mode
285 */
286 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
287 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
288 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
289 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
290
291 ctx->modulctrl = l;
292}
293
294static void omap2_mcspi_set_fifo(const struct spi_device *spi,
295 struct spi_transfer *t, int enable)
296{
297 struct spi_master *master = spi->master;
298 struct omap2_mcspi_cs *cs = spi->controller_state;
299 struct omap2_mcspi *mcspi;
300 unsigned int wcnt;
301 int max_fifo_depth, fifo_depth, bytes_per_word;
302 u32 chconf, xferlevel;
303
304 mcspi = spi_master_get_devdata(master);
305
306 chconf = mcspi_cached_chconf0(spi);
307 if (enable) {
308 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
309 if (t->len % bytes_per_word != 0)
310 goto disable_fifo;
311
312 if (t->rx_buf != NULL && t->tx_buf != NULL)
313 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
314 else
315 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
316
317 fifo_depth = gcd(t->len, max_fifo_depth);
318 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
319 goto disable_fifo;
320
321 wcnt = t->len / bytes_per_word;
322 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
323 goto disable_fifo;
324
325 xferlevel = wcnt << 16;
326 if (t->rx_buf != NULL) {
327 chconf |= OMAP2_MCSPI_CHCONF_FFER;
328 xferlevel |= (fifo_depth - 1) << 8;
329 }
330 if (t->tx_buf != NULL) {
331 chconf |= OMAP2_MCSPI_CHCONF_FFET;
332 xferlevel |= fifo_depth - 1;
333 }
334
335 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
336 mcspi_write_chconf0(spi, chconf);
337 mcspi->fifo_depth = fifo_depth;
338
339 return;
340 }
341
342disable_fifo:
343 if (t->rx_buf != NULL)
344 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
345
346 if (t->tx_buf != NULL)
347 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
348
349 mcspi_write_chconf0(spi, chconf);
350 mcspi->fifo_depth = 0;
351}
352
353static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
354{
355 struct spi_master *spi_cntrl = mcspi->master;
356 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
357 struct omap2_mcspi_cs *cs;
358
359 /* McSPI: context restore */
360 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
361 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
362
363 list_for_each_entry(cs, &ctx->cs, node)
364 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
365}
366
367static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
368{
369 unsigned long timeout;
370
371 timeout = jiffies + msecs_to_jiffies(1000);
372 while (!(readl_relaxed(reg) & bit)) {
373 if (time_after(jiffies, timeout)) {
374 if (!(readl_relaxed(reg) & bit))
375 return -ETIMEDOUT;
376 else
377 return 0;
378 }
379 cpu_relax();
380 }
381 return 0;
382}
383
384static void omap2_mcspi_rx_callback(void *data)
385{
386 struct spi_device *spi = data;
387 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
388 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
389
390 /* We must disable the DMA RX request */
391 omap2_mcspi_set_dma_req(spi, 1, 0);
392
393 complete(&mcspi_dma->dma_rx_completion);
394}
395
396static void omap2_mcspi_tx_callback(void *data)
397{
398 struct spi_device *spi = data;
399 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
400 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
401
402 /* We must disable the DMA TX request */
403 omap2_mcspi_set_dma_req(spi, 0, 0);
404
405 complete(&mcspi_dma->dma_tx_completion);
406}
407
408static void omap2_mcspi_tx_dma(struct spi_device *spi,
409 struct spi_transfer *xfer,
410 struct dma_slave_config cfg)
411{
412 struct omap2_mcspi *mcspi;
413 struct omap2_mcspi_dma *mcspi_dma;
414 unsigned int count;
415
416 mcspi = spi_master_get_devdata(spi->master);
417 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
418 count = xfer->len;
419
420 if (mcspi_dma->dma_tx) {
421 struct dma_async_tx_descriptor *tx;
422
423 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
424
425 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
426 xfer->tx_sg.nents,
427 DMA_MEM_TO_DEV,
428 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
429 if (tx) {
430 tx->callback = omap2_mcspi_tx_callback;
431 tx->callback_param = spi;
432 dmaengine_submit(tx);
433 } else {
434 /* FIXME: fall back to PIO? */
435 }
436 }
437 dma_async_issue_pending(mcspi_dma->dma_tx);
438 omap2_mcspi_set_dma_req(spi, 0, 1);
439
440}
441
442static unsigned
443omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
444 struct dma_slave_config cfg,
445 unsigned es)
446{
447 struct omap2_mcspi *mcspi;
448 struct omap2_mcspi_dma *mcspi_dma;
449 unsigned int count, transfer_reduction = 0;
450 struct scatterlist *sg_out[2];
451 int nb_sizes = 0, out_mapped_nents[2], ret, x;
452 size_t sizes[2];
453 u32 l;
454 int elements = 0;
455 int word_len, element_count;
456 struct omap2_mcspi_cs *cs = spi->controller_state;
457 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
458
459 mcspi = spi_master_get_devdata(spi->master);
460 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
461 count = xfer->len;
462
463 /*
464 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
465 * it mentions reducing DMA transfer length by one element in master
466 * normal mode.
467 */
468 if (mcspi->fifo_depth == 0)
469 transfer_reduction = es;
470
471 word_len = cs->word_len;
472 l = mcspi_cached_chconf0(spi);
473
474 if (word_len <= 8)
475 element_count = count;
476 else if (word_len <= 16)
477 element_count = count >> 1;
478 else /* word_len <= 32 */
479 element_count = count >> 2;
480
481 if (mcspi_dma->dma_rx) {
482 struct dma_async_tx_descriptor *tx;
483
484 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
485
486 /*
487 * Reduce DMA transfer length by one more if McSPI is
488 * configured in turbo mode.
489 */
490 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
491 transfer_reduction += es;
492
493 if (transfer_reduction) {
494 /* Split sgl into two. The second sgl won't be used. */
495 sizes[0] = count - transfer_reduction;
496 sizes[1] = transfer_reduction;
497 nb_sizes = 2;
498 } else {
499 /*
500 * Don't bother splitting the sgl. This essentially
501 * clones the original sgl.
502 */
503 sizes[0] = count;
504 nb_sizes = 1;
505 }
506
507 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
508 0, nb_sizes,
509 sizes,
510 sg_out, out_mapped_nents,
511 GFP_KERNEL);
512
513 if (ret < 0) {
514 dev_err(&spi->dev, "sg_split failed\n");
515 return 0;
516 }
517
518 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
519 sg_out[0],
520 out_mapped_nents[0],
521 DMA_DEV_TO_MEM,
522 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
523 if (tx) {
524 tx->callback = omap2_mcspi_rx_callback;
525 tx->callback_param = spi;
526 dmaengine_submit(tx);
527 } else {
528 /* FIXME: fall back to PIO? */
529 }
530 }
531
532 dma_async_issue_pending(mcspi_dma->dma_rx);
533 omap2_mcspi_set_dma_req(spi, 1, 1);
534
535 wait_for_completion(&mcspi_dma->dma_rx_completion);
536
537 for (x = 0; x < nb_sizes; x++)
538 kfree(sg_out[x]);
539
540 if (mcspi->fifo_depth > 0)
541 return count;
542
543 /*
544 * Due to the DMA transfer length reduction the missing bytes must
545 * be read manually to receive all of the expected data.
546 */
547 omap2_mcspi_set_enable(spi, 0);
548
549 elements = element_count - 1;
550
551 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
552 elements--;
553
554 if (!mcspi_wait_for_reg_bit(chstat_reg,
555 OMAP2_MCSPI_CHSTAT_RXS)) {
556 u32 w;
557
558 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
559 if (word_len <= 8)
560 ((u8 *)xfer->rx_buf)[elements++] = w;
561 else if (word_len <= 16)
562 ((u16 *)xfer->rx_buf)[elements++] = w;
563 else /* word_len <= 32 */
564 ((u32 *)xfer->rx_buf)[elements++] = w;
565 } else {
566 int bytes_per_word = mcspi_bytes_per_word(word_len);
567 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
568 count -= (bytes_per_word << 1);
569 omap2_mcspi_set_enable(spi, 1);
570 return count;
571 }
572 }
573 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
574 u32 w;
575
576 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
577 if (word_len <= 8)
578 ((u8 *)xfer->rx_buf)[elements] = w;
579 else if (word_len <= 16)
580 ((u16 *)xfer->rx_buf)[elements] = w;
581 else /* word_len <= 32 */
582 ((u32 *)xfer->rx_buf)[elements] = w;
583 } else {
584 dev_err(&spi->dev, "DMA RX last word empty\n");
585 count -= mcspi_bytes_per_word(word_len);
586 }
587 omap2_mcspi_set_enable(spi, 1);
588 return count;
589}
590
591static unsigned
592omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
593{
594 struct omap2_mcspi *mcspi;
595 struct omap2_mcspi_cs *cs = spi->controller_state;
596 struct omap2_mcspi_dma *mcspi_dma;
597 unsigned int count;
598 u32 l;
599 u8 *rx;
600 const u8 *tx;
601 struct dma_slave_config cfg;
602 enum dma_slave_buswidth width;
603 unsigned es;
604 u32 burst;
605 void __iomem *chstat_reg;
606 void __iomem *irqstat_reg;
607 int wait_res;
608
609 mcspi = spi_master_get_devdata(spi->master);
610 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
611 l = mcspi_cached_chconf0(spi);
612
613
614 if (cs->word_len <= 8) {
615 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
616 es = 1;
617 } else if (cs->word_len <= 16) {
618 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
619 es = 2;
620 } else {
621 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
622 es = 4;
623 }
624
625 count = xfer->len;
626 burst = 1;
627
628 if (mcspi->fifo_depth > 0) {
629 if (count > mcspi->fifo_depth)
630 burst = mcspi->fifo_depth / es;
631 else
632 burst = count / es;
633 }
634
635 memset(&cfg, 0, sizeof(cfg));
636 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
637 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
638 cfg.src_addr_width = width;
639 cfg.dst_addr_width = width;
640 cfg.src_maxburst = burst;
641 cfg.dst_maxburst = burst;
642
643 rx = xfer->rx_buf;
644 tx = xfer->tx_buf;
645
646 if (tx != NULL)
647 omap2_mcspi_tx_dma(spi, xfer, cfg);
648
649 if (rx != NULL)
650 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
651
652 if (tx != NULL) {
653 wait_for_completion(&mcspi_dma->dma_tx_completion);
654
655 if (mcspi->fifo_depth > 0) {
656 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
657
658 if (mcspi_wait_for_reg_bit(irqstat_reg,
659 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
660 dev_err(&spi->dev, "EOW timed out\n");
661
662 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
663 OMAP2_MCSPI_IRQSTATUS_EOW);
664 }
665
666 /* for TX_ONLY mode, be sure all words have shifted out */
667 if (rx == NULL) {
668 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
669 if (mcspi->fifo_depth > 0) {
670 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
671 OMAP2_MCSPI_CHSTAT_TXFFE);
672 if (wait_res < 0)
673 dev_err(&spi->dev, "TXFFE timed out\n");
674 } else {
675 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
676 OMAP2_MCSPI_CHSTAT_TXS);
677 if (wait_res < 0)
678 dev_err(&spi->dev, "TXS timed out\n");
679 }
680 if (wait_res >= 0 &&
681 (mcspi_wait_for_reg_bit(chstat_reg,
682 OMAP2_MCSPI_CHSTAT_EOT) < 0))
683 dev_err(&spi->dev, "EOT timed out\n");
684 }
685 }
686 return count;
687}
688
689static unsigned
690omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
691{
692 struct omap2_mcspi *mcspi;
693 struct omap2_mcspi_cs *cs = spi->controller_state;
694 unsigned int count, c;
695 u32 l;
696 void __iomem *base = cs->base;
697 void __iomem *tx_reg;
698 void __iomem *rx_reg;
699 void __iomem *chstat_reg;
700 int word_len;
701
702 mcspi = spi_master_get_devdata(spi->master);
703 count = xfer->len;
704 c = count;
705 word_len = cs->word_len;
706
707 l = mcspi_cached_chconf0(spi);
708
709 /* We store the pre-calculated register addresses on stack to speed
710 * up the transfer loop. */
711 tx_reg = base + OMAP2_MCSPI_TX0;
712 rx_reg = base + OMAP2_MCSPI_RX0;
713 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
714
715 if (c < (word_len>>3))
716 return 0;
717
718 if (word_len <= 8) {
719 u8 *rx;
720 const u8 *tx;
721
722 rx = xfer->rx_buf;
723 tx = xfer->tx_buf;
724
725 do {
726 c -= 1;
727 if (tx != NULL) {
728 if (mcspi_wait_for_reg_bit(chstat_reg,
729 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
730 dev_err(&spi->dev, "TXS timed out\n");
731 goto out;
732 }
733 dev_vdbg(&spi->dev, "write-%d %02x\n",
734 word_len, *tx);
735 writel_relaxed(*tx++, tx_reg);
736 }
737 if (rx != NULL) {
738 if (mcspi_wait_for_reg_bit(chstat_reg,
739 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
740 dev_err(&spi->dev, "RXS timed out\n");
741 goto out;
742 }
743
744 if (c == 1 && tx == NULL &&
745 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
746 omap2_mcspi_set_enable(spi, 0);
747 *rx++ = readl_relaxed(rx_reg);
748 dev_vdbg(&spi->dev, "read-%d %02x\n",
749 word_len, *(rx - 1));
750 if (mcspi_wait_for_reg_bit(chstat_reg,
751 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
752 dev_err(&spi->dev,
753 "RXS timed out\n");
754 goto out;
755 }
756 c = 0;
757 } else if (c == 0 && tx == NULL) {
758 omap2_mcspi_set_enable(spi, 0);
759 }
760
761 *rx++ = readl_relaxed(rx_reg);
762 dev_vdbg(&spi->dev, "read-%d %02x\n",
763 word_len, *(rx - 1));
764 }
765 } while (c);
766 } else if (word_len <= 16) {
767 u16 *rx;
768 const u16 *tx;
769
770 rx = xfer->rx_buf;
771 tx = xfer->tx_buf;
772 do {
773 c -= 2;
774 if (tx != NULL) {
775 if (mcspi_wait_for_reg_bit(chstat_reg,
776 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
777 dev_err(&spi->dev, "TXS timed out\n");
778 goto out;
779 }
780 dev_vdbg(&spi->dev, "write-%d %04x\n",
781 word_len, *tx);
782 writel_relaxed(*tx++, tx_reg);
783 }
784 if (rx != NULL) {
785 if (mcspi_wait_for_reg_bit(chstat_reg,
786 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
787 dev_err(&spi->dev, "RXS timed out\n");
788 goto out;
789 }
790
791 if (c == 2 && tx == NULL &&
792 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
793 omap2_mcspi_set_enable(spi, 0);
794 *rx++ = readl_relaxed(rx_reg);
795 dev_vdbg(&spi->dev, "read-%d %04x\n",
796 word_len, *(rx - 1));
797 if (mcspi_wait_for_reg_bit(chstat_reg,
798 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
799 dev_err(&spi->dev,
800 "RXS timed out\n");
801 goto out;
802 }
803 c = 0;
804 } else if (c == 0 && tx == NULL) {
805 omap2_mcspi_set_enable(spi, 0);
806 }
807
808 *rx++ = readl_relaxed(rx_reg);
809 dev_vdbg(&spi->dev, "read-%d %04x\n",
810 word_len, *(rx - 1));
811 }
812 } while (c >= 2);
813 } else if (word_len <= 32) {
814 u32 *rx;
815 const u32 *tx;
816
817 rx = xfer->rx_buf;
818 tx = xfer->tx_buf;
819 do {
820 c -= 4;
821 if (tx != NULL) {
822 if (mcspi_wait_for_reg_bit(chstat_reg,
823 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
824 dev_err(&spi->dev, "TXS timed out\n");
825 goto out;
826 }
827 dev_vdbg(&spi->dev, "write-%d %08x\n",
828 word_len, *tx);
829 writel_relaxed(*tx++, tx_reg);
830 }
831 if (rx != NULL) {
832 if (mcspi_wait_for_reg_bit(chstat_reg,
833 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
834 dev_err(&spi->dev, "RXS timed out\n");
835 goto out;
836 }
837
838 if (c == 4 && tx == NULL &&
839 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
840 omap2_mcspi_set_enable(spi, 0);
841 *rx++ = readl_relaxed(rx_reg);
842 dev_vdbg(&spi->dev, "read-%d %08x\n",
843 word_len, *(rx - 1));
844 if (mcspi_wait_for_reg_bit(chstat_reg,
845 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
846 dev_err(&spi->dev,
847 "RXS timed out\n");
848 goto out;
849 }
850 c = 0;
851 } else if (c == 0 && tx == NULL) {
852 omap2_mcspi_set_enable(spi, 0);
853 }
854
855 *rx++ = readl_relaxed(rx_reg);
856 dev_vdbg(&spi->dev, "read-%d %08x\n",
857 word_len, *(rx - 1));
858 }
859 } while (c >= 4);
860 }
861
862 /* for TX_ONLY mode, be sure all words have shifted out */
863 if (xfer->rx_buf == NULL) {
864 if (mcspi_wait_for_reg_bit(chstat_reg,
865 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
866 dev_err(&spi->dev, "TXS timed out\n");
867 } else if (mcspi_wait_for_reg_bit(chstat_reg,
868 OMAP2_MCSPI_CHSTAT_EOT) < 0)
869 dev_err(&spi->dev, "EOT timed out\n");
870
871 /* disable chan to purge rx datas received in TX_ONLY transfer,
872 * otherwise these rx datas will affect the direct following
873 * RX_ONLY transfer.
874 */
875 omap2_mcspi_set_enable(spi, 0);
876 }
877out:
878 omap2_mcspi_set_enable(spi, 1);
879 return count - c;
880}
881
882static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
883{
884 u32 div;
885
886 for (div = 0; div < 15; div++)
887 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
888 return div;
889
890 return 15;
891}
892
893/* called only when no transfer is active to this device */
894static int omap2_mcspi_setup_transfer(struct spi_device *spi,
895 struct spi_transfer *t)
896{
897 struct omap2_mcspi_cs *cs = spi->controller_state;
898 struct omap2_mcspi *mcspi;
899 struct spi_master *spi_cntrl;
900 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
901 u8 word_len = spi->bits_per_word;
902 u32 speed_hz = spi->max_speed_hz;
903
904 mcspi = spi_master_get_devdata(spi->master);
905 spi_cntrl = mcspi->master;
906
907 if (t != NULL && t->bits_per_word)
908 word_len = t->bits_per_word;
909
910 cs->word_len = word_len;
911
912 if (t && t->speed_hz)
913 speed_hz = t->speed_hz;
914
915 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
916 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
917 clkd = omap2_mcspi_calc_divisor(speed_hz);
918 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
919 clkg = 0;
920 } else {
921 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
922 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
923 clkd = (div - 1) & 0xf;
924 extclk = (div - 1) >> 4;
925 clkg = OMAP2_MCSPI_CHCONF_CLKG;
926 }
927
928 l = mcspi_cached_chconf0(spi);
929
930 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
931 * REVISIT: this controller could support SPI_3WIRE mode.
932 */
933 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
934 l &= ~OMAP2_MCSPI_CHCONF_IS;
935 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
936 l |= OMAP2_MCSPI_CHCONF_DPE0;
937 } else {
938 l |= OMAP2_MCSPI_CHCONF_IS;
939 l |= OMAP2_MCSPI_CHCONF_DPE1;
940 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
941 }
942
943 /* wordlength */
944 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
945 l |= (word_len - 1) << 7;
946
947 /* set chipselect polarity; manage with FORCE */
948 if (!(spi->mode & SPI_CS_HIGH))
949 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
950 else
951 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
952
953 /* set clock divisor */
954 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
955 l |= clkd << 2;
956
957 /* set clock granularity */
958 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
959 l |= clkg;
960 if (clkg) {
961 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
962 cs->chctrl0 |= extclk << 8;
963 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
964 }
965
966 /* set SPI mode 0..3 */
967 if (spi->mode & SPI_CPOL)
968 l |= OMAP2_MCSPI_CHCONF_POL;
969 else
970 l &= ~OMAP2_MCSPI_CHCONF_POL;
971 if (spi->mode & SPI_CPHA)
972 l |= OMAP2_MCSPI_CHCONF_PHA;
973 else
974 l &= ~OMAP2_MCSPI_CHCONF_PHA;
975
976 mcspi_write_chconf0(spi, l);
977
978 cs->mode = spi->mode;
979
980 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
981 speed_hz,
982 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
983 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
984
985 return 0;
986}
987
988/*
989 * Note that we currently allow DMA only if we get a channel
990 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
991 */
992static int omap2_mcspi_request_dma(struct spi_device *spi)
993{
994 struct spi_master *master = spi->master;
995 struct omap2_mcspi *mcspi;
996 struct omap2_mcspi_dma *mcspi_dma;
997 int ret = 0;
998
999 mcspi = spi_master_get_devdata(master);
1000 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1001
1002 init_completion(&mcspi_dma->dma_rx_completion);
1003 init_completion(&mcspi_dma->dma_tx_completion);
1004
1005 mcspi_dma->dma_rx = dma_request_chan(&master->dev,
1006 mcspi_dma->dma_rx_ch_name);
1007 if (IS_ERR(mcspi_dma->dma_rx)) {
1008 ret = PTR_ERR(mcspi_dma->dma_rx);
1009 mcspi_dma->dma_rx = NULL;
1010 goto no_dma;
1011 }
1012
1013 mcspi_dma->dma_tx = dma_request_chan(&master->dev,
1014 mcspi_dma->dma_tx_ch_name);
1015 if (IS_ERR(mcspi_dma->dma_tx)) {
1016 ret = PTR_ERR(mcspi_dma->dma_tx);
1017 mcspi_dma->dma_tx = NULL;
1018 dma_release_channel(mcspi_dma->dma_rx);
1019 mcspi_dma->dma_rx = NULL;
1020 }
1021
1022no_dma:
1023 return ret;
1024}
1025
1026static int omap2_mcspi_setup(struct spi_device *spi)
1027{
1028 int ret;
1029 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1030 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1031 struct omap2_mcspi_dma *mcspi_dma;
1032 struct omap2_mcspi_cs *cs = spi->controller_state;
1033
1034 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1035
1036 if (!cs) {
1037 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1038 if (!cs)
1039 return -ENOMEM;
1040 cs->base = mcspi->base + spi->chip_select * 0x14;
1041 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1042 cs->mode = 0;
1043 cs->chconf0 = 0;
1044 cs->chctrl0 = 0;
1045 spi->controller_state = cs;
1046 /* Link this to context save list */
1047 list_add_tail(&cs->node, &ctx->cs);
1048
1049 if (gpio_is_valid(spi->cs_gpio)) {
1050 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1051 if (ret) {
1052 dev_err(&spi->dev, "failed to request gpio\n");
1053 return ret;
1054 }
1055 gpio_direction_output(spi->cs_gpio,
1056 !(spi->mode & SPI_CS_HIGH));
1057 }
1058 }
1059
1060 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1061 ret = omap2_mcspi_request_dma(spi);
1062 if (ret)
1063 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1064 ret);
1065 }
1066
1067 ret = pm_runtime_get_sync(mcspi->dev);
1068 if (ret < 0)
1069 return ret;
1070
1071 ret = omap2_mcspi_setup_transfer(spi, NULL);
1072 pm_runtime_mark_last_busy(mcspi->dev);
1073 pm_runtime_put_autosuspend(mcspi->dev);
1074
1075 return ret;
1076}
1077
1078static void omap2_mcspi_cleanup(struct spi_device *spi)
1079{
1080 struct omap2_mcspi *mcspi;
1081 struct omap2_mcspi_dma *mcspi_dma;
1082 struct omap2_mcspi_cs *cs;
1083
1084 mcspi = spi_master_get_devdata(spi->master);
1085
1086 if (spi->controller_state) {
1087 /* Unlink controller state from context save list */
1088 cs = spi->controller_state;
1089 list_del(&cs->node);
1090
1091 kfree(cs);
1092 }
1093
1094 if (spi->chip_select < spi->master->num_chipselect) {
1095 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1096
1097 if (mcspi_dma->dma_rx) {
1098 dma_release_channel(mcspi_dma->dma_rx);
1099 mcspi_dma->dma_rx = NULL;
1100 }
1101 if (mcspi_dma->dma_tx) {
1102 dma_release_channel(mcspi_dma->dma_tx);
1103 mcspi_dma->dma_tx = NULL;
1104 }
1105 }
1106
1107 if (gpio_is_valid(spi->cs_gpio))
1108 gpio_free(spi->cs_gpio);
1109}
1110
1111static int omap2_mcspi_transfer_one(struct spi_master *master,
1112 struct spi_device *spi,
1113 struct spi_transfer *t)
1114{
1115
1116 /* We only enable one channel at a time -- the one whose message is
1117 * -- although this controller would gladly
1118 * arbitrate among multiple channels. This corresponds to "single
1119 * channel" master mode. As a side effect, we need to manage the
1120 * chipselect with the FORCE bit ... CS != channel enable.
1121 */
1122
1123 struct omap2_mcspi *mcspi;
1124 struct omap2_mcspi_dma *mcspi_dma;
1125 struct omap2_mcspi_cs *cs;
1126 struct omap2_mcspi_device_config *cd;
1127 int par_override = 0;
1128 int status = 0;
1129 u32 chconf;
1130
1131 mcspi = spi_master_get_devdata(master);
1132 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1133 cs = spi->controller_state;
1134 cd = spi->controller_data;
1135
1136 /*
1137 * The slave driver could have changed spi->mode in which case
1138 * it will be different from cs->mode (the current hardware setup).
1139 * If so, set par_override (even though its not a parity issue) so
1140 * omap2_mcspi_setup_transfer will be called to configure the hardware
1141 * with the correct mode on the first iteration of the loop below.
1142 */
1143 if (spi->mode != cs->mode)
1144 par_override = 1;
1145
1146 omap2_mcspi_set_enable(spi, 0);
1147
1148 if (gpio_is_valid(spi->cs_gpio))
1149 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1150
1151 if (par_override ||
1152 (t->speed_hz != spi->max_speed_hz) ||
1153 (t->bits_per_word != spi->bits_per_word)) {
1154 par_override = 1;
1155 status = omap2_mcspi_setup_transfer(spi, t);
1156 if (status < 0)
1157 goto out;
1158 if (t->speed_hz == spi->max_speed_hz &&
1159 t->bits_per_word == spi->bits_per_word)
1160 par_override = 0;
1161 }
1162 if (cd && cd->cs_per_word) {
1163 chconf = mcspi->ctx.modulctrl;
1164 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1165 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1166 mcspi->ctx.modulctrl =
1167 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1168 }
1169
1170 chconf = mcspi_cached_chconf0(spi);
1171 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1172 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1173
1174 if (t->tx_buf == NULL)
1175 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1176 else if (t->rx_buf == NULL)
1177 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1178
1179 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1180 /* Turbo mode is for more than one word */
1181 if (t->len > ((cs->word_len + 7) >> 3))
1182 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1183 }
1184
1185 mcspi_write_chconf0(spi, chconf);
1186
1187 if (t->len) {
1188 unsigned count;
1189
1190 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1191 master->cur_msg_mapped &&
1192 master->can_dma(master, spi, t))
1193 omap2_mcspi_set_fifo(spi, t, 1);
1194
1195 omap2_mcspi_set_enable(spi, 1);
1196
1197 /* RX_ONLY mode needs dummy data in TX reg */
1198 if (t->tx_buf == NULL)
1199 writel_relaxed(0, cs->base
1200 + OMAP2_MCSPI_TX0);
1201
1202 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1203 master->cur_msg_mapped &&
1204 master->can_dma(master, spi, t))
1205 count = omap2_mcspi_txrx_dma(spi, t);
1206 else
1207 count = omap2_mcspi_txrx_pio(spi, t);
1208
1209 if (count != t->len) {
1210 status = -EIO;
1211 goto out;
1212 }
1213 }
1214
1215 omap2_mcspi_set_enable(spi, 0);
1216
1217 if (mcspi->fifo_depth > 0)
1218 omap2_mcspi_set_fifo(spi, t, 0);
1219
1220out:
1221 /* Restore defaults if they were overriden */
1222 if (par_override) {
1223 par_override = 0;
1224 status = omap2_mcspi_setup_transfer(spi, NULL);
1225 }
1226
1227 if (cd && cd->cs_per_word) {
1228 chconf = mcspi->ctx.modulctrl;
1229 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1230 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1231 mcspi->ctx.modulctrl =
1232 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1233 }
1234
1235 omap2_mcspi_set_enable(spi, 0);
1236
1237 if (gpio_is_valid(spi->cs_gpio))
1238 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1239
1240 if (mcspi->fifo_depth > 0 && t)
1241 omap2_mcspi_set_fifo(spi, t, 0);
1242
1243 return status;
1244}
1245
1246static int omap2_mcspi_prepare_message(struct spi_master *master,
1247 struct spi_message *msg)
1248{
1249 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1250 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1251 struct omap2_mcspi_cs *cs;
1252
1253 /* Only a single channel can have the FORCE bit enabled
1254 * in its chconf0 register.
1255 * Scan all channels and disable them except the current one.
1256 * A FORCE can remain from a last transfer having cs_change enabled
1257 */
1258 list_for_each_entry(cs, &ctx->cs, node) {
1259 if (msg->spi->controller_state == cs)
1260 continue;
1261
1262 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1263 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1264 writel_relaxed(cs->chconf0,
1265 cs->base + OMAP2_MCSPI_CHCONF0);
1266 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1267 }
1268 }
1269
1270 return 0;
1271}
1272
1273static bool omap2_mcspi_can_dma(struct spi_master *master,
1274 struct spi_device *spi,
1275 struct spi_transfer *xfer)
1276{
1277 return (xfer->len >= DMA_MIN_BYTES);
1278}
1279
1280static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1281{
1282 struct spi_master *master = mcspi->master;
1283 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1284 int ret = 0;
1285
1286 ret = pm_runtime_get_sync(mcspi->dev);
1287 if (ret < 0)
1288 return ret;
1289
1290 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1291 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1292 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1293
1294 omap2_mcspi_set_master_mode(master);
1295 pm_runtime_mark_last_busy(mcspi->dev);
1296 pm_runtime_put_autosuspend(mcspi->dev);
1297 return 0;
1298}
1299
1300static int omap_mcspi_runtime_resume(struct device *dev)
1301{
1302 struct omap2_mcspi *mcspi;
1303 struct spi_master *master;
1304
1305 master = dev_get_drvdata(dev);
1306 mcspi = spi_master_get_devdata(master);
1307 omap2_mcspi_restore_ctx(mcspi);
1308
1309 return 0;
1310}
1311
1312static struct omap2_mcspi_platform_config omap2_pdata = {
1313 .regs_offset = 0,
1314};
1315
1316static struct omap2_mcspi_platform_config omap4_pdata = {
1317 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1318};
1319
1320static const struct of_device_id omap_mcspi_of_match[] = {
1321 {
1322 .compatible = "ti,omap2-mcspi",
1323 .data = &omap2_pdata,
1324 },
1325 {
1326 .compatible = "ti,omap4-mcspi",
1327 .data = &omap4_pdata,
1328 },
1329 { },
1330};
1331MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1332
1333static int omap2_mcspi_probe(struct platform_device *pdev)
1334{
1335 struct spi_master *master;
1336 const struct omap2_mcspi_platform_config *pdata;
1337 struct omap2_mcspi *mcspi;
1338 struct resource *r;
1339 int status = 0, i;
1340 u32 regs_offset = 0;
1341 struct device_node *node = pdev->dev.of_node;
1342 const struct of_device_id *match;
1343
1344 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1345 if (master == NULL) {
1346 dev_dbg(&pdev->dev, "master allocation failed\n");
1347 return -ENOMEM;
1348 }
1349
1350 /* the spi->mode bits understood by this driver: */
1351 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1352 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1353 master->setup = omap2_mcspi_setup;
1354 master->auto_runtime_pm = true;
1355 master->prepare_message = omap2_mcspi_prepare_message;
1356 master->can_dma = omap2_mcspi_can_dma;
1357 master->transfer_one = omap2_mcspi_transfer_one;
1358 master->set_cs = omap2_mcspi_set_cs;
1359 master->cleanup = omap2_mcspi_cleanup;
1360 master->dev.of_node = node;
1361 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1362 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1363
1364 platform_set_drvdata(pdev, master);
1365
1366 mcspi = spi_master_get_devdata(master);
1367 mcspi->master = master;
1368
1369 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1370 if (match) {
1371 u32 num_cs = 1; /* default number of chipselect */
1372 pdata = match->data;
1373
1374 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1375 master->num_chipselect = num_cs;
1376 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1377 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1378 } else {
1379 pdata = dev_get_platdata(&pdev->dev);
1380 master->num_chipselect = pdata->num_cs;
1381 mcspi->pin_dir = pdata->pin_dir;
1382 }
1383 regs_offset = pdata->regs_offset;
1384
1385 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1387 if (IS_ERR(mcspi->base)) {
1388 status = PTR_ERR(mcspi->base);
1389 goto free_master;
1390 }
1391 mcspi->phys = r->start + regs_offset;
1392 mcspi->base += regs_offset;
1393
1394 mcspi->dev = &pdev->dev;
1395
1396 INIT_LIST_HEAD(&mcspi->ctx.cs);
1397
1398 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1399 sizeof(struct omap2_mcspi_dma),
1400 GFP_KERNEL);
1401 if (mcspi->dma_channels == NULL) {
1402 status = -ENOMEM;
1403 goto free_master;
1404 }
1405
1406 for (i = 0; i < master->num_chipselect; i++) {
1407 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1408 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1409 }
1410
1411 pm_runtime_use_autosuspend(&pdev->dev);
1412 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1413 pm_runtime_enable(&pdev->dev);
1414
1415 status = omap2_mcspi_master_setup(mcspi);
1416 if (status < 0)
1417 goto disable_pm;
1418
1419 status = devm_spi_register_master(&pdev->dev, master);
1420 if (status < 0)
1421 goto disable_pm;
1422
1423 return status;
1424
1425disable_pm:
1426 pm_runtime_dont_use_autosuspend(&pdev->dev);
1427 pm_runtime_put_sync(&pdev->dev);
1428 pm_runtime_disable(&pdev->dev);
1429free_master:
1430 spi_master_put(master);
1431 return status;
1432}
1433
1434static int omap2_mcspi_remove(struct platform_device *pdev)
1435{
1436 struct spi_master *master = platform_get_drvdata(pdev);
1437 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1438
1439 pm_runtime_dont_use_autosuspend(mcspi->dev);
1440 pm_runtime_put_sync(mcspi->dev);
1441 pm_runtime_disable(&pdev->dev);
1442
1443 return 0;
1444}
1445
1446/* work with hotplug and coldplug */
1447MODULE_ALIAS("platform:omap2_mcspi");
1448
1449#ifdef CONFIG_SUSPEND
1450/*
1451 * When SPI wake up from off-mode, CS is in activate state. If it was in
1452 * unactive state when driver was suspend, then force it to unactive state at
1453 * wake up.
1454 */
1455static int omap2_mcspi_resume(struct device *dev)
1456{
1457 struct spi_master *master = dev_get_drvdata(dev);
1458 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1459 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1460 struct omap2_mcspi_cs *cs;
1461
1462 pm_runtime_get_sync(mcspi->dev);
1463 list_for_each_entry(cs, &ctx->cs, node) {
1464 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1465 /*
1466 * We need to toggle CS state for OMAP take this
1467 * change in account.
1468 */
1469 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1470 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1471 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1472 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1473 }
1474 }
1475 pm_runtime_mark_last_busy(mcspi->dev);
1476 pm_runtime_put_autosuspend(mcspi->dev);
1477
1478 return pinctrl_pm_select_default_state(dev);
1479}
1480
1481static int omap2_mcspi_suspend(struct device *dev)
1482{
1483 return pinctrl_pm_select_sleep_state(dev);
1484}
1485
1486#else
1487#define omap2_mcspi_suspend NULL
1488#define omap2_mcspi_resume NULL
1489#endif
1490
1491static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1492 .resume = omap2_mcspi_resume,
1493 .suspend = omap2_mcspi_suspend,
1494 .runtime_resume = omap_mcspi_runtime_resume,
1495};
1496
1497static struct platform_driver omap2_mcspi_driver = {
1498 .driver = {
1499 .name = "omap2_mcspi",
1500 .pm = &omap2_mcspi_pm_ops,
1501 .of_match_table = omap_mcspi_of_match,
1502 },
1503 .probe = omap2_mcspi_probe,
1504 .remove = omap2_mcspi_remove,
1505};
1506
1507module_platform_driver(omap2_mcspi_driver);
1508MODULE_LICENSE("GPL");