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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright IBM Corp. 2016
4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
5 *
6 * Adjunct processor bus inline assemblies.
7 */
8
9#ifndef _AP_ASM_H_
10#define _AP_ASM_H_
11
12#include <asm/isc.h>
13
14/**
15 * ap_intructions_available() - Test if AP instructions are available.
16 *
17 * Returns 0 if the AP instructions are installed.
18 */
19static inline int ap_instructions_available(void)
20{
21 register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
22 register unsigned long reg1 asm ("1") = -ENODEV;
23 register unsigned long reg2 asm ("2") = 0UL;
24
25 asm volatile(
26 " .long 0xb2af0000\n" /* PQAP(TAPQ) */
27 "0: la %1,0\n"
28 "1:\n"
29 EX_TABLE(0b, 1b)
30 : "+d" (reg0), "+d" (reg1), "+d" (reg2) : : "cc");
31 return reg1;
32}
33
34/**
35 * ap_tapq(): Test adjunct processor queue.
36 * @qid: The AP queue number
37 * @info: Pointer to queue descriptor
38 *
39 * Returns AP queue status structure.
40 */
41static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
42{
43 register unsigned long reg0 asm ("0") = qid;
44 register struct ap_queue_status reg1 asm ("1");
45 register unsigned long reg2 asm ("2") = 0UL;
46
47 asm volatile(".long 0xb2af0000" /* PQAP(TAPQ) */
48 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc");
49 if (info)
50 *info = reg2;
51 return reg1;
52}
53
54/**
55 * ap_pqap_rapq(): Reset adjunct processor queue.
56 * @qid: The AP queue number
57 *
58 * Returns AP queue status structure.
59 */
60static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
61{
62 register unsigned long reg0 asm ("0") = qid | 0x01000000UL;
63 register struct ap_queue_status reg1 asm ("1");
64 register unsigned long reg2 asm ("2") = 0UL;
65
66 asm volatile(
67 ".long 0xb2af0000" /* PQAP(RAPQ) */
68 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc");
69 return reg1;
70}
71
72/**
73 * ap_aqic(): Control interruption for a specific AP.
74 * @qid: The AP queue number
75 * @qirqctrl: struct ap_qirq_ctrl (64 bit value)
76 * @ind: The notification indicator byte
77 *
78 * Returns AP queue status.
79 */
80static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
81 struct ap_qirq_ctrl qirqctrl,
82 void *ind)
83{
84 register unsigned long reg0 asm ("0") = qid | (3UL << 24);
85 register struct ap_qirq_ctrl reg1_in asm ("1") = qirqctrl;
86 register struct ap_queue_status reg1_out asm ("1");
87 register void *reg2 asm ("2") = ind;
88
89 asm volatile(
90 ".long 0xb2af0000" /* PQAP(AQIC) */
91 : "+d" (reg0), "+d" (reg1_in), "=d" (reg1_out), "+d" (reg2)
92 :
93 : "cc");
94 return reg1_out;
95}
96
97/**
98 * ap_qci(): Get AP configuration data
99 *
100 * Returns 0 on success, or -EOPNOTSUPP.
101 */
102static inline int ap_qci(void *config)
103{
104 register unsigned long reg0 asm ("0") = 0x04000000UL;
105 register unsigned long reg1 asm ("1") = -EINVAL;
106 register void *reg2 asm ("2") = (void *) config;
107
108 asm volatile(
109 ".long 0xb2af0000\n" /* PQAP(QCI) */
110 "0: la %1,0\n"
111 "1:\n"
112 EX_TABLE(0b, 1b)
113 : "+d" (reg0), "+d" (reg1), "+d" (reg2)
114 :
115 : "cc", "memory");
116
117 return reg1;
118}
119
120/*
121 * union ap_qact_ap_info - used together with the
122 * ap_aqic() function to provide a convenient way
123 * to handle the ap info needed by the qact function.
124 */
125union ap_qact_ap_info {
126 unsigned long val;
127 struct {
128 unsigned int : 3;
129 unsigned int mode : 3;
130 unsigned int : 26;
131 unsigned int cat : 8;
132 unsigned int : 8;
133 unsigned char ver[2];
134 };
135};
136
137/**
138 * ap_qact(): Query AP combatibility type.
139 * @qid: The AP queue number
140 * @apinfo: On input the info about the AP queue. On output the
141 * alternate AP queue info provided by the qact function
142 * in GR2 is stored in.
143 *
144 * Returns AP queue status. Check response_code field for failures.
145 */
146static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
147 union ap_qact_ap_info *apinfo)
148{
149 register unsigned long reg0 asm ("0") = qid | (5UL << 24)
150 | ((ifbit & 0x01) << 22);
151 register unsigned long reg1_in asm ("1") = apinfo->val;
152 register struct ap_queue_status reg1_out asm ("1");
153 register unsigned long reg2 asm ("2") = 0;
154
155 asm volatile(
156 ".long 0xb2af0000" /* PQAP(QACT) */
157 : "+d" (reg0), "+d" (reg1_in), "=d" (reg1_out), "+d" (reg2)
158 : : "cc");
159 apinfo->val = reg2;
160 return reg1_out;
161}
162
163/**
164 * ap_nqap(): Send message to adjunct processor queue.
165 * @qid: The AP queue number
166 * @psmid: The program supplied message identifier
167 * @msg: The message text
168 * @length: The message length
169 *
170 * Returns AP queue status structure.
171 * Condition code 1 on NQAP can't happen because the L bit is 1.
172 * Condition code 2 on NQAP also means the send is incomplete,
173 * because a segment boundary was reached. The NQAP is repeated.
174 */
175static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
176 unsigned long long psmid,
177 void *msg, size_t length)
178{
179 register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
180 register struct ap_queue_status reg1 asm ("1");
181 register unsigned long reg2 asm ("2") = (unsigned long) msg;
182 register unsigned long reg3 asm ("3") = (unsigned long) length;
183 register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
184 register unsigned long reg5 asm ("5") = psmid & 0xffffffff;
185
186 asm volatile (
187 "0: .long 0xb2ad0042\n" /* NQAP */
188 " brc 2,0b"
189 : "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
190 : "d" (reg4), "d" (reg5)
191 : "cc", "memory");
192 return reg1;
193}
194
195/**
196 * ap_dqap(): Receive message from adjunct processor queue.
197 * @qid: The AP queue number
198 * @psmid: Pointer to program supplied message identifier
199 * @msg: The message text
200 * @length: The message length
201 *
202 * Returns AP queue status structure.
203 * Condition code 1 on DQAP means the receive has taken place
204 * but only partially. The response is incomplete, hence the
205 * DQAP is repeated.
206 * Condition code 2 on DQAP also means the receive is incomplete,
207 * this time because a segment boundary was reached. Again, the
208 * DQAP is repeated.
209 * Note that gpr2 is used by the DQAP instruction to keep track of
210 * any 'residual' length, in case the instruction gets interrupted.
211 * Hence it gets zeroed before the instruction.
212 */
213static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
214 unsigned long long *psmid,
215 void *msg, size_t length)
216{
217 register unsigned long reg0 asm("0") = qid | 0x80000000UL;
218 register struct ap_queue_status reg1 asm ("1");
219 register unsigned long reg2 asm("2") = 0UL;
220 register unsigned long reg4 asm("4") = (unsigned long) msg;
221 register unsigned long reg5 asm("5") = (unsigned long) length;
222 register unsigned long reg6 asm("6") = 0UL;
223 register unsigned long reg7 asm("7") = 0UL;
224
225
226 asm volatile(
227 "0: .long 0xb2ae0064\n" /* DQAP */
228 " brc 6,0b\n"
229 : "+d" (reg0), "=d" (reg1), "+d" (reg2),
230 "+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
231 : : "cc", "memory");
232 *psmid = (((unsigned long long) reg6) << 32) + reg7;
233 return reg1;
234}
235
236#endif /* _AP_ASM_H_ */