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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 <http://rt2x00.serialmonkey.com>
5
6 */
7
8/*
9 Module: rt2400pci
10 Abstract: rt2400pci device specific routines.
11 Supported chipsets: RT2460.
12 */
13
14#include <linux/delay.h>
15#include <linux/etherdevice.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/eeprom_93cx6.h>
20#include <linux/slab.h>
21
22#include "rt2x00.h"
23#include "rt2x00mmio.h"
24#include "rt2x00pci.h"
25#include "rt2400pci.h"
26
27/*
28 * Register access.
29 * All access to the CSR registers will go through the methods
30 * rt2x00mmio_register_read and rt2x00mmio_register_write.
31 * BBP and RF register require indirect register access,
32 * and use the CSR registers BBPCSR and RFCSR to achieve this.
33 * These indirect registers work with busy bits,
34 * and we will try maximal REGISTER_BUSY_COUNT times to access
35 * the register while taking a REGISTER_BUSY_DELAY us delay
36 * between each attempt. When the busy bit is still set at that time,
37 * the access attempt is considered to have failed,
38 * and we will print an error.
39 */
40#define WAIT_FOR_BBP(__dev, __reg) \
41 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
42#define WAIT_FOR_RF(__dev, __reg) \
43 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
44
45static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
46 const unsigned int word, const u8 value)
47{
48 u32 reg;
49
50 mutex_lock(&rt2x00dev->csr_mutex);
51
52 /*
53 * Wait until the BBP becomes available, afterwards we
54 * can safely write the new data into the register.
55 */
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
57 reg = 0;
58 rt2x00_set_field32(®, BBPCSR_VALUE, value);
59 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
60 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
62
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
64 }
65
66 mutex_unlock(&rt2x00dev->csr_mutex);
67}
68
69static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
70 const unsigned int word)
71{
72 u32 reg;
73 u8 value;
74
75 mutex_lock(&rt2x00dev->csr_mutex);
76
77 /*
78 * Wait until the BBP becomes available, afterwards we
79 * can safely write the read request into the register.
80 * After the data has been written, we wait until hardware
81 * returns the correct value, if at any time the register
82 * doesn't become available in time, reg will be 0xffffffff
83 * which means we return 0xff to the caller.
84 */
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
86 reg = 0;
87 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
88 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
89 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
90
91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
92
93 WAIT_FOR_BBP(rt2x00dev, ®);
94 }
95
96 value = rt2x00_get_field32(reg, BBPCSR_VALUE);
97
98 mutex_unlock(&rt2x00dev->csr_mutex);
99
100 return value;
101}
102
103static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
104 const unsigned int word, const u32 value)
105{
106 u32 reg;
107
108 mutex_lock(&rt2x00dev->csr_mutex);
109
110 /*
111 * Wait until the RF becomes available, afterwards we
112 * can safely write the new data into the register.
113 */
114 if (WAIT_FOR_RF(rt2x00dev, ®)) {
115 reg = 0;
116 rt2x00_set_field32(®, RFCSR_VALUE, value);
117 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
118 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
119 rt2x00_set_field32(®, RFCSR_BUSY, 1);
120
121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
122 rt2x00_rf_write(rt2x00dev, word, value);
123 }
124
125 mutex_unlock(&rt2x00dev->csr_mutex);
126}
127
128static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
129{
130 struct rt2x00_dev *rt2x00dev = eeprom->data;
131 u32 reg;
132
133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
134
135 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
136 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
137 eeprom->reg_data_clock =
138 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
139 eeprom->reg_chip_select =
140 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
141}
142
143static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
144{
145 struct rt2x00_dev *rt2x00dev = eeprom->data;
146 u32 reg = 0;
147
148 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
149 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
150 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
151 !!eeprom->reg_data_clock);
152 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
153 !!eeprom->reg_chip_select);
154
155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
156}
157
158#ifdef CONFIG_RT2X00_LIB_DEBUGFS
159static const struct rt2x00debug rt2400pci_rt2x00debug = {
160 .owner = THIS_MODULE,
161 .csr = {
162 .read = rt2x00mmio_register_read,
163 .write = rt2x00mmio_register_write,
164 .flags = RT2X00DEBUGFS_OFFSET,
165 .word_base = CSR_REG_BASE,
166 .word_size = sizeof(u32),
167 .word_count = CSR_REG_SIZE / sizeof(u32),
168 },
169 .eeprom = {
170 .read = rt2x00_eeprom_read,
171 .write = rt2x00_eeprom_write,
172 .word_base = EEPROM_BASE,
173 .word_size = sizeof(u16),
174 .word_count = EEPROM_SIZE / sizeof(u16),
175 },
176 .bbp = {
177 .read = rt2400pci_bbp_read,
178 .write = rt2400pci_bbp_write,
179 .word_base = BBP_BASE,
180 .word_size = sizeof(u8),
181 .word_count = BBP_SIZE / sizeof(u8),
182 },
183 .rf = {
184 .read = rt2x00_rf_read,
185 .write = rt2400pci_rf_write,
186 .word_base = RF_BASE,
187 .word_size = sizeof(u32),
188 .word_count = RF_SIZE / sizeof(u32),
189 },
190};
191#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
192
193static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
194{
195 u32 reg;
196
197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
198 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
199}
200
201#ifdef CONFIG_RT2X00_LIB_LEDS
202static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
203 enum led_brightness brightness)
204{
205 struct rt2x00_led *led =
206 container_of(led_cdev, struct rt2x00_led, led_dev);
207 unsigned int enabled = brightness != LED_OFF;
208 u32 reg;
209
210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
211
212 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
213 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
214 else if (led->type == LED_TYPE_ACTIVITY)
215 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
216
217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
218}
219
220static int rt2400pci_blink_set(struct led_classdev *led_cdev,
221 unsigned long *delay_on,
222 unsigned long *delay_off)
223{
224 struct rt2x00_led *led =
225 container_of(led_cdev, struct rt2x00_led, led_dev);
226 u32 reg;
227
228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
229 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
230 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
232
233 return 0;
234}
235
236static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
237 struct rt2x00_led *led,
238 enum led_type type)
239{
240 led->rt2x00dev = rt2x00dev;
241 led->type = type;
242 led->led_dev.brightness_set = rt2400pci_brightness_set;
243 led->led_dev.blink_set = rt2400pci_blink_set;
244 led->flags = LED_INITIALIZED;
245}
246#endif /* CONFIG_RT2X00_LIB_LEDS */
247
248/*
249 * Configuration handlers.
250 */
251static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
252 const unsigned int filter_flags)
253{
254 u32 reg;
255
256 /*
257 * Start configuration steps.
258 * Note that the version error will always be dropped
259 * since there is no filter for it at this time.
260 */
261 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
262 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
263 !(filter_flags & FIF_FCSFAIL));
264 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
265 !(filter_flags & FIF_PLCPFAIL));
266 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
267 !(filter_flags & FIF_CONTROL));
268 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
269 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
270 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
271 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
272 !rt2x00dev->intf_ap_count);
273 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
274 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
275}
276
277static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
278 struct rt2x00_intf *intf,
279 struct rt2x00intf_conf *conf,
280 const unsigned int flags)
281{
282 unsigned int bcn_preload;
283 u32 reg;
284
285 if (flags & CONFIG_UPDATE_TYPE) {
286 /*
287 * Enable beacon config
288 */
289 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
290 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
291 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
292 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
293
294 /*
295 * Enable synchronisation.
296 */
297 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
298 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
299 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
300 }
301
302 if (flags & CONFIG_UPDATE_MAC)
303 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
304 conf->mac, sizeof(conf->mac));
305
306 if (flags & CONFIG_UPDATE_BSSID)
307 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
308 conf->bssid,
309 sizeof(conf->bssid));
310}
311
312static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
313 struct rt2x00lib_erp *erp,
314 u32 changed)
315{
316 int preamble_mask;
317 u32 reg;
318
319 /*
320 * When short preamble is enabled, we should set bit 0x08
321 */
322 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
323 preamble_mask = erp->short_preamble << 3;
324
325 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
326 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff);
327 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a);
328 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
329 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
330 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
331
332 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
333 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
334 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
335 rt2x00_set_field32(®, ARCSR2_LENGTH,
336 GET_DURATION(ACK_SIZE, 10));
337 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
338
339 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
340 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
341 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
342 rt2x00_set_field32(®, ARCSR2_LENGTH,
343 GET_DURATION(ACK_SIZE, 20));
344 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
345
346 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
347 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
348 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
349 rt2x00_set_field32(®, ARCSR2_LENGTH,
350 GET_DURATION(ACK_SIZE, 55));
351 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
352
353 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
354 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
355 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
356 rt2x00_set_field32(®, ARCSR2_LENGTH,
357 GET_DURATION(ACK_SIZE, 110));
358 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
359 }
360
361 if (changed & BSS_CHANGED_BASIC_RATES)
362 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
363
364 if (changed & BSS_CHANGED_ERP_SLOT) {
365 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
366 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
367 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
368
369 reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
370 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
371 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
372 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
373
374 reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
375 rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
376 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
377 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
378 }
379
380 if (changed & BSS_CHANGED_BEACON_INT) {
381 reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
382 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
383 erp->beacon_int * 16);
384 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
385 erp->beacon_int * 16);
386 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
387 }
388}
389
390static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
391 struct antenna_setup *ant)
392{
393 u8 r1;
394 u8 r4;
395
396 /*
397 * We should never come here because rt2x00lib is supposed
398 * to catch this and send us the correct antenna explicitely.
399 */
400 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
401 ant->tx == ANTENNA_SW_DIVERSITY);
402
403 r4 = rt2400pci_bbp_read(rt2x00dev, 4);
404 r1 = rt2400pci_bbp_read(rt2x00dev, 1);
405
406 /*
407 * Configure the TX antenna.
408 */
409 switch (ant->tx) {
410 case ANTENNA_HW_DIVERSITY:
411 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
412 break;
413 case ANTENNA_A:
414 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
415 break;
416 case ANTENNA_B:
417 default:
418 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
419 break;
420 }
421
422 /*
423 * Configure the RX antenna.
424 */
425 switch (ant->rx) {
426 case ANTENNA_HW_DIVERSITY:
427 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
428 break;
429 case ANTENNA_A:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
431 break;
432 case ANTENNA_B:
433 default:
434 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
435 break;
436 }
437
438 rt2400pci_bbp_write(rt2x00dev, 4, r4);
439 rt2400pci_bbp_write(rt2x00dev, 1, r1);
440}
441
442static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
443 struct rf_channel *rf)
444{
445 /*
446 * Switch on tuning bits.
447 */
448 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
449 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
450
451 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
452 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
453 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
454
455 /*
456 * RF2420 chipset don't need any additional actions.
457 */
458 if (rt2x00_rf(rt2x00dev, RF2420))
459 return;
460
461 /*
462 * For the RT2421 chipsets we need to write an invalid
463 * reference clock rate to activate auto_tune.
464 * After that we set the value back to the correct channel.
465 */
466 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
467 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
468 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
469
470 msleep(1);
471
472 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
473 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
474 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
475
476 msleep(1);
477
478 /*
479 * Switch off tuning bits.
480 */
481 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
482 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
483
484 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
485 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
486
487 /*
488 * Clear false CRC during channel switch.
489 */
490 rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
491}
492
493static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
494{
495 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
496}
497
498static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
499 struct rt2x00lib_conf *libconf)
500{
501 u32 reg;
502
503 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
504 rt2x00_set_field32(®, CSR11_LONG_RETRY,
505 libconf->conf->long_frame_max_tx_count);
506 rt2x00_set_field32(®, CSR11_SHORT_RETRY,
507 libconf->conf->short_frame_max_tx_count);
508 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
509}
510
511static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
512 struct rt2x00lib_conf *libconf)
513{
514 enum dev_state state =
515 (libconf->conf->flags & IEEE80211_CONF_PS) ?
516 STATE_SLEEP : STATE_AWAKE;
517 u32 reg;
518
519 if (state == STATE_SLEEP) {
520 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
521 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN,
522 (rt2x00dev->beacon_int - 20) * 16);
523 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP,
524 libconf->conf->listen_interval - 1);
525
526 /* We must first disable autowake before it can be enabled */
527 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
528 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
529
530 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1);
531 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
532 } else {
533 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
534 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
535 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
536 }
537
538 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
539}
540
541static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
542 struct rt2x00lib_conf *libconf,
543 const unsigned int flags)
544{
545 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
546 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
547 if (flags & IEEE80211_CONF_CHANGE_POWER)
548 rt2400pci_config_txpower(rt2x00dev,
549 libconf->conf->power_level);
550 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
551 rt2400pci_config_retry_limit(rt2x00dev, libconf);
552 if (flags & IEEE80211_CONF_CHANGE_PS)
553 rt2400pci_config_ps(rt2x00dev, libconf);
554}
555
556static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
557 const int cw_min, const int cw_max)
558{
559 u32 reg;
560
561 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
562 rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
563 rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
564 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
565}
566
567/*
568 * Link tuning
569 */
570static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
571 struct link_qual *qual)
572{
573 u32 reg;
574 u8 bbp;
575
576 /*
577 * Update FCS error count from register.
578 */
579 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
580 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
581
582 /*
583 * Update False CCA count from register.
584 */
585 bbp = rt2400pci_bbp_read(rt2x00dev, 39);
586 qual->false_cca = bbp;
587}
588
589static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
590 struct link_qual *qual, u8 vgc_level)
591{
592 if (qual->vgc_level_reg != vgc_level) {
593 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
594 qual->vgc_level = vgc_level;
595 qual->vgc_level_reg = vgc_level;
596 }
597}
598
599static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
600 struct link_qual *qual)
601{
602 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
603}
604
605static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
606 struct link_qual *qual, const u32 count)
607{
608 /*
609 * The link tuner should not run longer then 60 seconds,
610 * and should run once every 2 seconds.
611 */
612 if (count > 60 || !(count & 1))
613 return;
614
615 /*
616 * Base r13 link tuning on the false cca count.
617 */
618 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
619 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
620 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
621 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
622}
623
624/*
625 * Queue handlers.
626 */
627static void rt2400pci_start_queue(struct data_queue *queue)
628{
629 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
630 u32 reg;
631
632 switch (queue->qid) {
633 case QID_RX:
634 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
635 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0);
636 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
637 break;
638 case QID_BEACON:
639 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
640 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
641 rt2x00_set_field32(®, CSR14_TBCN, 1);
642 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
643 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
644 break;
645 default:
646 break;
647 }
648}
649
650static void rt2400pci_kick_queue(struct data_queue *queue)
651{
652 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
653 u32 reg;
654
655 switch (queue->qid) {
656 case QID_AC_VO:
657 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
658 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
659 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
660 break;
661 case QID_AC_VI:
662 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
663 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
664 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
665 break;
666 case QID_ATIM:
667 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
668 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
669 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
670 break;
671 default:
672 break;
673 }
674}
675
676static void rt2400pci_stop_queue(struct data_queue *queue)
677{
678 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
679 u32 reg;
680
681 switch (queue->qid) {
682 case QID_AC_VO:
683 case QID_AC_VI:
684 case QID_ATIM:
685 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
686 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
687 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
688 break;
689 case QID_RX:
690 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
691 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1);
692 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
693 break;
694 case QID_BEACON:
695 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
696 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
697 rt2x00_set_field32(®, CSR14_TBCN, 0);
698 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
699 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
700
701 /*
702 * Wait for possibly running tbtt tasklets.
703 */
704 tasklet_kill(&rt2x00dev->tbtt_tasklet);
705 break;
706 default:
707 break;
708 }
709}
710
711/*
712 * Initialization functions.
713 */
714static bool rt2400pci_get_entry_state(struct queue_entry *entry)
715{
716 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
717 u32 word;
718
719 if (entry->queue->qid == QID_RX) {
720 word = rt2x00_desc_read(entry_priv->desc, 0);
721
722 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
723 } else {
724 word = rt2x00_desc_read(entry_priv->desc, 0);
725
726 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
727 rt2x00_get_field32(word, TXD_W0_VALID));
728 }
729}
730
731static void rt2400pci_clear_entry(struct queue_entry *entry)
732{
733 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
734 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
735 u32 word;
736
737 if (entry->queue->qid == QID_RX) {
738 word = rt2x00_desc_read(entry_priv->desc, 2);
739 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
740 rt2x00_desc_write(entry_priv->desc, 2, word);
741
742 word = rt2x00_desc_read(entry_priv->desc, 1);
743 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
744 rt2x00_desc_write(entry_priv->desc, 1, word);
745
746 word = rt2x00_desc_read(entry_priv->desc, 0);
747 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
748 rt2x00_desc_write(entry_priv->desc, 0, word);
749 } else {
750 word = rt2x00_desc_read(entry_priv->desc, 0);
751 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
752 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
753 rt2x00_desc_write(entry_priv->desc, 0, word);
754 }
755}
756
757static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
758{
759 struct queue_entry_priv_mmio *entry_priv;
760 u32 reg;
761
762 /*
763 * Initialize registers.
764 */
765 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
766 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
767 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
768 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
769 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
770 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
771
772 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
773 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
774 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
775 entry_priv->desc_dma);
776 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
777
778 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
779 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
780 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
781 entry_priv->desc_dma);
782 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
783
784 entry_priv = rt2x00dev->atim->entries[0].priv_data;
785 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
786 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
787 entry_priv->desc_dma);
788 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
789
790 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
791 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
792 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
793 entry_priv->desc_dma);
794 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
795
796 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
797 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
798 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
799 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
800
801 entry_priv = rt2x00dev->rx->entries[0].priv_data;
802 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
803 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
804 entry_priv->desc_dma);
805 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
806
807 return 0;
808}
809
810static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
811{
812 u32 reg;
813
814 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
815 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
816 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
817 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
818
819 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
820 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
821 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
822 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
823 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
824
825 reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
826 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
827 (rt2x00dev->rx->data_size / 128));
828 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
829
830 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
831 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
832 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
833 rt2x00_set_field32(®, CSR14_TBCN, 0);
834 rt2x00_set_field32(®, CSR14_TCFP, 0);
835 rt2x00_set_field32(®, CSR14_TATIMW, 0);
836 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
837 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
838 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
839 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
840
841 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
842
843 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);
844 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
845 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
846 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
847 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
848 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
849
850 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
851 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
852 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
853 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
854 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
855 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
856 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
857 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
858
859 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
860
861 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
862 return -EBUSY;
863
864 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
865 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
866
867 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
868 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
869 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
870
871 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
872 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
873 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
874 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
875 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
876 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
877
878 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
879 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
880 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
881 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
882 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
883
884 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
885 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
886 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
887 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
888
889 /*
890 * We must clear the FCS and FIFO error count.
891 * These registers are cleared on read,
892 * so we may pass a useless variable to store the value.
893 */
894 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
895 reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
896
897 return 0;
898}
899
900static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
901{
902 unsigned int i;
903 u8 value;
904
905 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
906 value = rt2400pci_bbp_read(rt2x00dev, 0);
907 if ((value != 0xff) && (value != 0x00))
908 return 0;
909 udelay(REGISTER_BUSY_DELAY);
910 }
911
912 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
913 return -EACCES;
914}
915
916static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
917{
918 unsigned int i;
919 u16 eeprom;
920 u8 reg_id;
921 u8 value;
922
923 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
924 return -EACCES;
925
926 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
927 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
928 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
929 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
930 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
931 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
932 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
933 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
934 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
935 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
936 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
937 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
938 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
939 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
940
941 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
942 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
943
944 if (eeprom != 0xffff && eeprom != 0x0000) {
945 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
946 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
947 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
948 }
949 }
950
951 return 0;
952}
953
954/*
955 * Device state switch handlers.
956 */
957static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
958 enum dev_state state)
959{
960 int mask = (state == STATE_RADIO_IRQ_OFF);
961 u32 reg;
962 unsigned long flags;
963
964 /*
965 * When interrupts are being enabled, the interrupt registers
966 * should clear the register to assure a clean state.
967 */
968 if (state == STATE_RADIO_IRQ_ON) {
969 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
970 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
971 }
972
973 /*
974 * Only toggle the interrupts bits we are going to use.
975 * Non-checked interrupt bits are disabled by default.
976 */
977 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
978
979 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
980 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
981 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
982 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
983 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
984 rt2x00_set_field32(®, CSR8_RXDONE, mask);
985 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
986
987 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
988
989 if (state == STATE_RADIO_IRQ_OFF) {
990 /*
991 * Ensure that all tasklets are finished before
992 * disabling the interrupts.
993 */
994 tasklet_kill(&rt2x00dev->txstatus_tasklet);
995 tasklet_kill(&rt2x00dev->rxdone_tasklet);
996 tasklet_kill(&rt2x00dev->tbtt_tasklet);
997 }
998}
999
1000static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1001{
1002 /*
1003 * Initialize all registers.
1004 */
1005 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1006 rt2400pci_init_registers(rt2x00dev) ||
1007 rt2400pci_init_bbp(rt2x00dev)))
1008 return -EIO;
1009
1010 return 0;
1011}
1012
1013static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1014{
1015 /*
1016 * Disable power
1017 */
1018 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1019}
1020
1021static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1022 enum dev_state state)
1023{
1024 u32 reg, reg2;
1025 unsigned int i;
1026 bool put_to_sleep;
1027 u8 bbp_state;
1028 u8 rf_state;
1029
1030 put_to_sleep = (state != STATE_AWAKE);
1031
1032 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1033 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
1034 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
1035 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
1036 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1037 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1038
1039 /*
1040 * Device is not guaranteed to be in the requested state yet.
1041 * We must wait until the register indicates that the
1042 * device has entered the correct state.
1043 */
1044 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1045 reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1046 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1047 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1048 if (bbp_state == state && rf_state == state)
1049 return 0;
1050 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1051 msleep(10);
1052 }
1053
1054 return -EBUSY;
1055}
1056
1057static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1058 enum dev_state state)
1059{
1060 int retval = 0;
1061
1062 switch (state) {
1063 case STATE_RADIO_ON:
1064 retval = rt2400pci_enable_radio(rt2x00dev);
1065 break;
1066 case STATE_RADIO_OFF:
1067 rt2400pci_disable_radio(rt2x00dev);
1068 break;
1069 case STATE_RADIO_IRQ_ON:
1070 case STATE_RADIO_IRQ_OFF:
1071 rt2400pci_toggle_irq(rt2x00dev, state);
1072 break;
1073 case STATE_DEEP_SLEEP:
1074 case STATE_SLEEP:
1075 case STATE_STANDBY:
1076 case STATE_AWAKE:
1077 retval = rt2400pci_set_state(rt2x00dev, state);
1078 break;
1079 default:
1080 retval = -ENOTSUPP;
1081 break;
1082 }
1083
1084 if (unlikely(retval))
1085 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1086 state, retval);
1087
1088 return retval;
1089}
1090
1091/*
1092 * TX descriptor initialization
1093 */
1094static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1095 struct txentry_desc *txdesc)
1096{
1097 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1098 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1099 __le32 *txd = entry_priv->desc;
1100 u32 word;
1101
1102 /*
1103 * Start writing the descriptor words.
1104 */
1105 word = rt2x00_desc_read(txd, 1);
1106 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1107 rt2x00_desc_write(txd, 1, word);
1108
1109 word = rt2x00_desc_read(txd, 2);
1110 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1111 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1112 rt2x00_desc_write(txd, 2, word);
1113
1114 word = rt2x00_desc_read(txd, 3);
1115 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1116 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1117 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1118 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1119 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1120 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1121 rt2x00_desc_write(txd, 3, word);
1122
1123 word = rt2x00_desc_read(txd, 4);
1124 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1125 txdesc->u.plcp.length_low);
1126 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1127 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1128 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1129 txdesc->u.plcp.length_high);
1130 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1131 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1132 rt2x00_desc_write(txd, 4, word);
1133
1134 /*
1135 * Writing TXD word 0 must the last to prevent a race condition with
1136 * the device, whereby the device may take hold of the TXD before we
1137 * finished updating it.
1138 */
1139 word = rt2x00_desc_read(txd, 0);
1140 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1141 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1142 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1143 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1144 rt2x00_set_field32(&word, TXD_W0_ACK,
1145 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1146 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1147 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1148 rt2x00_set_field32(&word, TXD_W0_RTS,
1149 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1150 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1151 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1152 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1153 rt2x00_desc_write(txd, 0, word);
1154
1155 /*
1156 * Register descriptor details in skb frame descriptor.
1157 */
1158 skbdesc->desc = txd;
1159 skbdesc->desc_len = TXD_DESC_SIZE;
1160}
1161
1162/*
1163 * TX data initialization
1164 */
1165static void rt2400pci_write_beacon(struct queue_entry *entry,
1166 struct txentry_desc *txdesc)
1167{
1168 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1169 u32 reg;
1170
1171 /*
1172 * Disable beaconing while we are reloading the beacon data,
1173 * otherwise we might be sending out invalid data.
1174 */
1175 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1176 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1177 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1178
1179 if (rt2x00queue_map_txskb(entry)) {
1180 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1181 goto out;
1182 }
1183 /*
1184 * Enable beaconing again.
1185 */
1186 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1187 /*
1188 * Write the TX descriptor for the beacon.
1189 */
1190 rt2400pci_write_tx_desc(entry, txdesc);
1191
1192 /*
1193 * Dump beacon to userspace through debugfs.
1194 */
1195 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1196out:
1197 /*
1198 * Enable beaconing again.
1199 */
1200 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1201 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1202}
1203
1204/*
1205 * RX control handlers
1206 */
1207static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1208 struct rxdone_entry_desc *rxdesc)
1209{
1210 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1211 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1212 u32 word0;
1213 u32 word2;
1214 u32 word3;
1215 u32 word4;
1216 u64 tsf;
1217 u32 rx_low;
1218 u32 rx_high;
1219
1220 word0 = rt2x00_desc_read(entry_priv->desc, 0);
1221 word2 = rt2x00_desc_read(entry_priv->desc, 2);
1222 word3 = rt2x00_desc_read(entry_priv->desc, 3);
1223 word4 = rt2x00_desc_read(entry_priv->desc, 4);
1224
1225 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1226 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1227 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1228 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1229
1230 /*
1231 * We only get the lower 32bits from the timestamp,
1232 * to get the full 64bits we must complement it with
1233 * the timestamp from get_tsf().
1234 * Note that when a wraparound of the lower 32bits
1235 * has occurred between the frame arrival and the get_tsf()
1236 * call, we must decrease the higher 32bits with 1 to get
1237 * to correct value.
1238 */
1239 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
1240 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1241 rx_high = upper_32_bits(tsf);
1242
1243 if ((u32)tsf <= rx_low)
1244 rx_high--;
1245
1246 /*
1247 * Obtain the status about this packet.
1248 * The signal is the PLCP value, and needs to be stripped
1249 * of the preamble bit (0x08).
1250 */
1251 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1252 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1253 rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) -
1254 entry->queue->rt2x00dev->rssi_offset;
1255 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1256
1257 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1258 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1259 rxdesc->dev_flags |= RXDONE_MY_BSS;
1260}
1261
1262/*
1263 * Interrupt functions.
1264 */
1265static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1266 const enum data_queue_qid queue_idx)
1267{
1268 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1269 struct queue_entry_priv_mmio *entry_priv;
1270 struct queue_entry *entry;
1271 struct txdone_entry_desc txdesc;
1272 u32 word;
1273
1274 while (!rt2x00queue_empty(queue)) {
1275 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1276 entry_priv = entry->priv_data;
1277 word = rt2x00_desc_read(entry_priv->desc, 0);
1278
1279 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1280 !rt2x00_get_field32(word, TXD_W0_VALID))
1281 break;
1282
1283 /*
1284 * Obtain the status about this packet.
1285 */
1286 txdesc.flags = 0;
1287 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1288 case 0: /* Success */
1289 case 1: /* Success with retry */
1290 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1291 break;
1292 case 2: /* Failure, excessive retries */
1293 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1294 fallthrough; /* this is a failed frame! */
1295 default: /* Failure */
1296 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1297 }
1298 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1299
1300 rt2x00lib_txdone(entry, &txdesc);
1301 }
1302}
1303
1304static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1305 struct rt2x00_field32 irq_field)
1306{
1307 u32 reg;
1308
1309 /*
1310 * Enable a single interrupt. The interrupt mask register
1311 * access needs locking.
1312 */
1313 spin_lock_irq(&rt2x00dev->irqmask_lock);
1314
1315 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1316 rt2x00_set_field32(®, irq_field, 0);
1317 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1318
1319 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1320}
1321
1322static void rt2400pci_txstatus_tasklet(struct tasklet_struct *t)
1323{
1324 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1325 txstatus_tasklet);
1326 u32 reg;
1327
1328 /*
1329 * Handle all tx queues.
1330 */
1331 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1332 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1333 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1334
1335 /*
1336 * Enable all TXDONE interrupts again.
1337 */
1338 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1339 spin_lock_irq(&rt2x00dev->irqmask_lock);
1340
1341 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1342 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
1343 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
1344 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
1345 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1346
1347 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1348 }
1349}
1350
1351static void rt2400pci_tbtt_tasklet(struct tasklet_struct *t)
1352{
1353 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);
1354 rt2x00lib_beacondone(rt2x00dev);
1355 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1356 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1357}
1358
1359static void rt2400pci_rxdone_tasklet(struct tasklet_struct *t)
1360{
1361 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,
1362 rxdone_tasklet);
1363 if (rt2x00mmio_rxdone(rt2x00dev))
1364 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1365 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1366 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1367}
1368
1369static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1370{
1371 struct rt2x00_dev *rt2x00dev = dev_instance;
1372 u32 reg, mask;
1373
1374 /*
1375 * Get the interrupt sources & saved to local variable.
1376 * Write register value back to clear pending interrupts.
1377 */
1378 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1379 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1380
1381 if (!reg)
1382 return IRQ_NONE;
1383
1384 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1385 return IRQ_HANDLED;
1386
1387 mask = reg;
1388
1389 /*
1390 * Schedule tasklets for interrupt handling.
1391 */
1392 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1393 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1394
1395 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1396 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1397
1398 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1399 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1400 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1401 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1402 /*
1403 * Mask out all txdone interrupts.
1404 */
1405 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1406 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1407 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1408 }
1409
1410 /*
1411 * Disable all interrupts for which a tasklet was scheduled right now,
1412 * the tasklet will reenable the appropriate interrupts.
1413 */
1414 spin_lock(&rt2x00dev->irqmask_lock);
1415
1416 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1417 reg |= mask;
1418 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1419
1420 spin_unlock(&rt2x00dev->irqmask_lock);
1421
1422
1423
1424 return IRQ_HANDLED;
1425}
1426
1427/*
1428 * Device probe functions.
1429 */
1430static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1431{
1432 struct eeprom_93cx6 eeprom;
1433 u32 reg;
1434 u16 word;
1435 u8 *mac;
1436
1437 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
1438
1439 eeprom.data = rt2x00dev;
1440 eeprom.register_read = rt2400pci_eepromregister_read;
1441 eeprom.register_write = rt2400pci_eepromregister_write;
1442 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1443 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1444 eeprom.reg_data_in = 0;
1445 eeprom.reg_data_out = 0;
1446 eeprom.reg_data_clock = 0;
1447 eeprom.reg_chip_select = 0;
1448
1449 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1450 EEPROM_SIZE / sizeof(u16));
1451
1452 /*
1453 * Start validation of the data that has been read.
1454 */
1455 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1456 rt2x00lib_set_mac_address(rt2x00dev, mac);
1457
1458 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1459 if (word == 0xffff) {
1460 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
1461 return -EINVAL;
1462 }
1463
1464 return 0;
1465}
1466
1467static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1468{
1469 u32 reg;
1470 u16 value;
1471 u16 eeprom;
1472
1473 /*
1474 * Read EEPROM word for configuration.
1475 */
1476 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1477
1478 /*
1479 * Identify RF chipset.
1480 */
1481 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1482 reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
1483 rt2x00_set_chip(rt2x00dev, RT2460, value,
1484 rt2x00_get_field32(reg, CSR0_REVISION));
1485
1486 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1487 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1488 return -ENODEV;
1489 }
1490
1491 /*
1492 * Identify default antenna configuration.
1493 */
1494 rt2x00dev->default_ant.tx =
1495 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1496 rt2x00dev->default_ant.rx =
1497 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1498
1499 /*
1500 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1501 * I am not 100% sure about this, but the legacy drivers do not
1502 * indicate antenna swapping in software is required when
1503 * diversity is enabled.
1504 */
1505 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1506 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1507 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1508 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1509
1510 /*
1511 * Store led mode, for correct led behaviour.
1512 */
1513#ifdef CONFIG_RT2X00_LIB_LEDS
1514 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1515
1516 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1517 if (value == LED_MODE_TXRX_ACTIVITY ||
1518 value == LED_MODE_DEFAULT ||
1519 value == LED_MODE_ASUS)
1520 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1521 LED_TYPE_ACTIVITY);
1522#endif /* CONFIG_RT2X00_LIB_LEDS */
1523
1524 /*
1525 * Detect if this device has an hardware controlled radio.
1526 */
1527 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1528 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1529
1530 /*
1531 * Check if the BBP tuning should be enabled.
1532 */
1533 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1534 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1535
1536 return 0;
1537}
1538
1539/*
1540 * RF value list for RF2420 & RF2421
1541 * Supports: 2.4 GHz
1542 */
1543static const struct rf_channel rf_vals_b[] = {
1544 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1545 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1546 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1547 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1548 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1549 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1550 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1551 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1552 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1553 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1554 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1555 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1556 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1557 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1558};
1559
1560static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1561{
1562 struct hw_mode_spec *spec = &rt2x00dev->spec;
1563 struct channel_info *info;
1564 u8 *tx_power;
1565 unsigned int i;
1566
1567 /*
1568 * Initialize all hw fields.
1569 */
1570 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1571 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1572 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1573 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
1574
1575 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1576 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1577 rt2x00_eeprom_addr(rt2x00dev,
1578 EEPROM_MAC_ADDR_0));
1579
1580 /*
1581 * Initialize hw_mode information.
1582 */
1583 spec->supported_bands = SUPPORT_BAND_2GHZ;
1584 spec->supported_rates = SUPPORT_RATE_CCK;
1585
1586 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1587 spec->channels = rf_vals_b;
1588
1589 /*
1590 * Create channel information array
1591 */
1592 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1593 if (!info)
1594 return -ENOMEM;
1595
1596 spec->channels_info = info;
1597
1598 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1599 for (i = 0; i < 14; i++) {
1600 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1601 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1602 }
1603
1604 return 0;
1605}
1606
1607static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1608{
1609 int retval;
1610 u32 reg;
1611
1612 /*
1613 * Allocate eeprom data.
1614 */
1615 retval = rt2400pci_validate_eeprom(rt2x00dev);
1616 if (retval)
1617 return retval;
1618
1619 retval = rt2400pci_init_eeprom(rt2x00dev);
1620 if (retval)
1621 return retval;
1622
1623 /*
1624 * Enable rfkill polling by setting GPIO direction of the
1625 * rfkill switch GPIO pin correctly.
1626 */
1627 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
1628 rt2x00_set_field32(®, GPIOCSR_DIR0, 1);
1629 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1630
1631 /*
1632 * Initialize hw specifications.
1633 */
1634 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1635 if (retval)
1636 return retval;
1637
1638 /*
1639 * This device requires the atim queue and DMA-mapped skbs.
1640 */
1641 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1642 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1643 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1644
1645 /*
1646 * Set the rssi offset.
1647 */
1648 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1649
1650 return 0;
1651}
1652
1653/*
1654 * IEEE80211 stack callback functions.
1655 */
1656static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1657 struct ieee80211_vif *vif,
1658 unsigned int link_id, u16 queue,
1659 const struct ieee80211_tx_queue_params *params)
1660{
1661 struct rt2x00_dev *rt2x00dev = hw->priv;
1662
1663 /*
1664 * We don't support variating cw_min and cw_max variables
1665 * per queue. So by default we only configure the TX queue,
1666 * and ignore all other configurations.
1667 */
1668 if (queue != 0)
1669 return -EINVAL;
1670
1671 if (rt2x00mac_conf_tx(hw, vif, link_id, queue, params))
1672 return -EINVAL;
1673
1674 /*
1675 * Write configuration to register.
1676 */
1677 rt2400pci_config_cw(rt2x00dev,
1678 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1679
1680 return 0;
1681}
1682
1683static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1684 struct ieee80211_vif *vif)
1685{
1686 struct rt2x00_dev *rt2x00dev = hw->priv;
1687 u64 tsf;
1688 u32 reg;
1689
1690 reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
1691 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1692 reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
1693 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1694
1695 return tsf;
1696}
1697
1698static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1699{
1700 struct rt2x00_dev *rt2x00dev = hw->priv;
1701 u32 reg;
1702
1703 reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
1704 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1705}
1706
1707static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1708 .tx = rt2x00mac_tx,
1709 .wake_tx_queue = ieee80211_handle_wake_tx_queue,
1710 .start = rt2x00mac_start,
1711 .stop = rt2x00mac_stop,
1712 .add_interface = rt2x00mac_add_interface,
1713 .remove_interface = rt2x00mac_remove_interface,
1714 .config = rt2x00mac_config,
1715 .configure_filter = rt2x00mac_configure_filter,
1716 .sw_scan_start = rt2x00mac_sw_scan_start,
1717 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1718 .get_stats = rt2x00mac_get_stats,
1719 .bss_info_changed = rt2x00mac_bss_info_changed,
1720 .conf_tx = rt2400pci_conf_tx,
1721 .get_tsf = rt2400pci_get_tsf,
1722 .tx_last_beacon = rt2400pci_tx_last_beacon,
1723 .rfkill_poll = rt2x00mac_rfkill_poll,
1724 .flush = rt2x00mac_flush,
1725 .set_antenna = rt2x00mac_set_antenna,
1726 .get_antenna = rt2x00mac_get_antenna,
1727 .get_ringparam = rt2x00mac_get_ringparam,
1728 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1729};
1730
1731static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1732 .irq_handler = rt2400pci_interrupt,
1733 .txstatus_tasklet = rt2400pci_txstatus_tasklet,
1734 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1735 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
1736 .probe_hw = rt2400pci_probe_hw,
1737 .initialize = rt2x00mmio_initialize,
1738 .uninitialize = rt2x00mmio_uninitialize,
1739 .get_entry_state = rt2400pci_get_entry_state,
1740 .clear_entry = rt2400pci_clear_entry,
1741 .set_device_state = rt2400pci_set_device_state,
1742 .rfkill_poll = rt2400pci_rfkill_poll,
1743 .link_stats = rt2400pci_link_stats,
1744 .reset_tuner = rt2400pci_reset_tuner,
1745 .link_tuner = rt2400pci_link_tuner,
1746 .start_queue = rt2400pci_start_queue,
1747 .kick_queue = rt2400pci_kick_queue,
1748 .stop_queue = rt2400pci_stop_queue,
1749 .flush_queue = rt2x00mmio_flush_queue,
1750 .write_tx_desc = rt2400pci_write_tx_desc,
1751 .write_beacon = rt2400pci_write_beacon,
1752 .fill_rxdone = rt2400pci_fill_rxdone,
1753 .config_filter = rt2400pci_config_filter,
1754 .config_intf = rt2400pci_config_intf,
1755 .config_erp = rt2400pci_config_erp,
1756 .config_ant = rt2400pci_config_ant,
1757 .config = rt2400pci_config,
1758};
1759
1760static void rt2400pci_queue_init(struct data_queue *queue)
1761{
1762 switch (queue->qid) {
1763 case QID_RX:
1764 queue->limit = 24;
1765 queue->data_size = DATA_FRAME_SIZE;
1766 queue->desc_size = RXD_DESC_SIZE;
1767 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1768 break;
1769
1770 case QID_AC_VO:
1771 case QID_AC_VI:
1772 case QID_AC_BE:
1773 case QID_AC_BK:
1774 queue->limit = 24;
1775 queue->data_size = DATA_FRAME_SIZE;
1776 queue->desc_size = TXD_DESC_SIZE;
1777 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1778 break;
1779
1780 case QID_BEACON:
1781 queue->limit = 1;
1782 queue->data_size = MGMT_FRAME_SIZE;
1783 queue->desc_size = TXD_DESC_SIZE;
1784 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1785 break;
1786
1787 case QID_ATIM:
1788 queue->limit = 8;
1789 queue->data_size = DATA_FRAME_SIZE;
1790 queue->desc_size = TXD_DESC_SIZE;
1791 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1792 break;
1793
1794 default:
1795 BUG();
1796 break;
1797 }
1798}
1799
1800static const struct rt2x00_ops rt2400pci_ops = {
1801 .name = KBUILD_MODNAME,
1802 .max_ap_intf = 1,
1803 .eeprom_size = EEPROM_SIZE,
1804 .rf_size = RF_SIZE,
1805 .tx_queues = NUM_TX_QUEUES,
1806 .queue_init = rt2400pci_queue_init,
1807 .lib = &rt2400pci_rt2x00_ops,
1808 .hw = &rt2400pci_mac80211_ops,
1809#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1810 .debugfs = &rt2400pci_rt2x00debug,
1811#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1812};
1813
1814/*
1815 * RT2400pci module information.
1816 */
1817static const struct pci_device_id rt2400pci_device_table[] = {
1818 { PCI_DEVICE(0x1814, 0x0101) },
1819 { 0, }
1820};
1821
1822
1823MODULE_AUTHOR(DRV_PROJECT);
1824MODULE_VERSION(DRV_VERSION);
1825MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1826MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1827MODULE_LICENSE("GPL");
1828
1829static int rt2400pci_probe(struct pci_dev *pci_dev,
1830 const struct pci_device_id *id)
1831{
1832 return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1833}
1834
1835static struct pci_driver rt2400pci_driver = {
1836 .name = KBUILD_MODNAME,
1837 .id_table = rt2400pci_device_table,
1838 .probe = rt2400pci_probe,
1839 .remove = rt2x00pci_remove,
1840 .driver.pm = &rt2x00pci_pm_ops,
1841};
1842
1843module_pci_driver(rt2400pci_driver);
1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19/*
20 Module: rt2400pci
21 Abstract: rt2400pci device specific routines.
22 Supported chipsets: RT2460.
23 */
24
25#include <linux/delay.h>
26#include <linux/etherdevice.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/eeprom_93cx6.h>
31#include <linux/slab.h>
32
33#include "rt2x00.h"
34#include "rt2x00mmio.h"
35#include "rt2x00pci.h"
36#include "rt2400pci.h"
37
38/*
39 * Register access.
40 * All access to the CSR registers will go through the methods
41 * rt2x00mmio_register_read and rt2x00mmio_register_write.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attempt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 */
51#define WAIT_FOR_BBP(__dev, __reg) \
52 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
53#define WAIT_FOR_RF(__dev, __reg) \
54 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
55
56static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
57 const unsigned int word, const u8 value)
58{
59 u32 reg;
60
61 mutex_lock(&rt2x00dev->csr_mutex);
62
63 /*
64 * Wait until the BBP becomes available, afterwards we
65 * can safely write the new data into the register.
66 */
67 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
68 reg = 0;
69 rt2x00_set_field32(®, BBPCSR_VALUE, value);
70 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
71 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
72 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
73
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
75 }
76
77 mutex_unlock(&rt2x00dev->csr_mutex);
78}
79
80static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
81 const unsigned int word)
82{
83 u32 reg;
84 u8 value;
85
86 mutex_lock(&rt2x00dev->csr_mutex);
87
88 /*
89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
97 reg = 0;
98 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
101
102 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
103
104 WAIT_FOR_BBP(rt2x00dev, ®);
105 }
106
107 value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110
111 return value;
112}
113
114static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
115 const unsigned int word, const u32 value)
116{
117 u32 reg;
118
119 mutex_lock(&rt2x00dev->csr_mutex);
120
121 /*
122 * Wait until the RF becomes available, afterwards we
123 * can safely write the new data into the register.
124 */
125 if (WAIT_FOR_RF(rt2x00dev, ®)) {
126 reg = 0;
127 rt2x00_set_field32(®, RFCSR_VALUE, value);
128 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
129 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
130 rt2x00_set_field32(®, RFCSR_BUSY, 1);
131
132 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
133 rt2x00_rf_write(rt2x00dev, word, value);
134 }
135
136 mutex_unlock(&rt2x00dev->csr_mutex);
137}
138
139static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
140{
141 struct rt2x00_dev *rt2x00dev = eeprom->data;
142 u32 reg;
143
144 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
145
146 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
147 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
148 eeprom->reg_data_clock =
149 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
150 eeprom->reg_chip_select =
151 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
152}
153
154static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
155{
156 struct rt2x00_dev *rt2x00dev = eeprom->data;
157 u32 reg = 0;
158
159 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
160 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
161 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
162 !!eeprom->reg_data_clock);
163 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
164 !!eeprom->reg_chip_select);
165
166 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
167}
168
169#ifdef CONFIG_RT2X00_LIB_DEBUGFS
170static const struct rt2x00debug rt2400pci_rt2x00debug = {
171 .owner = THIS_MODULE,
172 .csr = {
173 .read = rt2x00mmio_register_read,
174 .write = rt2x00mmio_register_write,
175 .flags = RT2X00DEBUGFS_OFFSET,
176 .word_base = CSR_REG_BASE,
177 .word_size = sizeof(u32),
178 .word_count = CSR_REG_SIZE / sizeof(u32),
179 },
180 .eeprom = {
181 .read = rt2x00_eeprom_read,
182 .write = rt2x00_eeprom_write,
183 .word_base = EEPROM_BASE,
184 .word_size = sizeof(u16),
185 .word_count = EEPROM_SIZE / sizeof(u16),
186 },
187 .bbp = {
188 .read = rt2400pci_bbp_read,
189 .write = rt2400pci_bbp_write,
190 .word_base = BBP_BASE,
191 .word_size = sizeof(u8),
192 .word_count = BBP_SIZE / sizeof(u8),
193 },
194 .rf = {
195 .read = rt2x00_rf_read,
196 .write = rt2400pci_rf_write,
197 .word_base = RF_BASE,
198 .word_size = sizeof(u32),
199 .word_count = RF_SIZE / sizeof(u32),
200 },
201};
202#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
203
204static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
205{
206 u32 reg;
207
208 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
209 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
210}
211
212#ifdef CONFIG_RT2X00_LIB_LEDS
213static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
214 enum led_brightness brightness)
215{
216 struct rt2x00_led *led =
217 container_of(led_cdev, struct rt2x00_led, led_dev);
218 unsigned int enabled = brightness != LED_OFF;
219 u32 reg;
220
221 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
222
223 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
224 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
225 else if (led->type == LED_TYPE_ACTIVITY)
226 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
227
228 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
229}
230
231static int rt2400pci_blink_set(struct led_classdev *led_cdev,
232 unsigned long *delay_on,
233 unsigned long *delay_off)
234{
235 struct rt2x00_led *led =
236 container_of(led_cdev, struct rt2x00_led, led_dev);
237 u32 reg;
238
239 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);
240 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
241 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
242 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
243
244 return 0;
245}
246
247static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
248 struct rt2x00_led *led,
249 enum led_type type)
250{
251 led->rt2x00dev = rt2x00dev;
252 led->type = type;
253 led->led_dev.brightness_set = rt2400pci_brightness_set;
254 led->led_dev.blink_set = rt2400pci_blink_set;
255 led->flags = LED_INITIALIZED;
256}
257#endif /* CONFIG_RT2X00_LIB_LEDS */
258
259/*
260 * Configuration handlers.
261 */
262static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
263 const unsigned int filter_flags)
264{
265 u32 reg;
266
267 /*
268 * Start configuration steps.
269 * Note that the version error will always be dropped
270 * since there is no filter for it at this time.
271 */
272 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
273 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
274 !(filter_flags & FIF_FCSFAIL));
275 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
276 !(filter_flags & FIF_PLCPFAIL));
277 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
278 !(filter_flags & FIF_CONTROL));
279 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
280 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
281 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
282 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
283 !rt2x00dev->intf_ap_count);
284 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
285 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
286}
287
288static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
289 struct rt2x00_intf *intf,
290 struct rt2x00intf_conf *conf,
291 const unsigned int flags)
292{
293 unsigned int bcn_preload;
294 u32 reg;
295
296 if (flags & CONFIG_UPDATE_TYPE) {
297 /*
298 * Enable beacon config
299 */
300 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
301 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);
302 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
303 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
304
305 /*
306 * Enable synchronisation.
307 */
308 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
309 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
310 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
311 }
312
313 if (flags & CONFIG_UPDATE_MAC)
314 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
315 conf->mac, sizeof(conf->mac));
316
317 if (flags & CONFIG_UPDATE_BSSID)
318 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
319 conf->bssid,
320 sizeof(conf->bssid));
321}
322
323static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
324 struct rt2x00lib_erp *erp,
325 u32 changed)
326{
327 int preamble_mask;
328 u32 reg;
329
330 /*
331 * When short preamble is enabled, we should set bit 0x08
332 */
333 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
334 preamble_mask = erp->short_preamble << 3;
335
336 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);
337 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff);
338 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a);
339 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
340 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
341 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
342
343 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);
344 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
345 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
346 rt2x00_set_field32(®, ARCSR2_LENGTH,
347 GET_DURATION(ACK_SIZE, 10));
348 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
349
350 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);
351 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
352 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
353 rt2x00_set_field32(®, ARCSR2_LENGTH,
354 GET_DURATION(ACK_SIZE, 20));
355 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
356
357 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);
358 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
359 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
360 rt2x00_set_field32(®, ARCSR2_LENGTH,
361 GET_DURATION(ACK_SIZE, 55));
362 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
363
364 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);
365 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
366 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
367 rt2x00_set_field32(®, ARCSR2_LENGTH,
368 GET_DURATION(ACK_SIZE, 110));
369 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
370 }
371
372 if (changed & BSS_CHANGED_BASIC_RATES)
373 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
374
375 if (changed & BSS_CHANGED_ERP_SLOT) {
376 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
377 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
378 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
379
380 reg = rt2x00mmio_register_read(rt2x00dev, CSR18);
381 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
382 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
383 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
384
385 reg = rt2x00mmio_register_read(rt2x00dev, CSR19);
386 rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
387 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
388 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
389 }
390
391 if (changed & BSS_CHANGED_BEACON_INT) {
392 reg = rt2x00mmio_register_read(rt2x00dev, CSR12);
393 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
394 erp->beacon_int * 16);
395 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
396 erp->beacon_int * 16);
397 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
398 }
399}
400
401static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
402 struct antenna_setup *ant)
403{
404 u8 r1;
405 u8 r4;
406
407 /*
408 * We should never come here because rt2x00lib is supposed
409 * to catch this and send us the correct antenna explicitely.
410 */
411 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
412 ant->tx == ANTENNA_SW_DIVERSITY);
413
414 r4 = rt2400pci_bbp_read(rt2x00dev, 4);
415 r1 = rt2400pci_bbp_read(rt2x00dev, 1);
416
417 /*
418 * Configure the TX antenna.
419 */
420 switch (ant->tx) {
421 case ANTENNA_HW_DIVERSITY:
422 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
423 break;
424 case ANTENNA_A:
425 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
426 break;
427 case ANTENNA_B:
428 default:
429 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
430 break;
431 }
432
433 /*
434 * Configure the RX antenna.
435 */
436 switch (ant->rx) {
437 case ANTENNA_HW_DIVERSITY:
438 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
439 break;
440 case ANTENNA_A:
441 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
442 break;
443 case ANTENNA_B:
444 default:
445 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
446 break;
447 }
448
449 rt2400pci_bbp_write(rt2x00dev, 4, r4);
450 rt2400pci_bbp_write(rt2x00dev, 1, r1);
451}
452
453static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
454 struct rf_channel *rf)
455{
456 /*
457 * Switch on tuning bits.
458 */
459 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
460 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
461
462 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
463 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
464 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
465
466 /*
467 * RF2420 chipset don't need any additional actions.
468 */
469 if (rt2x00_rf(rt2x00dev, RF2420))
470 return;
471
472 /*
473 * For the RT2421 chipsets we need to write an invalid
474 * reference clock rate to activate auto_tune.
475 * After that we set the value back to the correct channel.
476 */
477 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
478 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
479 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
480
481 msleep(1);
482
483 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
484 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
485 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
486
487 msleep(1);
488
489 /*
490 * Switch off tuning bits.
491 */
492 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
493 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
494
495 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
496 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
497
498 /*
499 * Clear false CRC during channel switch.
500 */
501 rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);
502}
503
504static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
505{
506 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
507}
508
509static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
510 struct rt2x00lib_conf *libconf)
511{
512 u32 reg;
513
514 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
515 rt2x00_set_field32(®, CSR11_LONG_RETRY,
516 libconf->conf->long_frame_max_tx_count);
517 rt2x00_set_field32(®, CSR11_SHORT_RETRY,
518 libconf->conf->short_frame_max_tx_count);
519 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
520}
521
522static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
523 struct rt2x00lib_conf *libconf)
524{
525 enum dev_state state =
526 (libconf->conf->flags & IEEE80211_CONF_PS) ?
527 STATE_SLEEP : STATE_AWAKE;
528 u32 reg;
529
530 if (state == STATE_SLEEP) {
531 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
532 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN,
533 (rt2x00dev->beacon_int - 20) * 16);
534 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP,
535 libconf->conf->listen_interval - 1);
536
537 /* We must first disable autowake before it can be enabled */
538 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
539 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
540
541 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1);
542 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
543 } else {
544 reg = rt2x00mmio_register_read(rt2x00dev, CSR20);
545 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
546 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
547 }
548
549 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
550}
551
552static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
553 struct rt2x00lib_conf *libconf,
554 const unsigned int flags)
555{
556 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
557 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
558 if (flags & IEEE80211_CONF_CHANGE_POWER)
559 rt2400pci_config_txpower(rt2x00dev,
560 libconf->conf->power_level);
561 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
562 rt2400pci_config_retry_limit(rt2x00dev, libconf);
563 if (flags & IEEE80211_CONF_CHANGE_PS)
564 rt2400pci_config_ps(rt2x00dev, libconf);
565}
566
567static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
568 const int cw_min, const int cw_max)
569{
570 u32 reg;
571
572 reg = rt2x00mmio_register_read(rt2x00dev, CSR11);
573 rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
574 rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
575 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
576}
577
578/*
579 * Link tuning
580 */
581static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
582 struct link_qual *qual)
583{
584 u32 reg;
585 u8 bbp;
586
587 /*
588 * Update FCS error count from register.
589 */
590 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
591 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
592
593 /*
594 * Update False CCA count from register.
595 */
596 bbp = rt2400pci_bbp_read(rt2x00dev, 39);
597 qual->false_cca = bbp;
598}
599
600static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
601 struct link_qual *qual, u8 vgc_level)
602{
603 if (qual->vgc_level_reg != vgc_level) {
604 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
605 qual->vgc_level = vgc_level;
606 qual->vgc_level_reg = vgc_level;
607 }
608}
609
610static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
611 struct link_qual *qual)
612{
613 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
614}
615
616static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
617 struct link_qual *qual, const u32 count)
618{
619 /*
620 * The link tuner should not run longer then 60 seconds,
621 * and should run once every 2 seconds.
622 */
623 if (count > 60 || !(count & 1))
624 return;
625
626 /*
627 * Base r13 link tuning on the false cca count.
628 */
629 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
630 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
631 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
632 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
633}
634
635/*
636 * Queue handlers.
637 */
638static void rt2400pci_start_queue(struct data_queue *queue)
639{
640 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
641 u32 reg;
642
643 switch (queue->qid) {
644 case QID_RX:
645 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
646 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0);
647 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
648 break;
649 case QID_BEACON:
650 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
651 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
652 rt2x00_set_field32(®, CSR14_TBCN, 1);
653 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
654 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
655 break;
656 default:
657 break;
658 }
659}
660
661static void rt2400pci_kick_queue(struct data_queue *queue)
662{
663 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
664 u32 reg;
665
666 switch (queue->qid) {
667 case QID_AC_VO:
668 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
669 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
670 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
671 break;
672 case QID_AC_VI:
673 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
674 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
675 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
676 break;
677 case QID_ATIM:
678 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
679 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
680 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
681 break;
682 default:
683 break;
684 }
685}
686
687static void rt2400pci_stop_queue(struct data_queue *queue)
688{
689 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
690 u32 reg;
691
692 switch (queue->qid) {
693 case QID_AC_VO:
694 case QID_AC_VI:
695 case QID_ATIM:
696 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);
697 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
698 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
699 break;
700 case QID_RX:
701 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);
702 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1);
703 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
704 break;
705 case QID_BEACON:
706 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
707 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
708 rt2x00_set_field32(®, CSR14_TBCN, 0);
709 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
710 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
711
712 /*
713 * Wait for possibly running tbtt tasklets.
714 */
715 tasklet_kill(&rt2x00dev->tbtt_tasklet);
716 break;
717 default:
718 break;
719 }
720}
721
722/*
723 * Initialization functions.
724 */
725static bool rt2400pci_get_entry_state(struct queue_entry *entry)
726{
727 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
728 u32 word;
729
730 if (entry->queue->qid == QID_RX) {
731 word = rt2x00_desc_read(entry_priv->desc, 0);
732
733 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
734 } else {
735 word = rt2x00_desc_read(entry_priv->desc, 0);
736
737 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
738 rt2x00_get_field32(word, TXD_W0_VALID));
739 }
740}
741
742static void rt2400pci_clear_entry(struct queue_entry *entry)
743{
744 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
745 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
746 u32 word;
747
748 if (entry->queue->qid == QID_RX) {
749 word = rt2x00_desc_read(entry_priv->desc, 2);
750 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
751 rt2x00_desc_write(entry_priv->desc, 2, word);
752
753 word = rt2x00_desc_read(entry_priv->desc, 1);
754 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
755 rt2x00_desc_write(entry_priv->desc, 1, word);
756
757 word = rt2x00_desc_read(entry_priv->desc, 0);
758 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
759 rt2x00_desc_write(entry_priv->desc, 0, word);
760 } else {
761 word = rt2x00_desc_read(entry_priv->desc, 0);
762 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
763 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
764 rt2x00_desc_write(entry_priv->desc, 0, word);
765 }
766}
767
768static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
769{
770 struct queue_entry_priv_mmio *entry_priv;
771 u32 reg;
772
773 /*
774 * Initialize registers.
775 */
776 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);
777 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
778 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
779 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
780 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
781 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
782
783 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
784 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);
785 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
786 entry_priv->desc_dma);
787 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
788
789 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
790 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);
791 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
792 entry_priv->desc_dma);
793 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
794
795 entry_priv = rt2x00dev->atim->entries[0].priv_data;
796 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);
797 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
798 entry_priv->desc_dma);
799 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
800
801 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
802 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);
803 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
804 entry_priv->desc_dma);
805 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
806
807 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);
808 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
809 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
810 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
811
812 entry_priv = rt2x00dev->rx->entries[0].priv_data;
813 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);
814 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
815 entry_priv->desc_dma);
816 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
817
818 return 0;
819}
820
821static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
822{
823 u32 reg;
824
825 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
826 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
827 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
828 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
829
830 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);
831 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
832 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
833 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
834 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
835
836 reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
837 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
838 (rt2x00dev->rx->data_size / 128));
839 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
840
841 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
842 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
843 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
844 rt2x00_set_field32(®, CSR14_TBCN, 0);
845 rt2x00_set_field32(®, CSR14_TCFP, 0);
846 rt2x00_set_field32(®, CSR14_TATIMW, 0);
847 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
848 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
849 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
850 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
851
852 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
853
854 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);
855 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
856 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
857 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
858 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
859 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
860
861 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);
862 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
863 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
864 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
865 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
866 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
867 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
868 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
869
870 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
871
872 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
873 return -EBUSY;
874
875 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
876 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
877
878 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);
879 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
880 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
881
882 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);
883 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
884 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
885 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
886 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
887 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
888
889 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
890 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
891 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
892 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
893 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
894
895 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
896 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
897 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
898 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
899
900 /*
901 * We must clear the FCS and FIFO error count.
902 * These registers are cleared on read,
903 * so we may pass a useless variable to store the value.
904 */
905 reg = rt2x00mmio_register_read(rt2x00dev, CNT0);
906 reg = rt2x00mmio_register_read(rt2x00dev, CNT4);
907
908 return 0;
909}
910
911static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
912{
913 unsigned int i;
914 u8 value;
915
916 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
917 value = rt2400pci_bbp_read(rt2x00dev, 0);
918 if ((value != 0xff) && (value != 0x00))
919 return 0;
920 udelay(REGISTER_BUSY_DELAY);
921 }
922
923 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
924 return -EACCES;
925}
926
927static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
928{
929 unsigned int i;
930 u16 eeprom;
931 u8 reg_id;
932 u8 value;
933
934 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
935 return -EACCES;
936
937 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
938 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
939 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
940 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
941 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
942 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
943 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
944 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
945 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
946 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
947 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
948 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
949 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
950 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
951
952 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
953 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
954
955 if (eeprom != 0xffff && eeprom != 0x0000) {
956 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
957 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
958 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
959 }
960 }
961
962 return 0;
963}
964
965/*
966 * Device state switch handlers.
967 */
968static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
969 enum dev_state state)
970{
971 int mask = (state == STATE_RADIO_IRQ_OFF);
972 u32 reg;
973 unsigned long flags;
974
975 /*
976 * When interrupts are being enabled, the interrupt registers
977 * should clear the register to assure a clean state.
978 */
979 if (state == STATE_RADIO_IRQ_ON) {
980 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
981 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
982 }
983
984 /*
985 * Only toggle the interrupts bits we are going to use.
986 * Non-checked interrupt bits are disabled by default.
987 */
988 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
989
990 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
991 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
992 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
993 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
994 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
995 rt2x00_set_field32(®, CSR8_RXDONE, mask);
996 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
997
998 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
999
1000 if (state == STATE_RADIO_IRQ_OFF) {
1001 /*
1002 * Ensure that all tasklets are finished before
1003 * disabling the interrupts.
1004 */
1005 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1006 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1007 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1008 }
1009}
1010
1011static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1012{
1013 /*
1014 * Initialize all registers.
1015 */
1016 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1017 rt2400pci_init_registers(rt2x00dev) ||
1018 rt2400pci_init_bbp(rt2x00dev)))
1019 return -EIO;
1020
1021 return 0;
1022}
1023
1024static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1025{
1026 /*
1027 * Disable power
1028 */
1029 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1030}
1031
1032static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1033 enum dev_state state)
1034{
1035 u32 reg, reg2;
1036 unsigned int i;
1037 char put_to_sleep;
1038 char bbp_state;
1039 char rf_state;
1040
1041 put_to_sleep = (state != STATE_AWAKE);
1042
1043 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1044 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
1045 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
1046 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
1047 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1048 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1049
1050 /*
1051 * Device is not guaranteed to be in the requested state yet.
1052 * We must wait until the register indicates that the
1053 * device has entered the correct state.
1054 */
1055 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1056 reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);
1057 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1058 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1059 if (bbp_state == state && rf_state == state)
1060 return 0;
1061 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1062 msleep(10);
1063 }
1064
1065 return -EBUSY;
1066}
1067
1068static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1069 enum dev_state state)
1070{
1071 int retval = 0;
1072
1073 switch (state) {
1074 case STATE_RADIO_ON:
1075 retval = rt2400pci_enable_radio(rt2x00dev);
1076 break;
1077 case STATE_RADIO_OFF:
1078 rt2400pci_disable_radio(rt2x00dev);
1079 break;
1080 case STATE_RADIO_IRQ_ON:
1081 case STATE_RADIO_IRQ_OFF:
1082 rt2400pci_toggle_irq(rt2x00dev, state);
1083 break;
1084 case STATE_DEEP_SLEEP:
1085 case STATE_SLEEP:
1086 case STATE_STANDBY:
1087 case STATE_AWAKE:
1088 retval = rt2400pci_set_state(rt2x00dev, state);
1089 break;
1090 default:
1091 retval = -ENOTSUPP;
1092 break;
1093 }
1094
1095 if (unlikely(retval))
1096 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1097 state, retval);
1098
1099 return retval;
1100}
1101
1102/*
1103 * TX descriptor initialization
1104 */
1105static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1106 struct txentry_desc *txdesc)
1107{
1108 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1109 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1110 __le32 *txd = entry_priv->desc;
1111 u32 word;
1112
1113 /*
1114 * Start writing the descriptor words.
1115 */
1116 word = rt2x00_desc_read(txd, 1);
1117 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1118 rt2x00_desc_write(txd, 1, word);
1119
1120 word = rt2x00_desc_read(txd, 2);
1121 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1122 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1123 rt2x00_desc_write(txd, 2, word);
1124
1125 word = rt2x00_desc_read(txd, 3);
1126 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1127 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1128 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1129 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1130 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1131 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1132 rt2x00_desc_write(txd, 3, word);
1133
1134 word = rt2x00_desc_read(txd, 4);
1135 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1136 txdesc->u.plcp.length_low);
1137 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1138 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1139 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1140 txdesc->u.plcp.length_high);
1141 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1142 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1143 rt2x00_desc_write(txd, 4, word);
1144
1145 /*
1146 * Writing TXD word 0 must the last to prevent a race condition with
1147 * the device, whereby the device may take hold of the TXD before we
1148 * finished updating it.
1149 */
1150 word = rt2x00_desc_read(txd, 0);
1151 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1152 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1153 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1154 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1155 rt2x00_set_field32(&word, TXD_W0_ACK,
1156 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1157 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1158 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1159 rt2x00_set_field32(&word, TXD_W0_RTS,
1160 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1161 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1162 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1163 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1164 rt2x00_desc_write(txd, 0, word);
1165
1166 /*
1167 * Register descriptor details in skb frame descriptor.
1168 */
1169 skbdesc->desc = txd;
1170 skbdesc->desc_len = TXD_DESC_SIZE;
1171}
1172
1173/*
1174 * TX data initialization
1175 */
1176static void rt2400pci_write_beacon(struct queue_entry *entry,
1177 struct txentry_desc *txdesc)
1178{
1179 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1180 u32 reg;
1181
1182 /*
1183 * Disable beaconing while we are reloading the beacon data,
1184 * otherwise we might be sending out invalid data.
1185 */
1186 reg = rt2x00mmio_register_read(rt2x00dev, CSR14);
1187 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1188 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1189
1190 if (rt2x00queue_map_txskb(entry)) {
1191 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1192 goto out;
1193 }
1194 /*
1195 * Enable beaconing again.
1196 */
1197 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1198 /*
1199 * Write the TX descriptor for the beacon.
1200 */
1201 rt2400pci_write_tx_desc(entry, txdesc);
1202
1203 /*
1204 * Dump beacon to userspace through debugfs.
1205 */
1206 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1207out:
1208 /*
1209 * Enable beaconing again.
1210 */
1211 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1212 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1213}
1214
1215/*
1216 * RX control handlers
1217 */
1218static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1219 struct rxdone_entry_desc *rxdesc)
1220{
1221 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1222 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1223 u32 word0;
1224 u32 word2;
1225 u32 word3;
1226 u32 word4;
1227 u64 tsf;
1228 u32 rx_low;
1229 u32 rx_high;
1230
1231 word0 = rt2x00_desc_read(entry_priv->desc, 0);
1232 word2 = rt2x00_desc_read(entry_priv->desc, 2);
1233 word3 = rt2x00_desc_read(entry_priv->desc, 3);
1234 word4 = rt2x00_desc_read(entry_priv->desc, 4);
1235
1236 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1237 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1238 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1239 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1240
1241 /*
1242 * We only get the lower 32bits from the timestamp,
1243 * to get the full 64bits we must complement it with
1244 * the timestamp from get_tsf().
1245 * Note that when a wraparound of the lower 32bits
1246 * has occurred between the frame arrival and the get_tsf()
1247 * call, we must decrease the higher 32bits with 1 to get
1248 * to correct value.
1249 */
1250 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
1251 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1252 rx_high = upper_32_bits(tsf);
1253
1254 if ((u32)tsf <= rx_low)
1255 rx_high--;
1256
1257 /*
1258 * Obtain the status about this packet.
1259 * The signal is the PLCP value, and needs to be stripped
1260 * of the preamble bit (0x08).
1261 */
1262 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1263 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1264 rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) -
1265 entry->queue->rt2x00dev->rssi_offset;
1266 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1267
1268 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1269 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1270 rxdesc->dev_flags |= RXDONE_MY_BSS;
1271}
1272
1273/*
1274 * Interrupt functions.
1275 */
1276static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1277 const enum data_queue_qid queue_idx)
1278{
1279 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1280 struct queue_entry_priv_mmio *entry_priv;
1281 struct queue_entry *entry;
1282 struct txdone_entry_desc txdesc;
1283 u32 word;
1284
1285 while (!rt2x00queue_empty(queue)) {
1286 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1287 entry_priv = entry->priv_data;
1288 word = rt2x00_desc_read(entry_priv->desc, 0);
1289
1290 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1291 !rt2x00_get_field32(word, TXD_W0_VALID))
1292 break;
1293
1294 /*
1295 * Obtain the status about this packet.
1296 */
1297 txdesc.flags = 0;
1298 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1299 case 0: /* Success */
1300 case 1: /* Success with retry */
1301 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1302 break;
1303 case 2: /* Failure, excessive retries */
1304 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1305 /* Don't break, this is a failed frame! */
1306 default: /* Failure */
1307 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1308 }
1309 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1310
1311 rt2x00lib_txdone(entry, &txdesc);
1312 }
1313}
1314
1315static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1316 struct rt2x00_field32 irq_field)
1317{
1318 u32 reg;
1319
1320 /*
1321 * Enable a single interrupt. The interrupt mask register
1322 * access needs locking.
1323 */
1324 spin_lock_irq(&rt2x00dev->irqmask_lock);
1325
1326 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1327 rt2x00_set_field32(®, irq_field, 0);
1328 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1329
1330 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1331}
1332
1333static void rt2400pci_txstatus_tasklet(unsigned long data)
1334{
1335 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1336 u32 reg;
1337
1338 /*
1339 * Handle all tx queues.
1340 */
1341 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1342 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1343 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1344
1345 /*
1346 * Enable all TXDONE interrupts again.
1347 */
1348 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1349 spin_lock_irq(&rt2x00dev->irqmask_lock);
1350
1351 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1352 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
1353 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
1354 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
1355 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1356
1357 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1358 }
1359}
1360
1361static void rt2400pci_tbtt_tasklet(unsigned long data)
1362{
1363 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1364 rt2x00lib_beacondone(rt2x00dev);
1365 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1366 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1367}
1368
1369static void rt2400pci_rxdone_tasklet(unsigned long data)
1370{
1371 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1372 if (rt2x00mmio_rxdone(rt2x00dev))
1373 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1374 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1375 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1376}
1377
1378static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1379{
1380 struct rt2x00_dev *rt2x00dev = dev_instance;
1381 u32 reg, mask;
1382
1383 /*
1384 * Get the interrupt sources & saved to local variable.
1385 * Write register value back to clear pending interrupts.
1386 */
1387 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1388 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1389
1390 if (!reg)
1391 return IRQ_NONE;
1392
1393 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1394 return IRQ_HANDLED;
1395
1396 mask = reg;
1397
1398 /*
1399 * Schedule tasklets for interrupt handling.
1400 */
1401 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1402 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1403
1404 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1405 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1406
1407 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1408 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1409 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1410 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1411 /*
1412 * Mask out all txdone interrupts.
1413 */
1414 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1415 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1416 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1417 }
1418
1419 /*
1420 * Disable all interrupts for which a tasklet was scheduled right now,
1421 * the tasklet will reenable the appropriate interrupts.
1422 */
1423 spin_lock(&rt2x00dev->irqmask_lock);
1424
1425 reg = rt2x00mmio_register_read(rt2x00dev, CSR8);
1426 reg |= mask;
1427 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1428
1429 spin_unlock(&rt2x00dev->irqmask_lock);
1430
1431
1432
1433 return IRQ_HANDLED;
1434}
1435
1436/*
1437 * Device probe functions.
1438 */
1439static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1440{
1441 struct eeprom_93cx6 eeprom;
1442 u32 reg;
1443 u16 word;
1444 u8 *mac;
1445
1446 reg = rt2x00mmio_register_read(rt2x00dev, CSR21);
1447
1448 eeprom.data = rt2x00dev;
1449 eeprom.register_read = rt2400pci_eepromregister_read;
1450 eeprom.register_write = rt2400pci_eepromregister_write;
1451 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1452 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1453 eeprom.reg_data_in = 0;
1454 eeprom.reg_data_out = 0;
1455 eeprom.reg_data_clock = 0;
1456 eeprom.reg_chip_select = 0;
1457
1458 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1459 EEPROM_SIZE / sizeof(u16));
1460
1461 /*
1462 * Start validation of the data that has been read.
1463 */
1464 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1465 rt2x00lib_set_mac_address(rt2x00dev, mac);
1466
1467 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1468 if (word == 0xffff) {
1469 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
1470 return -EINVAL;
1471 }
1472
1473 return 0;
1474}
1475
1476static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1477{
1478 u32 reg;
1479 u16 value;
1480 u16 eeprom;
1481
1482 /*
1483 * Read EEPROM word for configuration.
1484 */
1485 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1486
1487 /*
1488 * Identify RF chipset.
1489 */
1490 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1491 reg = rt2x00mmio_register_read(rt2x00dev, CSR0);
1492 rt2x00_set_chip(rt2x00dev, RT2460, value,
1493 rt2x00_get_field32(reg, CSR0_REVISION));
1494
1495 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1496 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1497 return -ENODEV;
1498 }
1499
1500 /*
1501 * Identify default antenna configuration.
1502 */
1503 rt2x00dev->default_ant.tx =
1504 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1505 rt2x00dev->default_ant.rx =
1506 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1507
1508 /*
1509 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1510 * I am not 100% sure about this, but the legacy drivers do not
1511 * indicate antenna swapping in software is required when
1512 * diversity is enabled.
1513 */
1514 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1515 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1516 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1517 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1518
1519 /*
1520 * Store led mode, for correct led behaviour.
1521 */
1522#ifdef CONFIG_RT2X00_LIB_LEDS
1523 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1524
1525 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1526 if (value == LED_MODE_TXRX_ACTIVITY ||
1527 value == LED_MODE_DEFAULT ||
1528 value == LED_MODE_ASUS)
1529 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1530 LED_TYPE_ACTIVITY);
1531#endif /* CONFIG_RT2X00_LIB_LEDS */
1532
1533 /*
1534 * Detect if this device has an hardware controlled radio.
1535 */
1536 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1537 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1538
1539 /*
1540 * Check if the BBP tuning should be enabled.
1541 */
1542 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1543 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1544
1545 return 0;
1546}
1547
1548/*
1549 * RF value list for RF2420 & RF2421
1550 * Supports: 2.4 GHz
1551 */
1552static const struct rf_channel rf_vals_b[] = {
1553 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1554 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1555 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1556 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1557 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1558 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1559 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1560 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1561 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1562 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1563 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1564 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1565 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1566 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1567};
1568
1569static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1570{
1571 struct hw_mode_spec *spec = &rt2x00dev->spec;
1572 struct channel_info *info;
1573 char *tx_power;
1574 unsigned int i;
1575
1576 /*
1577 * Initialize all hw fields.
1578 */
1579 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1580 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1581 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1582 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
1583
1584 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1585 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1586 rt2x00_eeprom_addr(rt2x00dev,
1587 EEPROM_MAC_ADDR_0));
1588
1589 /*
1590 * Initialize hw_mode information.
1591 */
1592 spec->supported_bands = SUPPORT_BAND_2GHZ;
1593 spec->supported_rates = SUPPORT_RATE_CCK;
1594
1595 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1596 spec->channels = rf_vals_b;
1597
1598 /*
1599 * Create channel information array
1600 */
1601 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1602 if (!info)
1603 return -ENOMEM;
1604
1605 spec->channels_info = info;
1606
1607 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1608 for (i = 0; i < 14; i++) {
1609 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1610 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1611 }
1612
1613 return 0;
1614}
1615
1616static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1617{
1618 int retval;
1619 u32 reg;
1620
1621 /*
1622 * Allocate eeprom data.
1623 */
1624 retval = rt2400pci_validate_eeprom(rt2x00dev);
1625 if (retval)
1626 return retval;
1627
1628 retval = rt2400pci_init_eeprom(rt2x00dev);
1629 if (retval)
1630 return retval;
1631
1632 /*
1633 * Enable rfkill polling by setting GPIO direction of the
1634 * rfkill switch GPIO pin correctly.
1635 */
1636 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);
1637 rt2x00_set_field32(®, GPIOCSR_DIR0, 1);
1638 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1639
1640 /*
1641 * Initialize hw specifications.
1642 */
1643 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1644 if (retval)
1645 return retval;
1646
1647 /*
1648 * This device requires the atim queue and DMA-mapped skbs.
1649 */
1650 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1651 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1652 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1653
1654 /*
1655 * Set the rssi offset.
1656 */
1657 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1658
1659 return 0;
1660}
1661
1662/*
1663 * IEEE80211 stack callback functions.
1664 */
1665static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1666 struct ieee80211_vif *vif, u16 queue,
1667 const struct ieee80211_tx_queue_params *params)
1668{
1669 struct rt2x00_dev *rt2x00dev = hw->priv;
1670
1671 /*
1672 * We don't support variating cw_min and cw_max variables
1673 * per queue. So by default we only configure the TX queue,
1674 * and ignore all other configurations.
1675 */
1676 if (queue != 0)
1677 return -EINVAL;
1678
1679 if (rt2x00mac_conf_tx(hw, vif, queue, params))
1680 return -EINVAL;
1681
1682 /*
1683 * Write configuration to register.
1684 */
1685 rt2400pci_config_cw(rt2x00dev,
1686 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1687
1688 return 0;
1689}
1690
1691static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1692 struct ieee80211_vif *vif)
1693{
1694 struct rt2x00_dev *rt2x00dev = hw->priv;
1695 u64 tsf;
1696 u32 reg;
1697
1698 reg = rt2x00mmio_register_read(rt2x00dev, CSR17);
1699 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1700 reg = rt2x00mmio_register_read(rt2x00dev, CSR16);
1701 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1702
1703 return tsf;
1704}
1705
1706static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1707{
1708 struct rt2x00_dev *rt2x00dev = hw->priv;
1709 u32 reg;
1710
1711 reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
1712 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1713}
1714
1715static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1716 .tx = rt2x00mac_tx,
1717 .start = rt2x00mac_start,
1718 .stop = rt2x00mac_stop,
1719 .add_interface = rt2x00mac_add_interface,
1720 .remove_interface = rt2x00mac_remove_interface,
1721 .config = rt2x00mac_config,
1722 .configure_filter = rt2x00mac_configure_filter,
1723 .sw_scan_start = rt2x00mac_sw_scan_start,
1724 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1725 .get_stats = rt2x00mac_get_stats,
1726 .bss_info_changed = rt2x00mac_bss_info_changed,
1727 .conf_tx = rt2400pci_conf_tx,
1728 .get_tsf = rt2400pci_get_tsf,
1729 .tx_last_beacon = rt2400pci_tx_last_beacon,
1730 .rfkill_poll = rt2x00mac_rfkill_poll,
1731 .flush = rt2x00mac_flush,
1732 .set_antenna = rt2x00mac_set_antenna,
1733 .get_antenna = rt2x00mac_get_antenna,
1734 .get_ringparam = rt2x00mac_get_ringparam,
1735 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1736};
1737
1738static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1739 .irq_handler = rt2400pci_interrupt,
1740 .txstatus_tasklet = rt2400pci_txstatus_tasklet,
1741 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1742 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
1743 .probe_hw = rt2400pci_probe_hw,
1744 .initialize = rt2x00mmio_initialize,
1745 .uninitialize = rt2x00mmio_uninitialize,
1746 .get_entry_state = rt2400pci_get_entry_state,
1747 .clear_entry = rt2400pci_clear_entry,
1748 .set_device_state = rt2400pci_set_device_state,
1749 .rfkill_poll = rt2400pci_rfkill_poll,
1750 .link_stats = rt2400pci_link_stats,
1751 .reset_tuner = rt2400pci_reset_tuner,
1752 .link_tuner = rt2400pci_link_tuner,
1753 .start_queue = rt2400pci_start_queue,
1754 .kick_queue = rt2400pci_kick_queue,
1755 .stop_queue = rt2400pci_stop_queue,
1756 .flush_queue = rt2x00mmio_flush_queue,
1757 .write_tx_desc = rt2400pci_write_tx_desc,
1758 .write_beacon = rt2400pci_write_beacon,
1759 .fill_rxdone = rt2400pci_fill_rxdone,
1760 .config_filter = rt2400pci_config_filter,
1761 .config_intf = rt2400pci_config_intf,
1762 .config_erp = rt2400pci_config_erp,
1763 .config_ant = rt2400pci_config_ant,
1764 .config = rt2400pci_config,
1765};
1766
1767static void rt2400pci_queue_init(struct data_queue *queue)
1768{
1769 switch (queue->qid) {
1770 case QID_RX:
1771 queue->limit = 24;
1772 queue->data_size = DATA_FRAME_SIZE;
1773 queue->desc_size = RXD_DESC_SIZE;
1774 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1775 break;
1776
1777 case QID_AC_VO:
1778 case QID_AC_VI:
1779 case QID_AC_BE:
1780 case QID_AC_BK:
1781 queue->limit = 24;
1782 queue->data_size = DATA_FRAME_SIZE;
1783 queue->desc_size = TXD_DESC_SIZE;
1784 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1785 break;
1786
1787 case QID_BEACON:
1788 queue->limit = 1;
1789 queue->data_size = MGMT_FRAME_SIZE;
1790 queue->desc_size = TXD_DESC_SIZE;
1791 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1792 break;
1793
1794 case QID_ATIM:
1795 queue->limit = 8;
1796 queue->data_size = DATA_FRAME_SIZE;
1797 queue->desc_size = TXD_DESC_SIZE;
1798 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1799 break;
1800
1801 default:
1802 BUG();
1803 break;
1804 }
1805}
1806
1807static const struct rt2x00_ops rt2400pci_ops = {
1808 .name = KBUILD_MODNAME,
1809 .max_ap_intf = 1,
1810 .eeprom_size = EEPROM_SIZE,
1811 .rf_size = RF_SIZE,
1812 .tx_queues = NUM_TX_QUEUES,
1813 .queue_init = rt2400pci_queue_init,
1814 .lib = &rt2400pci_rt2x00_ops,
1815 .hw = &rt2400pci_mac80211_ops,
1816#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1817 .debugfs = &rt2400pci_rt2x00debug,
1818#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1819};
1820
1821/*
1822 * RT2400pci module information.
1823 */
1824static const struct pci_device_id rt2400pci_device_table[] = {
1825 { PCI_DEVICE(0x1814, 0x0101) },
1826 { 0, }
1827};
1828
1829
1830MODULE_AUTHOR(DRV_PROJECT);
1831MODULE_VERSION(DRV_VERSION);
1832MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1833MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1834MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1835MODULE_LICENSE("GPL");
1836
1837static int rt2400pci_probe(struct pci_dev *pci_dev,
1838 const struct pci_device_id *id)
1839{
1840 return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1841}
1842
1843static struct pci_driver rt2400pci_driver = {
1844 .name = KBUILD_MODNAME,
1845 .id_table = rt2400pci_device_table,
1846 .probe = rt2400pci_probe,
1847 .remove = rt2x00pci_remove,
1848 .suspend = rt2x00pci_suspend,
1849 .resume = rt2x00pci_resume,
1850};
1851
1852module_pci_driver(rt2400pci_driver);