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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2020, 2022 Intel Corporation
5 */
6#ifndef __iwl_context_info_file_h__
7#define __iwl_context_info_file_h__
8
9/* maximmum number of DRAM map entries supported by FW */
10#define IWL_MAX_DRAM_ENTRY 64
11#define CSR_CTXT_INFO_BA 0x40
12
13/**
14 * enum iwl_context_info_flags - Context information control flags
15 * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
16 * the init done for driver command that configures several system modes
17 * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
18 * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
19 * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size
20 * exponent, the actual size is 2**value, valid sizes are 8-2048.
21 * The value is four bits long. Maximum valid exponent is 12
22 * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
23 * default is short format - not supported by the driver)
24 * @IWL_CTXT_INFO_RB_SIZE: RB size mask
25 * (values are IWL_CTXT_INFO_RB_SIZE_*K)
26 * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
27 * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
28 * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
29 * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
30 * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
31 * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
32 * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
33 * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
34 * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
35 * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
36 */
37enum iwl_context_info_flags {
38 IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001,
39 IWL_CTXT_INFO_EARLY_DEBUG = 0x0002,
40 IWL_CTXT_INFO_ENABLE_CDMP = 0x0004,
41 IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0,
42 IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100,
43 IWL_CTXT_INFO_RB_SIZE = 0x1e00,
44 IWL_CTXT_INFO_RB_SIZE_1K = 0x1,
45 IWL_CTXT_INFO_RB_SIZE_2K = 0x2,
46 IWL_CTXT_INFO_RB_SIZE_4K = 0x4,
47 IWL_CTXT_INFO_RB_SIZE_8K = 0x8,
48 IWL_CTXT_INFO_RB_SIZE_12K = 0x9,
49 IWL_CTXT_INFO_RB_SIZE_16K = 0xa,
50 IWL_CTXT_INFO_RB_SIZE_20K = 0xb,
51 IWL_CTXT_INFO_RB_SIZE_24K = 0xc,
52 IWL_CTXT_INFO_RB_SIZE_28K = 0xd,
53 IWL_CTXT_INFO_RB_SIZE_32K = 0xe,
54};
55
56/*
57 * struct iwl_context_info_version - version structure
58 * @mac_id: SKU and revision id
59 * @version: context information version id
60 * @size: the size of the context information in DWs
61 */
62struct iwl_context_info_version {
63 __le16 mac_id;
64 __le16 version;
65 __le16 size;
66 __le16 reserved;
67} __packed;
68
69/*
70 * struct iwl_context_info_control - version structure
71 * @control_flags: context information flags see &enum iwl_context_info_flags
72 */
73struct iwl_context_info_control {
74 __le32 control_flags;
75 __le32 reserved;
76} __packed;
77
78/*
79 * struct iwl_context_info_dram - images DRAM map
80 * each entry in the map represents a DRAM chunk of up to 32 KB
81 * @umac_img: UMAC image DRAM map
82 * @lmac_img: LMAC image DRAM map
83 * @virtual_img: paged image DRAM map
84 */
85struct iwl_context_info_dram {
86 __le64 umac_img[IWL_MAX_DRAM_ENTRY];
87 __le64 lmac_img[IWL_MAX_DRAM_ENTRY];
88 __le64 virtual_img[IWL_MAX_DRAM_ENTRY];
89} __packed;
90
91/*
92 * struct iwl_context_info_rbd_cfg - RBDs configuration
93 * @free_rbd_addr: default queue free RB CB base address
94 * @used_rbd_addr: default queue used RB CB base address
95 * @status_wr_ptr: default queue used RB status write pointer
96 */
97struct iwl_context_info_rbd_cfg {
98 __le64 free_rbd_addr;
99 __le64 used_rbd_addr;
100 __le64 status_wr_ptr;
101} __packed;
102
103/*
104 * struct iwl_context_info_hcmd_cfg - command queue configuration
105 * @cmd_queue_addr: address of command queue
106 * @cmd_queue_size: number of entries
107 */
108struct iwl_context_info_hcmd_cfg {
109 __le64 cmd_queue_addr;
110 u8 cmd_queue_size;
111 u8 reserved[7];
112} __packed;
113
114/*
115 * struct iwl_context_info_dump_cfg - Core Dump configuration
116 * @core_dump_addr: core dump (debug DRAM address) start address
117 * @core_dump_size: size, in DWs
118 */
119struct iwl_context_info_dump_cfg {
120 __le64 core_dump_addr;
121 __le32 core_dump_size;
122 __le32 reserved;
123} __packed;
124
125/*
126 * struct iwl_context_info_pnvm_cfg - platform NVM data configuration
127 * @platform_nvm_addr: Platform NVM data start address
128 * @platform_nvm_size: size in DWs
129 */
130struct iwl_context_info_pnvm_cfg {
131 __le64 platform_nvm_addr;
132 __le32 platform_nvm_size;
133 __le32 reserved;
134} __packed;
135
136/*
137 * struct iwl_context_info_early_dbg_cfg - early debug configuration for
138 * dumping DRAM addresses
139 * @early_debug_addr: early debug start address
140 * @early_debug_size: size in DWs
141 */
142struct iwl_context_info_early_dbg_cfg {
143 __le64 early_debug_addr;
144 __le32 early_debug_size;
145 __le32 reserved;
146} __packed;
147
148/*
149 * struct iwl_context_info - device INIT configuration
150 * @version: version information of context info and HW
151 * @control: control flags of FH configurations
152 * @rbd_cfg: default RX queue configuration
153 * @hcmd_cfg: command queue configuration
154 * @dump_cfg: core dump data
155 * @edbg_cfg: early debug configuration
156 * @pnvm_cfg: platform nvm configuration
157 * @dram: firmware image addresses in DRAM
158 */
159struct iwl_context_info {
160 struct iwl_context_info_version version;
161 struct iwl_context_info_control control;
162 __le64 reserved0;
163 struct iwl_context_info_rbd_cfg rbd_cfg;
164 struct iwl_context_info_hcmd_cfg hcmd_cfg;
165 __le32 reserved1[4];
166 struct iwl_context_info_dump_cfg dump_cfg;
167 struct iwl_context_info_early_dbg_cfg edbg_cfg;
168 struct iwl_context_info_pnvm_cfg pnvm_cfg;
169 __le32 reserved2[16];
170 struct iwl_context_info_dram dram;
171 __le32 reserved3[16];
172} __packed;
173
174int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw);
175void iwl_pcie_ctxt_info_free(struct iwl_trans *trans);
176void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
177int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
178 const struct fw_img *fw,
179 struct iwl_context_info_dram *ctxt_dram);
180void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
181 size_t size,
182 dma_addr_t *phys);
183int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
184 const void *data, u32 len,
185 struct iwl_dram_data *dram);
186
187#endif /* __iwl_context_info_file_h__ */
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2017 Intel Deutschland GmbH
22 * All rights reserved.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 * * Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * * Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
33 * distribution.
34 * * Neither the name Intel Corporation nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 *****************************************************************************/
51
52#ifndef __iwl_context_info_file_h__
53#define __iwl_context_info_file_h__
54
55/* maximmum number of DRAM map entries supported by FW */
56#define IWL_MAX_DRAM_ENTRY 64
57#define CSR_CTXT_INFO_BA 0x40
58
59/**
60 * enum iwl_context_info_flags - Context information control flags
61 * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
62 * the init done for driver command that configures several system modes
63 * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
64 * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
65 * @IWL_CTXT_INFO_RB_SIZE_4K: Use 4K RB size (the default is 2K)
66 * @IWL_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size
67 * exponent, the actual size is 2**value, valid sizes are 8-2048.
68 * The value is four bits long. Maximum valid exponent is 12
69 * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
70 * default is short format - not supported by the driver)
71 */
72enum iwl_context_info_flags {
73 IWL_CTXT_INFO_AUTO_FUNC_INIT = BIT(0),
74 IWL_CTXT_INFO_EARLY_DEBUG = BIT(1),
75 IWL_CTXT_INFO_ENABLE_CDMP = BIT(2),
76 IWL_CTXT_INFO_RB_SIZE_4K = BIT(3),
77 IWL_CTXT_INFO_RB_CB_SIZE_POS = 4,
78 IWL_CTXT_INFO_TFD_FORMAT_LONG = BIT(8),
79};
80
81/*
82 * struct iwl_context_info_version - version structure
83 * @mac_id: SKU and revision id
84 * @version: context information version id
85 * @size: the size of the context information in DWs
86 */
87struct iwl_context_info_version {
88 __le16 mac_id;
89 __le16 version;
90 __le16 size;
91 __le16 reserved;
92} __packed;
93
94/*
95 * struct iwl_context_info_control - version structure
96 * @control_flags: context information flags see &enum iwl_context_info_flags
97 */
98struct iwl_context_info_control {
99 __le32 control_flags;
100 __le32 reserved;
101} __packed;
102
103/*
104 * struct iwl_context_info_dram - images DRAM map
105 * each entry in the map represents a DRAM chunk of up to 32 KB
106 * @umac_img: UMAC image DRAM map
107 * @lmac_img: LMAC image DRAM map
108 * @virtual_img: paged image DRAM map
109 */
110struct iwl_context_info_dram {
111 __le64 umac_img[IWL_MAX_DRAM_ENTRY];
112 __le64 lmac_img[IWL_MAX_DRAM_ENTRY];
113 __le64 virtual_img[IWL_MAX_DRAM_ENTRY];
114} __packed;
115
116/*
117 * struct iwl_context_info_rbd_cfg - RBDs configuration
118 * @free_rbd_addr: default queue free RB CB base address
119 * @used_rbd_addr: default queue used RB CB base address
120 * @status_wr_ptr: default queue used RB status write pointer
121 */
122struct iwl_context_info_rbd_cfg {
123 __le64 free_rbd_addr;
124 __le64 used_rbd_addr;
125 __le64 status_wr_ptr;
126} __packed;
127
128/*
129 * struct iwl_context_info_hcmd_cfg - command queue configuration
130 * @cmd_queue_addr: address of command queue
131 * @cmd_queue_size: number of entries
132 */
133struct iwl_context_info_hcmd_cfg {
134 __le64 cmd_queue_addr;
135 u8 cmd_queue_size;
136 u8 reserved[7];
137} __packed;
138
139/*
140 * struct iwl_context_info_dump_cfg - Core Dump configuration
141 * @core_dump_addr: core dump (debug DRAM address) start address
142 * @core_dump_size: size, in DWs
143 */
144struct iwl_context_info_dump_cfg {
145 __le64 core_dump_addr;
146 __le32 core_dump_size;
147 __le32 reserved;
148} __packed;
149
150/*
151 * struct iwl_context_info_pnvm_cfg - platform NVM data configuration
152 * @platform_nvm_addr: Platform NVM data start address
153 * @platform_nvm_size: size in DWs
154 */
155struct iwl_context_info_pnvm_cfg {
156 __le64 platform_nvm_addr;
157 __le32 platform_nvm_size;
158 __le32 reserved;
159} __packed;
160
161/*
162 * struct iwl_context_info_early_dbg_cfg - early debug configuration for
163 * dumping DRAM addresses
164 * @early_debug_addr: early debug start address
165 * @early_debug_size: size in DWs
166 */
167struct iwl_context_info_early_dbg_cfg {
168 __le64 early_debug_addr;
169 __le32 early_debug_size;
170 __le32 reserved;
171} __packed;
172
173/*
174 * struct iwl_context_info - device INIT configuration
175 * @version: version information of context info and HW
176 * @control: control flags of FH configurations
177 * @rbd_cfg: default RX queue configuration
178 * @hcmd_cfg: command queue configuration
179 * @dump_cfg: core dump data
180 * @edbg_cfg: early debug configuration
181 * @pnvm_cfg: platform nvm configuration
182 * @dram: firmware image addresses in DRAM
183 */
184struct iwl_context_info {
185 struct iwl_context_info_version version;
186 struct iwl_context_info_control control;
187 __le64 reserved0;
188 struct iwl_context_info_rbd_cfg rbd_cfg;
189 struct iwl_context_info_hcmd_cfg hcmd_cfg;
190 __le32 reserved1[4];
191 struct iwl_context_info_dump_cfg dump_cfg;
192 struct iwl_context_info_early_dbg_cfg edbg_cfg;
193 struct iwl_context_info_pnvm_cfg pnvm_cfg;
194 __le32 reserved2[16];
195 struct iwl_context_info_dram dram;
196 __le32 reserved3[16];
197} __packed;
198
199int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw);
200void iwl_pcie_ctxt_info_free(struct iwl_trans *trans);
201void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
202
203#endif /* __iwl_context_info_file_h__ */