1/*
   2 * Copyright (c) 2010-2011 Atheros Communications Inc.
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#include <asm/unaligned.h>
  18#include <linux/kernel.h>
  19#include "hw.h"
  20#include "ar9003_phy.h"
  21#include "ar9003_eeprom.h"
  22#include "ar9003_mci.h"
  23
  24#define COMP_HDR_LEN 4
  25#define COMP_CKSUM_LEN 2
  26
  27#define LE16(x) cpu_to_le16(x)
  28#define LE32(x) cpu_to_le32(x)
  29
  30/* Local defines to distinguish between extension and control CTL's */
  31#define EXT_ADDITIVE (0x8000)
  32#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  33#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  34#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  35
  36#define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  37#define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  38
  39#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  40
  41#define EEPROM_DATA_LEN_9485	1088
  42
  43static int ar9003_hw_power_interpolate(int32_t x,
  44				       int32_t *px, int32_t *py, u_int16_t np);
  45
  46static const struct ar9300_eeprom ar9300_default = {
  47	.eepromVersion = 2,
  48	.templateVersion = 2,
  49	.macAddr = {0, 2, 3, 4, 5, 6},
  50	.custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  51		     0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  52	.baseEepHeader = {
  53		.regDmn = { LE16(0), LE16(0x1f) },
  54		.txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  55		.opCapFlags = {
  56			.opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
  57			.eepMisc = AR9300_EEPMISC_LITTLE_ENDIAN,
  58		},
  59		.rfSilent = 0,
  60		.blueToothOptions = 0,
  61		.deviceCap = 0,
  62		.deviceType = 5, /* takes lower byte in eeprom location */
  63		.pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  64		.params_for_tuning_caps = {0, 0},
  65		.featureEnable = 0x0c,
  66		 /*
  67		  * bit0 - enable tx temp comp - disabled
  68		  * bit1 - enable tx volt comp - disabled
  69		  * bit2 - enable fastClock - enabled
  70		  * bit3 - enable doubling - enabled
  71		  * bit4 - enable internal regulator - disabled
  72		  * bit5 - enable pa predistortion - disabled
  73		  */
  74		.miscConfiguration = 0, /* bit0 - turn down drivestrength */
  75		.eepromWriteEnableGpio = 3,
  76		.wlanDisableGpio = 0,
  77		.wlanLedGpio = 8,
  78		.rxBandSelectGpio = 0xff,
  79		.txrxgain = 0,
  80		.swreg = 0,
  81	 },
  82	.modalHeader2G = {
  83	/* ar9300_modal_eep_header  2g */
  84		/* 4 idle,t1,t2,b(4 bits per setting) */
  85		.antCtrlCommon = LE32(0x110),
  86		/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  87		.antCtrlCommon2 = LE32(0x22222),
  88
  89		/*
  90		 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  91		 * rx1, rx12, b (2 bits each)
  92		 */
  93		.antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
  94
  95		/*
  96		 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
  97		 * for ar9280 (0xa20c/b20c 5:0)
  98		 */
  99		.xatten1DB = {0, 0, 0},
 100
 101		/*
 102		 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 103		 * for ar9280 (0xa20c/b20c 16:12
 104		 */
 105		.xatten1Margin = {0, 0, 0},
 106		.tempSlope = 36,
 107		.voltSlope = 0,
 108
 109		/*
 110		 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 111		 * channels in usual fbin coding format
 112		 */
 113		.spurChans = {0, 0, 0, 0, 0},
 114
 115		/*
 116		 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 117		 * if the register is per chain
 118		 */
 119		.noiseFloorThreshCh = {-1, 0, 0},
 120		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 121		.quick_drop = 0,
 122		.xpaBiasLvl = 0,
 123		.txFrameToDataStart = 0x0e,
 124		.txFrameToPaOn = 0x0e,
 125		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 126		.antennaGain = 0,
 127		.switchSettling = 0x2c,
 128		.adcDesiredSize = -30,
 129		.txEndToXpaOff = 0,
 130		.txEndToRxOn = 0x2,
 131		.txFrameToXpaOn = 0xe,
 132		.thresh62 = 28,
 133		.papdRateMaskHt20 = LE32(0x0cf0e0e0),
 134		.papdRateMaskHt40 = LE32(0x6cf0e0e0),
 135		.switchcomspdt = 0,
 136		.xlna_bias_strength = 0,
 137		.futureModal = {
 138			0, 0, 0, 0, 0, 0, 0,
 139		},
 140	 },
 141	.base_ext1 = {
 142		.ant_div_control = 0,
 143		.future = {0, 0},
 144		.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
 145	},
 146	.calFreqPier2G = {
 147		FREQ2FBIN(2412, 1),
 148		FREQ2FBIN(2437, 1),
 149		FREQ2FBIN(2472, 1),
 150	 },
 151	/* ar9300_cal_data_per_freq_op_loop 2g */
 152	.calPierData2G = {
 153		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 154		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 155		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 156	 },
 157	.calTarget_freqbin_Cck = {
 158		FREQ2FBIN(2412, 1),
 159		FREQ2FBIN(2484, 1),
 160	 },
 161	.calTarget_freqbin_2G = {
 162		FREQ2FBIN(2412, 1),
 163		FREQ2FBIN(2437, 1),
 164		FREQ2FBIN(2472, 1)
 165	 },
 166	.calTarget_freqbin_2GHT20 = {
 167		FREQ2FBIN(2412, 1),
 168		FREQ2FBIN(2437, 1),
 169		FREQ2FBIN(2472, 1)
 170	 },
 171	.calTarget_freqbin_2GHT40 = {
 172		FREQ2FBIN(2412, 1),
 173		FREQ2FBIN(2437, 1),
 174		FREQ2FBIN(2472, 1)
 175	 },
 176	.calTargetPowerCck = {
 177		 /* 1L-5L,5S,11L,11S */
 178		 { {36, 36, 36, 36} },
 179		 { {36, 36, 36, 36} },
 180	},
 181	.calTargetPower2G = {
 182		 /* 6-24,36,48,54 */
 183		 { {32, 32, 28, 24} },
 184		 { {32, 32, 28, 24} },
 185		 { {32, 32, 28, 24} },
 186	},
 187	.calTargetPower2GHT20 = {
 188		{ {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 189		{ {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 190		{ {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 191	},
 192	.calTargetPower2GHT40 = {
 193		{ {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 194		{ {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 195		{ {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 196	},
 197	.ctlIndex_2G =  {
 198		0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 199		0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 200	},
 201	.ctl_freqbin_2G = {
 202		{
 203			FREQ2FBIN(2412, 1),
 204			FREQ2FBIN(2417, 1),
 205			FREQ2FBIN(2457, 1),
 206			FREQ2FBIN(2462, 1)
 207		},
 208		{
 209			FREQ2FBIN(2412, 1),
 210			FREQ2FBIN(2417, 1),
 211			FREQ2FBIN(2462, 1),
 212			0xFF,
 213		},
 214
 215		{
 216			FREQ2FBIN(2412, 1),
 217			FREQ2FBIN(2417, 1),
 218			FREQ2FBIN(2462, 1),
 219			0xFF,
 220		},
 221		{
 222			FREQ2FBIN(2422, 1),
 223			FREQ2FBIN(2427, 1),
 224			FREQ2FBIN(2447, 1),
 225			FREQ2FBIN(2452, 1)
 226		},
 227
 228		{
 229			/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 230			/* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 231			/* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 232			/* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 233		},
 234
 235		{
 236			/* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 237			/* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 238			/* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 239			0,
 240		},
 241
 242		{
 243			/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 244			/* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 245			FREQ2FBIN(2472, 1),
 246			0,
 247		},
 248
 249		{
 250			/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 251			/* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 252			/* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 253			/* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 254		},
 255
 256		{
 257			/* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 258			/* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 259			/* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 260		},
 261
 262		{
 263			/* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 264			/* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 265			/* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 266			0
 267		},
 268
 269		{
 270			/* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 271			/* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 272			/* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 273			0
 274		},
 275
 276		{
 277			/* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 278			/* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 279			/* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 280			/* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 281		}
 282	 },
 283	.ctlPowerData_2G = {
 284		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 285		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 286		 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 287
 288		 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 289		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 290		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 291
 292		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 293		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 294		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 295
 296		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 297		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 298		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 299	 },
 300	.modalHeader5G = {
 301		/* 4 idle,t1,t2,b (4 bits per setting) */
 302		.antCtrlCommon = LE32(0x110),
 303		/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 304		.antCtrlCommon2 = LE32(0x22222),
 305		 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 306		.antCtrlChain = {
 307			LE16(0x000), LE16(0x000), LE16(0x000),
 308		},
 309		 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 310		.xatten1DB = {0, 0, 0},
 311
 312		/*
 313		 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 314		 * for merlin (0xa20c/b20c 16:12
 315		 */
 316		.xatten1Margin = {0, 0, 0},
 317		.tempSlope = 68,
 318		.voltSlope = 0,
 319		/* spurChans spur channels in usual fbin coding format */
 320		.spurChans = {0, 0, 0, 0, 0},
 321		/* noiseFloorThreshCh Check if the register is per chain */
 322		.noiseFloorThreshCh = {-1, 0, 0},
 323		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 324		.quick_drop = 0,
 325		.xpaBiasLvl = 0,
 326		.txFrameToDataStart = 0x0e,
 327		.txFrameToPaOn = 0x0e,
 328		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 329		.antennaGain = 0,
 330		.switchSettling = 0x2d,
 331		.adcDesiredSize = -30,
 332		.txEndToXpaOff = 0,
 333		.txEndToRxOn = 0x2,
 334		.txFrameToXpaOn = 0xe,
 335		.thresh62 = 28,
 336		.papdRateMaskHt20 = LE32(0x0c80c080),
 337		.papdRateMaskHt40 = LE32(0x0080c080),
 338		.switchcomspdt = 0,
 339		.xlna_bias_strength = 0,
 340		.futureModal = {
 341			0, 0, 0, 0, 0, 0, 0,
 342		},
 343	 },
 344	.base_ext2 = {
 345		.tempSlopeLow = 0,
 346		.tempSlopeHigh = 0,
 347		.xatten1DBLow = {0, 0, 0},
 348		.xatten1MarginLow = {0, 0, 0},
 349		.xatten1DBHigh = {0, 0, 0},
 350		.xatten1MarginHigh = {0, 0, 0}
 351	},
 352	.calFreqPier5G = {
 353		FREQ2FBIN(5180, 0),
 354		FREQ2FBIN(5220, 0),
 355		FREQ2FBIN(5320, 0),
 356		FREQ2FBIN(5400, 0),
 357		FREQ2FBIN(5500, 0),
 358		FREQ2FBIN(5600, 0),
 359		FREQ2FBIN(5725, 0),
 360		FREQ2FBIN(5825, 0)
 361	},
 362	.calPierData5G = {
 363			{
 364				{0, 0, 0, 0, 0},
 365				{0, 0, 0, 0, 0},
 366				{0, 0, 0, 0, 0},
 367				{0, 0, 0, 0, 0},
 368				{0, 0, 0, 0, 0},
 369				{0, 0, 0, 0, 0},
 370				{0, 0, 0, 0, 0},
 371				{0, 0, 0, 0, 0},
 372			},
 373			{
 374				{0, 0, 0, 0, 0},
 375				{0, 0, 0, 0, 0},
 376				{0, 0, 0, 0, 0},
 377				{0, 0, 0, 0, 0},
 378				{0, 0, 0, 0, 0},
 379				{0, 0, 0, 0, 0},
 380				{0, 0, 0, 0, 0},
 381				{0, 0, 0, 0, 0},
 382			},
 383			{
 384				{0, 0, 0, 0, 0},
 385				{0, 0, 0, 0, 0},
 386				{0, 0, 0, 0, 0},
 387				{0, 0, 0, 0, 0},
 388				{0, 0, 0, 0, 0},
 389				{0, 0, 0, 0, 0},
 390				{0, 0, 0, 0, 0},
 391				{0, 0, 0, 0, 0},
 392			},
 393
 394	},
 395	.calTarget_freqbin_5G = {
 396		FREQ2FBIN(5180, 0),
 397		FREQ2FBIN(5220, 0),
 398		FREQ2FBIN(5320, 0),
 399		FREQ2FBIN(5400, 0),
 400		FREQ2FBIN(5500, 0),
 401		FREQ2FBIN(5600, 0),
 402		FREQ2FBIN(5725, 0),
 403		FREQ2FBIN(5825, 0)
 404	},
 405	.calTarget_freqbin_5GHT20 = {
 406		FREQ2FBIN(5180, 0),
 407		FREQ2FBIN(5240, 0),
 408		FREQ2FBIN(5320, 0),
 409		FREQ2FBIN(5500, 0),
 410		FREQ2FBIN(5700, 0),
 411		FREQ2FBIN(5745, 0),
 412		FREQ2FBIN(5725, 0),
 413		FREQ2FBIN(5825, 0)
 414	},
 415	.calTarget_freqbin_5GHT40 = {
 416		FREQ2FBIN(5180, 0),
 417		FREQ2FBIN(5240, 0),
 418		FREQ2FBIN(5320, 0),
 419		FREQ2FBIN(5500, 0),
 420		FREQ2FBIN(5700, 0),
 421		FREQ2FBIN(5745, 0),
 422		FREQ2FBIN(5725, 0),
 423		FREQ2FBIN(5825, 0)
 424	 },
 425	.calTargetPower5G = {
 426		/* 6-24,36,48,54 */
 427		{ {20, 20, 20, 10} },
 428		{ {20, 20, 20, 10} },
 429		{ {20, 20, 20, 10} },
 430		{ {20, 20, 20, 10} },
 431		{ {20, 20, 20, 10} },
 432		{ {20, 20, 20, 10} },
 433		{ {20, 20, 20, 10} },
 434		{ {20, 20, 20, 10} },
 435	 },
 436	.calTargetPower5GHT20 = {
 437		/*
 438		 * 0_8_16,1-3_9-11_17-19,
 439		 * 4,5,6,7,12,13,14,15,20,21,22,23
 440		 */
 441		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 442		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 443		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 444		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 445		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 446		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 447		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 448		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 449	 },
 450	.calTargetPower5GHT40 =  {
 451		/*
 452		 * 0_8_16,1-3_9-11_17-19,
 453		 * 4,5,6,7,12,13,14,15,20,21,22,23
 454		 */
 455		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 456		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 457		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 458		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 459		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 460		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 461		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 462		{ {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 463	 },
 464	.ctlIndex_5G =  {
 465		0x10, 0x16, 0x18, 0x40, 0x46,
 466		0x48, 0x30, 0x36, 0x38
 467	},
 468	.ctl_freqbin_5G =  {
 469		{
 470			/* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 471			/* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 472			/* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 473			/* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 474			/* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 475			/* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 476			/* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 477			/* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 478		},
 479		{
 480			/* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 481			/* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 482			/* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 483			/* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 484			/* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 485			/* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 486			/* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 487			/* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 488		},
 489
 490		{
 491			/* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 492			/* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 493			/* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 494			/* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 495			/* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 496			/* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 497			/* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 498			/* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 499		},
 500
 501		{
 502			/* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 503			/* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 504			/* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 505			/* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 506			/* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 507			/* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 508			/* Data[3].ctlEdges[6].bChannel */ 0xFF,
 509			/* Data[3].ctlEdges[7].bChannel */ 0xFF,
 510		},
 511
 512		{
 513			/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 514			/* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 515			/* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 516			/* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 517			/* Data[4].ctlEdges[4].bChannel */ 0xFF,
 518			/* Data[4].ctlEdges[5].bChannel */ 0xFF,
 519			/* Data[4].ctlEdges[6].bChannel */ 0xFF,
 520			/* Data[4].ctlEdges[7].bChannel */ 0xFF,
 521		},
 522
 523		{
 524			/* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 525			/* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 526			/* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 527			/* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 528			/* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 529			/* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 530			/* Data[5].ctlEdges[6].bChannel */ 0xFF,
 531			/* Data[5].ctlEdges[7].bChannel */ 0xFF
 532		},
 533
 534		{
 535			/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 536			/* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 537			/* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 538			/* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 539			/* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 540			/* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 541			/* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 542			/* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 543		},
 544
 545		{
 546			/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 547			/* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 548			/* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 549			/* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 550			/* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 551			/* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 552			/* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 553			/* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 554		},
 555
 556		{
 557			/* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 558			/* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 559			/* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 560			/* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 561			/* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 562			/* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 563			/* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 564			/* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 565		}
 566	 },
 567	.ctlPowerData_5G = {
 568		{
 569			{
 570				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 571				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 572			}
 573		},
 574		{
 575			{
 576				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 577				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 578			}
 579		},
 580		{
 581			{
 582				CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 583				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 584			}
 585		},
 586		{
 587			{
 588				CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 589				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 590			}
 591		},
 592		{
 593			{
 594				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 595				CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 596			}
 597		},
 598		{
 599			{
 600				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 601				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 602			}
 603		},
 604		{
 605			{
 606				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 607				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 608			}
 609		},
 610		{
 611			{
 612				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 613				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 614			}
 615		},
 616		{
 617			{
 618				CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
 619				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 620			}
 621		},
 622	 }
 623};
 624
 625static const struct ar9300_eeprom ar9300_x113 = {
 626	.eepromVersion = 2,
 627	.templateVersion = 6,
 628	.macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 629	.custData = {"x113-023-f0000"},
 630	.baseEepHeader = {
 631		.regDmn = { LE16(0), LE16(0x1f) },
 632		.txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 633		.opCapFlags = {
 634			.opFlags = AR5416_OPFLAGS_11A,
 635			.eepMisc = AR9300_EEPMISC_LITTLE_ENDIAN,
 636		},
 637		.rfSilent = 0,
 638		.blueToothOptions = 0,
 639		.deviceCap = 0,
 640		.deviceType = 5, /* takes lower byte in eeprom location */
 641		.pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 642		.params_for_tuning_caps = {0, 0},
 643		.featureEnable = 0x0d,
 644		 /*
 645		  * bit0 - enable tx temp comp - disabled
 646		  * bit1 - enable tx volt comp - disabled
 647		  * bit2 - enable fastClock - enabled
 648		  * bit3 - enable doubling - enabled
 649		  * bit4 - enable internal regulator - disabled
 650		  * bit5 - enable pa predistortion - disabled
 651		  */
 652		.miscConfiguration = 0, /* bit0 - turn down drivestrength */
 653		.eepromWriteEnableGpio = 6,
 654		.wlanDisableGpio = 0,
 655		.wlanLedGpio = 8,
 656		.rxBandSelectGpio = 0xff,
 657		.txrxgain = 0x21,
 658		.swreg = 0,
 659	 },
 660	.modalHeader2G = {
 661	/* ar9300_modal_eep_header  2g */
 662		/* 4 idle,t1,t2,b(4 bits per setting) */
 663		.antCtrlCommon = LE32(0x110),
 664		/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 665		.antCtrlCommon2 = LE32(0x44444),
 666
 667		/*
 668		 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 669		 * rx1, rx12, b (2 bits each)
 670		 */
 671		.antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 672
 673		/*
 674		 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 675		 * for ar9280 (0xa20c/b20c 5:0)
 676		 */
 677		.xatten1DB = {0, 0, 0},
 678
 679		/*
 680		 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 681		 * for ar9280 (0xa20c/b20c 16:12
 682		 */
 683		.xatten1Margin = {0, 0, 0},
 684		.tempSlope = 25,
 685		.voltSlope = 0,
 686
 687		/*
 688		 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 689		 * channels in usual fbin coding format
 690		 */
 691		.spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 692
 693		/*
 694		 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 695		 * if the register is per chain
 696		 */
 697		.noiseFloorThreshCh = {-1, 0, 0},
 698		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 699		.quick_drop = 0,
 700		.xpaBiasLvl = 0,
 701		.txFrameToDataStart = 0x0e,
 702		.txFrameToPaOn = 0x0e,
 703		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 704		.antennaGain = 0,
 705		.switchSettling = 0x2c,
 706		.adcDesiredSize = -30,
 707		.txEndToXpaOff = 0,
 708		.txEndToRxOn = 0x2,
 709		.txFrameToXpaOn = 0xe,
 710		.thresh62 = 28,
 711		.papdRateMaskHt20 = LE32(0x0c80c080),
 712		.papdRateMaskHt40 = LE32(0x0080c080),
 713		.switchcomspdt = 0,
 714		.xlna_bias_strength = 0,
 715		.futureModal = {
 716			0, 0, 0, 0, 0, 0, 0,
 717		},
 718	 },
 719	 .base_ext1 = {
 720		.ant_div_control = 0,
 721		.future = {0, 0},
 722		.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
 723	 },
 724	.calFreqPier2G = {
 725		FREQ2FBIN(2412, 1),
 726		FREQ2FBIN(2437, 1),
 727		FREQ2FBIN(2472, 1),
 728	 },
 729	/* ar9300_cal_data_per_freq_op_loop 2g */
 730	.calPierData2G = {
 731		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 732		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 733		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 734	 },
 735	.calTarget_freqbin_Cck = {
 736		FREQ2FBIN(2412, 1),
 737		FREQ2FBIN(2472, 1),
 738	 },
 739	.calTarget_freqbin_2G = {
 740		FREQ2FBIN(2412, 1),
 741		FREQ2FBIN(2437, 1),
 742		FREQ2FBIN(2472, 1)
 743	 },
 744	.calTarget_freqbin_2GHT20 = {
 745		FREQ2FBIN(2412, 1),
 746		FREQ2FBIN(2437, 1),
 747		FREQ2FBIN(2472, 1)
 748	 },
 749	.calTarget_freqbin_2GHT40 = {
 750		FREQ2FBIN(2412, 1),
 751		FREQ2FBIN(2437, 1),
 752		FREQ2FBIN(2472, 1)
 753	 },
 754	.calTargetPowerCck = {
 755		 /* 1L-5L,5S,11L,11S */
 756		 { {34, 34, 34, 34} },
 757		 { {34, 34, 34, 34} },
 758	},
 759	.calTargetPower2G = {
 760		 /* 6-24,36,48,54 */
 761		 { {34, 34, 32, 32} },
 762		 { {34, 34, 32, 32} },
 763		 { {34, 34, 32, 32} },
 764	},
 765	.calTargetPower2GHT20 = {
 766		{ {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 767		{ {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 768		{ {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 769	},
 770	.calTargetPower2GHT40 = {
 771		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 772		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 773		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 774	},
 775	.ctlIndex_2G =  {
 776		0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 777		0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 778	},
 779	.ctl_freqbin_2G = {
 780		{
 781			FREQ2FBIN(2412, 1),
 782			FREQ2FBIN(2417, 1),
 783			FREQ2FBIN(2457, 1),
 784			FREQ2FBIN(2462, 1)
 785		},
 786		{
 787			FREQ2FBIN(2412, 1),
 788			FREQ2FBIN(2417, 1),
 789			FREQ2FBIN(2462, 1),
 790			0xFF,
 791		},
 792
 793		{
 794			FREQ2FBIN(2412, 1),
 795			FREQ2FBIN(2417, 1),
 796			FREQ2FBIN(2462, 1),
 797			0xFF,
 798		},
 799		{
 800			FREQ2FBIN(2422, 1),
 801			FREQ2FBIN(2427, 1),
 802			FREQ2FBIN(2447, 1),
 803			FREQ2FBIN(2452, 1)
 804		},
 805
 806		{
 807			/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 808			/* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 809			/* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 810			/* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 811		},
 812
 813		{
 814			/* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 815			/* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 816			/* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 817			0,
 818		},
 819
 820		{
 821			/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 822			/* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 823			FREQ2FBIN(2472, 1),
 824			0,
 825		},
 826
 827		{
 828			/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 829			/* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 830			/* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 831			/* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 832		},
 833
 834		{
 835			/* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 836			/* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 837			/* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 838		},
 839
 840		{
 841			/* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 842			/* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 843			/* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 844			0
 845		},
 846
 847		{
 848			/* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 849			/* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 850			/* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 851			0
 852		},
 853
 854		{
 855			/* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 856			/* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 857			/* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 858			/* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 859		}
 860	 },
 861	.ctlPowerData_2G = {
 862		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 863		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 864		 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 865
 866		 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 867		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 868		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 869
 870		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 871		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 872		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 873
 874		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 875		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 876		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 877	 },
 878	.modalHeader5G = {
 879		/* 4 idle,t1,t2,b (4 bits per setting) */
 880		.antCtrlCommon = LE32(0x220),
 881		/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 882		.antCtrlCommon2 = LE32(0x11111),
 883		 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 884		.antCtrlChain = {
 885			LE16(0x150), LE16(0x150), LE16(0x150),
 886		},
 887		 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 888		.xatten1DB = {0, 0, 0},
 889
 890		/*
 891		 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 892		 * for merlin (0xa20c/b20c 16:12
 893		 */
 894		.xatten1Margin = {0, 0, 0},
 895		.tempSlope = 68,
 896		.voltSlope = 0,
 897		/* spurChans spur channels in usual fbin coding format */
 898		.spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 899		/* noiseFloorThreshCh Check if the register is per chain */
 900		.noiseFloorThreshCh = {-1, 0, 0},
 901		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 902		.quick_drop = 0,
 903		.xpaBiasLvl = 0xf,
 904		.txFrameToDataStart = 0x0e,
 905		.txFrameToPaOn = 0x0e,
 906		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 907		.antennaGain = 0,
 908		.switchSettling = 0x2d,
 909		.adcDesiredSize = -30,
 910		.txEndToXpaOff = 0,
 911		.txEndToRxOn = 0x2,
 912		.txFrameToXpaOn = 0xe,
 913		.thresh62 = 28,
 914		.papdRateMaskHt20 = LE32(0x0cf0e0e0),
 915		.papdRateMaskHt40 = LE32(0x6cf0e0e0),
 916		.switchcomspdt = 0,
 917		.xlna_bias_strength = 0,
 918		.futureModal = {
 919			0, 0, 0, 0, 0, 0, 0,
 920		},
 921	 },
 922	.base_ext2 = {
 923		.tempSlopeLow = 72,
 924		.tempSlopeHigh = 105,
 925		.xatten1DBLow = {0, 0, 0},
 926		.xatten1MarginLow = {0, 0, 0},
 927		.xatten1DBHigh = {0, 0, 0},
 928		.xatten1MarginHigh = {0, 0, 0}
 929	 },
 930	.calFreqPier5G = {
 931		FREQ2FBIN(5180, 0),
 932		FREQ2FBIN(5240, 0),
 933		FREQ2FBIN(5320, 0),
 934		FREQ2FBIN(5400, 0),
 935		FREQ2FBIN(5500, 0),
 936		FREQ2FBIN(5600, 0),
 937		FREQ2FBIN(5745, 0),
 938		FREQ2FBIN(5785, 0)
 939	},
 940	.calPierData5G = {
 941			{
 942				{0, 0, 0, 0, 0},
 943				{0, 0, 0, 0, 0},
 944				{0, 0, 0, 0, 0},
 945				{0, 0, 0, 0, 0},
 946				{0, 0, 0, 0, 0},
 947				{0, 0, 0, 0, 0},
 948				{0, 0, 0, 0, 0},
 949				{0, 0, 0, 0, 0},
 950			},
 951			{
 952				{0, 0, 0, 0, 0},
 953				{0, 0, 0, 0, 0},
 954				{0, 0, 0, 0, 0},
 955				{0, 0, 0, 0, 0},
 956				{0, 0, 0, 0, 0},
 957				{0, 0, 0, 0, 0},
 958				{0, 0, 0, 0, 0},
 959				{0, 0, 0, 0, 0},
 960			},
 961			{
 962				{0, 0, 0, 0, 0},
 963				{0, 0, 0, 0, 0},
 964				{0, 0, 0, 0, 0},
 965				{0, 0, 0, 0, 0},
 966				{0, 0, 0, 0, 0},
 967				{0, 0, 0, 0, 0},
 968				{0, 0, 0, 0, 0},
 969				{0, 0, 0, 0, 0},
 970			},
 971
 972	},
 973	.calTarget_freqbin_5G = {
 974		FREQ2FBIN(5180, 0),
 975		FREQ2FBIN(5220, 0),
 976		FREQ2FBIN(5320, 0),
 977		FREQ2FBIN(5400, 0),
 978		FREQ2FBIN(5500, 0),
 979		FREQ2FBIN(5600, 0),
 980		FREQ2FBIN(5745, 0),
 981		FREQ2FBIN(5785, 0)
 982	},
 983	.calTarget_freqbin_5GHT20 = {
 984		FREQ2FBIN(5180, 0),
 985		FREQ2FBIN(5240, 0),
 986		FREQ2FBIN(5320, 0),
 987		FREQ2FBIN(5400, 0),
 988		FREQ2FBIN(5500, 0),
 989		FREQ2FBIN(5700, 0),
 990		FREQ2FBIN(5745, 0),
 991		FREQ2FBIN(5825, 0)
 992	},
 993	.calTarget_freqbin_5GHT40 = {
 994		FREQ2FBIN(5190, 0),
 995		FREQ2FBIN(5230, 0),
 996		FREQ2FBIN(5320, 0),
 997		FREQ2FBIN(5410, 0),
 998		FREQ2FBIN(5510, 0),
 999		FREQ2FBIN(5670, 0),
1000		FREQ2FBIN(5755, 0),
1001		FREQ2FBIN(5825, 0)
1002	 },
1003	.calTargetPower5G = {
1004		/* 6-24,36,48,54 */
1005		{ {42, 40, 40, 34} },
1006		{ {42, 40, 40, 34} },
1007		{ {42, 40, 40, 34} },
1008		{ {42, 40, 40, 34} },
1009		{ {42, 40, 40, 34} },
1010		{ {42, 40, 40, 34} },
1011		{ {42, 40, 40, 34} },
1012		{ {42, 40, 40, 34} },
1013	 },
1014	.calTargetPower5GHT20 = {
1015		/*
1016		 * 0_8_16,1-3_9-11_17-19,
1017		 * 4,5,6,7,12,13,14,15,20,21,22,23
1018		 */
1019		{ {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1020		{ {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1021		{ {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1022		{ {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1023		{ {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1024		{ {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1025		{ {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1026		{ {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1027	 },
1028	.calTargetPower5GHT40 =  {
1029		/*
1030		 * 0_8_16,1-3_9-11_17-19,
1031		 * 4,5,6,7,12,13,14,15,20,21,22,23
1032		 */
1033		{ {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1034		{ {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1035		{ {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1036		{ {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1037		{ {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1038		{ {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1039		{ {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1040		{ {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1041	 },
1042	.ctlIndex_5G =  {
1043		0x10, 0x16, 0x18, 0x40, 0x46,
1044		0x48, 0x30, 0x36, 0x38
1045	},
1046	.ctl_freqbin_5G =  {
1047		{
1048			/* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1049			/* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1050			/* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1051			/* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1052			/* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1053			/* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1054			/* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1055			/* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1056		},
1057		{
1058			/* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1059			/* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1060			/* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1061			/* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1062			/* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1063			/* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1064			/* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1065			/* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1066		},
1067
1068		{
1069			/* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1070			/* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1071			/* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1072			/* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1073			/* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1074			/* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1075			/* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1076			/* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1077		},
1078
1079		{
1080			/* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1081			/* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1082			/* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1083			/* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1084			/* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1085			/* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1086			/* Data[3].ctlEdges[6].bChannel */ 0xFF,
1087			/* Data[3].ctlEdges[7].bChannel */ 0xFF,
1088		},
1089
1090		{
1091			/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1092			/* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1093			/* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1094			/* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1095			/* Data[4].ctlEdges[4].bChannel */ 0xFF,
1096			/* Data[4].ctlEdges[5].bChannel */ 0xFF,
1097			/* Data[4].ctlEdges[6].bChannel */ 0xFF,
1098			/* Data[4].ctlEdges[7].bChannel */ 0xFF,
1099		},
1100
1101		{
1102			/* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1103			/* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1104			/* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1105			/* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1106			/* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1107			/* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1108			/* Data[5].ctlEdges[6].bChannel */ 0xFF,
1109			/* Data[5].ctlEdges[7].bChannel */ 0xFF
1110		},
1111
1112		{
1113			/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1114			/* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1115			/* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1116			/* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1117			/* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1118			/* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1119			/* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1120			/* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1121		},
1122
1123		{
1124			/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1125			/* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1126			/* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1127			/* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1128			/* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1129			/* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1130			/* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1131			/* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1132		},
1133
1134		{
1135			/* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1136			/* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1137			/* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1138			/* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1139			/* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1140			/* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1141			/* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1142			/* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1143		}
1144	 },
1145	.ctlPowerData_5G = {
1146		{
1147			{
1148				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1149				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1150			}
1151		},
1152		{
1153			{
1154				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1155				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1156			}
1157		},
1158		{
1159			{
1160				CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1161				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1162			}
1163		},
1164		{
1165			{
1166				CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1167				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1168			}
1169		},
1170		{
1171			{
1172				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1173				CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1174			}
1175		},
1176		{
1177			{
1178				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1179				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1180			}
1181		},
1182		{
1183			{
1184				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1185				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1186			}
1187		},
1188		{
1189			{
1190				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1191				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1192			}
1193		},
1194		{
1195			{
1196				CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1197				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1198			}
1199		},
1200	 }
1201};
1202
1203
1204static const struct ar9300_eeprom ar9300_h112 = {
1205	.eepromVersion = 2,
1206	.templateVersion = 3,
1207	.macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1208	.custData = {"h112-241-f0000"},
1209	.baseEepHeader = {
1210		.regDmn = { LE16(0), LE16(0x1f) },
1211		.txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1212		.opCapFlags = {
1213			.opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1214			.eepMisc = AR9300_EEPMISC_LITTLE_ENDIAN,
1215		},
1216		.rfSilent = 0,
1217		.blueToothOptions = 0,
1218		.deviceCap = 0,
1219		.deviceType = 5, /* takes lower byte in eeprom location */
1220		.pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1221		.params_for_tuning_caps = {0, 0},
1222		.featureEnable = 0x0d,
1223		/*
1224		 * bit0 - enable tx temp comp - disabled
1225		 * bit1 - enable tx volt comp - disabled
1226		 * bit2 - enable fastClock - enabled
1227		 * bit3 - enable doubling - enabled
1228		 * bit4 - enable internal regulator - disabled
1229		 * bit5 - enable pa predistortion - disabled
1230		 */
1231		.miscConfiguration = 0, /* bit0 - turn down drivestrength */
1232		.eepromWriteEnableGpio = 6,
1233		.wlanDisableGpio = 0,
1234		.wlanLedGpio = 8,
1235		.rxBandSelectGpio = 0xff,
1236		.txrxgain = 0x10,
1237		.swreg = 0,
1238	},
1239	.modalHeader2G = {
1240		/* ar9300_modal_eep_header  2g */
1241		/* 4 idle,t1,t2,b(4 bits per setting) */
1242		.antCtrlCommon = LE32(0x110),
1243		/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1244		.antCtrlCommon2 = LE32(0x44444),
1245
1246		/*
1247		 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1248		 * rx1, rx12, b (2 bits each)
1249		 */
1250		.antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1251
1252		/*
1253		 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1254		 * for ar9280 (0xa20c/b20c 5:0)
1255		 */
1256		.xatten1DB = {0, 0, 0},
1257
1258		/*
1259		 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1260		 * for ar9280 (0xa20c/b20c 16:12
1261		 */
1262		.xatten1Margin = {0, 0, 0},
1263		.tempSlope = 25,
1264		.voltSlope = 0,
1265
1266		/*
1267		 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1268		 * channels in usual fbin coding format
1269		 */
1270		.spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1271
1272		/*
1273		 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1274		 * if the register is per chain
1275		 */
1276		.noiseFloorThreshCh = {-1, 0, 0},
1277		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1278		.quick_drop = 0,
1279		.xpaBiasLvl = 0,
1280		.txFrameToDataStart = 0x0e,
1281		.txFrameToPaOn = 0x0e,
1282		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1283		.antennaGain = 0,
1284		.switchSettling = 0x2c,
1285		.adcDesiredSize = -30,
1286		.txEndToXpaOff = 0,
1287		.txEndToRxOn = 0x2,
1288		.txFrameToXpaOn = 0xe,
1289		.thresh62 = 28,
1290		.papdRateMaskHt20 = LE32(0x0c80c080),
1291		.papdRateMaskHt40 = LE32(0x0080c080),
1292		.switchcomspdt = 0,
1293		.xlna_bias_strength = 0,
1294		.futureModal = {
1295			0, 0, 0, 0, 0, 0, 0,
1296		},
1297	},
1298	.base_ext1 = {
1299		.ant_div_control = 0,
1300		.future = {0, 0},
1301		.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
1302	},
1303	.calFreqPier2G = {
1304		FREQ2FBIN(2412, 1),
1305		FREQ2FBIN(2437, 1),
1306		FREQ2FBIN(2462, 1),
1307	},
1308	/* ar9300_cal_data_per_freq_op_loop 2g */
1309	.calPierData2G = {
1310		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1311		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1312		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1313	},
1314	.calTarget_freqbin_Cck = {
1315		FREQ2FBIN(2412, 1),
1316		FREQ2FBIN(2472, 1),
1317	},
1318	.calTarget_freqbin_2G = {
1319		FREQ2FBIN(2412, 1),
1320		FREQ2FBIN(2437, 1),
1321		FREQ2FBIN(2472, 1)
1322	},
1323	.calTarget_freqbin_2GHT20 = {
1324		FREQ2FBIN(2412, 1),
1325		FREQ2FBIN(2437, 1),
1326		FREQ2FBIN(2472, 1)
1327	},
1328	.calTarget_freqbin_2GHT40 = {
1329		FREQ2FBIN(2412, 1),
1330		FREQ2FBIN(2437, 1),
1331		FREQ2FBIN(2472, 1)
1332	},
1333	.calTargetPowerCck = {
1334		/* 1L-5L,5S,11L,11S */
1335		{ {34, 34, 34, 34} },
1336		{ {34, 34, 34, 34} },
1337	},
1338	.calTargetPower2G = {
1339		/* 6-24,36,48,54 */
1340		{ {34, 34, 32, 32} },
1341		{ {34, 34, 32, 32} },
1342		{ {34, 34, 32, 32} },
1343	},
1344	.calTargetPower2GHT20 = {
1345		{ {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1346		{ {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1347		{ {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1348	},
1349	.calTargetPower2GHT40 = {
1350		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1351		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1352		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1353	},
1354	.ctlIndex_2G =  {
1355		0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1356		0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1357	},
1358	.ctl_freqbin_2G = {
1359		{
1360			FREQ2FBIN(2412, 1),
1361			FREQ2FBIN(2417, 1),
1362			FREQ2FBIN(2457, 1),
1363			FREQ2FBIN(2462, 1)
1364		},
1365		{
1366			FREQ2FBIN(2412, 1),
1367			FREQ2FBIN(2417, 1),
1368			FREQ2FBIN(2462, 1),
1369			0xFF,
1370		},
1371
1372		{
1373			FREQ2FBIN(2412, 1),
1374			FREQ2FBIN(2417, 1),
1375			FREQ2FBIN(2462, 1),
1376			0xFF,
1377		},
1378		{
1379			FREQ2FBIN(2422, 1),
1380			FREQ2FBIN(2427, 1),
1381			FREQ2FBIN(2447, 1),
1382			FREQ2FBIN(2452, 1)
1383		},
1384
1385		{
1386			/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1387			/* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1388			/* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1389			/* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1390		},
1391
1392		{
1393			/* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1394			/* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1395			/* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1396			0,
1397		},
1398
1399		{
1400			/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1401			/* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1402			FREQ2FBIN(2472, 1),
1403			0,
1404		},
1405
1406		{
1407			/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1408			/* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1409			/* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1410			/* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1411		},
1412
1413		{
1414			/* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1415			/* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1416			/* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1417		},
1418
1419		{
1420			/* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1421			/* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1422			/* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1423			0
1424		},
1425
1426		{
1427			/* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1428			/* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1429			/* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1430			0
1431		},
1432
1433		{
1434			/* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1435			/* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1436			/* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1437			/* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1438		}
1439	},
1440	.ctlPowerData_2G = {
1441		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1442		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1443		{ { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1444
1445		{ { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1446		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1447		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1448
1449		{ { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1450		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1451		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1452
1453		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1454		{ { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1455		{ { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1456	},
1457	.modalHeader5G = {
1458		/* 4 idle,t1,t2,b (4 bits per setting) */
1459		.antCtrlCommon = LE32(0x220),
1460		/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1461		.antCtrlCommon2 = LE32(0x44444),
1462		/* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1463		.antCtrlChain = {
1464			LE16(0x150), LE16(0x150), LE16(0x150),
1465		},
1466		/* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1467		.xatten1DB = {0, 0, 0},
1468
1469		/*
1470		 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1471		 * for merlin (0xa20c/b20c 16:12
1472		 */
1473		.xatten1Margin = {0, 0, 0},
1474		.tempSlope = 45,
1475		.voltSlope = 0,
1476		/* spurChans spur channels in usual fbin coding format */
1477		.spurChans = {0, 0, 0, 0, 0},
1478		/* noiseFloorThreshCh Check if the register is per chain */
1479		.noiseFloorThreshCh = {-1, 0, 0},
1480		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1481		.quick_drop = 0,
1482		.xpaBiasLvl = 0,
1483		.txFrameToDataStart = 0x0e,
1484		.txFrameToPaOn = 0x0e,
1485		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1486		.antennaGain = 0,
1487		.switchSettling = 0x2d,
1488		.adcDesiredSize = -30,
1489		.txEndToXpaOff = 0,
1490		.txEndToRxOn = 0x2,
1491		.txFrameToXpaOn = 0xe,
1492		.thresh62 = 28,
1493		.papdRateMaskHt20 = LE32(0x0cf0e0e0),
1494		.papdRateMaskHt40 = LE32(0x6cf0e0e0),
1495		.switchcomspdt = 0,
1496		.xlna_bias_strength = 0,
1497		.futureModal = {
1498			0, 0, 0, 0, 0, 0, 0,
1499		},
1500	},
1501	.base_ext2 = {
1502		.tempSlopeLow = 40,
1503		.tempSlopeHigh = 50,
1504		.xatten1DBLow = {0, 0, 0},
1505		.xatten1MarginLow = {0, 0, 0},
1506		.xatten1DBHigh = {0, 0, 0},
1507		.xatten1MarginHigh = {0, 0, 0}
1508	},
1509	.calFreqPier5G = {
1510		FREQ2FBIN(5180, 0),
1511		FREQ2FBIN(5220, 0),
1512		FREQ2FBIN(5320, 0),
1513		FREQ2FBIN(5400, 0),
1514		FREQ2FBIN(5500, 0),
1515		FREQ2FBIN(5600, 0),
1516		FREQ2FBIN(5700, 0),
1517		FREQ2FBIN(5785, 0)
1518	},
1519	.calPierData5G = {
1520		{
1521			{0, 0, 0, 0, 0},
1522			{0, 0, 0, 0, 0},
1523			{0, 0, 0, 0, 0},
1524			{0, 0, 0, 0, 0},
1525			{0, 0, 0, 0, 0},
1526			{0, 0, 0, 0, 0},
1527			{0, 0, 0, 0, 0},
1528			{0, 0, 0, 0, 0},
1529		},
1530		{
1531			{0, 0, 0, 0, 0},
1532			{0, 0, 0, 0, 0},
1533			{0, 0, 0, 0, 0},
1534			{0, 0, 0, 0, 0},
1535			{0, 0, 0, 0, 0},
1536			{0, 0, 0, 0, 0},
1537			{0, 0, 0, 0, 0},
1538			{0, 0, 0, 0, 0},
1539		},
1540		{
1541			{0, 0, 0, 0, 0},
1542			{0, 0, 0, 0, 0},
1543			{0, 0, 0, 0, 0},
1544			{0, 0, 0, 0, 0},
1545			{0, 0, 0, 0, 0},
1546			{0, 0, 0, 0, 0},
1547			{0, 0, 0, 0, 0},
1548			{0, 0, 0, 0, 0},
1549		},
1550
1551	},
1552	.calTarget_freqbin_5G = {
1553		FREQ2FBIN(5180, 0),
1554		FREQ2FBIN(5240, 0),
1555		FREQ2FBIN(5320, 0),
1556		FREQ2FBIN(5400, 0),
1557		FREQ2FBIN(5500, 0),
1558		FREQ2FBIN(5600, 0),
1559		FREQ2FBIN(5700, 0),
1560		FREQ2FBIN(5825, 0)
1561	},
1562	.calTarget_freqbin_5GHT20 = {
1563		FREQ2FBIN(5180, 0),
1564		FREQ2FBIN(5240, 0),
1565		FREQ2FBIN(5320, 0),
1566		FREQ2FBIN(5400, 0),
1567		FREQ2FBIN(5500, 0),
1568		FREQ2FBIN(5700, 0),
1569		FREQ2FBIN(5745, 0),
1570		FREQ2FBIN(5825, 0)
1571	},
1572	.calTarget_freqbin_5GHT40 = {
1573		FREQ2FBIN(5180, 0),
1574		FREQ2FBIN(5240, 0),
1575		FREQ2FBIN(5320, 0),
1576		FREQ2FBIN(5400, 0),
1577		FREQ2FBIN(5500, 0),
1578		FREQ2FBIN(5700, 0),
1579		FREQ2FBIN(5745, 0),
1580		FREQ2FBIN(5825, 0)
1581	},
1582	.calTargetPower5G = {
1583		/* 6-24,36,48,54 */
1584		{ {30, 30, 28, 24} },
1585		{ {30, 30, 28, 24} },
1586		{ {30, 30, 28, 24} },
1587		{ {30, 30, 28, 24} },
1588		{ {30, 30, 28, 24} },
1589		{ {30, 30, 28, 24} },
1590		{ {30, 30, 28, 24} },
1591		{ {30, 30, 28, 24} },
1592	},
1593	.calTargetPower5GHT20 = {
1594		/*
1595		 * 0_8_16,1-3_9-11_17-19,
1596		 * 4,5,6,7,12,13,14,15,20,21,22,23
1597		 */
1598		{ {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1599		{ {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1600		{ {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1601		{ {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1602		{ {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1603		{ {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1604		{ {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1605		{ {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1606	},
1607	.calTargetPower5GHT40 =  {
1608		/*
1609		 * 0_8_16,1-3_9-11_17-19,
1610		 * 4,5,6,7,12,13,14,15,20,21,22,23
1611		 */
1612		{ {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1613		{ {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1614		{ {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1615		{ {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1616		{ {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1617		{ {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1618		{ {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1619		{ {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1620	},
1621	.ctlIndex_5G =  {
1622		0x10, 0x16, 0x18, 0x40, 0x46,
1623		0x48, 0x30, 0x36, 0x38
1624	},
1625	.ctl_freqbin_5G =  {
1626		{
1627			/* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1628			/* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1629			/* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1630			/* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1631			/* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1632			/* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1633			/* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1634			/* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1635		},
1636		{
1637			/* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1638			/* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1639			/* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1640			/* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1641			/* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1642			/* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1643			/* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1644			/* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1645		},
1646
1647		{
1648			/* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1649			/* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1650			/* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1651			/* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1652			/* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1653			/* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1654			/* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1655			/* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1656		},
1657
1658		{
1659			/* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1660			/* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1661			/* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1662			/* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1663			/* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1664			/* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1665			/* Data[3].ctlEdges[6].bChannel */ 0xFF,
1666			/* Data[3].ctlEdges[7].bChannel */ 0xFF,
1667		},
1668
1669		{
1670			/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1671			/* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1672			/* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1673			/* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1674			/* Data[4].ctlEdges[4].bChannel */ 0xFF,
1675			/* Data[4].ctlEdges[5].bChannel */ 0xFF,
1676			/* Data[4].ctlEdges[6].bChannel */ 0xFF,
1677			/* Data[4].ctlEdges[7].bChannel */ 0xFF,
1678		},
1679
1680		{
1681			/* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1682			/* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1683			/* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1684			/* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1685			/* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1686			/* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1687			/* Data[5].ctlEdges[6].bChannel */ 0xFF,
1688			/* Data[5].ctlEdges[7].bChannel */ 0xFF
1689		},
1690
1691		{
1692			/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1693			/* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1694			/* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1695			/* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1696			/* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1697			/* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1698			/* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1699			/* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1700		},
1701
1702		{
1703			/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1704			/* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1705			/* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1706			/* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1707			/* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1708			/* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1709			/* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1710			/* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1711		},
1712
1713		{
1714			/* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1715			/* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1716			/* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1717			/* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1718			/* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1719			/* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1720			/* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1721			/* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1722		}
1723	},
1724	.ctlPowerData_5G = {
1725		{
1726			{
1727				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1728				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1729			}
1730		},
1731		{
1732			{
1733				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1734				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1735			}
1736		},
1737		{
1738			{
1739				CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1740				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1741			}
1742		},
1743		{
1744			{
1745				CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1746				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1747			}
1748		},
1749		{
1750			{
1751				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1752				CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1753			}
1754		},
1755		{
1756			{
1757				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1758				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1759			}
1760		},
1761		{
1762			{
1763				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1764				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1765			}
1766		},
1767		{
1768			{
1769				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1770				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1771			}
1772		},
1773		{
1774			{
1775				CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1776				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1777			}
1778		},
1779	}
1780};
1781
1782
1783static const struct ar9300_eeprom ar9300_x112 = {
1784	.eepromVersion = 2,
1785	.templateVersion = 5,
1786	.macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1787	.custData = {"x112-041-f0000"},
1788	.baseEepHeader = {
1789		.regDmn = { LE16(0), LE16(0x1f) },
1790		.txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1791		.opCapFlags = {
1792			.opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1793			.eepMisc = AR9300_EEPMISC_LITTLE_ENDIAN,
1794		},
1795		.rfSilent = 0,
1796		.blueToothOptions = 0,
1797		.deviceCap = 0,
1798		.deviceType = 5, /* takes lower byte in eeprom location */
1799		.pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1800		.params_for_tuning_caps = {0, 0},
1801		.featureEnable = 0x0d,
1802		/*
1803		 * bit0 - enable tx temp comp - disabled
1804		 * bit1 - enable tx volt comp - disabled
1805		 * bit2 - enable fastclock - enabled
1806		 * bit3 - enable doubling - enabled
1807		 * bit4 - enable internal regulator - disabled
1808		 * bit5 - enable pa predistortion - disabled
1809		 */
1810		.miscConfiguration = 0, /* bit0 - turn down drivestrength */
1811		.eepromWriteEnableGpio = 6,
1812		.wlanDisableGpio = 0,
1813		.wlanLedGpio = 8,
1814		.rxBandSelectGpio = 0xff,
1815		.txrxgain = 0x0,
1816		.swreg = 0,
1817	},
1818	.modalHeader2G = {
1819		/* ar9300_modal_eep_header  2g */
1820		/* 4 idle,t1,t2,b(4 bits per setting) */
1821		.antCtrlCommon = LE32(0x110),
1822		/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1823		.antCtrlCommon2 = LE32(0x22222),
1824
1825		/*
1826		 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1827		 * rx1, rx12, b (2 bits each)
1828		 */
1829		.antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1830
1831		/*
1832		 * xatten1DB[AR9300_max_chains];  3 xatten1_db
1833		 * for ar9280 (0xa20c/b20c 5:0)
1834		 */
1835		.xatten1DB = {0x1b, 0x1b, 0x1b},
1836
1837		/*
1838		 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1839		 * for ar9280 (0xa20c/b20c 16:12
1840		 */
1841		.xatten1Margin = {0x15, 0x15, 0x15},
1842		.tempSlope = 50,
1843		.voltSlope = 0,
1844
1845		/*
1846		 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1847		 * channels in usual fbin coding format
1848		 */
1849		.spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1850
1851		/*
1852		 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1853		 * if the register is per chain
1854		 */
1855		.noiseFloorThreshCh = {-1, 0, 0},
1856		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1857		.quick_drop = 0,
1858		.xpaBiasLvl = 0,
1859		.txFrameToDataStart = 0x0e,
1860		.txFrameToPaOn = 0x0e,
1861		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1862		.antennaGain = 0,
1863		.switchSettling = 0x2c,
1864		.adcDesiredSize = -30,
1865		.txEndToXpaOff = 0,
1866		.txEndToRxOn = 0x2,
1867		.txFrameToXpaOn = 0xe,
1868		.thresh62 = 28,
1869		.papdRateMaskHt20 = LE32(0x0c80c080),
1870		.papdRateMaskHt40 = LE32(0x0080c080),
1871		.switchcomspdt = 0,
1872		.xlna_bias_strength = 0,
1873		.futureModal = {
1874			0, 0, 0, 0, 0, 0, 0,
1875		},
1876	},
1877	.base_ext1 = {
1878		.ant_div_control = 0,
1879		.future = {0, 0},
1880		.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
1881	},
1882	.calFreqPier2G = {
1883		FREQ2FBIN(2412, 1),
1884		FREQ2FBIN(2437, 1),
1885		FREQ2FBIN(2472, 1),
1886	},
1887	/* ar9300_cal_data_per_freq_op_loop 2g */
1888	.calPierData2G = {
1889		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1890		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1891		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1892	},
1893	.calTarget_freqbin_Cck = {
1894		FREQ2FBIN(2412, 1),
1895		FREQ2FBIN(2472, 1),
1896	},
1897	.calTarget_freqbin_2G = {
1898		FREQ2FBIN(2412, 1),
1899		FREQ2FBIN(2437, 1),
1900		FREQ2FBIN(2472, 1)
1901	},
1902	.calTarget_freqbin_2GHT20 = {
1903		FREQ2FBIN(2412, 1),
1904		FREQ2FBIN(2437, 1),
1905		FREQ2FBIN(2472, 1)
1906	},
1907	.calTarget_freqbin_2GHT40 = {
1908		FREQ2FBIN(2412, 1),
1909		FREQ2FBIN(2437, 1),
1910		FREQ2FBIN(2472, 1)
1911	},
1912	.calTargetPowerCck = {
1913		/* 1L-5L,5S,11L,11s */
1914		{ {38, 38, 38, 38} },
1915		{ {38, 38, 38, 38} },
1916	},
1917	.calTargetPower2G = {
1918		/* 6-24,36,48,54 */
1919		{ {38, 38, 36, 34} },
1920		{ {38, 38, 36, 34} },
1921		{ {38, 38, 34, 32} },
1922	},
1923	.calTargetPower2GHT20 = {
1924		{ {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1925		{ {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1926		{ {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1927	},
1928	.calTargetPower2GHT40 = {
1929		{ {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1930		{ {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1931		{ {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1932	},
1933	.ctlIndex_2G =  {
1934		0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1935		0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1936	},
1937	.ctl_freqbin_2G = {
1938		{
1939			FREQ2FBIN(2412, 1),
1940			FREQ2FBIN(2417, 1),
1941			FREQ2FBIN(2457, 1),
1942			FREQ2FBIN(2462, 1)
1943		},
1944		{
1945			FREQ2FBIN(2412, 1),
1946			FREQ2FBIN(2417, 1),
1947			FREQ2FBIN(2462, 1),
1948			0xFF,
1949		},
1950
1951		{
1952			FREQ2FBIN(2412, 1),
1953			FREQ2FBIN(2417, 1),
1954			FREQ2FBIN(2462, 1),
1955			0xFF,
1956		},
1957		{
1958			FREQ2FBIN(2422, 1),
1959			FREQ2FBIN(2427, 1),
1960			FREQ2FBIN(2447, 1),
1961			FREQ2FBIN(2452, 1)
1962		},
1963
1964		{
1965			/* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1966			/* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1967			/* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1968			/* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1969		},
1970
1971		{
1972			/* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1973			/* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1974			/* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1975			0,
1976		},
1977
1978		{
1979			/* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1980			/* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1981			FREQ2FBIN(2472, 1),
1982			0,
1983		},
1984
1985		{
1986			/* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1987			/* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1988			/* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1989			/* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1990		},
1991
1992		{
1993			/* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1994			/* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1995			/* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1996		},
1997
1998		{
1999			/* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2000			/* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2001			/* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2002			0
2003		},
2004
2005		{
2006			/* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2007			/* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2008			/* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2009			0
2010		},
2011
2012		{
2013			/* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2014			/* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2015			/* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2016			/* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2017		}
2018	},
2019	.ctlPowerData_2G = {
2020		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2021		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2022		{ { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2023
2024		{ { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2025		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2026		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2027
2028		{ { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2029		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2030		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2031
2032		{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2033		{ { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2034		{ { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2035	},
2036	.modalHeader5G = {
2037		/* 4 idle,t1,t2,b (4 bits per setting) */
2038		.antCtrlCommon = LE32(0x110),
2039		/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2040		.antCtrlCommon2 = LE32(0x22222),
2041		/* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2042		.antCtrlChain = {
2043			LE16(0x0), LE16(0x0), LE16(0x0),
2044		},
2045		/* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2046		.xatten1DB = {0x13, 0x19, 0x17},
2047
2048		/*
2049		 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2050		 * for merlin (0xa20c/b20c 16:12
2051		 */
2052		.xatten1Margin = {0x19, 0x19, 0x19},
2053		.tempSlope = 70,
2054		.voltSlope = 15,
2055		/* spurChans spur channels in usual fbin coding format */
2056		.spurChans = {0, 0, 0, 0, 0},
2057		/* noiseFloorThreshch check if the register is per chain */
2058		.noiseFloorThreshCh = {-1, 0, 0},
2059		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2060		.quick_drop = 0,
2061		.xpaBiasLvl = 0,
2062		.txFrameToDataStart = 0x0e,
2063		.txFrameToPaOn = 0x0e,
2064		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2065		.antennaGain = 0,
2066		.switchSettling = 0x2d,
2067		.adcDesiredSize = -30,
2068		.txEndToXpaOff = 0,
2069		.txEndToRxOn = 0x2,
2070		.txFrameToXpaOn = 0xe,
2071		.thresh62 = 28,
2072		.papdRateMaskHt20 = LE32(0x0cf0e0e0),
2073		.papdRateMaskHt40 = LE32(0x6cf0e0e0),
2074		.switchcomspdt = 0,
2075		.xlna_bias_strength = 0,
2076		.futureModal = {
2077			0, 0, 0, 0, 0, 0, 0,
2078		},
2079	},
2080	.base_ext2 = {
2081		.tempSlopeLow = 72,
2082		.tempSlopeHigh = 105,
2083		.xatten1DBLow = {0x10, 0x14, 0x10},
2084		.xatten1MarginLow = {0x19, 0x19 , 0x19},
2085		.xatten1DBHigh = {0x1d, 0x20, 0x24},
2086		.xatten1MarginHigh = {0x10, 0x10, 0x10}
2087	},
2088	.calFreqPier5G = {
2089		FREQ2FBIN(5180, 0),
2090		FREQ2FBIN(5220, 0),
2091		FREQ2FBIN(5320, 0),
2092		FREQ2FBIN(5400, 0),
2093		FREQ2FBIN(5500, 0),
2094		FREQ2FBIN(5600, 0),
2095		FREQ2FBIN(5700, 0),
2096		FREQ2FBIN(5785, 0)
2097	},
2098	.calPierData5G = {
2099		{
2100			{0, 0, 0, 0, 0},
2101			{0, 0, 0, 0, 0},
2102			{0, 0, 0, 0, 0},
2103			{0, 0, 0, 0, 0},
2104			{0, 0, 0, 0, 0},
2105			{0, 0, 0, 0, 0},
2106			{0, 0, 0, 0, 0},
2107			{0, 0, 0, 0, 0},
2108		},
2109		{
2110			{0, 0, 0, 0, 0},
2111			{0, 0, 0, 0, 0},
2112			{0, 0, 0, 0, 0},
2113			{0, 0, 0, 0, 0},
2114			{0, 0, 0, 0, 0},
2115			{0, 0, 0, 0, 0},
2116			{0, 0, 0, 0, 0},
2117			{0, 0, 0, 0, 0},
2118		},
2119		{
2120			{0, 0, 0, 0, 0},
2121			{0, 0, 0, 0, 0},
2122			{0, 0, 0, 0, 0},
2123			{0, 0, 0, 0, 0},
2124			{0, 0, 0, 0, 0},
2125			{0, 0, 0, 0, 0},
2126			{0, 0, 0, 0, 0},
2127			{0, 0, 0, 0, 0},
2128		},
2129
2130	},
2131	.calTarget_freqbin_5G = {
2132		FREQ2FBIN(5180, 0),
2133		FREQ2FBIN(5220, 0),
2134		FREQ2FBIN(5320, 0),
2135		FREQ2FBIN(5400, 0),
2136		FREQ2FBIN(5500, 0),
2137		FREQ2FBIN(5600, 0),
2138		FREQ2FBIN(5725, 0),
2139		FREQ2FBIN(5825, 0)
2140	},
2141	.calTarget_freqbin_5GHT20 = {
2142		FREQ2FBIN(5180, 0),
2143		FREQ2FBIN(5220, 0),
2144		FREQ2FBIN(5320, 0),
2145		FREQ2FBIN(5400, 0),
2146		FREQ2FBIN(5500, 0),
2147		FREQ2FBIN(5600, 0),
2148		FREQ2FBIN(5725, 0),
2149		FREQ2FBIN(5825, 0)
2150	},
2151	.calTarget_freqbin_5GHT40 = {
2152		FREQ2FBIN(5180, 0),
2153		FREQ2FBIN(5220, 0),
2154		FREQ2FBIN(5320, 0),
2155		FREQ2FBIN(5400, 0),
2156		FREQ2FBIN(5500, 0),
2157		FREQ2FBIN(5600, 0),
2158		FREQ2FBIN(5725, 0),
2159		FREQ2FBIN(5825, 0)
2160	},
2161	.calTargetPower5G = {
2162		/* 6-24,36,48,54 */
2163		{ {32, 32, 28, 26} },
2164		{ {32, 32, 28, 26} },
2165		{ {32, 32, 28, 26} },
2166		{ {32, 32, 26, 24} },
2167		{ {32, 32, 26, 24} },
2168		{ {32, 32, 24, 22} },
2169		{ {30, 30, 24, 22} },
2170		{ {30, 30, 24, 22} },
2171	},
2172	.calTargetPower5GHT20 = {
2173		/*
2174		 * 0_8_16,1-3_9-11_17-19,
2175		 * 4,5,6,7,12,13,14,15,20,21,22,23
2176		 */
2177		{ {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2178		{ {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2179		{ {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2180		{ {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2181		{ {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2182		{ {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2183		{ {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2184		{ {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2185	},
2186	.calTargetPower5GHT40 =  {
2187		/*
2188		 * 0_8_16,1-3_9-11_17-19,
2189		 * 4,5,6,7,12,13,14,15,20,21,22,23
2190		 */
2191		{ {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2192		{ {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2193		{ {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2194		{ {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2195		{ {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2196		{ {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2197		{ {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2198		{ {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2199	},
2200	.ctlIndex_5G =  {
2201		0x10, 0x16, 0x18, 0x40, 0x46,
2202		0x48, 0x30, 0x36, 0x38
2203	},
2204	.ctl_freqbin_5G =  {
2205		{
2206			/* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2207			/* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2208			/* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2209			/* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2210			/* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2211			/* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2212			/* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2213			/* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2214		},
2215		{
2216			/* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2217			/* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2218			/* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2219			/* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2220			/* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2221			/* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2222			/* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2223			/* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2224		},
2225
2226		{
2227			/* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2228			/* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2229			/* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2230			/* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2231			/* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2232			/* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2233			/* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2234			/* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2235		},
2236
2237		{
2238			/* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2239			/* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2240			/* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2241			/* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2242			/* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2243			/* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2244			/* Data[3].ctledges[6].bchannel */ 0xFF,
2245			/* Data[3].ctledges[7].bchannel */ 0xFF,
2246		},
2247
2248		{
2249			/* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2250			/* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2251			/* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2252			/* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2253			/* Data[4].ctledges[4].bchannel */ 0xFF,
2254			/* Data[4].ctledges[5].bchannel */ 0xFF,
2255			/* Data[4].ctledges[6].bchannel */ 0xFF,
2256			/* Data[4].ctledges[7].bchannel */ 0xFF,
2257		},
2258
2259		{
2260			/* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2261			/* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2262			/* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2263			/* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2264			/* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2265			/* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2266			/* Data[5].ctledges[6].bchannel */ 0xFF,
2267			/* Data[5].ctledges[7].bchannel */ 0xFF
2268		},
2269
2270		{
2271			/* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2272			/* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2273			/* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2274			/* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2275			/* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2276			/* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2277			/* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2278			/* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2279		},
2280
2281		{
2282			/* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2283			/* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2284			/* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2285			/* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2286			/* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2287			/* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2288			/* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2289			/* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2290		},
2291
2292		{
2293			/* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2294			/* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2295			/* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2296			/* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2297			/* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2298			/* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2299			/* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2300			/* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2301		}
2302	},
2303	.ctlPowerData_5G = {
2304		{
2305			{
2306				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2307				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2308			}
2309		},
2310		{
2311			{
2312				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2313				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2314			}
2315		},
2316		{
2317			{
2318				CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2319				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2320			}
2321		},
2322		{
2323			{
2324				CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2325				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2326			}
2327		},
2328		{
2329			{
2330				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2331				CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2332			}
2333		},
2334		{
2335			{
2336				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2337				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2338			}
2339		},
2340		{
2341			{
2342				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2343				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2344			}
2345		},
2346		{
2347			{
2348				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2349				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2350			}
2351		},
2352		{
2353			{
2354				CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2355				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2356			}
2357		},
2358	}
2359};
2360
2361static const struct ar9300_eeprom ar9300_h116 = {
2362	.eepromVersion = 2,
2363	.templateVersion = 4,
2364	.macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2365	.custData = {"h116-041-f0000"},
2366	.baseEepHeader = {
2367		.regDmn = { LE16(0), LE16(0x1f) },
2368		.txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2369		.opCapFlags = {
2370			.opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2371			.eepMisc = AR9300_EEPMISC_LITTLE_ENDIAN,
2372		},
2373		.rfSilent = 0,
2374		.blueToothOptions = 0,
2375		.deviceCap = 0,
2376		.deviceType = 5, /* takes lower byte in eeprom location */
2377		.pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2378		.params_for_tuning_caps = {0, 0},
2379		.featureEnable = 0x0d,
2380		 /*
2381		  * bit0 - enable tx temp comp - disabled
2382		  * bit1 - enable tx volt comp - disabled
2383		  * bit2 - enable fastClock - enabled
2384		  * bit3 - enable doubling - enabled
2385		  * bit4 - enable internal regulator - disabled
2386		  * bit5 - enable pa predistortion - disabled
2387		  */
2388		.miscConfiguration = 0, /* bit0 - turn down drivestrength */
2389		.eepromWriteEnableGpio = 6,
2390		.wlanDisableGpio = 0,
2391		.wlanLedGpio = 8,
2392		.rxBandSelectGpio = 0xff,
2393		.txrxgain = 0x10,
2394		.swreg = 0,
2395	 },
2396	.modalHeader2G = {
2397	/* ar9300_modal_eep_header  2g */
2398		/* 4 idle,t1,t2,b(4 bits per setting) */
2399		.antCtrlCommon = LE32(0x110),
2400		/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2401		.antCtrlCommon2 = LE32(0x44444),
2402
2403		/*
2404		 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2405		 * rx1, rx12, b (2 bits each)
2406		 */
2407		.antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2408
2409		/*
2410		 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2411		 * for ar9280 (0xa20c/b20c 5:0)
2412		 */
2413		.xatten1DB = {0x1f, 0x1f, 0x1f},
2414
2415		/*
2416		 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2417		 * for ar9280 (0xa20c/b20c 16:12
2418		 */
2419		.xatten1Margin = {0x12, 0x12, 0x12},
2420		.tempSlope = 25,
2421		.voltSlope = 0,
2422
2423		/*
2424		 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2425		 * channels in usual fbin coding format
2426		 */
2427		.spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2428
2429		/*
2430		 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2431		 * if the register is per chain
2432		 */
2433		.noiseFloorThreshCh = {-1, 0, 0},
2434		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2435		.quick_drop = 0,
2436		.xpaBiasLvl = 0,
2437		.txFrameToDataStart = 0x0e,
2438		.txFrameToPaOn = 0x0e,
2439		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2440		.antennaGain = 0,
2441		.switchSettling = 0x2c,
2442		.adcDesiredSize = -30,
2443		.txEndToXpaOff = 0,
2444		.txEndToRxOn = 0x2,
2445		.txFrameToXpaOn = 0xe,
2446		.thresh62 = 28,
2447		.papdRateMaskHt20 = LE32(0x0c80C080),
2448		.papdRateMaskHt40 = LE32(0x0080C080),
2449		.switchcomspdt = 0,
2450		.xlna_bias_strength = 0,
2451		.futureModal = {
2452			0, 0, 0, 0, 0, 0, 0,
2453		},
2454	 },
2455	 .base_ext1 = {
2456		.ant_div_control = 0,
2457		.future = {0, 0},
2458		.tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
2459	 },
2460	.calFreqPier2G = {
2461		FREQ2FBIN(2412, 1),
2462		FREQ2FBIN(2437, 1),
2463		FREQ2FBIN(2462, 1),
2464	 },
2465	/* ar9300_cal_data_per_freq_op_loop 2g */
2466	.calPierData2G = {
2467		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2468		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2469		{ {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2470	 },
2471	.calTarget_freqbin_Cck = {
2472		FREQ2FBIN(2412, 1),
2473		FREQ2FBIN(2472, 1),
2474	 },
2475	.calTarget_freqbin_2G = {
2476		FREQ2FBIN(2412, 1),
2477		FREQ2FBIN(2437, 1),
2478		FREQ2FBIN(2472, 1)
2479	 },
2480	.calTarget_freqbin_2GHT20 = {
2481		FREQ2FBIN(2412, 1),
2482		FREQ2FBIN(2437, 1),
2483		FREQ2FBIN(2472, 1)
2484	 },
2485	.calTarget_freqbin_2GHT40 = {
2486		FREQ2FBIN(2412, 1),
2487		FREQ2FBIN(2437, 1),
2488		FREQ2FBIN(2472, 1)
2489	 },
2490	.calTargetPowerCck = {
2491		 /* 1L-5L,5S,11L,11S */
2492		 { {34, 34, 34, 34} },
2493		 { {34, 34, 34, 34} },
2494	},
2495	.calTargetPower2G = {
2496		 /* 6-24,36,48,54 */
2497		 { {34, 34, 32, 32} },
2498		 { {34, 34, 32, 32} },
2499		 { {34, 34, 32, 32} },
2500	},
2501	.calTargetPower2GHT20 = {
2502		{ {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2503		{ {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2504		{ {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2505	},
2506	.calTargetPower2GHT40 = {
2507		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2508		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2509		{ {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2510	},
2511	.ctlIndex_2G =  {
2512		0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2513		0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2514	},
2515	.ctl_freqbin_2G = {
2516		{
2517			FREQ2FBIN(2412, 1),
2518			FREQ2FBIN(2417, 1),
2519			FREQ2FBIN(2457, 1),
2520			FREQ2FBIN(2462, 1)
2521		},
2522		{
2523			FREQ2FBIN(2412, 1),
2524			FREQ2FBIN(2417, 1),
2525			FREQ2FBIN(2462, 1),
2526			0xFF,
2527		},
2528
2529		{
2530			FREQ2FBIN(2412, 1),
2531			FREQ2FBIN(2417, 1),
2532			FREQ2FBIN(2462, 1),
2533			0xFF,
2534		},
2535		{
2536			FREQ2FBIN(2422, 1),
2537			FREQ2FBIN(2427, 1),
2538			FREQ2FBIN(2447, 1),
2539			FREQ2FBIN(2452, 1)
2540		},
2541
2542		{
2543			/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2544			/* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2545			/* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2546			/* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2547		},
2548
2549		{
2550			/* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2551			/* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2552			/* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2553			0,
2554		},
2555
2556		{
2557			/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2558			/* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2559			FREQ2FBIN(2472, 1),
2560			0,
2561		},
2562
2563		{
2564			/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2565			/* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2566			/* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2567			/* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2568		},
2569
2570		{
2571			/* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2572			/* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2573			/* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2574		},
2575
2576		{
2577			/* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2578			/* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2579			/* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2580			0
2581		},
2582
2583		{
2584			/* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2585			/* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2586			/* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2587			0
2588		},
2589
2590		{
2591			/* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2592			/* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2593			/* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2594			/* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2595		}
2596	 },
2597	.ctlPowerData_2G = {
2598		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2599		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2600		 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2601
2602		 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2603		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2604		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2605
2606		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2607		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2608		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2609
2610		 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2611		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2612		 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2613	 },
2614	.modalHeader5G = {
2615		/* 4 idle,t1,t2,b (4 bits per setting) */
2616		.antCtrlCommon = LE32(0x220),
2617		/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2618		.antCtrlCommon2 = LE32(0x44444),
2619		 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2620		.antCtrlChain = {
2621			LE16(0x150), LE16(0x150), LE16(0x150),
2622		},
2623		 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2624		.xatten1DB = {0x19, 0x19, 0x19},
2625
2626		/*
2627		 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2628		 * for merlin (0xa20c/b20c 16:12
2629		 */
2630		.xatten1Margin = {0x14, 0x14, 0x14},
2631		.tempSlope = 70,
2632		.voltSlope = 0,
2633		/* spurChans spur channels in usual fbin coding format */
2634		.spurChans = {0, 0, 0, 0, 0},
2635		/* noiseFloorThreshCh Check if the register is per chain */
2636		.noiseFloorThreshCh = {-1, 0, 0},
2637		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2638		.quick_drop = 0,
2639		.xpaBiasLvl = 0,
2640		.txFrameToDataStart = 0x0e,
2641		.txFrameToPaOn = 0x0e,
2642		.txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2643		.antennaGain = 0,
2644		.switchSettling = 0x2d,
2645		.adcDesiredSize = -30,
2646		.txEndToXpaOff = 0,
2647		.txEndToRxOn = 0x2,
2648		.txFrameToXpaOn = 0xe,
2649		.thresh62 = 28,
2650		.papdRateMaskHt20 = LE32(0x0cf0e0e0),
2651		.papdRateMaskHt40 = LE32(0x6cf0e0e0),
2652		.switchcomspdt = 0,
2653		.xlna_bias_strength = 0,
2654		.futureModal = {
2655			0, 0, 0, 0, 0, 0, 0,
2656		},
2657	 },
2658	.base_ext2 = {
2659		.tempSlopeLow = 35,
2660		.tempSlopeHigh = 50,
2661		.xatten1DBLow = {0, 0, 0},
2662		.xatten1MarginLow = {0, 0, 0},
2663		.xatten1DBHigh = {0, 0, 0},
2664		.xatten1MarginHigh = {0, 0, 0}
2665	 },
2666	.calFreqPier5G = {
2667		FREQ2FBIN(5160, 0),
2668		FREQ2FBIN(5220, 0),
2669		FREQ2FBIN(5320, 0),
2670		FREQ2FBIN(5400, 0),
2671		FREQ2FBIN(5500, 0),
2672		FREQ2FBIN(5600, 0),
2673		FREQ2FBIN(5700, 0),
2674		FREQ2FBIN(5785, 0)
2675	},
2676	.calPierData5G = {
2677			{
2678				{0, 0, 0, 0, 0},
2679				{0, 0, 0, 0, 0},
2680				{0, 0, 0, 0, 0},
2681				{0, 0, 0, 0, 0},
2682				{0, 0, 0, 0, 0},
2683				{0, 0, 0, 0, 0},
2684				{0, 0, 0, 0, 0},
2685				{0, 0, 0, 0, 0},
2686			},
2687			{
2688				{0, 0, 0, 0, 0},
2689				{0, 0, 0, 0, 0},
2690				{0, 0, 0, 0, 0},
2691				{0, 0, 0, 0, 0},
2692				{0, 0, 0, 0, 0},
2693				{0, 0, 0, 0, 0},
2694				{0, 0, 0, 0, 0},
2695				{0, 0, 0, 0, 0},
2696			},
2697			{
2698				{0, 0, 0, 0, 0},
2699				{0, 0, 0, 0, 0},
2700				{0, 0, 0, 0, 0},
2701				{0, 0, 0, 0, 0},
2702				{0, 0, 0, 0, 0},
2703				{0, 0, 0, 0, 0},
2704				{0, 0, 0, 0, 0},
2705				{0, 0, 0, 0, 0},
2706			},
2707
2708	},
2709	.calTarget_freqbin_5G = {
2710		FREQ2FBIN(5180, 0),
2711		FREQ2FBIN(5240, 0),
2712		FREQ2FBIN(5320, 0),
2713		FREQ2FBIN(5400, 0),
2714		FREQ2FBIN(5500, 0),
2715		FREQ2FBIN(5600, 0),
2716		FREQ2FBIN(5700, 0),
2717		FREQ2FBIN(5825, 0)
2718	},
2719	.calTarget_freqbin_5GHT20 = {
2720		FREQ2FBIN(5180, 0),
2721		FREQ2FBIN(5240, 0),
2722		FREQ2FBIN(5320, 0),
2723		FREQ2FBIN(5400, 0),
2724		FREQ2FBIN(5500, 0),
2725		FREQ2FBIN(5700, 0),
2726		FREQ2FBIN(5745, 0),
2727		FREQ2FBIN(5825, 0)
2728	},
2729	.calTarget_freqbin_5GHT40 = {
2730		FREQ2FBIN(5180, 0),
2731		FREQ2FBIN(5240, 0),
2732		FREQ2FBIN(5320, 0),
2733		FREQ2FBIN(5400, 0),
2734		FREQ2FBIN(5500, 0),
2735		FREQ2FBIN(5700, 0),
2736		FREQ2FBIN(5745, 0),
2737		FREQ2FBIN(5825, 0)
2738	 },
2739	.calTargetPower5G = {
2740		/* 6-24,36,48,54 */
2741		{ {30, 30, 28, 24} },
2742		{ {30, 30, 28, 24} },
2743		{ {30, 30, 28, 24} },
2744		{ {30, 30, 28, 24} },
2745		{ {30, 30, 28, 24} },
2746		{ {30, 30, 28, 24} },
2747		{ {30, 30, 28, 24} },
2748		{ {30, 30, 28, 24} },
2749	 },
2750	.calTargetPower5GHT20 = {
2751		/*
2752		 * 0_8_16,1-3_9-11_17-19,
2753		 * 4,5,6,7,12,13,14,15,20,21,22,23
2754		 */
2755		{ {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2756		{ {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2757		{ {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2758		{ {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2759		{ {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2760		{ {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2761		{ {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2762		{ {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2763	 },
2764	.calTargetPower5GHT40 =  {
2765		/*
2766		 * 0_8_16,1-3_9-11_17-19,
2767		 * 4,5,6,7,12,13,14,15,20,21,22,23
2768		 */
2769		{ {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2770		{ {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2771		{ {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2772		{ {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2773		{ {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2774		{ {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2775		{ {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2776		{ {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2777	 },
2778	.ctlIndex_5G =  {
2779		0x10, 0x16, 0x18, 0x40, 0x46,
2780		0x48, 0x30, 0x36, 0x38
2781	},
2782	.ctl_freqbin_5G =  {
2783		{
2784			/* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2785			/* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2786			/* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2787			/* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2788			/* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2789			/* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2790			/* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2791			/* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2792		},
2793		{
2794			/* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2795			/* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2796			/* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2797			/* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2798			/* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2799			/* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2800			/* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2801			/* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2802		},
2803
2804		{
2805			/* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2806			/* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2807			/* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2808			/* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2809			/* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2810			/* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2811			/* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2812			/* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2813		},
2814
2815		{
2816			/* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2817			/* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2818			/* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2819			/* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2820			/* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2821			/* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2822			/* Data[3].ctlEdges[6].bChannel */ 0xFF,
2823			/* Data[3].ctlEdges[7].bChannel */ 0xFF,
2824		},
2825
2826		{
2827			/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2828			/* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2829			/* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2830			/* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2831			/* Data[4].ctlEdges[4].bChannel */ 0xFF,
2832			/* Data[4].ctlEdges[5].bChannel */ 0xFF,
2833			/* Data[4].ctlEdges[6].bChannel */ 0xFF,
2834			/* Data[4].ctlEdges[7].bChannel */ 0xFF,
2835		},
2836
2837		{
2838			/* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2839			/* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2840			/* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2841			/* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2842			/* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2843			/* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2844			/* Data[5].ctlEdges[6].bChannel */ 0xFF,
2845			/* Data[5].ctlEdges[7].bChannel */ 0xFF
2846		},
2847
2848		{
2849			/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2850			/* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2851			/* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2852			/* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2853			/* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2854			/* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2855			/* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2856			/* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2857		},
2858
2859		{
2860			/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2861			/* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2862			/* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2863			/* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2864			/* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2865			/* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2866			/* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2867			/* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2868		},
2869
2870		{
2871			/* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2872			/* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2873			/* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2874			/* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2875			/* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2876			/* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2877			/* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2878			/* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2879		}
2880	 },
2881	.ctlPowerData_5G = {
2882		{
2883			{
2884				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2885				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2886			}
2887		},
2888		{
2889			{
2890				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2891				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2892			}
2893		},
2894		{
2895			{
2896				CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2897				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2898			}
2899		},
2900		{
2901			{
2902				CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2903				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2904			}
2905		},
2906		{
2907			{
2908				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2909				CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2910			}
2911		},
2912		{
2913			{
2914				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2915				CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2916			}
2917		},
2918		{
2919			{
2920				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2921				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2922			}
2923		},
2924		{
2925			{
2926				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2927				CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2928			}
2929		},
2930		{
2931			{
2932				CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2933				CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2934			}
2935		},
2936	 }
2937};
2938
2939
2940static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2941	&ar9300_default,
2942	&ar9300_x112,
2943	&ar9300_h116,
2944	&ar9300_h112,
2945	&ar9300_x113,
2946};
2947
2948static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2949{
2950	int it;
2951
2952	for (it = 0; it < ARRAY_SIZE(ar9300_eep_templates); it++)
2953		if (ar9300_eep_templates[it]->templateVersion == id)
2954			return ar9300_eep_templates[it];
2955	return NULL;
2956}
2957
2958static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2959{
2960	return 0;
2961}
2962
2963static int interpolate(int x, int xa, int xb, int ya, int yb)
2964{
2965	int bf, factor, plus;
2966
2967	bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2968	factor = bf / 2;
2969	plus = bf % 2;
2970	return ya + factor + plus;
2971}
2972
2973static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2974				      enum eeprom_param param)
2975{
2976	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2977	struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2978
2979	switch (param) {
2980	case EEP_MAC_LSW:
2981		return get_unaligned_be16(eep->macAddr);
2982	case EEP_MAC_MID:
2983		return get_unaligned_be16(eep->macAddr + 2);
2984	case EEP_MAC_MSW:
2985		return get_unaligned_be16(eep->macAddr + 4);
2986	case EEP_REG_0:
2987		return le16_to_cpu(pBase->regDmn[0]);
2988	case EEP_OP_CAP:
2989		return pBase->deviceCap;
2990	case EEP_OP_MODE:
2991		return pBase->opCapFlags.opFlags;
2992	case EEP_RF_SILENT:
2993		return pBase->rfSilent;
2994	case EEP_TX_MASK:
2995		return (pBase->txrxMask >> 4) & 0xf;
2996	case EEP_RX_MASK:
2997		return pBase->txrxMask & 0xf;
2998	case EEP_PAPRD:
2999		return !!(pBase->featureEnable & BIT(5));
3000	case EEP_CHAIN_MASK_REDUCE:
3001		return (pBase->miscConfiguration >> 0x3) & 0x1;
3002	case EEP_ANT_DIV_CTL1:
3003		if (AR_SREV_9565(ah))
3004			return AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE;
3005		else
3006			return eep->base_ext1.ant_div_control;
3007	case EEP_ANTENNA_GAIN_5G:
3008		return eep->modalHeader5G.antennaGain;
3009	case EEP_ANTENNA_GAIN_2G:
3010		return eep->modalHeader2G.antennaGain;
3011	default:
3012		return 0;
3013	}
3014}
3015
3016static bool ar9300_eeprom_read_byte(struct ath_hw *ah, int address,
3017				    u8 *buffer)
3018{
3019	u16 val;
3020
3021	if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val)))
3022		return false;
3023
3024	*buffer = (val >> (8 * (address % 2))) & 0xff;
3025	return true;
3026}
3027
3028static bool ar9300_eeprom_read_word(struct ath_hw *ah, int address,
3029				    u8 *buffer)
3030{
3031	u16 val;
3032
3033	if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val)))
3034		return false;
3035
3036	buffer[0] = val >> 8;
3037	buffer[1] = val & 0xff;
3038
3039	return true;
3040}
3041
3042static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3043			       int count)
3044{
3045	struct ath_common *common = ath9k_hw_common(ah);
3046	int i;
3047
3048	if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3049		ath_dbg(common, EEPROM, "eeprom address not in range\n");
3050		return false;
3051	}
3052
3053	/*
3054	 * Since we're reading the bytes in reverse order from a little-endian
3055	 * word stream, an even address means we only use the lower half of
3056	 * the 16-bit word at that address
3057	 */
3058	if (address % 2 == 0) {
3059		if (!ar9300_eeprom_read_byte(ah, address--, buffer++))
3060			goto error;
3061
3062		count--;
3063	}
3064
3065	for (i = 0; i < count / 2; i++) {
3066		if (!ar9300_eeprom_read_word(ah, address, buffer))
3067			goto error;
3068
3069		address -= 2;
3070		buffer += 2;
3071	}
3072
3073	if (count % 2)
3074		if (!ar9300_eeprom_read_byte(ah, address, buffer))
3075			goto error;
3076
3077	return true;
3078
3079error:
3080	ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3081		address);
3082	return false;
3083}
3084
3085static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3086{
3087	REG_READ(ah, AR9300_OTP_BASE(ah) + (4 * addr));
3088
3089	if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS(ah), AR9300_OTP_STATUS_TYPE,
3090			   AR9300_OTP_STATUS_VALID, 1000))
3091		return false;
3092
3093	*data = REG_READ(ah, AR9300_OTP_READ_DATA(ah));
3094	return true;
3095}
3096
3097static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3098			    int count)
3099{
3100	u32 data;
3101	int i;
3102
3103	for (i = 0; i < count; i++) {
3104		int offset = 8 * ((address - i) % 4);
3105		if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3106			return false;
3107
3108		buffer[i] = (data >> offset) & 0xff;
3109	}
3110
3111	return true;
3112}
3113
3114
3115static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3116				   int *length, int *major, int *minor)
3117{
3118	unsigned long value[4];
3119
3120	value[0] = best[0];
3121	value[1] = best[1];
3122	value[2] = best[2];
3123	value[3] = best[3];
3124	*code = ((value[0] >> 5) & 0x0007);
3125	*reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3126	*length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3127	*major = (value[2] & 0x000f);
3128	*minor = (value[3] & 0x00ff);
3129}
3130
3131static u16 ar9300_comp_cksum(u8 *data, int dsize)
3132{
3133	int it, checksum = 0;
3134
3135	for (it = 0; it < dsize; it++) {
3136		checksum += data[it];
3137		checksum &= 0xffff;
3138	}
3139
3140	return checksum;
3141}
3142
3143static bool ar9300_uncompress_block(struct ath_hw *ah,
3144				    u8 *mptr,
3145				    int mdataSize,
3146				    u8 *block,
3147				    int size)
3148{
3149	int it;
3150	int spot;
3151	int offset;
3152	int length;
3153	struct ath_common *common = ath9k_hw_common(ah);
3154
3155	spot = 0;
3156
3157	for (it = 0; it < size; it += (length+2)) {
3158		offset = block[it];
3159		offset &= 0xff;
3160		spot += offset;
3161		length = block[it+1];
3162		length &= 0xff;
3163
3164		if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3165			ath_dbg(common, EEPROM,
3166				"Restore at %d: spot=%d offset=%d length=%d\n",
3167				it, spot, offset, length);
3168			memcpy(&mptr[spot], &block[it+2], length);
3169			spot += length;
3170		} else if (length > 0) {
3171			ath_dbg(common, EEPROM,
3172				"Bad restore at %d: spot=%d offset=%d length=%d\n",
3173				it, spot, offset, length);
3174			return false;
3175		}
3176	}
3177	return true;
3178}
3179
3180static int ar9300_compress_decision(struct ath_hw *ah,
3181				    int it,
3182				    int code,
3183				    int reference,
3184				    u8 *mptr,
3185				    u8 *word, int length, int mdata_size)
3186{
3187	struct ath_common *common = ath9k_hw_common(ah);
3188	const struct ar9300_eeprom *eep = NULL;
3189
3190	switch (code) {
3191	case _CompressNone:
3192		if (length != mdata_size) {
3193			ath_dbg(common, EEPROM,
3194				"EEPROM structure size mismatch memory=%d eeprom=%d\n",
3195				mdata_size, length);
3196			return -1;
3197		}
3198		memcpy(mptr, word + COMP_HDR_LEN, length);
3199		ath_dbg(common, EEPROM,
3200			"restored eeprom %d: uncompressed, length %d\n",
3201			it, length);
3202		break;
3203	case _CompressBlock:
3204		if (reference != 0) {
3205			eep = ar9003_eeprom_struct_find_by_id(reference);
3206			if (eep == NULL) {
3207				ath_dbg(common, EEPROM,
3208					"can't find reference eeprom struct %d\n",
3209					reference);
3210				return -1;
3211			}
3212			memcpy(mptr, eep, mdata_size);
3213		}
3214		ath_dbg(common, EEPROM,
3215			"restore eeprom %d: block, reference %d, length %d\n",
3216			it, reference, length);
3217		ar9300_uncompress_block(ah, mptr, mdata_size,
3218					(word + COMP_HDR_LEN), length);
3219		break;
3220	default:
3221		ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3222		return -1;
3223	}
3224	return 0;
3225}
3226
3227typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3228			       int count);
3229
3230static bool ar9300_check_header(void *data)
3231{
3232	u32 *word = data;
3233	return !(*word == 0 || *word == ~0);
3234}
3235
3236static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3237				       int base_addr)
3238{
3239	u8 header[4];
3240
3241	if (!read(ah, base_addr, header, 4))
3242		return false;
3243
3244	return ar9300_check_header(header);
3245}
3246
3247static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3248				       int mdata_size)
3249{
3250	u16 *data = (u16 *) mptr;
3251	int i;
3252
3253	for (i = 0; i < mdata_size / 2; i++, data++)
3254		if (!ath9k_hw_nvram_read(ah, i, data))
3255			return -EIO;
3256
3257	return 0;
3258}
3259/*
3260 * Read the configuration data from the eeprom.
3261 * The data can be put in any specified memory buffer.
3262 *
3263 * Returns -1 on error.
3264 * Returns address of next memory location on success.
3265 */
3266static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3267					  u8 *mptr, int mdata_size)
3268{
3269#define MDEFAULT 15
3270#define MSTATE 100
3271	int cptr;
3272	u8 *word;
3273	int code;
3274	int reference, length, major, minor;
3275	int osize;
3276	int it;
3277	u16 checksum, mchecksum;
3278	struct ath_common *common = ath9k_hw_common(ah);
3279	struct ar9300_eeprom *eep;
3280	eeprom_read_op read;
3281
3282	if (ath9k_hw_use_flash(ah)) {
3283		u8 txrx;
3284
3285		if (ar9300_eeprom_restore_flash(ah, mptr, mdata_size))
3286			return -EIO;
3287
3288		/* check if eeprom contains valid data */
3289		eep = (struct ar9300_eeprom *) mptr;
3290		txrx = eep->baseEepHeader.txrxMask;
3291		if (txrx != 0 && txrx != 0xff)
3292			return 0;
3293	}
3294
3295	word = kzalloc(2048, GFP_KERNEL);
3296	if (!word)
3297		return -ENOMEM;
3298
3299	memcpy(mptr, &ar9300_default, mdata_size);
3300
3301	read = ar9300_read_eeprom;
3302	if (AR_SREV_9485(ah))
3303		cptr = AR9300_BASE_ADDR_4K;
3304	else if (AR_SREV_9330(ah))
3305		cptr = AR9300_BASE_ADDR_512;
3306	else
3307		cptr = AR9300_BASE_ADDR;
3308	ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3309		cptr);
3310	if (ar9300_check_eeprom_header(ah, read, cptr))
3311		goto found;
3312
3313	cptr = AR9300_BASE_ADDR_4K;
3314	ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3315		cptr);
3316	if (ar9300_check_eeprom_header(ah, read, cptr))
3317		goto found;
3318
3319	cptr = AR9300_BASE_ADDR_512;
3320	ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3321		cptr);
3322	if (ar9300_check_eeprom_header(ah, read, cptr))
3323		goto found;
3324
3325	read = ar9300_read_otp;
3326	cptr = AR9300_BASE_ADDR;
3327	ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3328	if (ar9300_check_eeprom_header(ah, read, cptr))
3329		goto found;
3330
3331	cptr = AR9300_BASE_ADDR_512;
3332	ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3333	if (ar9300_check_eeprom_header(ah, read, cptr))
3334		goto found;
3335
3336	goto fail;
3337
3338found:
3339	ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3340
3341	for (it = 0; it < MSTATE; it++) {
3342		if (!read(ah, cptr, word, COMP_HDR_LEN))
3343			goto fail;
3344
3345		if (!ar9300_check_header(word))
3346			break;
3347
3348		ar9300_comp_hdr_unpack(word, &code, &reference,
3349				       &length, &major, &minor);
3350		ath_dbg(common, EEPROM,
3351			"Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3352			cptr, code, reference, length, major, minor);
3353		if ((!AR_SREV_9485(ah) && length >= 1024) ||
3354		    (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485) ||
3355		    (length > cptr)) {
3356			ath_dbg(common, EEPROM, "Skipping bad header\n");
3357			cptr -= COMP_HDR_LEN;
3358			continue;
3359		}
3360
3361		osize = length;
3362		read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3363		checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3364		mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3365		ath_dbg(common, EEPROM, "checksum %x %x\n",
3366			checksum, mchecksum);
3367		if (checksum == mchecksum) {
3368			ar9300_compress_decision(ah, it, code, reference, mptr,
3369						 word, length, mdata_size);
3370		} else {
3371			ath_dbg(common, EEPROM,
3372				"skipping block with bad checksum\n");
3373		}
3374		cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3375	}
3376
3377	kfree(word);
3378	return cptr;
3379
3380fail:
3381	kfree(word);
3382	return -1;
3383}
3384
3385/*
3386 * Restore the configuration structure by reading the eeprom.
3387 * This function destroys any existing in-memory structure
3388 * content.
3389 */
3390static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3391{
3392	u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3393
3394	if (ar9300_eeprom_restore_internal(ah, mptr,
3395			sizeof(struct ar9300_eeprom)) < 0)
3396		return false;
3397
3398	return true;
3399}
3400
3401#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3402static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3403				    struct ar9300_modal_eep_header *modal_hdr)
3404{
3405	PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3406	PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3407	PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3408	PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3409	PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3410	PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3411	PR_EEP("Switch Settle", modal_hdr->switchSettling);
3412	PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3413	PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3414	PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3415	PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3416	PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3417	PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3418	PR_EEP("Temp Slope", modal_hdr->tempSlope);
3419	PR_EEP("Volt Slope", modal_hdr->voltSlope);
3420	PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3421	PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3422	PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3423	PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3424	PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3425	PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3426	PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3427	PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3428	PR_EEP("Quick Drop", modal_hdr->quick_drop);
3429	PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3430	PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3431	PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3432	PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3433	PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3434	PR_EEP("txClip", modal_hdr->txClip);
3435	PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3436
3437	return len;
3438}
3439
3440static u32 ar9003_dump_cal_data(struct ath_hw *ah, char *buf, u32 len, u32 size,
3441				bool is_2g)
3442{
3443	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3444	struct ar9300_base_eep_hdr *pBase;
3445	struct ar9300_cal_data_per_freq_op_loop *cal_pier;
3446	int cal_pier_nr;
3447	int freq;
3448	int i, j;
3449
3450	pBase = &eep->baseEepHeader;
3451
3452	if (is_2g)
3453		cal_pier_nr = AR9300_NUM_2G_CAL_PIERS;
3454	else
3455		cal_pier_nr = AR9300_NUM_5G_CAL_PIERS;
3456
3457	for (i = 0; i < AR9300_MAX_CHAINS; i++) {
3458		if (!((pBase->txrxMask >> i) & 1))
3459			continue;
3460
3461		len += scnprintf(buf + len, size - len, "Chain %d\n", i);
3462
3463		len += scnprintf(buf + len, size - len,
3464			"Freq\t ref\tvolt\ttemp\tnf_cal\tnf_pow\trx_temp\n");
3465
3466		for (j = 0; j < cal_pier_nr; j++) {
3467			if (is_2g) {
3468				cal_pier = &eep->calPierData2G[i][j];
3469				freq = 2300 + eep->calFreqPier2G[j];
3470			} else {
3471				cal_pier = &eep->calPierData5G[i][j];
3472				freq = 4800 + eep->calFreqPier5G[j] * 5;
3473			}
3474
3475			len += scnprintf(buf + len, size - len,
3476				"%d\t", freq);
3477
3478			len += scnprintf(buf + len, size - len,
3479				"%d\t%d\t%d\t%d\t%d\t%d\n",
3480				cal_pier->refPower,
3481				cal_pier->voltMeas,
3482				cal_pier->tempMeas,
3483				cal_pier->rxTempMeas ?
3484				N2DBM(cal_pier->rxNoisefloorCal) : 0,
3485				cal_pier->rxTempMeas ?
3486				N2DBM(cal_pier->rxNoisefloorPower) : 0,
3487				cal_pier->rxTempMeas);
3488		}
3489	}
3490
3491	return len;
3492}
3493
3494static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3495				       u8 *buf, u32 len, u32 size)
3496{
3497	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3498	struct ar9300_base_eep_hdr *pBase;
3499
3500	if (!dump_base_hdr) {
3501		len += scnprintf(buf + len, size - len,
3502				 "%20s :\n", "2GHz modal Header");
3503		len = ar9003_dump_modal_eeprom(buf, len, size,
3504						&eep->modalHeader2G);
3505
3506		len += scnprintf(buf + len, size - len, "Calibration data\n");
3507		len = ar9003_dump_cal_data(ah, buf, len, size, true);
3508
3509		len += scnprintf(buf + len, size - len,
3510				 "%20s :\n", "5GHz modal Header");
3511		len = ar9003_dump_modal_eeprom(buf, len, size,
3512						&eep->modalHeader5G);
3513
3514		len += scnprintf(buf + len, size - len, "Calibration data\n");
3515		len = ar9003_dump_cal_data(ah, buf, len, size, false);
3516
3517		goto out;
3518	}
3519
3520	pBase = &eep->baseEepHeader;
3521
3522	PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3523	PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3524	PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3525	PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3526	PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3527	PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3528				AR5416_OPFLAGS_11A));
3529	PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3530				AR5416_OPFLAGS_11G));
3531	PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3532					AR5416_OPFLAGS_N_2G_HT20));
3533	PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3534					AR5416_OPFLAGS_N_2G_HT40));
3535	PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3536					AR5416_OPFLAGS_N_5G_HT20));
3537	PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3538					AR5416_OPFLAGS_N_5G_HT40));
3539	PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc &
3540				AR5416_EEPMISC_BIG_ENDIAN));
3541	PR_EEP("RF Silent", pBase->rfSilent);
3542	PR_EEP("BT option", pBase->blueToothOptions);
3543	PR_EEP("Device Cap", pBase->deviceCap);
3544	PR_EEP("Device Type", pBase->deviceType);
3545	PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3546	PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3547	PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3548	PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3549	PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3550	PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3551	PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3552	PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3553	PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3554	PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3555	PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3556	PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3557	PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3558	PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3559	PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3560	PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3561	PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3562	PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3563	PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3564
3565	len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3566			 ah->eeprom.ar9300_eep.macAddr);
3567out:
3568	if (len > size)
3569		len = size;
3570
3571	return len;
3572}
3573#else
3574static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3575				       u8 *buf, u32 len, u32 size)
3576{
3577	return 0;
3578}
3579#endif
3580
3581/* XXX: review hardware docs */
3582static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3583{
3584	return ah->eeprom.ar9300_eep.eepromVersion;
3585}
3586
3587/* XXX: could be read from the eepromVersion, not sure yet */
3588static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3589{
3590	return 0;
3591}
3592
3593static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
3594							   bool is2ghz)
3595{
3596	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3597
3598	if (is2ghz)
3599		return &eep->modalHeader2G;
3600	else
3601		return &eep->modalHeader5G;
3602}
3603
3604static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3605{
3606	int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
3607
3608	if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
3609	    AR_SREV_9531(ah) || AR_SREV_9561(ah))
3610		REG_RMW_FIELD(ah, AR_CH0_TOP2(ah), AR_CH0_TOP2_XPABIASLVL, bias);
3611	else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))
3612		REG_RMW_FIELD(ah, AR_CH0_TOP(ah), AR_CH0_TOP_XPABIASLVL, bias);
3613	else {
3614		REG_RMW_FIELD(ah, AR_CH0_TOP(ah), AR_CH0_TOP_XPABIASLVL, bias);
3615		REG_RMW_FIELD(ah, AR_CH0_THERM(ah),
3616				AR_CH0_THERM_XPABIASLVL_MSB,
3617				bias >> 2);
3618		REG_RMW_FIELD(ah, AR_CH0_THERM(ah),
3619				AR_CH0_THERM_XPASHORT2GND, 1);
3620	}
3621}
3622
3623static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
3624{
3625	return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
3626}
3627
3628u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3629{
3630	return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
3631}
3632
3633u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3634{
3635	return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
3636}
3637
3638static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
3639					bool is2ghz)
3640{
3641	__le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
3642	return le16_to_cpu(val);
3643}
3644
3645static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3646{
3647	struct ath_common *common = ath9k_hw_common(ah);
3648	struct ath9k_hw_capabilities *pCap = &ah->caps;
3649	int chain;
3650	u32 regval, value, gpio;
3651	static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3652			AR_PHY_SWITCH_CHAIN_0,
3653			AR_PHY_SWITCH_CHAIN_1,
3654			AR_PHY_SWITCH_CHAIN_2,
3655	};
3656
3657	if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) {
3658		if (ah->config.xlna_gpio)
3659			gpio = ah->config.xlna_gpio;
3660		else
3661			gpio = AR9300_EXT_LNA_CTL_GPIO_AR9485;
3662
3663		ath9k_hw_gpio_request_out(ah, gpio, NULL,
3664					  AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED);
3665	}
3666
3667	value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3668
3669	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3670		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3671				AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3672	} else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
3673		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3674				AR_SWITCH_TABLE_COM_AR9550_ALL, value);
3675	} else
3676		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3677			      AR_SWITCH_TABLE_COM_ALL, value);
3678
3679
3680	/*
3681	 *   AR9462 defines new switch table for BT/WLAN,
3682	 *       here's new field name in XXX.ref for both 2G and 5G.
3683	 *   Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3684	 *   15:12   R/W     SWITCH_TABLE_COM_SPDT_WLAN_RX
3685	 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3686	 *
3687	 *   11:8     R/W     SWITCH_TABLE_COM_SPDT_WLAN_TX
3688	 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3689	 *
3690	 *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3691	 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3692	 */
3693	if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) {
3694		value = ar9003_switch_com_spdt_get(ah, is2ghz);
3695		REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3696				AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3697		REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3698	}
3699
3700	value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3701	if (AR_SREV_9485(ah) && common->bt_ant_diversity) {
3702		value &= ~AR_SWITCH_TABLE_COM2_ALL;
3703		value |= ah->config.ant_ctrl_comm2g_switch_enable;
3704
3705	}
3706	REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3707
3708	if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) {
3709		value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3710		REG_RMW_FIELD(ah, switch_chain_reg[0],
3711			      AR_SWITCH_TABLE_ALL, value);
3712	}
3713
3714	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3715		if ((ah->rxchainmask & BIT(chain)) ||
3716		    (ah->txchainmask & BIT(chain))) {
3717			value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3718							     is2ghz);
3719			REG_RMW_FIELD(ah, switch_chain_reg[chain],
3720				      AR_SWITCH_TABLE_ALL, value);
3721		}
3722	}
3723
3724	if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3725		value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3726		/*
3727		 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3728		 * are the fields present
3729		 */
3730		regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3731		regval &= (~AR_ANT_DIV_CTRL_ALL);
3732		regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3733		/* enable_lnadiv */
3734		regval &= (~AR_PHY_ANT_DIV_LNADIV);
3735		regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
3736
3737		if (AR_SREV_9485(ah) && common->bt_ant_diversity)
3738			regval |= AR_ANT_DIV_ENABLE;
3739
3740		if (AR_SREV_9565(ah)) {
3741			if (common->bt_ant_diversity) {
3742				regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);
3743
3744				REG_SET_BIT(ah, AR_PHY_RESTART,
3745					    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
3746
3747				/* Force WLAN LNA diversity ON */
3748				REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
3749					    AR_BTCOEX_WL_LNADIV_FORCE_ON);
3750			} else {
3751				regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S);
3752				regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S);
3753
3754				REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
3755					    (1 << AR_PHY_ANT_SW_RX_PROT_S));
3756
3757				/* Force WLAN LNA diversity OFF */
3758				REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
3759					    AR_BTCOEX_WL_LNADIV_FORCE_ON);
3760			}
3761		}
3762
3763		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3764
3765		/* enable fast_div */
3766		regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3767		regval &= (~AR_FAST_DIV_ENABLE);
3768		regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
3769
3770		if ((AR_SREV_9485(ah) || AR_SREV_9565(ah))
3771		    && common->bt_ant_diversity)
3772			regval |= AR_FAST_DIV_ENABLE;
3773
3774		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3775
3776		if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
3777			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3778			/*
3779			 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3780			 * main_tb, alt_tb
3781			 */
3782			regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
3783				     AR_PHY_ANT_DIV_ALT_LNACONF |
3784				     AR_PHY_ANT_DIV_ALT_GAINTB |
3785				     AR_PHY_ANT_DIV_MAIN_GAINTB));
3786			/* by default use LNA1 for the main antenna */
3787			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
3788				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
3789			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
3790				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
3791			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3792		}
3793	}
3794}
3795
3796static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3797{
3798	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3799	struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3800	int drive_strength;
3801	unsigned long reg;
3802
3803	drive_strength = pBase->miscConfiguration & BIT(0);
3804	if (!drive_strength)
3805		return;
3806
3807	reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3808	reg &= ~0x00ffffc0;
3809	reg |= 0x5 << 21;
3810	reg |= 0x5 << 18;
3811	reg |= 0x5 << 15;
3812	reg |= 0x5 << 12;
3813	reg |= 0x5 << 9;
3814	reg |= 0x5 << 6;
3815	REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3816
3817	reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3818	reg &= ~0xffffffe0;
3819	reg |= 0x5 << 29;
3820	reg |= 0x5 << 26;
3821	reg |= 0x5 << 23;
3822	reg |= 0x5 << 20;
3823	reg |= 0x5 << 17;
3824	reg |= 0x5 << 14;
3825	reg |= 0x5 << 11;
3826	reg |= 0x5 << 8;
3827	reg |= 0x5 << 5;
3828	REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3829
3830	reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3831	reg &= ~0xff800000;
3832	reg |= 0x5 << 29;
3833	reg |= 0x5 << 26;
3834	reg |= 0x5 << 23;
3835	REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3836}
3837
3838static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3839				     struct ath9k_channel *chan)
3840{
3841	int f[3], t[3];
3842	u16 value;
3843	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3844
3845	if (chain >= 0 && chain < 3) {
3846		if (IS_CHAN_2GHZ(chan))
3847			return eep->modalHeader2G.xatten1DB[chain];
3848		else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3849			t[0] = eep->base_ext2.xatten1DBLow[chain];
3850			f[0] = 5180;
3851			t[1] = eep->modalHeader5G.xatten1DB[chain];
3852			f[1] = 5500;
3853			t[2] = eep->base_ext2.xatten1DBHigh[chain];
3854			f[2] = 5785;
3855			value = ar9003_hw_power_interpolate((s32) chan->channel,
3856							    f, t, 3);
3857			return value;
3858		} else
3859			return eep->modalHeader5G.xatten1DB[chain];
3860	}
3861
3862	return 0;
3863}
3864
3865
3866static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3867					    struct ath9k_channel *chan)
3868{
3869	int f[3], t[3];
3870	u16 value;
3871	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3872
3873	if (chain >= 0 && chain < 3) {
3874		if (IS_CHAN_2GHZ(chan))
3875			return eep->modalHeader2G.xatten1Margin[chain];
3876		else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3877			t[0] = eep->base_ext2.xatten1MarginLow[chain];
3878			f[0] = 5180;
3879			t[1] = eep->modalHeader5G.xatten1Margin[chain];
3880			f[1] = 5500;
3881			t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3882			f[2] = 5785;
3883			value = ar9003_hw_power_interpolate((s32) chan->channel,
3884							    f, t, 3);
3885			return value;
3886		} else
3887			return eep->modalHeader5G.xatten1Margin[chain];
3888	}
3889
3890	return 0;
3891}
3892
3893static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3894{
3895	int i;
3896	u16 value;
3897	unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3898					  AR_PHY_EXT_ATTEN_CTL_1,
3899					  AR_PHY_EXT_ATTEN_CTL_2,
3900					 };
3901
3902	if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) {
3903		value = ar9003_hw_atten_chain_get(ah, 1, chan);
3904		REG_RMW_FIELD(ah, ext_atten_reg[0],
3905			      AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3906
3907		value = ar9003_hw_atten_chain_get_margin(ah, 1, chan);
3908		REG_RMW_FIELD(ah, ext_atten_reg[0],
3909			      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3910			      value);
3911	}
3912
3913	/* Test value. if 0 then attenuation is unused. Don't load anything. */
3914	for (i = 0; i < AR9300_MAX_CHAINS; i++) {
3915		if (ah->txchainmask & BIT(i)) {
3916			value = ar9003_hw_atten_chain_get(ah, i, chan);
3917			REG_RMW_FIELD(ah, ext_atten_reg[i],
3918				      AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3919
3920			if (AR_SREV_9485(ah) &&
3921			    (ar9003_hw_get_rx_gain_idx(ah) == 0) &&
3922			    ah->config.xatten_margin_cfg)
3923				value = 5;
3924			else
3925				value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3926
3927			if (ah->config.alt_mingainidx)
3928				REG_RMW_FIELD(ah, AR_PHY_EXT_ATTEN_CTL_0,
3929					      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3930					      value);
3931
3932			REG_RMW_FIELD(ah, ext_atten_reg[i],
3933				      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3934				      value);
3935		}
3936	}
3937}
3938
3939static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3940{
3941	int timeout = 100;
3942
3943	while (pmu_set != REG_READ(ah, pmu_reg)) {
3944		if (timeout-- == 0)
3945			return false;
3946		REG_WRITE(ah, pmu_reg, pmu_set);
3947		udelay(10);
3948	}
3949
3950	return true;
3951}
3952
3953void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3954{
3955	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3956	struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3957	u32 reg_val;
3958
3959	if (pBase->featureEnable & BIT(4)) {
3960		if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3961			int reg_pmu_set;
3962
3963			reg_pmu_set = REG_READ(ah, AR_PHY_PMU2(ah)) & ~AR_PHY_PMU2_PGM;
3964			REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
3965			if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))
3966				return;
3967
3968			if (AR_SREV_9330(ah)) {
3969				if (ah->is_clk_25mhz) {
3970					reg_pmu_set = (3 << 1) | (8 << 4) |
3971						      (3 << 8) | (1 << 14) |
3972						      (6 << 17) | (1 << 20) |
3973						      (3 << 24);
3974				} else {
3975					reg_pmu_set = (4 << 1)  | (7 << 4) |
3976						      (3 << 8)  | (1 << 14) |
3977						      (6 << 17) | (1 << 20) |
3978						      (3 << 24);
3979				}
3980			} else {
3981				reg_pmu_set = (5 << 1) | (7 << 4) |
3982					      (2 << 8) | (2 << 14) |
3983					      (6 << 17) | (1 << 20) |
3984					      (3 << 24) | (1 << 28);
3985			}
3986
3987			REG_WRITE(ah, AR_PHY_PMU1(ah), reg_pmu_set);
3988			if (!is_pmu_set(ah, AR_PHY_PMU1(ah), reg_pmu_set))
3989				return;
3990
3991			reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2(ah)) & ~0xFFC00000)
3992					| (4 << 26);
3993			REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
3994			if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))
3995				return;
3996
3997			reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2(ah)) & ~0x00200000)
3998					| (1 << 21);
3999			REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
4000			if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))
4001				return;
4002		} else if (AR_SREV_9462(ah) || AR_SREV_9565(ah) ||
4003			   AR_SREV_9561(ah)) {
4004			reg_val = le32_to_cpu(pBase->swreg);
4005			REG_WRITE(ah, AR_PHY_PMU1(ah), reg_val);
4006
4007			if (AR_SREV_9561(ah))
4008				REG_WRITE(ah, AR_PHY_PMU2(ah), 0x10200000);
4009		} else {
4010			/* Internal regulator is ON. Write swreg register. */
4011			reg_val = le32_to_cpu(pBase->swreg);
4012			REG_WRITE(ah, AR_RTC_REG_CONTROL1,
4013				  REG_READ(ah, AR_RTC_REG_CONTROL1) &
4014				  (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
4015			REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
4016			/* Set REG_CONTROL1.SWREG_PROGRAM */
4017			REG_WRITE(ah, AR_RTC_REG_CONTROL1,
4018				  REG_READ(ah,
4019					   AR_RTC_REG_CONTROL1) |
4020					   AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
4021		}
4022	} else {
4023		if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
4024			REG_RMW_FIELD(ah, AR_PHY_PMU2(ah), AR_PHY_PMU2_PGM, 0);
4025			while (REG_READ_FIELD(ah, AR_PHY_PMU2(ah),
4026						AR_PHY_PMU2_PGM))
4027				udelay(10);
4028
4029			REG_RMW_FIELD(ah, AR_PHY_PMU1(ah), AR_PHY_PMU1_PWD, 0x1);
4030			while (!REG_READ_FIELD(ah, AR_PHY_PMU1(ah),
4031						AR_PHY_PMU1_PWD))
4032				udelay(10);
4033			REG_RMW_FIELD(ah, AR_PHY_PMU2(ah), AR_PHY_PMU2_PGM, 0x1);
4034			while (!REG_READ_FIELD(ah, AR_PHY_PMU2(ah),
4035						AR_PHY_PMU2_PGM))
4036				udelay(10);
4037		} else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
4038			REG_RMW_FIELD(ah, AR_PHY_PMU1(ah), AR_PHY_PMU1_PWD, 0x1);
4039		else {
4040			reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK(ah)) |
4041				AR_RTC_FORCE_SWREG_PRD;
4042			REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), reg_val);
4043		}
4044	}
4045
4046}
4047
4048static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
4049{
4050	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4051	u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
4052
4053	if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
4054		return;
4055
4056	if (eep->baseEepHeader.featureEnable & 0x40) {
4057		tuning_caps_param &= 0x7f;
4058		REG_RMW_FIELD(ah, AR_CH0_XTAL(ah), AR_CH0_XTAL_CAPINDAC,
4059			      tuning_caps_param);
4060		REG_RMW_FIELD(ah, AR_CH0_XTAL(ah), AR_CH0_XTAL_CAPOUTDAC,
4061			      tuning_caps_param);
4062	}
4063}
4064
4065static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
4066{
4067	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4068	struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
4069	int quick_drop;
4070	s32 t[3], f[3] = {5180, 5500, 5785};
4071
4072	if (!(pBase->miscConfiguration & BIT(4)))
4073		return;
4074
4075	if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {
4076		if (freq < 4000) {
4077			quick_drop = eep->modalHeader2G.quick_drop;
4078		} else {
4079			t[0] = eep->base_ext1.quick_drop_low;
4080			t[1] = eep->modalHeader5G.quick_drop;
4081			t[2] = eep->base_ext1.quick_drop_high;
4082			quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
4083		}
4084		REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
4085	}
4086}
4087
4088static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
4089{
4090	u32 value;
4091
4092	value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
4093
4094	REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4095		      AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
4096	REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4097		      AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
4098}
4099
4100static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
4101{
4102	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4103	u8 xpa_ctl;
4104
4105	if (!(eep->baseEepHeader.featureEnable & 0x80))
4106		return;
4107
4108	if (!AR_SREV_9300(ah) &&
4109	    !AR_SREV_9340(ah) &&
4110	    !AR_SREV_9580(ah) &&
4111	    !AR_SREV_9531(ah) &&
4112	    !AR_SREV_9561(ah))
4113		return;
4114
4115	xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
4116	if (is2ghz)
4117		REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4118			      AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
4119	else
4120		REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4121			      AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
4122}
4123
4124static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
4125{
4126	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4127	u8 bias;
4128
4129	if (!(eep->baseEepHeader.miscConfiguration & 0x40))
4130		return;
4131
4132	if (!AR_SREV_9300(ah))
4133		return;
4134
4135	bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
4136	REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4137		      bias & 0x3);
4138	bias >>= 2;
4139	REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4140		      bias & 0x3);
4141	bias >>= 2;
4142	REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4143		      bias & 0x3);
4144}
4145
4146static int ar9003_hw_get_thermometer(struct ath_hw *ah)
4147{
4148	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4149	struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
4150	int thermometer =  (pBase->miscConfiguration >> 1) & 0x3;
4151
4152	return --thermometer;
4153}
4154
4155static void ar9003_hw_thermometer_apply(struct ath_hw *ah)
4156{
4157	struct ath9k_hw_capabilities *pCap = &ah->caps;
4158	int thermometer = ar9003_hw_get_thermometer(ah);
4159	u8 therm_on = (thermometer < 0) ? 0 : 1;
4160
4161	REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4162		      AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4163	if (pCap->chip_chainmask & BIT(1))
4164		REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4165			      AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4166	if (pCap->chip_chainmask & BIT(2))
4167		REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4168			      AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4169
4170	therm_on = thermometer == 0;
4171	REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4172		      AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4173	if (pCap->chip_chainmask & BIT(1)) {
4174		therm_on = thermometer == 1;
4175		REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4176			      AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4177	}
4178	if (pCap->chip_chainmask & BIT(2)) {
4179		therm_on = thermometer == 2;
4180		REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4181			      AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4182	}
4183}
4184
4185static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
4186{
4187	u32 data = 0, ko, kg;
4188
4189	if (!AR_SREV_9462_20_OR_LATER(ah))
4190		return;
4191
4192	ar9300_otp_read_word(ah, 1, &data);
4193	ko = data & 0xff;
4194	kg = (data >> 8) & 0xff;
4195	if (ko || kg) {
4196		REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4197			      AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET, ko);
4198		REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4199			      AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN,
4200			      kg + 256);
4201	}
4202}
4203
4204static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah,
4205					     bool is2ghz)
4206{
4207	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4208	const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = {
4209		AR_PHY_CCA_CTRL_0,
4210		AR_PHY_CCA_CTRL_1,
4211		AR_PHY_CCA_CTRL_2,
4212	};
4213	int chain;
4214	u32 val;
4215
4216	if (is2ghz) {
4217		if (!(eep->base_ext1.misc_enable & BIT(2)))
4218			return;
4219	} else {
4220		if (!(eep->base_ext1.misc_enable & BIT(3)))
4221			return;
4222	}
4223
4224	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
4225		if (!(ah->caps.tx_chainmask & BIT(chain)))
4226			continue;
4227
4228		val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain];
4229		REG_RMW_FIELD(ah, cca_ctrl[chain],
4230			      AR_PHY_EXT_CCA0_THRESH62_1, val);
4231	}
4232
4233}
4234
4235static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
4236					     struct ath9k_channel *chan)
4237{
4238	bool is2ghz = IS_CHAN_2GHZ(chan);
4239	ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
4240	ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
4241	ar9003_hw_ant_ctrl_apply(ah, is2ghz);
4242	ar9003_hw_drive_strength_apply(ah);
4243	ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
4244	ar9003_hw_atten_apply(ah, chan);
4245	ar9003_hw_quick_drop_apply(ah, chan->channel);
4246	if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9531(ah))
4247		ar9003_hw_internal_regulator_apply(ah);
4248	ar9003_hw_apply_tuning_caps(ah);
4249	ar9003_hw_apply_minccapwr_thresh(ah, is2ghz);
4250	ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
4251	ar9003_hw_thermometer_apply(ah);
4252	ar9003_hw_thermo_cal_apply(ah);
4253}
4254
4255static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
4256				      struct ath9k_channel *chan)
4257{
4258}
4259
4260/*
4261 * Returns the interpolated y value corresponding to the specified x value
4262 * from the np ordered pairs of data (px,py).
4263 * The pairs do not have to be in any order.
4264 * If the specified x value is less than any of the px,
4265 * the returned y value is equal to the py for the lowest px.
4266 * If the specified x value is greater than any of the px,
4267 * the returned y value is equal to the py for the highest px.
4268 */
4269static int ar9003_hw_power_interpolate(int32_t x,
4270				       int32_t *px, int32_t *py, u_int16_t np)
4271{
4272	int ip = 0;
4273	int lx = 0, ly = 0, lhave = 0;
4274	int hx = 0, hy = 0, hhave = 0;
4275	int dx = 0;
4276	int y = 0;
4277
4278	lhave = 0;
4279	hhave = 0;
4280
4281	/* identify best lower and higher x calibration measurement */
4282	for (ip = 0; ip < np; ip++) {
4283		dx = x - px[ip];
4284
4285		/* this measurement is higher than our desired x */
4286		if (dx <= 0) {
4287			if (!hhave || dx > (x - hx)) {
4288				/* new best higher x measurement */
4289				hx = px[ip];
4290				hy = py[ip];
4291				hhave = 1;
4292			}
4293		}
4294		/* this measurement is lower than our desired x */
4295		if (dx >= 0) {
4296			if (!lhave || dx < (x - lx)) {
4297				/* new best lower x measurement */
4298				lx = px[ip];
4299				ly = py[ip];
4300				lhave = 1;
4301			}
4302		}
4303	}
4304
4305	/* the low x is good */
4306	if (lhave) {
4307		/* so is the high x */
4308		if (hhave) {
4309			/* they're the same, so just pick one */
4310			if (hx == lx)
4311				y = ly;
4312			else	/* interpolate  */
4313				y = interpolate(x, lx, hx, ly, hy);
4314		} else		/* only low is good, use it */
4315			y = ly;
4316	} else if (hhave)	/* only high is good, use it */
4317		y = hy;
4318	else /* nothing is good,this should never happen unless np=0, ???? */
4319		y = -(1 << 30);
4320	return y;
4321}
4322
4323static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4324				       u16 rateIndex, u16 freq, bool is2GHz)
4325{
4326	u16 numPiers, i;
4327	s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4328	s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4329	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4330	struct cal_tgt_pow_legacy *pEepromTargetPwr;
4331	u8 *pFreqBin;
4332
4333	if (is2GHz) {
4334		numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4335		pEepromTargetPwr = eep->calTargetPower2G;
4336		pFreqBin = eep->calTarget_freqbin_2G;
4337	} else {
4338		numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4339		pEepromTargetPwr = eep->calTargetPower5G;
4340		pFreqBin = eep->calTarget_freqbin_5G;
4341	}
4342
4343	/*
4344	 * create array of channels and targetpower from
4345	 * targetpower piers stored on eeprom
4346	 */
4347	for (i = 0; i < numPiers; i++) {
4348		freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4349		targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4350	}
4351
4352	/* interpolate to get target power for given frequency */
4353	return (u8) ar9003_hw_power_interpolate((s32) freq,
4354						 freqArray,
4355						 targetPowerArray, numPiers);
4356}
4357
4358static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4359					    u16 rateIndex,
4360					    u16 freq, bool is2GHz)
4361{
4362	u16 numPiers, i;
4363	s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4364	s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4365	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4366	struct cal_tgt_pow_ht *pEepromTargetPwr;
4367	u8 *pFreqBin;
4368
4369	if (is2GHz) {
4370		numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4371		pEepromTargetPwr = eep->calTargetPower2GHT20;
4372		pFreqBin = eep->calTarget_freqbin_2GHT20;
4373	} else {
4374		numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4375		pEepromTargetPwr = eep->calTargetPower5GHT20;
4376		pFreqBin = eep->calTarget_freqbin_5GHT20;
4377	}
4378
4379	/*
4380	 * create array of channels and targetpower
4381	 * from targetpower piers stored on eeprom
4382	 */
4383	for (i = 0; i < numPiers; i++) {
4384		freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4385		targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4386	}
4387
4388	/* interpolate to get target power for given frequency */
4389	return (u8) ar9003_hw_power_interpolate((s32) freq,
4390						 freqArray,
4391						 targetPowerArray, numPiers);
4392}
4393
4394static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4395					    u16 rateIndex,
4396					    u16 freq, bool is2GHz)
4397{
4398	u16 numPiers, i;
4399	s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4400	s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4401	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4402	struct cal_tgt_pow_ht *pEepromTargetPwr;
4403	u8 *pFreqBin;
4404
4405	if (is2GHz) {
4406		numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4407		pEepromTargetPwr = eep->calTargetPower2GHT40;
4408		pFreqBin = eep->calTarget_freqbin_2GHT40;
4409	} else {
4410		numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4411		pEepromTargetPwr = eep->calTargetPower5GHT40;
4412		pFreqBin = eep->calTarget_freqbin_5GHT40;
4413	}
4414
4415	/*
4416	 * create array of channels and targetpower from
4417	 * targetpower piers stored on eeprom
4418	 */
4419	for (i = 0; i < numPiers; i++) {
4420		freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4421		targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4422	}
4423
4424	/* interpolate to get target power for given frequency */
4425	return (u8) ar9003_hw_power_interpolate((s32) freq,
4426						 freqArray,
4427						 targetPowerArray, numPiers);
4428}
4429
4430static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4431					   u16 rateIndex, u16 freq)
4432{
4433	u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4434	s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4435	s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4436	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4437	struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4438	u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4439
4440	/*
4441	 * create array of channels and targetpower from
4442	 * targetpower piers stored on eeprom
4443	 */
4444	for (i = 0; i < numPiers; i++) {
4445		freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
4446		targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4447	}
4448
4449	/* interpolate to get target power for given frequency */
4450	return (u8) ar9003_hw_power_interpolate((s32) freq,
4451						 freqArray,
4452						 targetPowerArray, numPiers);
4453}
4454
4455static void ar9003_hw_selfgen_tpc_txpower(struct ath_hw *ah,
4456					  struct ath9k_channel *chan,
4457					  u8 *pwr_array)
4458{
4459	u32 val;
4460
4461	/* target power values for self generated frames (ACK,RTS/CTS) */
4462	if (IS_CHAN_2GHZ(chan)) {
4463		val = SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) |
4464		      SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_CTS) |
4465		      SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT);
4466	} else {
4467		val = SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_ACK) |
4468		      SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_CTS) |
4469		      SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT);
4470	}
4471	REG_WRITE(ah, AR_TPC, val);
4472}
4473
4474/* Set tx power registers to array of values passed in */
4475int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4476{
4477#define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
4478	/* make sure forced gain is not set */
4479	REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4480
4481	/* Write the OFDM power per rate set */
4482
4483	/* 6 (LSB), 9, 12, 18 (MSB) */
4484	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4485		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4486		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4487		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4488		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4489
4490	/* 24 (LSB), 36, 48, 54 (MSB) */
4491	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4492		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4493		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4494		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4495		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4496
4497	/* Write the CCK power per rate set */
4498
4499	/* 1L (LSB), reserved, 2L, 2S (MSB) */
4500	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4501		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4502		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4503		  /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
4504		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4505
4506	/* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4507	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4508		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4509		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4510		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4511		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4512	    );
4513
4514        /* Write the power for duplicated frames - HT40 */
4515
4516        /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4517	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4518		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4519		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4520		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
4521		  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
4522	    );
4523
4524	/* Write the HT20 power per rate set */
4525
4526	/* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4527	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4528		  POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4529		  POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4530		  POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4531		  POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4532	    );
4533
4534	/* 6 (LSB), 7, 12, 13 (MSB) */
4535	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4536		  POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4537		  POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4538		  POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4539		  POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4540	    );
4541
4542	/* 14 (LSB), 15, 20, 21 */
4543	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4544		  POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4545		  POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4546		  POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4547		  POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4548	    );
4549
4550	/* Mixed HT20 and HT40 rates */
4551
4552	/* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4553	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4554		  POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4555		  POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4556		  POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4557		  POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4558	    );
4559
4560	/*
4561	 * Write the HT40 power per rate set
4562	 * correct PAR difference between HT40 and HT20/LEGACY
4563	 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4564	 */
4565	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4566		  POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4567		  POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4568		  POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4569		  POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4570	    );
4571
4572	/* 6 (LSB), 7, 12, 13 (MSB) */
4573	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4574		  POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4575		  POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4576		  POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4577		  POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4578	    );
4579
4580	/* 14 (LSB), 15, 20, 21 */
4581	REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4582		  POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4583		  POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4584		  POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4585		  POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4586	    );
4587
4588	return 0;
4589#undef POW_SM
4590}
4591
4592static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4593					       u8 *targetPowerValT2,
4594					       bool is2GHz)
4595{
4596	targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4597	    ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4598					 is2GHz);
4599	targetPowerValT2[ALL_TARGET_LEGACY_36] =
4600	    ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4601					 is2GHz);
4602	targetPowerValT2[ALL_TARGET_LEGACY_48] =
4603	    ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4604					 is2GHz);
4605	targetPowerValT2[ALL_TARGET_LEGACY_54] =
4606	    ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4607					 is2GHz);
4608}
4609
4610static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4611					    u8 *targetPowerValT2)
4612{
4613	targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4614	    ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4615					     freq);
4616	targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4617	    ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4618	targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4619	    ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4620	targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4621	    ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4622}
4623
4624static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4625					     u8 *targetPowerValT2, bool is2GHz)
4626{
4627	targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4628	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4629					      is2GHz);
4630	targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4631	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4632					      freq, is2GHz);
4633	targetPowerValT2[ALL_TARGET_HT20_4] =
4634	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4635					      is2GHz);
4636	targetPowerValT2[ALL_TARGET_HT20_5] =
4637	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4638					      is2GHz);
4639	targetPowerValT2[ALL_TARGET_HT20_6] =
4640	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4641					      is2GHz);
4642	targetPowerValT2[ALL_TARGET_HT20_7] =
4643	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4644					      is2GHz);
4645	targetPowerValT2[ALL_TARGET_HT20_12] =
4646	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4647					      is2GHz);
4648	targetPowerValT2[ALL_TARGET_HT20_13] =
4649	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4650					      is2GHz);
4651	targetPowerValT2[ALL_TARGET_HT20_14] =
4652	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4653					      is2GHz);
4654	targetPowerValT2[ALL_TARGET_HT20_15] =
4655	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4656					      is2GHz);
4657	targetPowerValT2[ALL_TARGET_HT20_20] =
4658	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4659					      is2GHz);
4660	targetPowerValT2[ALL_TARGET_HT20_21] =
4661	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4662					      is2GHz);
4663	targetPowerValT2[ALL_TARGET_HT20_22] =
4664	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4665					      is2GHz);
4666	targetPowerValT2[ALL_TARGET_HT20_23] =
4667	    ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4668					      is2GHz);
4669}
4670
4671static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4672						   u16 freq,
4673						   u8 *targetPowerValT2,
4674						   bool is2GHz)
4675{
4676	/* XXX: hard code for now, need to get from eeprom struct */
4677	u8 ht40PowerIncForPdadc = 0;
4678
4679	targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4680	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4681					      is2GHz) + ht40PowerIncForPdadc;
4682	targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4683	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4684					      freq,
4685					      is2GHz) + ht40PowerIncForPdadc;
4686	targetPowerValT2[ALL_TARGET_HT40_4] =
4687	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4688					      is2GHz) + ht40PowerIncForPdadc;
4689	targetPowerValT2[ALL_TARGET_HT40_5] =
4690	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4691					      is2GHz) + ht40PowerIncForPdadc;
4692	targetPowerValT2[ALL_TARGET_HT40_6] =
4693	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4694					      is2GHz) + ht40PowerIncForPdadc;
4695	targetPowerValT2[ALL_TARGET_HT40_7] =
4696	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4697					      is2GHz) + ht40PowerIncForPdadc;
4698	targetPowerValT2[ALL_TARGET_HT40_12] =
4699	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4700					      is2GHz) + ht40PowerIncForPdadc;
4701	targetPowerValT2[ALL_TARGET_HT40_13] =
4702	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4703					      is2GHz) + ht40PowerIncForPdadc;
4704	targetPowerValT2[ALL_TARGET_HT40_14] =
4705	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4706					      is2GHz) + ht40PowerIncForPdadc;
4707	targetPowerValT2[ALL_TARGET_HT40_15] =
4708	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4709					      is2GHz) + ht40PowerIncForPdadc;
4710	targetPowerValT2[ALL_TARGET_HT40_20] =
4711	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4712					      is2GHz) + ht40PowerIncForPdadc;
4713	targetPowerValT2[ALL_TARGET_HT40_21] =
4714	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4715					      is2GHz) + ht40PowerIncForPdadc;
4716	targetPowerValT2[ALL_TARGET_HT40_22] =
4717	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4718					      is2GHz) + ht40PowerIncForPdadc;
4719	targetPowerValT2[ALL_TARGET_HT40_23] =
4720	    ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4721					      is2GHz) + ht40PowerIncForPdadc;
4722}
4723
4724static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4725					      struct ath9k_channel *chan,
4726					      u8 *targetPowerValT2)
4727{
4728	bool is2GHz = IS_CHAN_2GHZ(chan);
4729	unsigned int i = 0;
4730	struct ath_common *common = ath9k_hw_common(ah);
4731	u16 freq = chan->channel;
4732
4733	if (is2GHz)
4734		ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4735
4736	ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4737	ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4738
4739	if (IS_CHAN_HT40(chan))
4740		ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4741						 is2GHz);
4742
4743	for (i = 0; i < ar9300RateSize; i++) {
4744		ath_dbg(common, REGULATORY, "TPC[%02d] 0x%08x\n",
4745			i, targetPowerValT2[i]);
4746	}
4747}
4748
4749static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4750				  bool is2ghz,
4751				  int ipier,
4752				  int ichain,
4753				  int *pfrequency,
4754				  int *pcorrection,
4755				  int *ptemperature, int *pvoltage,
4756				  int *pnf_cal, int *pnf_power)
4757{
4758	u8 *pCalPier;
4759	struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
 
4760	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4761	struct ath_common *common = ath9k_hw_common(ah);
4762
4763	if (ichain >= AR9300_MAX_CHAINS) {
4764		ath_dbg(common, EEPROM,
4765			"Invalid chain index, must be less than %d\n",
4766			AR9300_MAX_CHAINS);
4767		return -1;
4768	}
4769
4770	if (is2ghz) {
 
 
 
 
 
 
 
 
 
 
4771		if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4772			ath_dbg(common, EEPROM,
4773				"Invalid 2GHz cal pier index, must be less than %d\n",
4774				AR9300_NUM_2G_CAL_PIERS);
4775			return -1;
4776		}
4777
4778		pCalPier = &(eep->calFreqPier2G[ipier]);
4779		pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4780	} else {
4781		if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4782			ath_dbg(common, EEPROM,
4783				"Invalid 5GHz cal pier index, must be less than %d\n",
4784				AR9300_NUM_5G_CAL_PIERS);
4785			return -1;
4786		}
4787		pCalPier = &(eep->calFreqPier5G[ipier]);
4788		pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4789	}
4790
4791	*pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2ghz);
4792	*pcorrection = pCalPierStruct->refPower;
4793	*ptemperature = pCalPierStruct->tempMeas;
4794	*pvoltage = pCalPierStruct->voltMeas;
4795	*pnf_cal = pCalPierStruct->rxTempMeas ?
4796			N2DBM(pCalPierStruct->rxNoisefloorCal) : 0;
4797	*pnf_power = pCalPierStruct->rxTempMeas ?
4798			N2DBM(pCalPierStruct->rxNoisefloorPower) : 0;
4799
4800	return 0;
4801}
4802
4803static void ar9003_hw_power_control_override(struct ath_hw *ah,
4804					     int frequency,
4805					     int *correction,
4806					     int *voltage, int *temperature)
4807{
4808	int temp_slope = 0, temp_slope1 = 0, temp_slope2 = 0;
4809	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4810	int f[8], t[8], t1[3], t2[3], i;
4811
4812	REG_RMW(ah, AR_PHY_TPC_11_B0,
4813		(correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4814		AR_PHY_TPC_OLPC_GAIN_DELTA);
4815	if (ah->caps.tx_chainmask & BIT(1))
4816		REG_RMW(ah, AR_PHY_TPC_11_B1,
4817			(correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4818			AR_PHY_TPC_OLPC_GAIN_DELTA);
4819	if (ah->caps.tx_chainmask & BIT(2))
4820		REG_RMW(ah, AR_PHY_TPC_11_B2,
4821			(correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4822			AR_PHY_TPC_OLPC_GAIN_DELTA);
4823
4824	/* enable open loop power control on chip */
4825	REG_RMW(ah, AR_PHY_TPC_6_B0,
4826		(3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4827		AR_PHY_TPC_6_ERROR_EST_MODE);
4828	if (ah->caps.tx_chainmask & BIT(1))
4829		REG_RMW(ah, AR_PHY_TPC_6_B1,
4830			(3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4831			AR_PHY_TPC_6_ERROR_EST_MODE);
4832	if (ah->caps.tx_chainmask & BIT(2))
4833		REG_RMW(ah, AR_PHY_TPC_6_B2,
4834			(3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4835			AR_PHY_TPC_6_ERROR_EST_MODE);
4836
4837	/*
4838	 * enable temperature compensation
4839	 * Need to use register names
4840	 */
4841	if (frequency < 4000) {
4842		temp_slope = eep->modalHeader2G.tempSlope;
4843	} else {
4844		if (AR_SREV_9550(ah)) {
4845			t[0] = eep->base_ext1.tempslopextension[2];
4846			t1[0] = eep->base_ext1.tempslopextension[3];
4847			t2[0] = eep->base_ext1.tempslopextension[4];
4848			f[0] = 5180;
4849
4850			t[1] = eep->modalHeader5G.tempSlope;
4851			t1[1] = eep->base_ext1.tempslopextension[0];
4852			t2[1] = eep->base_ext1.tempslopextension[1];
4853			f[1] = 5500;
4854
4855			t[2] = eep->base_ext1.tempslopextension[5];
4856			t1[2] = eep->base_ext1.tempslopextension[6];
4857			t2[2] = eep->base_ext1.tempslopextension[7];
4858			f[2] = 5785;
4859
4860			temp_slope = ar9003_hw_power_interpolate(frequency,
4861								 f, t, 3);
4862			temp_slope1 = ar9003_hw_power_interpolate(frequency,
4863								   f, t1, 3);
4864			temp_slope2 = ar9003_hw_power_interpolate(frequency,
4865								   f, t2, 3);
4866
4867			goto tempslope;
4868		}
4869
4870		if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) {
4871			for (i = 0; i < 8; i++) {
4872				t[i] = eep->base_ext1.tempslopextension[i];
4873				f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0);
4874			}
4875			temp_slope = ar9003_hw_power_interpolate((s32) frequency,
4876								 f, t, 8);
4877		} else if (eep->base_ext2.tempSlopeLow != 0) {
4878			t[0] = eep->base_ext2.tempSlopeLow;
4879			f[0] = 5180;
4880			t[1] = eep->modalHeader5G.tempSlope;
4881			f[1] = 5500;
4882			t[2] = eep->base_ext2.tempSlopeHigh;
4883			f[2] = 5785;
4884			temp_slope = ar9003_hw_power_interpolate((s32) frequency,
4885								 f, t, 3);
4886		} else {
4887			temp_slope = eep->modalHeader5G.tempSlope;
4888		}
4889	}
4890
4891tempslope:
4892	if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
4893		u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4;
4894
4895		/*
4896		 * AR955x has tempSlope register for each chain.
4897		 * Check whether temp_compensation feature is enabled or not.
4898		 */
4899		if (eep->baseEepHeader.featureEnable & 0x1) {
4900			if (frequency < 4000) {
4901				if (txmask & BIT(0))
4902					REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4903						      AR_PHY_TPC_19_ALPHA_THERM,
4904						      eep->base_ext2.tempSlopeLow);
4905				if (txmask & BIT(1))
4906					REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4907						      AR_PHY_TPC_19_ALPHA_THERM,
4908						      temp_slope);
4909				if (txmask & BIT(2))
4910					REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4911						      AR_PHY_TPC_19_ALPHA_THERM,
4912						      eep->base_ext2.tempSlopeHigh);
4913			} else {
4914				if (txmask & BIT(0))
4915					REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4916						      AR_PHY_TPC_19_ALPHA_THERM,
4917						      temp_slope);
4918				if (txmask & BIT(1))
4919					REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4920						      AR_PHY_TPC_19_ALPHA_THERM,
4921						      temp_slope1);
4922				if (txmask & BIT(2))
4923					REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4924						      AR_PHY_TPC_19_ALPHA_THERM,
4925						      temp_slope2);
4926			}
4927		} else {
4928			/*
4929			 * If temp compensation is not enabled,
4930			 * set all registers to 0.
4931			 */
4932			if (txmask & BIT(0))
4933				REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4934					      AR_PHY_TPC_19_ALPHA_THERM, 0);
4935			if (txmask & BIT(1))
4936				REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4937					      AR_PHY_TPC_19_ALPHA_THERM, 0);
4938			if (txmask & BIT(2))
4939				REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4940					      AR_PHY_TPC_19_ALPHA_THERM, 0);
4941		}
4942	} else {
4943		REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4944			      AR_PHY_TPC_19_ALPHA_THERM, temp_slope);
4945	}
4946
4947	if (AR_SREV_9462_20_OR_LATER(ah))
4948		REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4949			      AR_PHY_TPC_19_B1_ALPHA_THERM, temp_slope);
4950
4951
4952	REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4953		      temperature[0]);
4954}
4955
4956/* Apply the recorded correction values. */
4957static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4958{
4959	int ichain, ipier, npier;
 
4960	int lfrequency[AR9300_MAX_CHAINS],
4961	    lcorrection[AR9300_MAX_CHAINS],
4962	    ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS],
4963	    lnf_cal[AR9300_MAX_CHAINS], lnf_pwr[AR9300_MAX_CHAINS];
4964	int hfrequency[AR9300_MAX_CHAINS],
4965	    hcorrection[AR9300_MAX_CHAINS],
4966	    htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS],
4967	    hnf_cal[AR9300_MAX_CHAINS], hnf_pwr[AR9300_MAX_CHAINS];
4968	int fdiff;
4969	int correction[AR9300_MAX_CHAINS],
4970	    voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS],
4971	    nf_cal[AR9300_MAX_CHAINS], nf_pwr[AR9300_MAX_CHAINS];
4972	int pfrequency, pcorrection, ptemperature, pvoltage,
4973	    pnf_cal, pnf_pwr;
4974	struct ath_common *common = ath9k_hw_common(ah);
4975	bool is2ghz = frequency < 4000;
4976
4977	if (is2ghz)
4978		npier = AR9300_NUM_2G_CAL_PIERS;
4979	else
4980		npier = AR9300_NUM_5G_CAL_PIERS;
 
 
4981
4982	for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4983		lfrequency[ichain] = 0;
4984		hfrequency[ichain] = 100000;
4985	}
4986	/* identify best lower and higher frequency calibration measurement */
4987	for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4988		for (ipier = 0; ipier < npier; ipier++) {
4989			if (!ar9003_hw_cal_pier_get(ah, is2ghz, ipier, ichain,
4990						    &pfrequency, &pcorrection,
4991						    &ptemperature, &pvoltage,
4992						    &pnf_cal, &pnf_pwr)) {
4993				fdiff = frequency - pfrequency;
4994
4995				/*
4996				 * this measurement is higher than
4997				 * our desired frequency
4998				 */
4999				if (fdiff <= 0) {
5000					if (hfrequency[ichain] <= 0 ||
5001					    hfrequency[ichain] >= 100000 ||
5002					    fdiff >
5003					    (frequency - hfrequency[ichain])) {
5004						/*
5005						 * new best higher
5006						 * frequency measurement
5007						 */
5008						hfrequency[ichain] = pfrequency;
5009						hcorrection[ichain] =
5010						    pcorrection;
5011						htemperature[ichain] =
5012						    ptemperature;
5013						hvoltage[ichain] = pvoltage;
5014						hnf_cal[ichain] = pnf_cal;
5015						hnf_pwr[ichain] = pnf_pwr;
5016					}
5017				}
5018				if (fdiff >= 0) {
5019					if (lfrequency[ichain] <= 0
5020					    || fdiff <
5021					    (frequency - lfrequency[ichain])) {
5022						/*
5023						 * new best lower
5024						 * frequency measurement
5025						 */
5026						lfrequency[ichain] = pfrequency;
5027						lcorrection[ichain] =
5028						    pcorrection;
5029						ltemperature[ichain] =
5030						    ptemperature;
5031						lvoltage[ichain] = pvoltage;
5032						lnf_cal[ichain] = pnf_cal;
5033						lnf_pwr[ichain] = pnf_pwr;
5034					}
5035				}
5036			}
5037		}
5038	}
5039
5040	/* interpolate  */
5041	for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
5042		ath_dbg(common, EEPROM,
5043			"ch=%d f=%d low=%d %d h=%d %d n=%d %d p=%d %d\n",
5044			ichain, frequency, lfrequency[ichain],
5045			lcorrection[ichain], hfrequency[ichain],
5046			hcorrection[ichain], lnf_cal[ichain],
5047			hnf_cal[ichain], lnf_pwr[ichain],
5048			hnf_pwr[ichain]);
5049		/* they're the same, so just pick one */
5050		if (hfrequency[ichain] == lfrequency[ichain]) {
5051			correction[ichain] = lcorrection[ichain];
5052			voltage[ichain] = lvoltage[ichain];
5053			temperature[ichain] = ltemperature[ichain];
5054			nf_cal[ichain] = lnf_cal[ichain];
5055			nf_pwr[ichain] = lnf_pwr[ichain];
5056		}
5057		/* the low frequency is good */
5058		else if (frequency - lfrequency[ichain] < 1000) {
5059			/* so is the high frequency, interpolate */
5060			if (hfrequency[ichain] - frequency < 1000) {
5061
5062				correction[ichain] = interpolate(frequency,
5063						lfrequency[ichain],
5064						hfrequency[ichain],
5065						lcorrection[ichain],
5066						hcorrection[ichain]);
5067
5068				temperature[ichain] = interpolate(frequency,
5069						lfrequency[ichain],
5070						hfrequency[ichain],
5071						ltemperature[ichain],
5072						htemperature[ichain]);
5073
5074				voltage[ichain] = interpolate(frequency,
5075						lfrequency[ichain],
5076						hfrequency[ichain],
5077						lvoltage[ichain],
5078						hvoltage[ichain]);
5079
5080				nf_cal[ichain] = interpolate(frequency,
5081						lfrequency[ichain],
5082						hfrequency[ichain],
5083						lnf_cal[ichain],
5084						hnf_cal[ichain]);
5085
5086				nf_pwr[ichain] = interpolate(frequency,
5087						lfrequency[ichain],
5088						hfrequency[ichain],
5089						lnf_pwr[ichain],
5090						hnf_pwr[ichain]);
5091			}
5092			/* only low is good, use it */
5093			else {
5094				correction[ichain] = lcorrection[ichain];
5095				temperature[ichain] = ltemperature[ichain];
5096				voltage[ichain] = lvoltage[ichain];
5097				nf_cal[ichain] = lnf_cal[ichain];
5098				nf_pwr[ichain] = lnf_pwr[ichain];
5099			}
5100		}
5101		/* only high is good, use it */
5102		else if (hfrequency[ichain] - frequency < 1000) {
5103			correction[ichain] = hcorrection[ichain];
5104			temperature[ichain] = htemperature[ichain];
5105			voltage[ichain] = hvoltage[ichain];
5106			nf_cal[ichain] = hnf_cal[ichain];
5107			nf_pwr[ichain] = hnf_pwr[ichain];
5108		} else {	/* nothing is good, presume 0???? */
5109			correction[ichain] = 0;
5110			temperature[ichain] = 0;
5111			voltage[ichain] = 0;
5112			nf_cal[ichain] = 0;
5113			nf_pwr[ichain] = 0;
5114		}
5115	}
5116
5117	ar9003_hw_power_control_override(ah, frequency, correction, voltage,
5118					 temperature);
5119
5120	ath_dbg(common, EEPROM,
5121		"for frequency=%d, calibration correction = %d %d %d\n",
5122		frequency, correction[0], correction[1], correction[2]);
5123
5124	/* Store calibrated noise floor values */
5125	for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++)
5126		if (is2ghz) {
5127			ah->nf_2g.cal[ichain] = nf_cal[ichain];
5128			ah->nf_2g.pwr[ichain] = nf_pwr[ichain];
5129		} else {
5130			ah->nf_5g.cal[ichain] = nf_cal[ichain];
5131			ah->nf_5g.pwr[ichain] = nf_pwr[ichain];
 
 
 
5132		}
5133
5134	return 0;
5135}
5136
5137static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
5138					   int idx,
5139					   int edge,
5140					   bool is2GHz)
5141{
5142	struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
5143	struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
5144
5145	if (is2GHz)
5146		return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
5147	else
5148		return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
5149}
5150
5151static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
5152					     int idx,
5153					     unsigned int edge,
5154					     u16 freq,
5155					     bool is2GHz)
5156{
5157	struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
5158	struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
5159
5160	u8 *ctl_freqbin = is2GHz ?
5161		&eep->ctl_freqbin_2G[idx][0] :
5162		&eep->ctl_freqbin_5G[idx][0];
5163
5164	if (is2GHz) {
5165		if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
5166		    CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
5167			return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
5168	} else {
5169		if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
5170		    CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
5171			return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
5172	}
5173
5174	return MAX_RATE_POWER;
5175}
5176
5177/*
5178 * Find the maximum conformance test limit for the given channel and CTL info
5179 */
5180static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
5181					u16 freq, int idx, bool is2GHz)
5182{
5183	u16 twiceMaxEdgePower = MAX_RATE_POWER;
5184	u8 *ctl_freqbin = is2GHz ?
5185		&eep->ctl_freqbin_2G[idx][0] :
5186		&eep->ctl_freqbin_5G[idx][0];
5187	u16 num_edges = is2GHz ?
5188		AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
5189	unsigned int edge;
5190
5191	/* Get the edge power */
5192	for (edge = 0;
5193	     (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
5194	     edge++) {
5195		/*
5196		 * If there's an exact channel match or an inband flag set
5197		 * on the lower channel use the given rdEdgePower
5198		 */
5199		if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
5200			twiceMaxEdgePower =
5201				ar9003_hw_get_direct_edge_power(eep, idx,
5202								edge, is2GHz);
5203			break;
5204		} else if ((edge > 0) &&
5205			   (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
5206						      is2GHz))) {
5207			twiceMaxEdgePower =
5208				ar9003_hw_get_indirect_edge_power(eep, idx,
5209								  edge, freq,
5210								  is2GHz);
5211			/*
5212			 * Leave loop - no more affecting edges possible in
5213			 * this monotonic increasing list
5214			 */
5215			break;
5216		}
5217	}
5218
5219	if (is2GHz && !twiceMaxEdgePower)
5220		twiceMaxEdgePower = 60;
5221
5222	return twiceMaxEdgePower;
5223}
5224
5225static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
5226					       struct ath9k_channel *chan,
5227					       u8 *pPwrArray, u16 cfgCtl,
5228					       u8 antenna_reduction,
5229					       u16 powerLimit)
5230{
5231	struct ath_common *common = ath9k_hw_common(ah);
5232	struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
5233	u16 twiceMaxEdgePower;
5234	int i;
5235	u16 scaledPower = 0, minCtlPower;
5236	static const u16 ctlModesFor11a[] = {
5237		CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
5238	};
5239	static const u16 ctlModesFor11g[] = {
5240		CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
5241		CTL_11G_EXT, CTL_2GHT40
5242	};
5243	u16 numCtlModes;
5244	const u16 *pCtlMode;
5245	u16 ctlMode, freq;
5246	struct chan_centers centers;
5247	u8 *ctlIndex;
5248	u8 ctlNum;
5249	u16 twiceMinEdgePower;
5250	bool is2ghz = IS_CHAN_2GHZ(chan);
5251
5252	ath9k_hw_get_channel_centers(ah, chan, &centers);
5253	scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
5254						antenna_reduction);
5255
5256	if (is2ghz) {
5257		/* Setup for CTL modes */
5258		/* CTL_11B, CTL_11G, CTL_2GHT20 */
5259		numCtlModes =
5260			ARRAY_SIZE(ctlModesFor11g) -
5261				   SUB_NUM_CTL_MODES_AT_2G_40;
5262		pCtlMode = ctlModesFor11g;
5263		if (IS_CHAN_HT40(chan))
5264			/* All 2G CTL's */
5265			numCtlModes = ARRAY_SIZE(ctlModesFor11g);
5266	} else {
5267		/* Setup for CTL modes */
5268		/* CTL_11A, CTL_5GHT20 */
5269		numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
5270					 SUB_NUM_CTL_MODES_AT_5G_40;
5271		pCtlMode = ctlModesFor11a;
5272		if (IS_CHAN_HT40(chan))
5273			/* All 5G CTL's */
5274			numCtlModes = ARRAY_SIZE(ctlModesFor11a);
5275	}
5276
5277	/*
5278	 * For MIMO, need to apply regulatory caps individually across
5279	 * dynamically running modes: CCK, OFDM, HT20, HT40
5280	 *
5281	 * The outer loop walks through each possible applicable runtime mode.
5282	 * The inner loop walks through each ctlIndex entry in EEPROM.
5283	 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
5284	 */
5285	for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
5286		bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
5287			(pCtlMode[ctlMode] == CTL_2GHT40);
5288		if (isHt40CtlMode)
5289			freq = centers.synth_center;
5290		else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
5291			freq = centers.ext_center;
5292		else
5293			freq = centers.ctl_center;
5294
5295		ath_dbg(common, REGULATORY,
5296			"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
5297			ctlMode, numCtlModes, isHt40CtlMode,
5298			(pCtlMode[ctlMode] & EXT_ADDITIVE));
5299
5300		/* walk through each CTL index stored in EEPROM */
5301		if (is2ghz) {
5302			ctlIndex = pEepData->ctlIndex_2G;
5303			ctlNum = AR9300_NUM_CTLS_2G;
5304		} else {
5305			ctlIndex = pEepData->ctlIndex_5G;
5306			ctlNum = AR9300_NUM_CTLS_5G;
5307		}
5308
5309		twiceMaxEdgePower = MAX_RATE_POWER;
5310		for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
5311			ath_dbg(common, REGULATORY,
5312				"LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
5313				i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
5314				chan->channel);
5315
5316			/*
5317			 * compare test group from regulatory
5318			 * channel list with test mode from pCtlMode
5319			 * list
5320			 */
5321			if ((((cfgCtl & ~CTL_MODE_M) |
5322			       (pCtlMode[ctlMode] & CTL_MODE_M)) ==
5323				ctlIndex[i]) ||
5324			    (((cfgCtl & ~CTL_MODE_M) |
5325			       (pCtlMode[ctlMode] & CTL_MODE_M)) ==
5326			     ((ctlIndex[i] & CTL_MODE_M) |
5327			       SD_NO_CTL))) {
5328				twiceMinEdgePower =
5329				  ar9003_hw_get_max_edge_power(pEepData,
5330							       freq, i,
5331							       is2ghz);
5332
5333				if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
5334					/*
5335					 * Find the minimum of all CTL
5336					 * edge powers that apply to
5337					 * this channel
5338					 */
5339					twiceMaxEdgePower =
5340						min(twiceMaxEdgePower,
5341						    twiceMinEdgePower);
5342				else {
5343					/* specific */
5344					twiceMaxEdgePower = twiceMinEdgePower;
5345					break;
5346				}
5347			}
5348		}
5349
5350		minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
5351
5352		ath_dbg(common, REGULATORY,
5353			"SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
5354			ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
5355			scaledPower, minCtlPower);
5356
5357		/* Apply ctl mode to correct target power set */
5358		switch (pCtlMode[ctlMode]) {
5359		case CTL_11B:
5360			for (i = ALL_TARGET_LEGACY_1L_5L;
5361			     i <= ALL_TARGET_LEGACY_11S; i++)
5362				pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5363						       minCtlPower);
5364			break;
5365		case CTL_11A:
5366		case CTL_11G:
5367			for (i = ALL_TARGET_LEGACY_6_24;
5368			     i <= ALL_TARGET_LEGACY_54; i++)
5369				pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5370						       minCtlPower);
5371			break;
5372		case CTL_5GHT20:
5373		case CTL_2GHT20:
5374			for (i = ALL_TARGET_HT20_0_8_16;
5375			     i <= ALL_TARGET_HT20_23; i++) {
5376				pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5377						       minCtlPower);
5378				if (ath9k_hw_mci_is_enabled(ah))
5379					pPwrArray[i] =
5380						(u8)min((u16)pPwrArray[i],
5381						ar9003_mci_get_max_txpower(ah,
5382							pCtlMode[ctlMode]));
5383			}
5384			break;
5385		case CTL_5GHT40:
5386		case CTL_2GHT40:
5387			for (i = ALL_TARGET_HT40_0_8_16;
5388			     i <= ALL_TARGET_HT40_23; i++) {
5389				pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5390						       minCtlPower);
5391				if (ath9k_hw_mci_is_enabled(ah))
5392					pPwrArray[i] =
5393						(u8)min((u16)pPwrArray[i],
5394						ar9003_mci_get_max_txpower(ah,
5395							pCtlMode[ctlMode]));
5396			}
5397			break;
5398		default:
5399			break;
5400		}
5401	} /* end ctl mode checking */
5402}
5403
5404static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
5405{
5406	u8 mod_idx = mcs_idx % 8;
5407
5408	if (mod_idx <= 3)
5409		return mod_idx ? (base_pwridx + 1) : base_pwridx;
5410	else
5411		return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
5412}
5413
5414static void ar9003_paprd_set_txpower(struct ath_hw *ah,
5415				     struct ath9k_channel *chan,
5416				     u8 *targetPowerValT2)
5417{
5418	int i;
5419
5420	if (!ar9003_is_paprd_enabled(ah))
5421		return;
5422
5423	if (IS_CHAN_HT40(chan))
5424		i = ALL_TARGET_HT40_7;
5425	else
5426		i = ALL_TARGET_HT20_7;
5427
5428	if (IS_CHAN_2GHZ(chan)) {
5429		if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) &&
5430		    !AR_SREV_9462(ah) && !AR_SREV_9565(ah)) {
5431			if (IS_CHAN_HT40(chan))
5432				i = ALL_TARGET_HT40_0_8_16;
5433			else
5434				i = ALL_TARGET_HT20_0_8_16;
5435		}
5436	}
5437
5438	ah->paprd_target_power = targetPowerValT2[i];
5439}
5440
5441static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5442					struct ath9k_channel *chan, u16 cfgCtl,
5443					u8 twiceAntennaReduction,
5444					u8 powerLimit, bool test)
5445{
5446	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5447	struct ath_common *common = ath9k_hw_common(ah);
 
 
5448	u8 targetPowerValT2[ar9300RateSize];
5449	u8 target_power_val_t2_eep[ar9300RateSize];
5450	u8 targetPowerValT2_tpc[ar9300RateSize];
5451	unsigned int i = 0, paprd_scale_factor = 0;
5452	u8 pwr_idx, min_pwridx = 0;
5453
5454	memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
5455
5456	/*
5457	 * Get target powers from EEPROM - our baseline for TX Power
5458	 */
5459	ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
5460
5461	if (ar9003_is_paprd_enabled(ah)) {
 
 
 
 
 
5462		ah->paprd_ratemask =
5463			ar9003_get_paprd_rate_mask_ht20(ah, IS_CHAN_2GHZ(chan)) &
5464			AR9300_PAPRD_RATE_MASK;
5465
5466		ah->paprd_ratemask_ht40 =
5467			ar9003_get_paprd_rate_mask_ht40(ah, IS_CHAN_2GHZ(chan)) &
5468			AR9300_PAPRD_RATE_MASK;
5469
5470		paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5471		min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5472						  ALL_TARGET_HT20_0_8_16;
5473
5474		if (!ah->paprd_table_write_done) {
5475			memcpy(target_power_val_t2_eep, targetPowerValT2,
5476			       sizeof(targetPowerValT2));
5477			for (i = 0; i < 24; i++) {
5478				pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5479				if (ah->paprd_ratemask & (1 << i)) {
5480					if (targetPowerValT2[pwr_idx] &&
5481					    targetPowerValT2[pwr_idx] ==
5482					    target_power_val_t2_eep[pwr_idx])
5483						targetPowerValT2[pwr_idx] -=
5484							paprd_scale_factor;
5485				}
5486			}
5487		}
5488		memcpy(target_power_val_t2_eep, targetPowerValT2,
5489		       sizeof(targetPowerValT2));
5490	}
5491
5492	ar9003_hw_set_power_per_rate_table(ah, chan,
5493					   targetPowerValT2, cfgCtl,
5494					   twiceAntennaReduction,
5495					   powerLimit);
5496
5497	memcpy(targetPowerValT2_tpc, targetPowerValT2,
5498	       sizeof(targetPowerValT2));
5499
5500	if (ar9003_is_paprd_enabled(ah)) {
5501		for (i = 0; i < ar9300RateSize; i++) {
5502			if ((ah->paprd_ratemask & (1 << i)) &&
5503			    (abs(targetPowerValT2[i] -
5504				target_power_val_t2_eep[i]) >
5505			    paprd_scale_factor)) {
5506				ah->paprd_ratemask &= ~(1 << i);
5507				ath_dbg(common, EEPROM,
5508					"paprd disabled for mcs %d\n", i);
5509			}
5510		}
5511	}
5512
5513	regulatory->max_power_level = 0;
5514	for (i = 0; i < ar9300RateSize; i++) {
5515		if (targetPowerValT2[i] > regulatory->max_power_level)
5516			regulatory->max_power_level = targetPowerValT2[i];
5517	}
5518
5519	ath9k_hw_update_regulatory_maxpower(ah);
5520
5521	if (test)
5522		return;
5523
5524	for (i = 0; i < ar9300RateSize; i++) {
5525		ath_dbg(common, REGULATORY, "TPC[%02d] 0x%08x\n",
5526			i, targetPowerValT2[i]);
5527	}
5528
5529	/* Write target power array to registers */
5530	ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5531	ar9003_hw_calibration_apply(ah, chan->channel);
5532	ar9003_paprd_set_txpower(ah, chan, targetPowerValT2);
5533
5534	ar9003_hw_selfgen_tpc_txpower(ah, chan, targetPowerValT2);
5535
5536	/* TPC initializations */
5537	if (ah->tpc_enabled) {
5538		u32 val;
5539
5540		ar9003_hw_init_rate_txpower(ah, targetPowerValT2_tpc, chan);
5541
5542		/* Enable TPC */
5543		REG_WRITE(ah, AR_PHY_PWRTX_MAX,
5544			  AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE);
5545		/* Disable per chain power reduction */
5546		val = REG_READ(ah, AR_PHY_POWER_TX_SUB);
5547		if (AR_SREV_9340(ah))
5548			REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
5549				  val & 0xFFFFFFC0);
5550		else
5551			REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
5552				  val & 0xFFFFF000);
5553	} else {
5554		/* Disable TPC */
5555		REG_WRITE(ah, AR_PHY_PWRTX_MAX, 0);
5556	}
5557}
5558
5559static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5560					    u16 i, bool is2GHz)
5561{
5562	return AR_NO_SPUR;
5563}
5564
5565s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5566{
5567	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5568
5569	return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5570}
5571
5572s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5573{
5574	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5575
5576	return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5577}
5578
5579u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
5580{
5581	return ar9003_modal_header(ah, is2ghz)->spurChans;
5582}
5583
5584u32 ar9003_get_paprd_rate_mask_ht20(struct ath_hw *ah, bool is2ghz)
5585{
5586	return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt20);
5587}
5588
5589u32 ar9003_get_paprd_rate_mask_ht40(struct ath_hw *ah, bool is2ghz)
5590{
5591	return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt40);
5592}
5593
5594unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5595					   struct ath9k_channel *chan)
5596{
5597	bool is2ghz = IS_CHAN_2GHZ(chan);
5598
5599	if (is2ghz)
5600		return MS(ar9003_get_paprd_rate_mask_ht20(ah, is2ghz),
5601			  AR9300_PAPRD_SCALE_1);
5602	else {
5603		if (chan->channel >= 5700)
5604			return MS(ar9003_get_paprd_rate_mask_ht20(ah, is2ghz),
5605				  AR9300_PAPRD_SCALE_1);
5606		else if (chan->channel >= 5400)
5607			return MS(ar9003_get_paprd_rate_mask_ht40(ah, is2ghz),
5608				  AR9300_PAPRD_SCALE_2);
5609		else
5610			return MS(ar9003_get_paprd_rate_mask_ht40(ah, is2ghz),
5611				  AR9300_PAPRD_SCALE_1);
5612	}
5613}
5614
5615static u8 ar9003_get_eepmisc(struct ath_hw *ah)
5616{
5617	return ah->eeprom.ar9300_eep.baseEepHeader.opCapFlags.eepMisc;
5618}
5619
5620const struct eeprom_ops eep_ar9300_ops = {
5621	.check_eeprom = ath9k_hw_ar9300_check_eeprom,
5622	.get_eeprom = ath9k_hw_ar9300_get_eeprom,
5623	.fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5624	.dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5625	.get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5626	.get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5627	.set_board_values = ath9k_hw_ar9300_set_board_values,
5628	.set_addac = ath9k_hw_ar9300_set_addac,
5629	.set_txpower = ath9k_hw_ar9300_set_txpower,
5630	.get_spur_channel = ath9k_hw_ar9300_get_spur_channel,
5631	.get_eepmisc = ar9003_get_eepmisc
5632};