Loading...
Note: File does not exist in v4.17.
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2021 Linaro Ltd.
5 */
6
7#include <linux/log2.h>
8
9#include "../gsi.h"
10#include "../ipa_data.h"
11#include "../ipa_endpoint.h"
12#include "../ipa_mem.h"
13
14/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.5.1 */
15enum ipa_resource_type {
16 /* Source resource types; first must have value 0 */
17 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
18 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
19 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
20 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
21 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
22
23 /* Destination resource types; first must have value 0 */
24 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
25 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
26};
27
28/* Resource groups used for an SoC having IPA v3.5.1 */
29enum ipa_rsrc_group_id {
30 /* Source resource group identifiers */
31 IPA_RSRC_GROUP_SRC_LWA_DL = 0,
32 IPA_RSRC_GROUP_SRC_UL_DL,
33 IPA_RSRC_GROUP_SRC_MHI_DMA,
34 IPA_RSRC_GROUP_SRC_UC_RX_Q,
35 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
36
37 /* Destination resource group identifiers */
38 IPA_RSRC_GROUP_DST_LWA_DL = 0,
39 IPA_RSRC_GROUP_DST_UL_DL_DPL,
40 IPA_RSRC_GROUP_DST_UNUSED_2,
41 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
42};
43
44/* QSB configuration data for an SoC having IPA v3.5.1 */
45static const struct ipa_qsb_data ipa_qsb_data[] = {
46 [IPA_QSB_MASTER_DDR] = {
47 .max_writes = 8,
48 .max_reads = 8,
49 },
50 [IPA_QSB_MASTER_PCIE] = {
51 .max_writes = 4,
52 .max_reads = 12,
53 },
54};
55
56/* Endpoint datdata for an SoC having IPA v3.5.1 */
57static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
58 [IPA_ENDPOINT_AP_COMMAND_TX] = {
59 .ee_id = GSI_EE_AP,
60 .channel_id = 4,
61 .endpoint_id = 5,
62 .toward_ipa = true,
63 .channel = {
64 .tre_count = 512,
65 .event_count = 256,
66 .tlv_count = 20,
67 },
68 .endpoint = {
69 .config = {
70 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
71 .dma_mode = true,
72 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
73 .tx = {
74 .seq_type = IPA_SEQ_DMA,
75 },
76 },
77 },
78 },
79 [IPA_ENDPOINT_AP_LAN_RX] = {
80 .ee_id = GSI_EE_AP,
81 .channel_id = 5,
82 .endpoint_id = 9,
83 .toward_ipa = false,
84 .channel = {
85 .tre_count = 256,
86 .event_count = 256,
87 .tlv_count = 8,
88 },
89 .endpoint = {
90 .config = {
91 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
92 .aggregation = true,
93 .status_enable = true,
94 .rx = {
95 .buffer_size = 8192,
96 .pad_align = ilog2(sizeof(u32)),
97 .aggr_time_limit = 500,
98 },
99 },
100 },
101 },
102 [IPA_ENDPOINT_AP_MODEM_TX] = {
103 .ee_id = GSI_EE_AP,
104 .channel_id = 3,
105 .endpoint_id = 2,
106 .toward_ipa = true,
107 .channel = {
108 .tre_count = 512,
109 .event_count = 512,
110 .tlv_count = 16,
111 },
112 .endpoint = {
113 .filter_support = true,
114 .config = {
115 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
116 .checksum = true,
117 .qmap = true,
118 .status_enable = true,
119 .tx = {
120 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
121 .seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
122 .status_endpoint =
123 IPA_ENDPOINT_MODEM_AP_RX,
124 },
125 },
126 },
127 },
128 [IPA_ENDPOINT_AP_MODEM_RX] = {
129 .ee_id = GSI_EE_AP,
130 .channel_id = 6,
131 .endpoint_id = 10,
132 .toward_ipa = false,
133 .channel = {
134 .tre_count = 256,
135 .event_count = 256,
136 .tlv_count = 8,
137 },
138 .endpoint = {
139 .config = {
140 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
141 .checksum = true,
142 .qmap = true,
143 .aggregation = true,
144 .rx = {
145 .buffer_size = 8192,
146 .aggr_time_limit = 500,
147 .aggr_close_eof = true,
148 },
149 },
150 },
151 },
152 [IPA_ENDPOINT_MODEM_LAN_TX] = {
153 .ee_id = GSI_EE_MODEM,
154 .channel_id = 0,
155 .endpoint_id = 3,
156 .toward_ipa = true,
157 .endpoint = {
158 .filter_support = true,
159 },
160 },
161 [IPA_ENDPOINT_MODEM_AP_TX] = {
162 .ee_id = GSI_EE_MODEM,
163 .channel_id = 4,
164 .endpoint_id = 6,
165 .toward_ipa = true,
166 .endpoint = {
167 .filter_support = true,
168 },
169 },
170 [IPA_ENDPOINT_MODEM_AP_RX] = {
171 .ee_id = GSI_EE_MODEM,
172 .channel_id = 2,
173 .endpoint_id = 12,
174 .toward_ipa = false,
175 },
176};
177
178/* Source resource configuration data for an SoC having IPA v3.5.1 */
179static const struct ipa_resource ipa_resource_src[] = {
180 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
181 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
182 .min = 1, .max = 63,
183 },
184 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
185 .min = 1, .max = 63,
186 },
187 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
188 .min = 1, .max = 63,
189 },
190 },
191 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
192 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
193 .min = 10, .max = 10,
194 },
195 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
196 .min = 10, .max = 10,
197 },
198 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
199 .min = 8, .max = 8,
200 },
201 },
202 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
203 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
204 .min = 12, .max = 12,
205 },
206 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
207 .min = 14, .max = 14,
208 },
209 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
210 .min = 8, .max = 8,
211 },
212 },
213 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
214 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
215 .min = 0, .max = 63,
216 },
217 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
218 .min = 0, .max = 63,
219 },
220 .limits[IPA_RSRC_GROUP_SRC_MHI_DMA] = {
221 .min = 0, .max = 63,
222 },
223 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
224 .min = 0, .max = 63,
225 },
226 },
227 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
228 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
229 .min = 14, .max = 14,
230 },
231 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
232 .min = 20, .max = 20,
233 },
234 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
235 .min = 14, .max = 14,
236 },
237 },
238};
239
240/* Destination resource configuration data for an SoC having IPA v3.5.1 */
241static const struct ipa_resource ipa_resource_dst[] = {
242 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
243 .limits[IPA_RSRC_GROUP_DST_LWA_DL] = {
244 .min = 4, .max = 4,
245 },
246 .limits[1] = {
247 .min = 4, .max = 4,
248 },
249 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
250 .min = 3, .max = 3,
251 }
252 },
253 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
254 .limits[IPA_RSRC_GROUP_DST_LWA_DL] = {
255 .min = 2, .max = 63,
256 },
257 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
258 .min = 1, .max = 63,
259 },
260 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
261 .min = 1, .max = 2,
262 }
263 },
264};
265
266/* Resource configuration data for an SoC having IPA v3.5.1 */
267static const struct ipa_resource_data ipa_resource_data = {
268 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
269 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
270 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
271 .resource_src = ipa_resource_src,
272 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
273 .resource_dst = ipa_resource_dst,
274};
275
276/* IPA-resident memory region data for an SoC having IPA v3.5.1 */
277static const struct ipa_mem ipa_mem_local_data[] = {
278 {
279 .id = IPA_MEM_UC_SHARED,
280 .offset = 0x0000,
281 .size = 0x0080,
282 .canary_count = 0,
283 },
284 {
285 .id = IPA_MEM_UC_INFO,
286 .offset = 0x0080,
287 .size = 0x0200,
288 .canary_count = 0,
289 },
290 {
291 .id = IPA_MEM_V4_FILTER_HASHED,
292 .offset = 0x0288,
293 .size = 0x0078,
294 .canary_count = 2,
295 },
296 {
297 .id = IPA_MEM_V4_FILTER,
298 .offset = 0x0308,
299 .size = 0x0078,
300 .canary_count = 2,
301 },
302 {
303 .id = IPA_MEM_V6_FILTER_HASHED,
304 .offset = 0x0388,
305 .size = 0x0078,
306 .canary_count = 2,
307 },
308 {
309 .id = IPA_MEM_V6_FILTER,
310 .offset = 0x0408,
311 .size = 0x0078,
312 .canary_count = 2,
313 },
314 {
315 .id = IPA_MEM_V4_ROUTE_HASHED,
316 .offset = 0x0488,
317 .size = 0x0078,
318 .canary_count = 2,
319 },
320 {
321 .id = IPA_MEM_V4_ROUTE,
322 .offset = 0x0508,
323 .size = 0x0078,
324 .canary_count = 2,
325 },
326 {
327 .id = IPA_MEM_V6_ROUTE_HASHED,
328 .offset = 0x0588,
329 .size = 0x0078,
330 .canary_count = 2,
331 },
332 {
333 .id = IPA_MEM_V6_ROUTE,
334 .offset = 0x0608,
335 .size = 0x0078,
336 .canary_count = 2,
337 },
338 {
339 .id = IPA_MEM_MODEM_HEADER,
340 .offset = 0x0688,
341 .size = 0x0140,
342 .canary_count = 2,
343 },
344 {
345 .id = IPA_MEM_MODEM_PROC_CTX,
346 .offset = 0x07d0,
347 .size = 0x0200,
348 .canary_count = 2,
349 },
350 {
351 .id = IPA_MEM_AP_PROC_CTX,
352 .offset = 0x09d0,
353 .size = 0x0200,
354 .canary_count = 0,
355 },
356 {
357 .id = IPA_MEM_MODEM,
358 .offset = 0x0bd8,
359 .size = 0x1024,
360 .canary_count = 0,
361 },
362 {
363 .id = IPA_MEM_UC_EVENT_RING,
364 .offset = 0x1c00,
365 .size = 0x0400,
366 .canary_count = 1,
367 },
368};
369
370/* Memory configuration data for an SoC having IPA v3.5.1 */
371static const struct ipa_mem_data ipa_mem_data = {
372 .local_count = ARRAY_SIZE(ipa_mem_local_data),
373 .local = ipa_mem_local_data,
374 .imem_addr = 0x146bd000,
375 .imem_size = 0x00002000,
376 .smem_id = 497,
377 .smem_size = 0x00002000,
378};
379
380/* Interconnect bandwidths are in 1000 byte/second units */
381static const struct ipa_interconnect_data ipa_interconnect_data[] = {
382 {
383 .name = "memory",
384 .peak_bandwidth = 600000, /* 600 MBps */
385 .average_bandwidth = 80000, /* 80 MBps */
386 },
387 /* Average bandwidth is unused for the next two interconnects */
388 {
389 .name = "imem",
390 .peak_bandwidth = 350000, /* 350 MBps */
391 .average_bandwidth = 0, /* unused */
392 },
393 {
394 .name = "config",
395 .peak_bandwidth = 40000, /* 40 MBps */
396 .average_bandwidth = 0, /* unused */
397 },
398};
399
400/* Clock and interconnect configuration data for an SoC having IPA v3.5.1 */
401static const struct ipa_power_data ipa_power_data = {
402 .core_clock_rate = 75 * 1000 * 1000, /* Hz */
403 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
404 .interconnect_data = ipa_interconnect_data,
405};
406
407/* Configuration data for an SoC having IPA v3.5.1 */
408const struct ipa_data ipa_data_v3_5_1 = {
409 .version = IPA_VERSION_3_5_1,
410 .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY) |
411 BIT(BCR_TX_NOT_USING_BRESP) |
412 BIT(BCR_SUSPEND_L2_IRQ) |
413 BIT(BCR_HOLB_DROP_L2_IRQ) |
414 BIT(BCR_DUAL_TX),
415 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
416 .qsb_data = ipa_qsb_data,
417 .modem_route_count = 8,
418 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
419 .endpoint_data = ipa_gsi_endpoint_data,
420 .resource_data = &ipa_resource_data,
421 .mem_data = &ipa_mem_data,
422 .power_data = &ipa_power_data,
423};