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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
4 *
5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
6 */
7
8#include <linux/clk.h>
9#include <linux/io.h>
10#include <linux/iopoll.h>
11#include <linux/mdio-mux.h>
12#include <linux/mfd/syscon.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_mdio.h>
16#include <linux/of_net.h>
17#include <linux/of_platform.h>
18#include <linux/phy.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/regulator/consumer.h>
22#include <linux/regmap.h>
23#include <linux/stmmac.h>
24
25#include "stmmac.h"
26#include "stmmac_platform.h"
27
28/* General notes on dwmac-sun8i:
29 * Locking: no locking is necessary in this file because all necessary locking
30 * is done in the "stmmac files"
31 */
32
33/* struct emac_variant - Describe dwmac-sun8i hardware variant
34 * @default_syscon_value: The default value of the EMAC register in syscon
35 * This value is used for disabling properly EMAC
36 * and used as a good starting value in case of the
37 * boot process(uboot) leave some stuff.
38 * @syscon_field reg_field for the syscon's gmac register
39 * @soc_has_internal_phy: Does the MAC embed an internal PHY
40 * @support_mii: Does the MAC handle MII
41 * @support_rmii: Does the MAC handle RMII
42 * @support_rgmii: Does the MAC handle RGMII
43 *
44 * @rx_delay_max: Maximum raw value for RX delay chain
45 * @tx_delay_max: Maximum raw value for TX delay chain
46 * These two also indicate the bitmask for
47 * the RX and TX delay chain registers. A
48 * value of zero indicates this is not supported.
49 */
50struct emac_variant {
51 u32 default_syscon_value;
52 const struct reg_field *syscon_field;
53 bool soc_has_internal_phy;
54 bool support_mii;
55 bool support_rmii;
56 bool support_rgmii;
57 u8 rx_delay_max;
58 u8 tx_delay_max;
59};
60
61/* struct sunxi_priv_data - hold all sunxi private data
62 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
63 * @regulator: reference to the optional regulator
64 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
65 * @variant: reference to the current board variant
66 * @regmap: regmap for using the syscon
67 * @internal_phy_powered: Does the internal PHY is enabled
68 * @use_internal_phy: Is the internal PHY selected for use
69 * @mux_handle: Internal pointer used by mdio-mux lib
70 */
71struct sunxi_priv_data {
72 struct clk *ephy_clk;
73 struct regulator *regulator;
74 struct reset_control *rst_ephy;
75 const struct emac_variant *variant;
76 struct regmap_field *regmap_field;
77 bool internal_phy_powered;
78 bool use_internal_phy;
79 void *mux_handle;
80};
81
82/* EMAC clock register @ 0x30 in the "system control" address range */
83static const struct reg_field sun8i_syscon_reg_field = {
84 .reg = 0x30,
85 .lsb = 0,
86 .msb = 31,
87};
88
89/* EMAC clock register @ 0x164 in the CCU address range */
90static const struct reg_field sun8i_ccu_reg_field = {
91 .reg = 0x164,
92 .lsb = 0,
93 .msb = 31,
94};
95
96static const struct emac_variant emac_variant_h3 = {
97 .default_syscon_value = 0x58000,
98 .syscon_field = &sun8i_syscon_reg_field,
99 .soc_has_internal_phy = true,
100 .support_mii = true,
101 .support_rmii = true,
102 .support_rgmii = true,
103 .rx_delay_max = 31,
104 .tx_delay_max = 7,
105};
106
107static const struct emac_variant emac_variant_v3s = {
108 .default_syscon_value = 0x38000,
109 .syscon_field = &sun8i_syscon_reg_field,
110 .soc_has_internal_phy = true,
111 .support_mii = true
112};
113
114static const struct emac_variant emac_variant_a83t = {
115 .default_syscon_value = 0,
116 .syscon_field = &sun8i_syscon_reg_field,
117 .soc_has_internal_phy = false,
118 .support_mii = true,
119 .support_rgmii = true,
120 .rx_delay_max = 31,
121 .tx_delay_max = 7,
122};
123
124static const struct emac_variant emac_variant_r40 = {
125 .default_syscon_value = 0,
126 .syscon_field = &sun8i_ccu_reg_field,
127 .support_mii = true,
128 .support_rgmii = true,
129 .rx_delay_max = 7,
130};
131
132static const struct emac_variant emac_variant_a64 = {
133 .default_syscon_value = 0,
134 .syscon_field = &sun8i_syscon_reg_field,
135 .soc_has_internal_phy = false,
136 .support_mii = true,
137 .support_rmii = true,
138 .support_rgmii = true,
139 .rx_delay_max = 31,
140 .tx_delay_max = 7,
141};
142
143static const struct emac_variant emac_variant_h6 = {
144 .default_syscon_value = 0x50000,
145 .syscon_field = &sun8i_syscon_reg_field,
146 /* The "Internal PHY" of H6 is not on the die. It's on the
147 * co-packaged AC200 chip instead.
148 */
149 .soc_has_internal_phy = false,
150 .support_mii = true,
151 .support_rmii = true,
152 .support_rgmii = true,
153 .rx_delay_max = 31,
154 .tx_delay_max = 7,
155};
156
157#define EMAC_BASIC_CTL0 0x00
158#define EMAC_BASIC_CTL1 0x04
159#define EMAC_INT_STA 0x08
160#define EMAC_INT_EN 0x0C
161#define EMAC_TX_CTL0 0x10
162#define EMAC_TX_CTL1 0x14
163#define EMAC_TX_FLOW_CTL 0x1C
164#define EMAC_TX_DESC_LIST 0x20
165#define EMAC_RX_CTL0 0x24
166#define EMAC_RX_CTL1 0x28
167#define EMAC_RX_DESC_LIST 0x34
168#define EMAC_RX_FRM_FLT 0x38
169#define EMAC_MDIO_CMD 0x48
170#define EMAC_MDIO_DATA 0x4C
171#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
172#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
173#define EMAC_TX_DMA_STA 0xB0
174#define EMAC_TX_CUR_DESC 0xB4
175#define EMAC_TX_CUR_BUF 0xB8
176#define EMAC_RX_DMA_STA 0xC0
177#define EMAC_RX_CUR_DESC 0xC4
178#define EMAC_RX_CUR_BUF 0xC8
179
180/* Use in EMAC_BASIC_CTL0 */
181#define EMAC_DUPLEX_FULL BIT(0)
182#define EMAC_LOOPBACK BIT(1)
183#define EMAC_SPEED_1000 0
184#define EMAC_SPEED_100 (0x03 << 2)
185#define EMAC_SPEED_10 (0x02 << 2)
186
187/* Use in EMAC_BASIC_CTL1 */
188#define EMAC_BURSTLEN_SHIFT 24
189
190/* Used in EMAC_RX_FRM_FLT */
191#define EMAC_FRM_FLT_RXALL BIT(0)
192#define EMAC_FRM_FLT_CTL BIT(13)
193#define EMAC_FRM_FLT_MULTICAST BIT(16)
194
195/* Used in RX_CTL1*/
196#define EMAC_RX_MD BIT(1)
197#define EMAC_RX_TH_MASK GENMASK(5, 4)
198#define EMAC_RX_TH_32 0
199#define EMAC_RX_TH_64 (0x1 << 4)
200#define EMAC_RX_TH_96 (0x2 << 4)
201#define EMAC_RX_TH_128 (0x3 << 4)
202#define EMAC_RX_DMA_EN BIT(30)
203#define EMAC_RX_DMA_START BIT(31)
204
205/* Used in TX_CTL1*/
206#define EMAC_TX_MD BIT(1)
207#define EMAC_TX_NEXT_FRM BIT(2)
208#define EMAC_TX_TH_MASK GENMASK(10, 8)
209#define EMAC_TX_TH_64 0
210#define EMAC_TX_TH_128 (0x1 << 8)
211#define EMAC_TX_TH_192 (0x2 << 8)
212#define EMAC_TX_TH_256 (0x3 << 8)
213#define EMAC_TX_DMA_EN BIT(30)
214#define EMAC_TX_DMA_START BIT(31)
215
216/* Used in RX_CTL0 */
217#define EMAC_RX_RECEIVER_EN BIT(31)
218#define EMAC_RX_DO_CRC BIT(27)
219#define EMAC_RX_FLOW_CTL_EN BIT(16)
220
221/* Used in TX_CTL0 */
222#define EMAC_TX_TRANSMITTER_EN BIT(31)
223
224/* Used in EMAC_TX_FLOW_CTL */
225#define EMAC_TX_FLOW_CTL_EN BIT(0)
226
227/* Used in EMAC_INT_STA */
228#define EMAC_TX_INT BIT(0)
229#define EMAC_TX_DMA_STOP_INT BIT(1)
230#define EMAC_TX_BUF_UA_INT BIT(2)
231#define EMAC_TX_TIMEOUT_INT BIT(3)
232#define EMAC_TX_UNDERFLOW_INT BIT(4)
233#define EMAC_TX_EARLY_INT BIT(5)
234#define EMAC_RX_INT BIT(8)
235#define EMAC_RX_BUF_UA_INT BIT(9)
236#define EMAC_RX_DMA_STOP_INT BIT(10)
237#define EMAC_RX_TIMEOUT_INT BIT(11)
238#define EMAC_RX_OVERFLOW_INT BIT(12)
239#define EMAC_RX_EARLY_INT BIT(13)
240#define EMAC_RGMII_STA_INT BIT(16)
241
242#define EMAC_INT_MSK_COMMON EMAC_RGMII_STA_INT
243#define EMAC_INT_MSK_TX (EMAC_TX_INT | \
244 EMAC_TX_DMA_STOP_INT | \
245 EMAC_TX_BUF_UA_INT | \
246 EMAC_TX_TIMEOUT_INT | \
247 EMAC_TX_UNDERFLOW_INT | \
248 EMAC_TX_EARLY_INT |\
249 EMAC_INT_MSK_COMMON)
250#define EMAC_INT_MSK_RX (EMAC_RX_INT | \
251 EMAC_RX_BUF_UA_INT | \
252 EMAC_RX_DMA_STOP_INT | \
253 EMAC_RX_TIMEOUT_INT | \
254 EMAC_RX_OVERFLOW_INT | \
255 EMAC_RX_EARLY_INT | \
256 EMAC_INT_MSK_COMMON)
257
258#define MAC_ADDR_TYPE_DST BIT(31)
259
260/* H3 specific bits for EPHY */
261#define H3_EPHY_ADDR_SHIFT 20
262#define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */
263#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
264#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
265#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
266#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
267#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1
268#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2
269
270/* H3/A64 specific bits */
271#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
272
273/* Generic system control EMAC_CLK bits */
274#define SYSCON_ETXDC_SHIFT 10
275#define SYSCON_ERXDC_SHIFT 5
276/* EMAC PHY Interface Type */
277#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
278#define SYSCON_ETCS_MASK GENMASK(1, 0)
279#define SYSCON_ETCS_MII 0x0
280#define SYSCON_ETCS_EXT_GMII 0x1
281#define SYSCON_ETCS_INT_GMII 0x2
282
283/* sun8i_dwmac_dma_reset() - reset the EMAC
284 * Called from stmmac via stmmac_dma_ops->reset
285 */
286static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
287{
288 writel(0, ioaddr + EMAC_RX_CTL1);
289 writel(0, ioaddr + EMAC_TX_CTL1);
290 writel(0, ioaddr + EMAC_RX_FRM_FLT);
291 writel(0, ioaddr + EMAC_RX_DESC_LIST);
292 writel(0, ioaddr + EMAC_TX_DESC_LIST);
293 writel(0, ioaddr + EMAC_INT_EN);
294 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
295 return 0;
296}
297
298/* sun8i_dwmac_dma_init() - initialize the EMAC
299 * Called from stmmac via stmmac_dma_ops->init
300 */
301static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
302 struct stmmac_dma_cfg *dma_cfg, int atds)
303{
304 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
305 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
306}
307
308static void sun8i_dwmac_dma_init_rx(struct stmmac_priv *priv,
309 void __iomem *ioaddr,
310 struct stmmac_dma_cfg *dma_cfg,
311 dma_addr_t dma_rx_phy, u32 chan)
312{
313 /* Write RX descriptors address */
314 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);
315}
316
317static void sun8i_dwmac_dma_init_tx(struct stmmac_priv *priv,
318 void __iomem *ioaddr,
319 struct stmmac_dma_cfg *dma_cfg,
320 dma_addr_t dma_tx_phy, u32 chan)
321{
322 /* Write TX descriptors address */
323 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST);
324}
325
326/* sun8i_dwmac_dump_regs() - Dump EMAC address space
327 * Called from stmmac_dma_ops->dump_regs
328 * Used for ethtool
329 */
330static void sun8i_dwmac_dump_regs(struct stmmac_priv *priv,
331 void __iomem *ioaddr, u32 *reg_space)
332{
333 int i;
334
335 for (i = 0; i < 0xC8; i += 4) {
336 if (i == 0x32 || i == 0x3C)
337 continue;
338 reg_space[i / 4] = readl(ioaddr + i);
339 }
340}
341
342/* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
343 * Called from stmmac_ops->dump_regs
344 * Used for ethtool
345 */
346static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
347 u32 *reg_space)
348{
349 int i;
350 void __iomem *ioaddr = hw->pcsr;
351
352 for (i = 0; i < 0xC8; i += 4) {
353 if (i == 0x32 || i == 0x3C)
354 continue;
355 reg_space[i / 4] = readl(ioaddr + i);
356 }
357}
358
359static void sun8i_dwmac_enable_dma_irq(struct stmmac_priv *priv,
360 void __iomem *ioaddr, u32 chan,
361 bool rx, bool tx)
362{
363 u32 value = readl(ioaddr + EMAC_INT_EN);
364
365 if (rx)
366 value |= EMAC_RX_INT;
367 if (tx)
368 value |= EMAC_TX_INT;
369
370 writel(value, ioaddr + EMAC_INT_EN);
371}
372
373static void sun8i_dwmac_disable_dma_irq(struct stmmac_priv *priv,
374 void __iomem *ioaddr, u32 chan,
375 bool rx, bool tx)
376{
377 u32 value = readl(ioaddr + EMAC_INT_EN);
378
379 if (rx)
380 value &= ~EMAC_RX_INT;
381 if (tx)
382 value &= ~EMAC_TX_INT;
383
384 writel(value, ioaddr + EMAC_INT_EN);
385}
386
387static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,
388 void __iomem *ioaddr, u32 chan)
389{
390 u32 v;
391
392 v = readl(ioaddr + EMAC_TX_CTL1);
393 v |= EMAC_TX_DMA_START;
394 v |= EMAC_TX_DMA_EN;
395 writel(v, ioaddr + EMAC_TX_CTL1);
396}
397
398static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
399{
400 u32 v;
401
402 v = readl(ioaddr + EMAC_TX_CTL1);
403 v |= EMAC_TX_DMA_START;
404 v |= EMAC_TX_DMA_EN;
405 writel(v, ioaddr + EMAC_TX_CTL1);
406}
407
408static void sun8i_dwmac_dma_stop_tx(struct stmmac_priv *priv,
409 void __iomem *ioaddr, u32 chan)
410{
411 u32 v;
412
413 v = readl(ioaddr + EMAC_TX_CTL1);
414 v &= ~EMAC_TX_DMA_EN;
415 writel(v, ioaddr + EMAC_TX_CTL1);
416}
417
418static void sun8i_dwmac_dma_start_rx(struct stmmac_priv *priv,
419 void __iomem *ioaddr, u32 chan)
420{
421 u32 v;
422
423 v = readl(ioaddr + EMAC_RX_CTL1);
424 v |= EMAC_RX_DMA_START;
425 v |= EMAC_RX_DMA_EN;
426 writel(v, ioaddr + EMAC_RX_CTL1);
427}
428
429static void sun8i_dwmac_dma_stop_rx(struct stmmac_priv *priv,
430 void __iomem *ioaddr, u32 chan)
431{
432 u32 v;
433
434 v = readl(ioaddr + EMAC_RX_CTL1);
435 v &= ~EMAC_RX_DMA_EN;
436 writel(v, ioaddr + EMAC_RX_CTL1);
437}
438
439static int sun8i_dwmac_dma_interrupt(struct stmmac_priv *priv,
440 void __iomem *ioaddr,
441 struct stmmac_extra_stats *x, u32 chan,
442 u32 dir)
443{
444 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats);
445 int ret = 0;
446 u32 v;
447
448 v = readl(ioaddr + EMAC_INT_STA);
449
450 if (dir == DMA_DIR_RX)
451 v &= EMAC_INT_MSK_RX;
452 else if (dir == DMA_DIR_TX)
453 v &= EMAC_INT_MSK_TX;
454
455 if (v & EMAC_TX_INT) {
456 ret |= handle_tx;
457 u64_stats_update_begin(&stats->syncp);
458 u64_stats_inc(&stats->tx_normal_irq_n[chan]);
459 u64_stats_update_end(&stats->syncp);
460 }
461
462 if (v & EMAC_TX_DMA_STOP_INT)
463 x->tx_process_stopped_irq++;
464
465 if (v & EMAC_TX_BUF_UA_INT)
466 x->tx_process_stopped_irq++;
467
468 if (v & EMAC_TX_TIMEOUT_INT)
469 ret |= tx_hard_error;
470
471 if (v & EMAC_TX_UNDERFLOW_INT) {
472 ret |= tx_hard_error;
473 x->tx_undeflow_irq++;
474 }
475
476 if (v & EMAC_TX_EARLY_INT)
477 x->tx_early_irq++;
478
479 if (v & EMAC_RX_INT) {
480 ret |= handle_rx;
481 u64_stats_update_begin(&stats->syncp);
482 u64_stats_inc(&stats->rx_normal_irq_n[chan]);
483 u64_stats_update_end(&stats->syncp);
484 }
485
486 if (v & EMAC_RX_BUF_UA_INT)
487 x->rx_buf_unav_irq++;
488
489 if (v & EMAC_RX_DMA_STOP_INT)
490 x->rx_process_stopped_irq++;
491
492 if (v & EMAC_RX_TIMEOUT_INT)
493 ret |= tx_hard_error;
494
495 if (v & EMAC_RX_OVERFLOW_INT) {
496 ret |= tx_hard_error;
497 x->rx_overflow_irq++;
498 }
499
500 if (v & EMAC_RX_EARLY_INT)
501 x->rx_early_irq++;
502
503 if (v & EMAC_RGMII_STA_INT)
504 x->irq_rgmii_n++;
505
506 writel(v, ioaddr + EMAC_INT_STA);
507
508 return ret;
509}
510
511static void sun8i_dwmac_dma_operation_mode_rx(struct stmmac_priv *priv,
512 void __iomem *ioaddr, int mode,
513 u32 channel, int fifosz, u8 qmode)
514{
515 u32 v;
516
517 v = readl(ioaddr + EMAC_RX_CTL1);
518 if (mode == SF_DMA_MODE) {
519 v |= EMAC_RX_MD;
520 } else {
521 v &= ~EMAC_RX_MD;
522 v &= ~EMAC_RX_TH_MASK;
523 if (mode < 32)
524 v |= EMAC_RX_TH_32;
525 else if (mode < 64)
526 v |= EMAC_RX_TH_64;
527 else if (mode < 96)
528 v |= EMAC_RX_TH_96;
529 else if (mode < 128)
530 v |= EMAC_RX_TH_128;
531 }
532 writel(v, ioaddr + EMAC_RX_CTL1);
533}
534
535static void sun8i_dwmac_dma_operation_mode_tx(struct stmmac_priv *priv,
536 void __iomem *ioaddr, int mode,
537 u32 channel, int fifosz, u8 qmode)
538{
539 u32 v;
540
541 v = readl(ioaddr + EMAC_TX_CTL1);
542 if (mode == SF_DMA_MODE) {
543 v |= EMAC_TX_MD;
544 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
545 * comment is
546 * "Operating on second frame increase the performance
547 * especially when transmit store-and-forward is used."
548 */
549 v |= EMAC_TX_NEXT_FRM;
550 } else {
551 v &= ~EMAC_TX_MD;
552 v &= ~EMAC_TX_TH_MASK;
553 if (mode < 64)
554 v |= EMAC_TX_TH_64;
555 else if (mode < 128)
556 v |= EMAC_TX_TH_128;
557 else if (mode < 192)
558 v |= EMAC_TX_TH_192;
559 else if (mode < 256)
560 v |= EMAC_TX_TH_256;
561 }
562 writel(v, ioaddr + EMAC_TX_CTL1);
563}
564
565static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
566 .reset = sun8i_dwmac_dma_reset,
567 .init = sun8i_dwmac_dma_init,
568 .init_rx_chan = sun8i_dwmac_dma_init_rx,
569 .init_tx_chan = sun8i_dwmac_dma_init_tx,
570 .dump_regs = sun8i_dwmac_dump_regs,
571 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx,
572 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx,
573 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
574 .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
575 .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
576 .start_tx = sun8i_dwmac_dma_start_tx,
577 .stop_tx = sun8i_dwmac_dma_stop_tx,
578 .start_rx = sun8i_dwmac_dma_start_rx,
579 .stop_rx = sun8i_dwmac_dma_stop_rx,
580 .dma_interrupt = sun8i_dwmac_dma_interrupt,
581};
582
583static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv);
584
585static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
586{
587 struct net_device *ndev = platform_get_drvdata(pdev);
588 struct sunxi_priv_data *gmac = priv;
589 int ret;
590
591 if (gmac->regulator) {
592 ret = regulator_enable(gmac->regulator);
593 if (ret) {
594 dev_err(&pdev->dev, "Fail to enable regulator\n");
595 return ret;
596 }
597 }
598
599 if (gmac->use_internal_phy) {
600 ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev));
601 if (ret)
602 goto err_disable_regulator;
603 }
604
605 return 0;
606
607err_disable_regulator:
608 if (gmac->regulator)
609 regulator_disable(gmac->regulator);
610
611 return ret;
612}
613
614static void sun8i_dwmac_core_init(struct mac_device_info *hw,
615 struct net_device *dev)
616{
617 void __iomem *ioaddr = hw->pcsr;
618 u32 v;
619
620 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
621 writel(v, ioaddr + EMAC_BASIC_CTL1);
622}
623
624static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
625{
626 u32 t, r;
627
628 t = readl(ioaddr + EMAC_TX_CTL0);
629 r = readl(ioaddr + EMAC_RX_CTL0);
630 if (enable) {
631 t |= EMAC_TX_TRANSMITTER_EN;
632 r |= EMAC_RX_RECEIVER_EN;
633 } else {
634 t &= ~EMAC_TX_TRANSMITTER_EN;
635 r &= ~EMAC_RX_RECEIVER_EN;
636 }
637 writel(t, ioaddr + EMAC_TX_CTL0);
638 writel(r, ioaddr + EMAC_RX_CTL0);
639}
640
641/* Set MAC address at slot reg_n
642 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
643 * If addr is NULL, clear the slot
644 */
645static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
646 const unsigned char *addr,
647 unsigned int reg_n)
648{
649 void __iomem *ioaddr = hw->pcsr;
650 u32 v;
651
652 if (!addr) {
653 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
654 return;
655 }
656
657 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
658 EMAC_MACADDR_LO(reg_n));
659 if (reg_n > 0) {
660 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
661 v |= MAC_ADDR_TYPE_DST;
662 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
663 }
664}
665
666static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
667 unsigned char *addr,
668 unsigned int reg_n)
669{
670 void __iomem *ioaddr = hw->pcsr;
671
672 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
673 EMAC_MACADDR_LO(reg_n));
674}
675
676/* caution this function must return non 0 to work */
677static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
678{
679 void __iomem *ioaddr = hw->pcsr;
680 u32 v;
681
682 v = readl(ioaddr + EMAC_RX_CTL0);
683 v |= EMAC_RX_DO_CRC;
684 writel(v, ioaddr + EMAC_RX_CTL0);
685
686 return 1;
687}
688
689static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
690 struct net_device *dev)
691{
692 void __iomem *ioaddr = hw->pcsr;
693 u32 v;
694 int i = 1;
695 struct netdev_hw_addr *ha;
696 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
697
698 v = EMAC_FRM_FLT_CTL;
699
700 if (dev->flags & IFF_PROMISC) {
701 v = EMAC_FRM_FLT_RXALL;
702 } else if (dev->flags & IFF_ALLMULTI) {
703 v |= EMAC_FRM_FLT_MULTICAST;
704 } else if (macaddrs <= hw->unicast_filter_entries) {
705 if (!netdev_mc_empty(dev)) {
706 netdev_for_each_mc_addr(ha, dev) {
707 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
708 i++;
709 }
710 }
711 if (!netdev_uc_empty(dev)) {
712 netdev_for_each_uc_addr(ha, dev) {
713 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
714 i++;
715 }
716 }
717 } else {
718 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL))
719 netdev_info(dev, "Too many address, switching to promiscuous\n");
720 v = EMAC_FRM_FLT_RXALL;
721 }
722
723 /* Disable unused address filter slots */
724 while (i < hw->unicast_filter_entries)
725 sun8i_dwmac_set_umac_addr(hw, NULL, i++);
726
727 writel(v, ioaddr + EMAC_RX_FRM_FLT);
728}
729
730static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
731 unsigned int duplex, unsigned int fc,
732 unsigned int pause_time, u32 tx_cnt)
733{
734 void __iomem *ioaddr = hw->pcsr;
735 u32 v;
736
737 v = readl(ioaddr + EMAC_RX_CTL0);
738 if (fc == FLOW_AUTO)
739 v |= EMAC_RX_FLOW_CTL_EN;
740 else
741 v &= ~EMAC_RX_FLOW_CTL_EN;
742 writel(v, ioaddr + EMAC_RX_CTL0);
743
744 v = readl(ioaddr + EMAC_TX_FLOW_CTL);
745 if (fc == FLOW_AUTO)
746 v |= EMAC_TX_FLOW_CTL_EN;
747 else
748 v &= ~EMAC_TX_FLOW_CTL_EN;
749 writel(v, ioaddr + EMAC_TX_FLOW_CTL);
750}
751
752static int sun8i_dwmac_reset(struct stmmac_priv *priv)
753{
754 u32 v;
755 int err;
756
757 v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
758 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
759
760 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
761 * need more if no cable plugged. 100ms seems OK
762 */
763 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
764 !(v & 0x01), 100, 100000);
765
766 if (err) {
767 dev_err(priv->device, "EMAC reset timeout\n");
768 return err;
769 }
770 return 0;
771}
772
773/* Search in mdio-mux node for internal PHY node and get its clk/reset */
774static int get_ephy_nodes(struct stmmac_priv *priv)
775{
776 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
777 struct device_node *mdio_mux, *iphynode;
778 struct device_node *mdio_internal;
779 int ret;
780
781 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
782 if (!mdio_mux) {
783 dev_err(priv->device, "Cannot get mdio-mux node\n");
784 return -ENODEV;
785 }
786
787 mdio_internal = of_get_compatible_child(mdio_mux,
788 "allwinner,sun8i-h3-mdio-internal");
789 of_node_put(mdio_mux);
790 if (!mdio_internal) {
791 dev_err(priv->device, "Cannot get internal_mdio node\n");
792 return -ENODEV;
793 }
794
795 /* Seek for internal PHY */
796 for_each_child_of_node(mdio_internal, iphynode) {
797 gmac->ephy_clk = of_clk_get(iphynode, 0);
798 if (IS_ERR(gmac->ephy_clk))
799 continue;
800 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
801 if (IS_ERR(gmac->rst_ephy)) {
802 ret = PTR_ERR(gmac->rst_ephy);
803 if (ret == -EPROBE_DEFER) {
804 of_node_put(iphynode);
805 of_node_put(mdio_internal);
806 return ret;
807 }
808 continue;
809 }
810 dev_info(priv->device, "Found internal PHY node\n");
811 of_node_put(iphynode);
812 of_node_put(mdio_internal);
813 return 0;
814 }
815
816 of_node_put(mdio_internal);
817 return -ENODEV;
818}
819
820static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
821{
822 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
823 int ret;
824
825 if (gmac->internal_phy_powered) {
826 dev_warn(priv->device, "Internal PHY already powered\n");
827 return 0;
828 }
829
830 dev_info(priv->device, "Powering internal PHY\n");
831 ret = clk_prepare_enable(gmac->ephy_clk);
832 if (ret) {
833 dev_err(priv->device, "Cannot enable internal PHY\n");
834 return ret;
835 }
836
837 /* Make sure the EPHY is properly reseted, as U-Boot may leave
838 * it at deasserted state, and thus it may fail to reset EMAC.
839 *
840 * This assumes the driver has exclusive access to the EPHY reset.
841 */
842 ret = reset_control_reset(gmac->rst_ephy);
843 if (ret) {
844 dev_err(priv->device, "Cannot reset internal PHY\n");
845 clk_disable_unprepare(gmac->ephy_clk);
846 return ret;
847 }
848
849 gmac->internal_phy_powered = true;
850
851 return 0;
852}
853
854static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
855{
856 if (!gmac->internal_phy_powered)
857 return;
858
859 clk_disable_unprepare(gmac->ephy_clk);
860 reset_control_assert(gmac->rst_ephy);
861 gmac->internal_phy_powered = false;
862}
863
864/* MDIO multiplexing switch function
865 * This function is called by the mdio-mux layer when it thinks the mdio bus
866 * multiplexer needs to switch.
867 * 'current_child' is the current value of the mux register
868 * 'desired_child' is the value of the 'reg' property of the target child MDIO
869 * node.
870 * The first time this function is called, current_child == -1.
871 * If current_child == desired_child, then the mux is already set to the
872 * correct bus.
873 */
874static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
875 void *data)
876{
877 struct stmmac_priv *priv = data;
878 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
879 u32 reg, val;
880 int ret = 0;
881
882 if (current_child ^ desired_child) {
883 regmap_field_read(gmac->regmap_field, ®);
884 switch (desired_child) {
885 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
886 dev_info(priv->device, "Switch mux to internal PHY");
887 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
888 gmac->use_internal_phy = true;
889 break;
890 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
891 dev_info(priv->device, "Switch mux to external PHY");
892 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
893 gmac->use_internal_phy = false;
894 break;
895 default:
896 dev_err(priv->device, "Invalid child ID %x\n",
897 desired_child);
898 return -EINVAL;
899 }
900 regmap_field_write(gmac->regmap_field, val);
901 if (gmac->use_internal_phy) {
902 ret = sun8i_dwmac_power_internal_phy(priv);
903 if (ret)
904 return ret;
905 } else {
906 sun8i_dwmac_unpower_internal_phy(gmac);
907 }
908 /* After changing syscon value, the MAC need reset or it will
909 * use the last value (and so the last PHY set).
910 */
911 ret = sun8i_dwmac_reset(priv);
912 }
913 return ret;
914}
915
916static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
917{
918 int ret;
919 struct device_node *mdio_mux;
920 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
921
922 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
923 if (!mdio_mux)
924 return -ENODEV;
925
926 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
927 &gmac->mux_handle, priv, priv->mii);
928 of_node_put(mdio_mux);
929 return ret;
930}
931
932static int sun8i_dwmac_set_syscon(struct device *dev,
933 struct plat_stmmacenet_data *plat)
934{
935 struct sunxi_priv_data *gmac = plat->bsp_priv;
936 struct device_node *node = dev->of_node;
937 int ret;
938 u32 reg, val;
939
940 ret = regmap_field_read(gmac->regmap_field, &val);
941 if (ret) {
942 dev_err(dev, "Fail to read from regmap field.\n");
943 return ret;
944 }
945
946 reg = gmac->variant->default_syscon_value;
947 if (reg != val)
948 dev_warn(dev,
949 "Current syscon value is not the default %x (expect %x)\n",
950 val, reg);
951
952 if (gmac->variant->soc_has_internal_phy) {
953 if (of_property_read_bool(node, "allwinner,leds-active-low"))
954 reg |= H3_EPHY_LED_POL;
955 else
956 reg &= ~H3_EPHY_LED_POL;
957
958 /* Force EPHY xtal frequency to 24MHz. */
959 reg |= H3_EPHY_CLK_SEL;
960
961 ret = of_mdio_parse_addr(dev, plat->phy_node);
962 if (ret < 0) {
963 dev_err(dev, "Could not parse MDIO addr\n");
964 return ret;
965 }
966 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
967 * address. No need to mask it again.
968 */
969 reg |= 1 << H3_EPHY_ADDR_SHIFT;
970 } else {
971 /* For SoCs without internal PHY the PHY selection bit should be
972 * set to 0 (external PHY).
973 */
974 reg &= ~H3_EPHY_SELECT;
975 }
976
977 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
978 if (val % 100) {
979 dev_err(dev, "tx-delay must be a multiple of 100\n");
980 return -EINVAL;
981 }
982 val /= 100;
983 dev_dbg(dev, "set tx-delay to %x\n", val);
984 if (val <= gmac->variant->tx_delay_max) {
985 reg &= ~(gmac->variant->tx_delay_max <<
986 SYSCON_ETXDC_SHIFT);
987 reg |= (val << SYSCON_ETXDC_SHIFT);
988 } else {
989 dev_err(dev, "Invalid TX clock delay: %d\n",
990 val);
991 return -EINVAL;
992 }
993 }
994
995 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
996 if (val % 100) {
997 dev_err(dev, "rx-delay must be a multiple of 100\n");
998 return -EINVAL;
999 }
1000 val /= 100;
1001 dev_dbg(dev, "set rx-delay to %x\n", val);
1002 if (val <= gmac->variant->rx_delay_max) {
1003 reg &= ~(gmac->variant->rx_delay_max <<
1004 SYSCON_ERXDC_SHIFT);
1005 reg |= (val << SYSCON_ERXDC_SHIFT);
1006 } else {
1007 dev_err(dev, "Invalid RX clock delay: %d\n",
1008 val);
1009 return -EINVAL;
1010 }
1011 }
1012
1013 /* Clear interface mode bits */
1014 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
1015 if (gmac->variant->support_rmii)
1016 reg &= ~SYSCON_RMII_EN;
1017
1018 switch (plat->mac_interface) {
1019 case PHY_INTERFACE_MODE_MII:
1020 /* default */
1021 break;
1022 case PHY_INTERFACE_MODE_RGMII:
1023 case PHY_INTERFACE_MODE_RGMII_ID:
1024 case PHY_INTERFACE_MODE_RGMII_RXID:
1025 case PHY_INTERFACE_MODE_RGMII_TXID:
1026 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
1027 break;
1028 case PHY_INTERFACE_MODE_RMII:
1029 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
1030 break;
1031 default:
1032 dev_err(dev, "Unsupported interface mode: %s",
1033 phy_modes(plat->mac_interface));
1034 return -EINVAL;
1035 }
1036
1037 regmap_field_write(gmac->regmap_field, reg);
1038
1039 return 0;
1040}
1041
1042static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
1043{
1044 u32 reg = gmac->variant->default_syscon_value;
1045
1046 regmap_field_write(gmac->regmap_field, reg);
1047}
1048
1049static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
1050{
1051 struct sunxi_priv_data *gmac = priv;
1052
1053 if (gmac->variant->soc_has_internal_phy)
1054 sun8i_dwmac_unpower_internal_phy(gmac);
1055
1056 if (gmac->regulator)
1057 regulator_disable(gmac->regulator);
1058}
1059
1060static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
1061{
1062 u32 value = readl(ioaddr + EMAC_BASIC_CTL0);
1063
1064 if (enable)
1065 value |= EMAC_LOOPBACK;
1066 else
1067 value &= ~EMAC_LOOPBACK;
1068
1069 writel(value, ioaddr + EMAC_BASIC_CTL0);
1070}
1071
1072static const struct stmmac_ops sun8i_dwmac_ops = {
1073 .core_init = sun8i_dwmac_core_init,
1074 .set_mac = sun8i_dwmac_set_mac,
1075 .dump_regs = sun8i_dwmac_dump_mac_regs,
1076 .rx_ipc = sun8i_dwmac_rx_ipc_enable,
1077 .set_filter = sun8i_dwmac_set_filter,
1078 .flow_ctrl = sun8i_dwmac_flow_ctrl,
1079 .set_umac_addr = sun8i_dwmac_set_umac_addr,
1080 .get_umac_addr = sun8i_dwmac_get_umac_addr,
1081 .set_mac_loopback = sun8i_dwmac_set_mac_loopback,
1082};
1083
1084static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
1085{
1086 struct mac_device_info *mac;
1087 struct stmmac_priv *priv = ppriv;
1088
1089 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
1090 if (!mac)
1091 return NULL;
1092
1093 mac->pcsr = priv->ioaddr;
1094 mac->mac = &sun8i_dwmac_ops;
1095 mac->dma = &sun8i_dwmac_dma_ops;
1096
1097 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1098
1099 /* The loopback bit seems to be re-set when link change
1100 * Simply mask it each time
1101 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
1102 */
1103 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
1104 mac->link.speed10 = EMAC_SPEED_10;
1105 mac->link.speed100 = EMAC_SPEED_100;
1106 mac->link.speed1000 = EMAC_SPEED_1000;
1107 mac->link.duplex = EMAC_DUPLEX_FULL;
1108 mac->mii.addr = EMAC_MDIO_CMD;
1109 mac->mii.data = EMAC_MDIO_DATA;
1110 mac->mii.reg_shift = 4;
1111 mac->mii.reg_mask = GENMASK(8, 4);
1112 mac->mii.addr_shift = 12;
1113 mac->mii.addr_mask = GENMASK(16, 12);
1114 mac->mii.clk_csr_shift = 20;
1115 mac->mii.clk_csr_mask = GENMASK(22, 20);
1116 mac->unicast_filter_entries = 8;
1117
1118 /* Synopsys Id is not available */
1119 priv->synopsys_id = 0;
1120
1121 return mac;
1122}
1123
1124static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node)
1125{
1126 struct device_node *syscon_node;
1127 struct platform_device *syscon_pdev;
1128 struct regmap *regmap = NULL;
1129
1130 syscon_node = of_parse_phandle(node, "syscon", 0);
1131 if (!syscon_node)
1132 return ERR_PTR(-ENODEV);
1133
1134 syscon_pdev = of_find_device_by_node(syscon_node);
1135 if (!syscon_pdev) {
1136 /* platform device might not be probed yet */
1137 regmap = ERR_PTR(-EPROBE_DEFER);
1138 goto out_put_node;
1139 }
1140
1141 /* If no regmap is found then the other device driver is at fault */
1142 regmap = dev_get_regmap(&syscon_pdev->dev, NULL);
1143 if (!regmap)
1144 regmap = ERR_PTR(-EINVAL);
1145
1146 platform_device_put(syscon_pdev);
1147out_put_node:
1148 of_node_put(syscon_node);
1149 return regmap;
1150}
1151
1152static int sun8i_dwmac_probe(struct platform_device *pdev)
1153{
1154 struct plat_stmmacenet_data *plat_dat;
1155 struct stmmac_resources stmmac_res;
1156 struct sunxi_priv_data *gmac;
1157 struct device *dev = &pdev->dev;
1158 phy_interface_t interface;
1159 int ret;
1160 struct stmmac_priv *priv;
1161 struct net_device *ndev;
1162 struct regmap *regmap;
1163
1164 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1165 if (ret)
1166 return ret;
1167
1168 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
1169 if (!gmac)
1170 return -ENOMEM;
1171
1172 gmac->variant = of_device_get_match_data(&pdev->dev);
1173 if (!gmac->variant) {
1174 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
1175 return -EINVAL;
1176 }
1177
1178 /* Optional regulator for PHY */
1179 gmac->regulator = devm_regulator_get_optional(dev, "phy");
1180 if (IS_ERR(gmac->regulator)) {
1181 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
1182 return -EPROBE_DEFER;
1183 dev_info(dev, "No regulator found\n");
1184 gmac->regulator = NULL;
1185 }
1186
1187 /* The "GMAC clock control" register might be located in the
1188 * CCU address range (on the R40), or the system control address
1189 * range (on most other sun8i and later SoCs).
1190 *
1191 * The former controls most if not all clocks in the SoC. The
1192 * latter has an SoC identification register, and on some SoCs,
1193 * controls to map device specific SRAM to either the intended
1194 * peripheral, or the CPU address space.
1195 *
1196 * In either case, there should be a coordinated and restricted
1197 * method of accessing the register needed here. This is done by
1198 * having the device export a custom regmap, instead of a generic
1199 * syscon, which grants all access to all registers.
1200 *
1201 * To support old device trees, we fall back to using the syscon
1202 * interface if possible.
1203 */
1204 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node);
1205 if (IS_ERR(regmap))
1206 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1207 "syscon");
1208 if (IS_ERR(regmap)) {
1209 ret = PTR_ERR(regmap);
1210 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
1211 return ret;
1212 }
1213
1214 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
1215 *gmac->variant->syscon_field);
1216 if (IS_ERR(gmac->regmap_field)) {
1217 ret = PTR_ERR(gmac->regmap_field);
1218 dev_err(dev, "Unable to map syscon register: %d\n", ret);
1219 return ret;
1220 }
1221
1222 ret = of_get_phy_mode(dev->of_node, &interface);
1223 if (ret)
1224 return -EINVAL;
1225
1226 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
1227 if (IS_ERR(plat_dat))
1228 return PTR_ERR(plat_dat);
1229
1230 /* platform data specifying hardware features and callbacks.
1231 * hardware features were copied from Allwinner drivers.
1232 */
1233 plat_dat->mac_interface = interface;
1234 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1235 plat_dat->tx_coe = 1;
1236 plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I;
1237 plat_dat->bsp_priv = gmac;
1238 plat_dat->init = sun8i_dwmac_init;
1239 plat_dat->exit = sun8i_dwmac_exit;
1240 plat_dat->setup = sun8i_dwmac_setup;
1241 plat_dat->tx_fifo_size = 4096;
1242 plat_dat->rx_fifo_size = 16384;
1243
1244 ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat);
1245 if (ret)
1246 return ret;
1247
1248 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
1249 if (ret)
1250 goto dwmac_syscon;
1251
1252 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1253 if (ret)
1254 goto dwmac_exit;
1255
1256 ndev = dev_get_drvdata(&pdev->dev);
1257 priv = netdev_priv(ndev);
1258
1259 /* the MAC is runtime suspended after stmmac_dvr_probe(), so we
1260 * need to ensure the MAC resume back before other operations such
1261 * as reset.
1262 */
1263 pm_runtime_get_sync(&pdev->dev);
1264
1265 /* The mux must be registered after parent MDIO
1266 * so after stmmac_dvr_probe()
1267 */
1268 if (gmac->variant->soc_has_internal_phy) {
1269 ret = get_ephy_nodes(priv);
1270 if (ret)
1271 goto dwmac_remove;
1272 ret = sun8i_dwmac_register_mdio_mux(priv);
1273 if (ret) {
1274 dev_err(&pdev->dev, "Failed to register mux\n");
1275 goto dwmac_mux;
1276 }
1277 } else {
1278 ret = sun8i_dwmac_reset(priv);
1279 if (ret)
1280 goto dwmac_remove;
1281 }
1282
1283 pm_runtime_put(&pdev->dev);
1284
1285 return 0;
1286
1287dwmac_mux:
1288 reset_control_put(gmac->rst_ephy);
1289 clk_put(gmac->ephy_clk);
1290dwmac_remove:
1291 pm_runtime_put_noidle(&pdev->dev);
1292 stmmac_dvr_remove(&pdev->dev);
1293dwmac_exit:
1294 sun8i_dwmac_exit(pdev, gmac);
1295dwmac_syscon:
1296 sun8i_dwmac_unset_syscon(gmac);
1297
1298 return ret;
1299}
1300
1301static void sun8i_dwmac_remove(struct platform_device *pdev)
1302{
1303 struct net_device *ndev = platform_get_drvdata(pdev);
1304 struct stmmac_priv *priv = netdev_priv(ndev);
1305 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
1306
1307 if (gmac->variant->soc_has_internal_phy) {
1308 mdio_mux_uninit(gmac->mux_handle);
1309 sun8i_dwmac_unpower_internal_phy(gmac);
1310 reset_control_put(gmac->rst_ephy);
1311 clk_put(gmac->ephy_clk);
1312 }
1313
1314 stmmac_pltfr_remove(pdev);
1315 sun8i_dwmac_unset_syscon(gmac);
1316}
1317
1318static void sun8i_dwmac_shutdown(struct platform_device *pdev)
1319{
1320 struct net_device *ndev = platform_get_drvdata(pdev);
1321 struct stmmac_priv *priv = netdev_priv(ndev);
1322 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
1323
1324 sun8i_dwmac_exit(pdev, gmac);
1325}
1326
1327static const struct of_device_id sun8i_dwmac_match[] = {
1328 { .compatible = "allwinner,sun8i-h3-emac",
1329 .data = &emac_variant_h3 },
1330 { .compatible = "allwinner,sun8i-v3s-emac",
1331 .data = &emac_variant_v3s },
1332 { .compatible = "allwinner,sun8i-a83t-emac",
1333 .data = &emac_variant_a83t },
1334 { .compatible = "allwinner,sun8i-r40-gmac",
1335 .data = &emac_variant_r40 },
1336 { .compatible = "allwinner,sun50i-a64-emac",
1337 .data = &emac_variant_a64 },
1338 { .compatible = "allwinner,sun50i-h6-emac",
1339 .data = &emac_variant_h6 },
1340 { }
1341};
1342MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
1343
1344static struct platform_driver sun8i_dwmac_driver = {
1345 .probe = sun8i_dwmac_probe,
1346 .remove_new = sun8i_dwmac_remove,
1347 .shutdown = sun8i_dwmac_shutdown,
1348 .driver = {
1349 .name = "dwmac-sun8i",
1350 .pm = &stmmac_pltfr_pm_ops,
1351 .of_match_table = sun8i_dwmac_match,
1352 },
1353};
1354module_platform_driver(sun8i_dwmac_driver);
1355
1356MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1357MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1358MODULE_LICENSE("GPL");
1/*
2 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
3 *
4 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/mdio-mux.h>
21#include <linux/mfd/syscon.h>
22#include <linux/module.h>
23#include <linux/of_device.h>
24#include <linux/of_mdio.h>
25#include <linux/of_net.h>
26#include <linux/phy.h>
27#include <linux/platform_device.h>
28#include <linux/regulator/consumer.h>
29#include <linux/regmap.h>
30#include <linux/stmmac.h>
31
32#include "stmmac.h"
33#include "stmmac_platform.h"
34
35/* General notes on dwmac-sun8i:
36 * Locking: no locking is necessary in this file because all necessary locking
37 * is done in the "stmmac files"
38 */
39
40/* struct emac_variant - Descrive dwmac-sun8i hardware variant
41 * @default_syscon_value: The default value of the EMAC register in syscon
42 * This value is used for disabling properly EMAC
43 * and used as a good starting value in case of the
44 * boot process(uboot) leave some stuff.
45 * @soc_has_internal_phy: Does the MAC embed an internal PHY
46 * @support_mii: Does the MAC handle MII
47 * @support_rmii: Does the MAC handle RMII
48 * @support_rgmii: Does the MAC handle RGMII
49 */
50struct emac_variant {
51 u32 default_syscon_value;
52 bool soc_has_internal_phy;
53 bool support_mii;
54 bool support_rmii;
55 bool support_rgmii;
56};
57
58/* struct sunxi_priv_data - hold all sunxi private data
59 * @tx_clk: reference to MAC TX clock
60 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
61 * @regulator: reference to the optional regulator
62 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
63 * @variant: reference to the current board variant
64 * @regmap: regmap for using the syscon
65 * @internal_phy_powered: Does the internal PHY is enabled
66 * @mux_handle: Internal pointer used by mdio-mux lib
67 */
68struct sunxi_priv_data {
69 struct clk *tx_clk;
70 struct clk *ephy_clk;
71 struct regulator *regulator;
72 struct reset_control *rst_ephy;
73 const struct emac_variant *variant;
74 struct regmap *regmap;
75 bool internal_phy_powered;
76 void *mux_handle;
77};
78
79static const struct emac_variant emac_variant_h3 = {
80 .default_syscon_value = 0x58000,
81 .soc_has_internal_phy = true,
82 .support_mii = true,
83 .support_rmii = true,
84 .support_rgmii = true
85};
86
87static const struct emac_variant emac_variant_v3s = {
88 .default_syscon_value = 0x38000,
89 .soc_has_internal_phy = true,
90 .support_mii = true
91};
92
93static const struct emac_variant emac_variant_a83t = {
94 .default_syscon_value = 0,
95 .soc_has_internal_phy = false,
96 .support_mii = true,
97 .support_rgmii = true
98};
99
100static const struct emac_variant emac_variant_a64 = {
101 .default_syscon_value = 0,
102 .soc_has_internal_phy = false,
103 .support_mii = true,
104 .support_rmii = true,
105 .support_rgmii = true
106};
107
108#define EMAC_BASIC_CTL0 0x00
109#define EMAC_BASIC_CTL1 0x04
110#define EMAC_INT_STA 0x08
111#define EMAC_INT_EN 0x0C
112#define EMAC_TX_CTL0 0x10
113#define EMAC_TX_CTL1 0x14
114#define EMAC_TX_FLOW_CTL 0x1C
115#define EMAC_TX_DESC_LIST 0x20
116#define EMAC_RX_CTL0 0x24
117#define EMAC_RX_CTL1 0x28
118#define EMAC_RX_DESC_LIST 0x34
119#define EMAC_RX_FRM_FLT 0x38
120#define EMAC_MDIO_CMD 0x48
121#define EMAC_MDIO_DATA 0x4C
122#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
123#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
124#define EMAC_TX_DMA_STA 0xB0
125#define EMAC_TX_CUR_DESC 0xB4
126#define EMAC_TX_CUR_BUF 0xB8
127#define EMAC_RX_DMA_STA 0xC0
128#define EMAC_RX_CUR_DESC 0xC4
129#define EMAC_RX_CUR_BUF 0xC8
130
131/* Use in EMAC_BASIC_CTL0 */
132#define EMAC_DUPLEX_FULL BIT(0)
133#define EMAC_LOOPBACK BIT(1)
134#define EMAC_SPEED_1000 0
135#define EMAC_SPEED_100 (0x03 << 2)
136#define EMAC_SPEED_10 (0x02 << 2)
137
138/* Use in EMAC_BASIC_CTL1 */
139#define EMAC_BURSTLEN_SHIFT 24
140
141/* Used in EMAC_RX_FRM_FLT */
142#define EMAC_FRM_FLT_RXALL BIT(0)
143#define EMAC_FRM_FLT_CTL BIT(13)
144#define EMAC_FRM_FLT_MULTICAST BIT(16)
145
146/* Used in RX_CTL1*/
147#define EMAC_RX_MD BIT(1)
148#define EMAC_RX_TH_MASK GENMASK(4, 5)
149#define EMAC_RX_TH_32 0
150#define EMAC_RX_TH_64 (0x1 << 4)
151#define EMAC_RX_TH_96 (0x2 << 4)
152#define EMAC_RX_TH_128 (0x3 << 4)
153#define EMAC_RX_DMA_EN BIT(30)
154#define EMAC_RX_DMA_START BIT(31)
155
156/* Used in TX_CTL1*/
157#define EMAC_TX_MD BIT(1)
158#define EMAC_TX_NEXT_FRM BIT(2)
159#define EMAC_TX_TH_MASK GENMASK(8, 10)
160#define EMAC_TX_TH_64 0
161#define EMAC_TX_TH_128 (0x1 << 8)
162#define EMAC_TX_TH_192 (0x2 << 8)
163#define EMAC_TX_TH_256 (0x3 << 8)
164#define EMAC_TX_DMA_EN BIT(30)
165#define EMAC_TX_DMA_START BIT(31)
166
167/* Used in RX_CTL0 */
168#define EMAC_RX_RECEIVER_EN BIT(31)
169#define EMAC_RX_DO_CRC BIT(27)
170#define EMAC_RX_FLOW_CTL_EN BIT(16)
171
172/* Used in TX_CTL0 */
173#define EMAC_TX_TRANSMITTER_EN BIT(31)
174
175/* Used in EMAC_TX_FLOW_CTL */
176#define EMAC_TX_FLOW_CTL_EN BIT(0)
177
178/* Used in EMAC_INT_STA */
179#define EMAC_TX_INT BIT(0)
180#define EMAC_TX_DMA_STOP_INT BIT(1)
181#define EMAC_TX_BUF_UA_INT BIT(2)
182#define EMAC_TX_TIMEOUT_INT BIT(3)
183#define EMAC_TX_UNDERFLOW_INT BIT(4)
184#define EMAC_TX_EARLY_INT BIT(5)
185#define EMAC_RX_INT BIT(8)
186#define EMAC_RX_BUF_UA_INT BIT(9)
187#define EMAC_RX_DMA_STOP_INT BIT(10)
188#define EMAC_RX_TIMEOUT_INT BIT(11)
189#define EMAC_RX_OVERFLOW_INT BIT(12)
190#define EMAC_RX_EARLY_INT BIT(13)
191#define EMAC_RGMII_STA_INT BIT(16)
192
193#define MAC_ADDR_TYPE_DST BIT(31)
194
195/* H3 specific bits for EPHY */
196#define H3_EPHY_ADDR_SHIFT 20
197#define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */
198#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
199#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
200#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
201#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
202#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1
203#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2
204
205/* H3/A64 specific bits */
206#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
207
208/* Generic system control EMAC_CLK bits */
209#define SYSCON_ETXDC_MASK GENMASK(2, 0)
210#define SYSCON_ETXDC_SHIFT 10
211#define SYSCON_ERXDC_MASK GENMASK(4, 0)
212#define SYSCON_ERXDC_SHIFT 5
213/* EMAC PHY Interface Type */
214#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
215#define SYSCON_ETCS_MASK GENMASK(1, 0)
216#define SYSCON_ETCS_MII 0x0
217#define SYSCON_ETCS_EXT_GMII 0x1
218#define SYSCON_ETCS_INT_GMII 0x2
219#define SYSCON_EMAC_REG 0x30
220
221/* sun8i_dwmac_dma_reset() - reset the EMAC
222 * Called from stmmac via stmmac_dma_ops->reset
223 */
224static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
225{
226 writel(0, ioaddr + EMAC_RX_CTL1);
227 writel(0, ioaddr + EMAC_TX_CTL1);
228 writel(0, ioaddr + EMAC_RX_FRM_FLT);
229 writel(0, ioaddr + EMAC_RX_DESC_LIST);
230 writel(0, ioaddr + EMAC_TX_DESC_LIST);
231 writel(0, ioaddr + EMAC_INT_EN);
232 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
233 return 0;
234}
235
236/* sun8i_dwmac_dma_init() - initialize the EMAC
237 * Called from stmmac via stmmac_dma_ops->init
238 */
239static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
240 struct stmmac_dma_cfg *dma_cfg,
241 u32 dma_tx, u32 dma_rx, int atds)
242{
243 /* Write TX and RX descriptors address */
244 writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST);
245 writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST);
246
247 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
248 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
249}
250
251/* sun8i_dwmac_dump_regs() - Dump EMAC address space
252 * Called from stmmac_dma_ops->dump_regs
253 * Used for ethtool
254 */
255static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)
256{
257 int i;
258
259 for (i = 0; i < 0xC8; i += 4) {
260 if (i == 0x32 || i == 0x3C)
261 continue;
262 reg_space[i / 4] = readl(ioaddr + i);
263 }
264}
265
266/* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
267 * Called from stmmac_ops->dump_regs
268 * Used for ethtool
269 */
270static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
271 u32 *reg_space)
272{
273 int i;
274 void __iomem *ioaddr = hw->pcsr;
275
276 for (i = 0; i < 0xC8; i += 4) {
277 if (i == 0x32 || i == 0x3C)
278 continue;
279 reg_space[i / 4] = readl(ioaddr + i);
280 }
281}
282
283static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
284{
285 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
286}
287
288static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
289{
290 writel(0, ioaddr + EMAC_INT_EN);
291}
292
293static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
294{
295 u32 v;
296
297 v = readl(ioaddr + EMAC_TX_CTL1);
298 v |= EMAC_TX_DMA_START;
299 v |= EMAC_TX_DMA_EN;
300 writel(v, ioaddr + EMAC_TX_CTL1);
301}
302
303static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
304{
305 u32 v;
306
307 v = readl(ioaddr + EMAC_TX_CTL1);
308 v |= EMAC_TX_DMA_START;
309 v |= EMAC_TX_DMA_EN;
310 writel(v, ioaddr + EMAC_TX_CTL1);
311}
312
313static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
314{
315 u32 v;
316
317 v = readl(ioaddr + EMAC_TX_CTL1);
318 v &= ~EMAC_TX_DMA_EN;
319 writel(v, ioaddr + EMAC_TX_CTL1);
320}
321
322static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
323{
324 u32 v;
325
326 v = readl(ioaddr + EMAC_RX_CTL1);
327 v |= EMAC_RX_DMA_START;
328 v |= EMAC_RX_DMA_EN;
329 writel(v, ioaddr + EMAC_RX_CTL1);
330}
331
332static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
333{
334 u32 v;
335
336 v = readl(ioaddr + EMAC_RX_CTL1);
337 v &= ~EMAC_RX_DMA_EN;
338 writel(v, ioaddr + EMAC_RX_CTL1);
339}
340
341static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
342 struct stmmac_extra_stats *x, u32 chan)
343{
344 u32 v;
345 int ret = 0;
346
347 v = readl(ioaddr + EMAC_INT_STA);
348
349 if (v & EMAC_TX_INT) {
350 ret |= handle_tx;
351 x->tx_normal_irq_n++;
352 }
353
354 if (v & EMAC_TX_DMA_STOP_INT)
355 x->tx_process_stopped_irq++;
356
357 if (v & EMAC_TX_BUF_UA_INT)
358 x->tx_process_stopped_irq++;
359
360 if (v & EMAC_TX_TIMEOUT_INT)
361 ret |= tx_hard_error;
362
363 if (v & EMAC_TX_UNDERFLOW_INT) {
364 ret |= tx_hard_error;
365 x->tx_undeflow_irq++;
366 }
367
368 if (v & EMAC_TX_EARLY_INT)
369 x->tx_early_irq++;
370
371 if (v & EMAC_RX_INT) {
372 ret |= handle_rx;
373 x->rx_normal_irq_n++;
374 }
375
376 if (v & EMAC_RX_BUF_UA_INT)
377 x->rx_buf_unav_irq++;
378
379 if (v & EMAC_RX_DMA_STOP_INT)
380 x->rx_process_stopped_irq++;
381
382 if (v & EMAC_RX_TIMEOUT_INT)
383 ret |= tx_hard_error;
384
385 if (v & EMAC_RX_OVERFLOW_INT) {
386 ret |= tx_hard_error;
387 x->rx_overflow_irq++;
388 }
389
390 if (v & EMAC_RX_EARLY_INT)
391 x->rx_early_irq++;
392
393 if (v & EMAC_RGMII_STA_INT)
394 x->irq_rgmii_n++;
395
396 writel(v, ioaddr + EMAC_INT_STA);
397
398 return ret;
399}
400
401static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode,
402 int rxmode, int rxfifosz)
403{
404 u32 v;
405
406 v = readl(ioaddr + EMAC_TX_CTL1);
407 if (txmode == SF_DMA_MODE) {
408 v |= EMAC_TX_MD;
409 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
410 * comment is
411 * "Operating on second frame increase the performance
412 * especially when transmit store-and-forward is used."
413 */
414 v |= EMAC_TX_NEXT_FRM;
415 } else {
416 v &= ~EMAC_TX_MD;
417 v &= ~EMAC_TX_TH_MASK;
418 if (txmode < 64)
419 v |= EMAC_TX_TH_64;
420 else if (txmode < 128)
421 v |= EMAC_TX_TH_128;
422 else if (txmode < 192)
423 v |= EMAC_TX_TH_192;
424 else if (txmode < 256)
425 v |= EMAC_TX_TH_256;
426 }
427 writel(v, ioaddr + EMAC_TX_CTL1);
428
429 v = readl(ioaddr + EMAC_RX_CTL1);
430 if (rxmode == SF_DMA_MODE) {
431 v |= EMAC_RX_MD;
432 } else {
433 v &= ~EMAC_RX_MD;
434 v &= ~EMAC_RX_TH_MASK;
435 if (rxmode < 32)
436 v |= EMAC_RX_TH_32;
437 else if (rxmode < 64)
438 v |= EMAC_RX_TH_64;
439 else if (rxmode < 96)
440 v |= EMAC_RX_TH_96;
441 else if (rxmode < 128)
442 v |= EMAC_RX_TH_128;
443 }
444 writel(v, ioaddr + EMAC_RX_CTL1);
445}
446
447static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
448 .reset = sun8i_dwmac_dma_reset,
449 .init = sun8i_dwmac_dma_init,
450 .dump_regs = sun8i_dwmac_dump_regs,
451 .dma_mode = sun8i_dwmac_dma_operation_mode,
452 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
453 .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
454 .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
455 .start_tx = sun8i_dwmac_dma_start_tx,
456 .stop_tx = sun8i_dwmac_dma_stop_tx,
457 .start_rx = sun8i_dwmac_dma_start_rx,
458 .stop_rx = sun8i_dwmac_dma_stop_rx,
459 .dma_interrupt = sun8i_dwmac_dma_interrupt,
460};
461
462static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
463{
464 struct sunxi_priv_data *gmac = priv;
465 int ret;
466
467 if (gmac->regulator) {
468 ret = regulator_enable(gmac->regulator);
469 if (ret) {
470 dev_err(&pdev->dev, "Fail to enable regulator\n");
471 return ret;
472 }
473 }
474
475 ret = clk_prepare_enable(gmac->tx_clk);
476 if (ret) {
477 if (gmac->regulator)
478 regulator_disable(gmac->regulator);
479 dev_err(&pdev->dev, "Could not enable AHB clock\n");
480 return ret;
481 }
482
483 return 0;
484}
485
486static void sun8i_dwmac_core_init(struct mac_device_info *hw,
487 struct net_device *dev)
488{
489 void __iomem *ioaddr = hw->pcsr;
490 u32 v;
491
492 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
493 writel(v, ioaddr + EMAC_BASIC_CTL1);
494}
495
496static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
497{
498 u32 t, r;
499
500 t = readl(ioaddr + EMAC_TX_CTL0);
501 r = readl(ioaddr + EMAC_RX_CTL0);
502 if (enable) {
503 t |= EMAC_TX_TRANSMITTER_EN;
504 r |= EMAC_RX_RECEIVER_EN;
505 } else {
506 t &= ~EMAC_TX_TRANSMITTER_EN;
507 r &= ~EMAC_RX_RECEIVER_EN;
508 }
509 writel(t, ioaddr + EMAC_TX_CTL0);
510 writel(r, ioaddr + EMAC_RX_CTL0);
511}
512
513/* Set MAC address at slot reg_n
514 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
515 * If addr is NULL, clear the slot
516 */
517static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
518 unsigned char *addr,
519 unsigned int reg_n)
520{
521 void __iomem *ioaddr = hw->pcsr;
522 u32 v;
523
524 if (!addr) {
525 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
526 return;
527 }
528
529 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
530 EMAC_MACADDR_LO(reg_n));
531 if (reg_n > 0) {
532 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
533 v |= MAC_ADDR_TYPE_DST;
534 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
535 }
536}
537
538static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
539 unsigned char *addr,
540 unsigned int reg_n)
541{
542 void __iomem *ioaddr = hw->pcsr;
543
544 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
545 EMAC_MACADDR_LO(reg_n));
546}
547
548/* caution this function must return non 0 to work */
549static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
550{
551 void __iomem *ioaddr = hw->pcsr;
552 u32 v;
553
554 v = readl(ioaddr + EMAC_RX_CTL0);
555 v |= EMAC_RX_DO_CRC;
556 writel(v, ioaddr + EMAC_RX_CTL0);
557
558 return 1;
559}
560
561static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
562 struct net_device *dev)
563{
564 void __iomem *ioaddr = hw->pcsr;
565 u32 v;
566 int i = 1;
567 struct netdev_hw_addr *ha;
568 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
569
570 v = EMAC_FRM_FLT_CTL;
571
572 if (dev->flags & IFF_PROMISC) {
573 v = EMAC_FRM_FLT_RXALL;
574 } else if (dev->flags & IFF_ALLMULTI) {
575 v |= EMAC_FRM_FLT_MULTICAST;
576 } else if (macaddrs <= hw->unicast_filter_entries) {
577 if (!netdev_mc_empty(dev)) {
578 netdev_for_each_mc_addr(ha, dev) {
579 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
580 i++;
581 }
582 }
583 if (!netdev_uc_empty(dev)) {
584 netdev_for_each_uc_addr(ha, dev) {
585 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
586 i++;
587 }
588 }
589 } else {
590 netdev_info(dev, "Too many address, switching to promiscuous\n");
591 v = EMAC_FRM_FLT_RXALL;
592 }
593
594 /* Disable unused address filter slots */
595 while (i < hw->unicast_filter_entries)
596 sun8i_dwmac_set_umac_addr(hw, NULL, i++);
597
598 writel(v, ioaddr + EMAC_RX_FRM_FLT);
599}
600
601static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
602 unsigned int duplex, unsigned int fc,
603 unsigned int pause_time, u32 tx_cnt)
604{
605 void __iomem *ioaddr = hw->pcsr;
606 u32 v;
607
608 v = readl(ioaddr + EMAC_RX_CTL0);
609 if (fc == FLOW_AUTO)
610 v |= EMAC_RX_FLOW_CTL_EN;
611 else
612 v &= ~EMAC_RX_FLOW_CTL_EN;
613 writel(v, ioaddr + EMAC_RX_CTL0);
614
615 v = readl(ioaddr + EMAC_TX_FLOW_CTL);
616 if (fc == FLOW_AUTO)
617 v |= EMAC_TX_FLOW_CTL_EN;
618 else
619 v &= ~EMAC_TX_FLOW_CTL_EN;
620 writel(v, ioaddr + EMAC_TX_FLOW_CTL);
621}
622
623static int sun8i_dwmac_reset(struct stmmac_priv *priv)
624{
625 u32 v;
626 int err;
627
628 v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
629 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
630
631 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
632 * need more if no cable plugged. 100ms seems OK
633 */
634 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
635 !(v & 0x01), 100, 100000);
636
637 if (err) {
638 dev_err(priv->device, "EMAC reset timeout\n");
639 return -EFAULT;
640 }
641 return 0;
642}
643
644/* Search in mdio-mux node for internal PHY node and get its clk/reset */
645static int get_ephy_nodes(struct stmmac_priv *priv)
646{
647 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
648 struct device_node *mdio_mux, *iphynode;
649 struct device_node *mdio_internal;
650 int ret;
651
652 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
653 if (!mdio_mux) {
654 dev_err(priv->device, "Cannot get mdio-mux node\n");
655 return -ENODEV;
656 }
657
658 mdio_internal = of_find_compatible_node(mdio_mux, NULL,
659 "allwinner,sun8i-h3-mdio-internal");
660 if (!mdio_internal) {
661 dev_err(priv->device, "Cannot get internal_mdio node\n");
662 return -ENODEV;
663 }
664
665 /* Seek for internal PHY */
666 for_each_child_of_node(mdio_internal, iphynode) {
667 gmac->ephy_clk = of_clk_get(iphynode, 0);
668 if (IS_ERR(gmac->ephy_clk))
669 continue;
670 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
671 if (IS_ERR(gmac->rst_ephy)) {
672 ret = PTR_ERR(gmac->rst_ephy);
673 if (ret == -EPROBE_DEFER)
674 return ret;
675 continue;
676 }
677 dev_info(priv->device, "Found internal PHY node\n");
678 return 0;
679 }
680 return -ENODEV;
681}
682
683static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
684{
685 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
686 int ret;
687
688 if (gmac->internal_phy_powered) {
689 dev_warn(priv->device, "Internal PHY already powered\n");
690 return 0;
691 }
692
693 dev_info(priv->device, "Powering internal PHY\n");
694 ret = clk_prepare_enable(gmac->ephy_clk);
695 if (ret) {
696 dev_err(priv->device, "Cannot enable internal PHY\n");
697 return ret;
698 }
699
700 /* Make sure the EPHY is properly reseted, as U-Boot may leave
701 * it at deasserted state, and thus it may fail to reset EMAC.
702 */
703 reset_control_assert(gmac->rst_ephy);
704
705 ret = reset_control_deassert(gmac->rst_ephy);
706 if (ret) {
707 dev_err(priv->device, "Cannot deassert internal phy\n");
708 clk_disable_unprepare(gmac->ephy_clk);
709 return ret;
710 }
711
712 gmac->internal_phy_powered = true;
713
714 return 0;
715}
716
717static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
718{
719 if (!gmac->internal_phy_powered)
720 return 0;
721
722 clk_disable_unprepare(gmac->ephy_clk);
723 reset_control_assert(gmac->rst_ephy);
724 gmac->internal_phy_powered = false;
725 return 0;
726}
727
728/* MDIO multiplexing switch function
729 * This function is called by the mdio-mux layer when it thinks the mdio bus
730 * multiplexer needs to switch.
731 * 'current_child' is the current value of the mux register
732 * 'desired_child' is the value of the 'reg' property of the target child MDIO
733 * node.
734 * The first time this function is called, current_child == -1.
735 * If current_child == desired_child, then the mux is already set to the
736 * correct bus.
737 */
738static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
739 void *data)
740{
741 struct stmmac_priv *priv = data;
742 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
743 u32 reg, val;
744 int ret = 0;
745 bool need_power_ephy = false;
746
747 if (current_child ^ desired_child) {
748 regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
749 switch (desired_child) {
750 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
751 dev_info(priv->device, "Switch mux to internal PHY");
752 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
753
754 need_power_ephy = true;
755 break;
756 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
757 dev_info(priv->device, "Switch mux to external PHY");
758 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
759 need_power_ephy = false;
760 break;
761 default:
762 dev_err(priv->device, "Invalid child ID %x\n",
763 desired_child);
764 return -EINVAL;
765 }
766 regmap_write(gmac->regmap, SYSCON_EMAC_REG, val);
767 if (need_power_ephy) {
768 ret = sun8i_dwmac_power_internal_phy(priv);
769 if (ret)
770 return ret;
771 } else {
772 sun8i_dwmac_unpower_internal_phy(gmac);
773 }
774 /* After changing syscon value, the MAC need reset or it will
775 * use the last value (and so the last PHY set).
776 */
777 ret = sun8i_dwmac_reset(priv);
778 }
779 return ret;
780}
781
782static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
783{
784 int ret;
785 struct device_node *mdio_mux;
786 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
787
788 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
789 if (!mdio_mux)
790 return -ENODEV;
791
792 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
793 &gmac->mux_handle, priv, priv->mii);
794 return ret;
795}
796
797static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
798{
799 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
800 struct device_node *node = priv->device->of_node;
801 int ret;
802 u32 reg, val;
803
804 regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val);
805 reg = gmac->variant->default_syscon_value;
806 if (reg != val)
807 dev_warn(priv->device,
808 "Current syscon value is not the default %x (expect %x)\n",
809 val, reg);
810
811 if (gmac->variant->soc_has_internal_phy) {
812 if (of_property_read_bool(node, "allwinner,leds-active-low"))
813 reg |= H3_EPHY_LED_POL;
814 else
815 reg &= ~H3_EPHY_LED_POL;
816
817 /* Force EPHY xtal frequency to 24MHz. */
818 reg |= H3_EPHY_CLK_SEL;
819
820 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);
821 if (ret < 0) {
822 dev_err(priv->device, "Could not parse MDIO addr\n");
823 return ret;
824 }
825 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
826 * address. No need to mask it again.
827 */
828 reg |= 1 << H3_EPHY_ADDR_SHIFT;
829 }
830
831 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
832 if (val % 100) {
833 dev_err(priv->device, "tx-delay must be a multiple of 100\n");
834 return -EINVAL;
835 }
836 val /= 100;
837 dev_dbg(priv->device, "set tx-delay to %x\n", val);
838 if (val <= SYSCON_ETXDC_MASK) {
839 reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT);
840 reg |= (val << SYSCON_ETXDC_SHIFT);
841 } else {
842 dev_err(priv->device, "Invalid TX clock delay: %d\n",
843 val);
844 return -EINVAL;
845 }
846 }
847
848 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
849 if (val % 100) {
850 dev_err(priv->device, "rx-delay must be a multiple of 100\n");
851 return -EINVAL;
852 }
853 val /= 100;
854 dev_dbg(priv->device, "set rx-delay to %x\n", val);
855 if (val <= SYSCON_ERXDC_MASK) {
856 reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT);
857 reg |= (val << SYSCON_ERXDC_SHIFT);
858 } else {
859 dev_err(priv->device, "Invalid RX clock delay: %d\n",
860 val);
861 return -EINVAL;
862 }
863 }
864
865 /* Clear interface mode bits */
866 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
867 if (gmac->variant->support_rmii)
868 reg &= ~SYSCON_RMII_EN;
869
870 switch (priv->plat->interface) {
871 case PHY_INTERFACE_MODE_MII:
872 /* default */
873 break;
874 case PHY_INTERFACE_MODE_RGMII:
875 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
876 break;
877 case PHY_INTERFACE_MODE_RMII:
878 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
879 break;
880 default:
881 dev_err(priv->device, "Unsupported interface mode: %s",
882 phy_modes(priv->plat->interface));
883 return -EINVAL;
884 }
885
886 regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
887
888 return 0;
889}
890
891static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
892{
893 u32 reg = gmac->variant->default_syscon_value;
894
895 regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
896}
897
898static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
899{
900 struct sunxi_priv_data *gmac = priv;
901
902 if (gmac->variant->soc_has_internal_phy) {
903 /* sun8i_dwmac_exit could be called with mdiomux uninit */
904 if (gmac->mux_handle)
905 mdio_mux_uninit(gmac->mux_handle);
906 if (gmac->internal_phy_powered)
907 sun8i_dwmac_unpower_internal_phy(gmac);
908 }
909
910 sun8i_dwmac_unset_syscon(gmac);
911
912 reset_control_put(gmac->rst_ephy);
913
914 clk_disable_unprepare(gmac->tx_clk);
915
916 if (gmac->regulator)
917 regulator_disable(gmac->regulator);
918}
919
920static const struct stmmac_ops sun8i_dwmac_ops = {
921 .core_init = sun8i_dwmac_core_init,
922 .set_mac = sun8i_dwmac_set_mac,
923 .dump_regs = sun8i_dwmac_dump_mac_regs,
924 .rx_ipc = sun8i_dwmac_rx_ipc_enable,
925 .set_filter = sun8i_dwmac_set_filter,
926 .flow_ctrl = sun8i_dwmac_flow_ctrl,
927 .set_umac_addr = sun8i_dwmac_set_umac_addr,
928 .get_umac_addr = sun8i_dwmac_get_umac_addr,
929};
930
931static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
932{
933 struct mac_device_info *mac;
934 struct stmmac_priv *priv = ppriv;
935 int ret;
936
937 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
938 if (!mac)
939 return NULL;
940
941 ret = sun8i_dwmac_set_syscon(priv);
942 if (ret)
943 return NULL;
944
945 mac->pcsr = priv->ioaddr;
946 mac->mac = &sun8i_dwmac_ops;
947 mac->dma = &sun8i_dwmac_dma_ops;
948
949 /* The loopback bit seems to be re-set when link change
950 * Simply mask it each time
951 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
952 */
953 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
954 mac->link.speed10 = EMAC_SPEED_10;
955 mac->link.speed100 = EMAC_SPEED_100;
956 mac->link.speed1000 = EMAC_SPEED_1000;
957 mac->link.duplex = EMAC_DUPLEX_FULL;
958 mac->mii.addr = EMAC_MDIO_CMD;
959 mac->mii.data = EMAC_MDIO_DATA;
960 mac->mii.reg_shift = 4;
961 mac->mii.reg_mask = GENMASK(8, 4);
962 mac->mii.addr_shift = 12;
963 mac->mii.addr_mask = GENMASK(16, 12);
964 mac->mii.clk_csr_shift = 20;
965 mac->mii.clk_csr_mask = GENMASK(22, 20);
966 mac->unicast_filter_entries = 8;
967
968 /* Synopsys Id is not available */
969 priv->synopsys_id = 0;
970
971 return mac;
972}
973
974static int sun8i_dwmac_probe(struct platform_device *pdev)
975{
976 struct plat_stmmacenet_data *plat_dat;
977 struct stmmac_resources stmmac_res;
978 struct sunxi_priv_data *gmac;
979 struct device *dev = &pdev->dev;
980 int ret;
981 struct stmmac_priv *priv;
982 struct net_device *ndev;
983
984 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
985 if (ret)
986 return ret;
987
988 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
989 if (IS_ERR(plat_dat))
990 return PTR_ERR(plat_dat);
991
992 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
993 if (!gmac)
994 return -ENOMEM;
995
996 gmac->variant = of_device_get_match_data(&pdev->dev);
997 if (!gmac->variant) {
998 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
999 return -EINVAL;
1000 }
1001
1002 gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
1003 if (IS_ERR(gmac->tx_clk)) {
1004 dev_err(dev, "Could not get TX clock\n");
1005 return PTR_ERR(gmac->tx_clk);
1006 }
1007
1008 /* Optional regulator for PHY */
1009 gmac->regulator = devm_regulator_get_optional(dev, "phy");
1010 if (IS_ERR(gmac->regulator)) {
1011 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
1012 return -EPROBE_DEFER;
1013 dev_info(dev, "No regulator found\n");
1014 gmac->regulator = NULL;
1015 }
1016
1017 gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1018 "syscon");
1019 if (IS_ERR(gmac->regmap)) {
1020 ret = PTR_ERR(gmac->regmap);
1021 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
1022 return ret;
1023 }
1024
1025 plat_dat->interface = of_get_phy_mode(dev->of_node);
1026
1027 /* platform data specifying hardware features and callbacks.
1028 * hardware features were copied from Allwinner drivers.
1029 */
1030 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1031 plat_dat->tx_coe = 1;
1032 plat_dat->has_sun8i = true;
1033 plat_dat->bsp_priv = gmac;
1034 plat_dat->init = sun8i_dwmac_init;
1035 plat_dat->exit = sun8i_dwmac_exit;
1036 plat_dat->setup = sun8i_dwmac_setup;
1037
1038 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
1039 if (ret)
1040 return ret;
1041
1042 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1043 if (ret)
1044 goto dwmac_exit;
1045
1046 ndev = dev_get_drvdata(&pdev->dev);
1047 priv = netdev_priv(ndev);
1048 /* The mux must be registered after parent MDIO
1049 * so after stmmac_dvr_probe()
1050 */
1051 if (gmac->variant->soc_has_internal_phy) {
1052 ret = get_ephy_nodes(priv);
1053 if (ret)
1054 goto dwmac_exit;
1055 ret = sun8i_dwmac_register_mdio_mux(priv);
1056 if (ret) {
1057 dev_err(&pdev->dev, "Failed to register mux\n");
1058 goto dwmac_mux;
1059 }
1060 } else {
1061 ret = sun8i_dwmac_reset(priv);
1062 if (ret)
1063 goto dwmac_exit;
1064 }
1065
1066 return ret;
1067dwmac_mux:
1068 sun8i_dwmac_unset_syscon(gmac);
1069dwmac_exit:
1070 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
1071return ret;
1072}
1073
1074static const struct of_device_id sun8i_dwmac_match[] = {
1075 { .compatible = "allwinner,sun8i-h3-emac",
1076 .data = &emac_variant_h3 },
1077 { .compatible = "allwinner,sun8i-v3s-emac",
1078 .data = &emac_variant_v3s },
1079 { .compatible = "allwinner,sun8i-a83t-emac",
1080 .data = &emac_variant_a83t },
1081 { .compatible = "allwinner,sun50i-a64-emac",
1082 .data = &emac_variant_a64 },
1083 { }
1084};
1085MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
1086
1087static struct platform_driver sun8i_dwmac_driver = {
1088 .probe = sun8i_dwmac_probe,
1089 .remove = stmmac_pltfr_remove,
1090 .driver = {
1091 .name = "dwmac-sun8i",
1092 .pm = &stmmac_pltfr_pm_ops,
1093 .of_match_table = sun8i_dwmac_match,
1094 },
1095};
1096module_platform_driver(sun8i_dwmac_driver);
1097
1098MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1099MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1100MODULE_LICENSE("GPL");