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1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/random.h>
17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
21#include "farch_regs.h"
22#include "io.h"
23#include "workarounds.h"
24#include "mcdi.h"
25#include "mcdi_pcol.h"
26#include "selftest.h"
27#include "siena_sriov.h"
28
29/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
30
31static void siena_init_wol(struct efx_nic *efx);
32
33
34static void siena_push_irq_moderation(struct efx_channel *channel)
35{
36 struct efx_nic *efx = channel->efx;
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation_us) {
40 unsigned int ticks;
41
42 ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us);
43 EFX_POPULATE_DWORD_2(timer_cmd,
44 FRF_CZ_TC_TIMER_MODE,
45 FFE_CZ_TIMER_MODE_INT_HLDOFF,
46 FRF_CZ_TC_TIMER_VAL,
47 ticks - 1);
48 } else {
49 EFX_POPULATE_DWORD_2(timer_cmd,
50 FRF_CZ_TC_TIMER_MODE,
51 FFE_CZ_TIMER_MODE_DIS,
52 FRF_CZ_TC_TIMER_VAL, 0);
53 }
54 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
55 channel->channel);
56}
57
58void siena_prepare_flush(struct efx_nic *efx)
59{
60 if (efx->fc_disable++ == 0)
61 efx_mcdi_set_mac(efx);
62}
63
64void siena_finish_flush(struct efx_nic *efx)
65{
66 if (--efx->fc_disable == 0)
67 efx_mcdi_set_mac(efx);
68}
69
70static const struct efx_farch_register_test siena_register_tests[] = {
71 { FR_AZ_ADR_REGION,
72 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
73 { FR_CZ_USR_EV_CFG,
74 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
75 { FR_AZ_RX_CFG,
76 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
77 { FR_AZ_TX_CFG,
78 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
79 { FR_AZ_TX_RESERVED,
80 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
81 { FR_AZ_SRM_TX_DC_CFG,
82 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
83 { FR_AZ_RX_DC_CFG,
84 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
85 { FR_AZ_RX_DC_PF_WM,
86 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
87 { FR_BZ_DP_CTRL,
88 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
89 { FR_BZ_RX_RSS_TKEY,
90 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
91 { FR_CZ_RX_RSS_IPV6_REG1,
92 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
93 { FR_CZ_RX_RSS_IPV6_REG2,
94 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
95 { FR_CZ_RX_RSS_IPV6_REG3,
96 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
97};
98
99static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
100{
101 enum reset_type reset_method = RESET_TYPE_ALL;
102 int rc, rc2;
103
104 efx_reset_down(efx, reset_method);
105
106 /* Reset the chip immediately so that it is completely
107 * quiescent regardless of what any VF driver does.
108 */
109 rc = efx_mcdi_reset(efx, reset_method);
110 if (rc)
111 goto out;
112
113 tests->registers =
114 efx_farch_test_registers(efx, siena_register_tests,
115 ARRAY_SIZE(siena_register_tests))
116 ? -1 : 1;
117
118 rc = efx_mcdi_reset(efx, reset_method);
119out:
120 rc2 = efx_reset_up(efx, reset_method, rc == 0);
121 return rc ? rc : rc2;
122}
123
124/**************************************************************************
125 *
126 * PTP
127 *
128 **************************************************************************
129 */
130
131static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
132{
133 _efx_writed(efx, cpu_to_le32(host_time),
134 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
135}
136
137static int siena_ptp_set_ts_config(struct efx_nic *efx,
138 struct hwtstamp_config *init)
139{
140 int rc;
141
142 switch (init->rx_filter) {
143 case HWTSTAMP_FILTER_NONE:
144 /* if TX timestamping is still requested then leave PTP on */
145 return efx_ptp_change_mode(efx,
146 init->tx_type != HWTSTAMP_TX_OFF,
147 efx_ptp_get_mode(efx));
148 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
149 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
150 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
151 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
152 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
153 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
154 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
155 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
156 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
157 rc = efx_ptp_change_mode(efx, true,
158 MC_CMD_PTP_MODE_V2_ENHANCED);
159 /* bug 33070 - old versions of the firmware do not support the
160 * improved UUID filtering option. Similarly old versions of the
161 * application do not expect it to be enabled. If the firmware
162 * does not accept the enhanced mode, fall back to the standard
163 * PTP v2 UUID filtering. */
164 if (rc != 0)
165 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
166 return rc;
167 default:
168 return -ERANGE;
169 }
170}
171
172/**************************************************************************
173 *
174 * Device reset
175 *
176 **************************************************************************
177 */
178
179static int siena_map_reset_flags(u32 *flags)
180{
181 enum {
182 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
183 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
184 ETH_RESET_PHY),
185 SIENA_RESET_MC = (SIENA_RESET_PORT |
186 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
187 };
188
189 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
190 *flags &= ~SIENA_RESET_MC;
191 return RESET_TYPE_WORLD;
192 }
193
194 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
195 *flags &= ~SIENA_RESET_PORT;
196 return RESET_TYPE_ALL;
197 }
198
199 /* no invisible reset implemented */
200
201 return -EINVAL;
202}
203
204#ifdef CONFIG_EEH
205/* When a PCI device is isolated from the bus, a subsequent MMIO read is
206 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
207 * was written to minimise MMIO read (for latency) then a periodic call to check
208 * the EEH status of the device is required so that device recovery can happen
209 * in a timely fashion.
210 */
211static void siena_monitor(struct efx_nic *efx)
212{
213 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
214
215 eeh_dev_check_failure(eehdev);
216}
217#endif
218
219static int siena_probe_nvconfig(struct efx_nic *efx)
220{
221 u32 caps = 0;
222 int rc;
223
224 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
225
226 efx->timer_quantum_ns =
227 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
228 3072 : 6144; /* 768 cycles */
229 efx->timer_max_ns = efx->type->timer_period_max *
230 efx->timer_quantum_ns;
231
232 return rc;
233}
234
235static int siena_dimension_resources(struct efx_nic *efx)
236{
237 /* Each port has a small block of internal SRAM dedicated to
238 * the buffer table and descriptor caches. In theory we can
239 * map both blocks to one port, but we don't.
240 */
241 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
242 return 0;
243}
244
245/* On all Falcon-architecture NICs, PFs use BAR 0 for I/O space and BAR 2(&3)
246 * for memory.
247 */
248static unsigned int siena_mem_bar(struct efx_nic *efx)
249{
250 return 2;
251}
252
253static unsigned int siena_mem_map_size(struct efx_nic *efx)
254{
255 return FR_CZ_MC_TREG_SMEM +
256 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
257}
258
259static int siena_probe_nic(struct efx_nic *efx)
260{
261 struct siena_nic_data *nic_data;
262 efx_oword_t reg;
263 int rc;
264
265 /* Allocate storage for hardware specific data */
266 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
267 if (!nic_data)
268 return -ENOMEM;
269 nic_data->efx = efx;
270 efx->nic_data = nic_data;
271
272 if (efx_farch_fpga_ver(efx) != 0) {
273 netif_err(efx, probe, efx->net_dev,
274 "Siena FPGA not supported\n");
275 rc = -ENODEV;
276 goto fail1;
277 }
278
279 efx->max_channels = EFX_MAX_CHANNELS;
280 efx->max_tx_channels = EFX_MAX_CHANNELS;
281
282 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
283 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
284
285 rc = efx_mcdi_init(efx);
286 if (rc)
287 goto fail1;
288
289 /* Now we can reset the NIC */
290 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
291 if (rc) {
292 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
293 goto fail3;
294 }
295
296 siena_init_wol(efx);
297
298 /* Allocate memory for INT_KER */
299 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
300 GFP_KERNEL);
301 if (rc)
302 goto fail4;
303 BUG_ON(efx->irq_status.dma_addr & 0x0f);
304
305 netif_dbg(efx, probe, efx->net_dev,
306 "INT_KER at %llx (virt %p phys %llx)\n",
307 (unsigned long long)efx->irq_status.dma_addr,
308 efx->irq_status.addr,
309 (unsigned long long)virt_to_phys(efx->irq_status.addr));
310
311 /* Read in the non-volatile configuration */
312 rc = siena_probe_nvconfig(efx);
313 if (rc == -EINVAL) {
314 netif_err(efx, probe, efx->net_dev,
315 "NVRAM is invalid therefore using defaults\n");
316 efx->phy_type = PHY_TYPE_NONE;
317 efx->mdio.prtad = MDIO_PRTAD_NONE;
318 } else if (rc) {
319 goto fail5;
320 }
321
322 rc = efx_mcdi_mon_probe(efx);
323 if (rc)
324 goto fail5;
325
326#ifdef CONFIG_SFC_SRIOV
327 efx_siena_sriov_probe(efx);
328#endif
329 efx_ptp_defer_probe_with_channel(efx);
330
331 return 0;
332
333fail5:
334 efx_nic_free_buffer(efx, &efx->irq_status);
335fail4:
336fail3:
337 efx_mcdi_detach(efx);
338 efx_mcdi_fini(efx);
339fail1:
340 kfree(efx->nic_data);
341 return rc;
342}
343
344static int siena_rx_pull_rss_config(struct efx_nic *efx)
345{
346 efx_oword_t temp;
347
348 /* Read from IPv6 RSS key as that's longer (the IPv4 key is just the
349 * first 128 bits of the same key, assuming it's been set by
350 * siena_rx_push_rss_config, below)
351 */
352 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
353 memcpy(efx->rss_context.rx_hash_key, &temp, sizeof(temp));
354 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
355 memcpy(efx->rss_context.rx_hash_key + sizeof(temp), &temp, sizeof(temp));
356 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
357 memcpy(efx->rss_context.rx_hash_key + 2 * sizeof(temp), &temp,
358 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
359 efx_farch_rx_pull_indir_table(efx);
360 return 0;
361}
362
363static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
364 const u32 *rx_indir_table, const u8 *key)
365{
366 efx_oword_t temp;
367
368 /* Set hash key for IPv4 */
369 if (key)
370 memcpy(efx->rss_context.rx_hash_key, key, sizeof(temp));
371 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
372 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
373
374 /* Enable IPv6 RSS */
375 BUILD_BUG_ON(sizeof(efx->rss_context.rx_hash_key) <
376 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
377 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
378 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
379 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
380 memcpy(&temp, efx->rss_context.rx_hash_key + sizeof(temp), sizeof(temp));
381 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
382 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
383 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
384 memcpy(&temp, efx->rss_context.rx_hash_key + 2 * sizeof(temp),
385 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
386 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
387
388 memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
389 sizeof(efx->rss_context.rx_indir_table));
390 efx_farch_rx_push_indir_table(efx);
391
392 return 0;
393}
394
395/* This call performs hardware-specific global initialisation, such as
396 * defining the descriptor cache sizes and number of RSS channels.
397 * It does not set up any buffers, descriptor rings or event queues.
398 */
399static int siena_init_nic(struct efx_nic *efx)
400{
401 efx_oword_t temp;
402 int rc;
403
404 /* Recover from a failed assertion post-reset */
405 rc = efx_mcdi_handle_assertion(efx);
406 if (rc)
407 return rc;
408
409 /* Squash TX of packets of 16 bytes or less */
410 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
411 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
412 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
413
414 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
415 * descriptors (which is bad).
416 */
417 efx_reado(efx, &temp, FR_AZ_TX_CFG);
418 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
419 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
420 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
421
422 efx_reado(efx, &temp, FR_AZ_RX_CFG);
423 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
424 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
425 /* Enable hash insertion. This is broken for the 'Falcon' hash
426 * if IPv6 hashing is also enabled, so also select Toeplitz
427 * TCP/IPv4 and IPv4 hashes. */
428 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
429 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
430 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
431 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
432 EFX_RX_USR_BUF_SIZE >> 5);
433 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
434
435 siena_rx_push_rss_config(efx, false, efx->rss_context.rx_indir_table, NULL);
436 efx->rss_context.context_id = 0; /* indicates RSS is active */
437
438 /* Enable event logging */
439 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
440 if (rc)
441 return rc;
442
443 /* Set destination of both TX and RX Flush events */
444 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
445 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
446
447 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
448 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
449
450 efx_farch_init_common(efx);
451 return 0;
452}
453
454static void siena_remove_nic(struct efx_nic *efx)
455{
456 efx_mcdi_mon_remove(efx);
457
458 efx_nic_free_buffer(efx, &efx->irq_status);
459
460 efx_mcdi_reset(efx, RESET_TYPE_ALL);
461
462 efx_mcdi_detach(efx);
463 efx_mcdi_fini(efx);
464
465 /* Tear down the private nic state */
466 kfree(efx->nic_data);
467 efx->nic_data = NULL;
468}
469
470#define SIENA_DMA_STAT(ext_name, mcdi_name) \
471 [SIENA_STAT_ ## ext_name] = \
472 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
473#define SIENA_OTHER_STAT(ext_name) \
474 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
475#define GENERIC_SW_STAT(ext_name) \
476 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
477
478static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
479 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
480 SIENA_OTHER_STAT(tx_good_bytes),
481 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
482 SIENA_DMA_STAT(tx_packets, TX_PKTS),
483 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
484 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
485 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
486 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
487 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
488 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
489 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
490 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
491 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
492 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
493 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
494 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
495 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
496 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
497 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
498 SIENA_OTHER_STAT(tx_collision),
499 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
500 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
501 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
502 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
503 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
504 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
505 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
506 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
507 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
508 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
509 SIENA_OTHER_STAT(rx_good_bytes),
510 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
511 SIENA_DMA_STAT(rx_packets, RX_PKTS),
512 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
513 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
514 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
515 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
516 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
517 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
518 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
519 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
520 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
521 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
522 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
523 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
524 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
525 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
526 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
527 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
528 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
529 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
530 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
531 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
532 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
533 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
534 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
535 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
536 GENERIC_SW_STAT(rx_nodesc_trunc),
537 GENERIC_SW_STAT(rx_noskb_drops),
538};
539static const unsigned long siena_stat_mask[] = {
540 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
541};
542
543static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
544{
545 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
546 siena_stat_mask, names);
547}
548
549static int siena_try_update_nic_stats(struct efx_nic *efx)
550{
551 struct siena_nic_data *nic_data = efx->nic_data;
552 u64 *stats = nic_data->stats;
553 __le64 *dma_stats;
554 __le64 generation_start, generation_end;
555
556 dma_stats = efx->stats_buffer.addr;
557
558 generation_end = dma_stats[efx->num_mac_stats - 1];
559 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
560 return 0;
561 rmb();
562 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
563 stats, efx->stats_buffer.addr, false);
564 rmb();
565 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
566 if (generation_end != generation_start)
567 return -EAGAIN;
568
569 /* Update derived statistics */
570 efx_nic_fix_nodesc_drop_stat(efx,
571 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
572 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
573 stats[SIENA_STAT_tx_bytes] -
574 stats[SIENA_STAT_tx_bad_bytes]);
575 stats[SIENA_STAT_tx_collision] =
576 stats[SIENA_STAT_tx_single_collision] +
577 stats[SIENA_STAT_tx_multiple_collision] +
578 stats[SIENA_STAT_tx_excessive_collision] +
579 stats[SIENA_STAT_tx_late_collision];
580 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
581 stats[SIENA_STAT_rx_bytes] -
582 stats[SIENA_STAT_rx_bad_bytes]);
583 efx_update_sw_stats(efx, stats);
584 return 0;
585}
586
587static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
588 struct rtnl_link_stats64 *core_stats)
589{
590 struct siena_nic_data *nic_data = efx->nic_data;
591 u64 *stats = nic_data->stats;
592 int retry;
593
594 /* If we're unlucky enough to read statistics wduring the DMA, wait
595 * up to 10ms for it to finish (typically takes <500us) */
596 for (retry = 0; retry < 100; ++retry) {
597 if (siena_try_update_nic_stats(efx) == 0)
598 break;
599 udelay(100);
600 }
601
602 if (full_stats)
603 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
604
605 if (core_stats) {
606 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
607 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
608 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
609 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
610 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
611 stats[GENERIC_STAT_rx_nodesc_trunc] +
612 stats[GENERIC_STAT_rx_noskb_drops];
613 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
614 core_stats->collisions = stats[SIENA_STAT_tx_collision];
615 core_stats->rx_length_errors =
616 stats[SIENA_STAT_rx_gtjumbo] +
617 stats[SIENA_STAT_rx_length_error];
618 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
619 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
620 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
621 core_stats->tx_window_errors =
622 stats[SIENA_STAT_tx_late_collision];
623
624 core_stats->rx_errors = (core_stats->rx_length_errors +
625 core_stats->rx_crc_errors +
626 core_stats->rx_frame_errors +
627 stats[SIENA_STAT_rx_symbol_error]);
628 core_stats->tx_errors = (core_stats->tx_window_errors +
629 stats[SIENA_STAT_tx_bad]);
630 }
631
632 return SIENA_STAT_COUNT;
633}
634
635static int siena_mac_reconfigure(struct efx_nic *efx)
636{
637 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
638 int rc;
639
640 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
641 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
642 sizeof(efx->multicast_hash));
643
644 efx_farch_filter_sync_rx_mode(efx);
645
646 WARN_ON(!mutex_is_locked(&efx->mac_lock));
647
648 rc = efx_mcdi_set_mac(efx);
649 if (rc != 0)
650 return rc;
651
652 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
653 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
654 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
655 inbuf, sizeof(inbuf), NULL, 0, NULL);
656}
657
658/**************************************************************************
659 *
660 * Wake on LAN
661 *
662 **************************************************************************
663 */
664
665static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
666{
667 struct siena_nic_data *nic_data = efx->nic_data;
668
669 wol->supported = WAKE_MAGIC;
670 if (nic_data->wol_filter_id != -1)
671 wol->wolopts = WAKE_MAGIC;
672 else
673 wol->wolopts = 0;
674 memset(&wol->sopass, 0, sizeof(wol->sopass));
675}
676
677
678static int siena_set_wol(struct efx_nic *efx, u32 type)
679{
680 struct siena_nic_data *nic_data = efx->nic_data;
681 int rc;
682
683 if (type & ~WAKE_MAGIC)
684 return -EINVAL;
685
686 if (type & WAKE_MAGIC) {
687 if (nic_data->wol_filter_id != -1)
688 efx_mcdi_wol_filter_remove(efx,
689 nic_data->wol_filter_id);
690 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
691 &nic_data->wol_filter_id);
692 if (rc)
693 goto fail;
694
695 pci_wake_from_d3(efx->pci_dev, true);
696 } else {
697 rc = efx_mcdi_wol_filter_reset(efx);
698 nic_data->wol_filter_id = -1;
699 pci_wake_from_d3(efx->pci_dev, false);
700 if (rc)
701 goto fail;
702 }
703
704 return 0;
705 fail:
706 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
707 __func__, type, rc);
708 return rc;
709}
710
711
712static void siena_init_wol(struct efx_nic *efx)
713{
714 struct siena_nic_data *nic_data = efx->nic_data;
715 int rc;
716
717 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
718
719 if (rc != 0) {
720 /* If it failed, attempt to get into a synchronised
721 * state with MC by resetting any set WoL filters */
722 efx_mcdi_wol_filter_reset(efx);
723 nic_data->wol_filter_id = -1;
724 } else if (nic_data->wol_filter_id != -1) {
725 pci_wake_from_d3(efx->pci_dev, true);
726 }
727}
728
729/**************************************************************************
730 *
731 * MCDI
732 *
733 **************************************************************************
734 */
735
736#define MCDI_PDU(efx) \
737 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
738#define MCDI_DOORBELL(efx) \
739 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
740#define MCDI_STATUS(efx) \
741 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
742
743static void siena_mcdi_request(struct efx_nic *efx,
744 const efx_dword_t *hdr, size_t hdr_len,
745 const efx_dword_t *sdu, size_t sdu_len)
746{
747 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
748 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
749 unsigned int i;
750 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
751
752 EFX_WARN_ON_PARANOID(hdr_len != 4);
753
754 efx_writed(efx, hdr, pdu);
755
756 for (i = 0; i < inlen_dw; i++)
757 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
758
759 /* Ensure the request is written out before the doorbell */
760 wmb();
761
762 /* ring the doorbell with a distinctive value */
763 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
764}
765
766static bool siena_mcdi_poll_response(struct efx_nic *efx)
767{
768 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
769 efx_dword_t hdr;
770
771 efx_readd(efx, &hdr, pdu);
772
773 /* All 1's indicates that shared memory is in reset (and is
774 * not a valid hdr). Wait for it to come out reset before
775 * completing the command
776 */
777 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
778 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
779}
780
781static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
782 size_t offset, size_t outlen)
783{
784 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
785 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
786 int i;
787
788 for (i = 0; i < outlen_dw; i++)
789 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
790}
791
792static int siena_mcdi_poll_reboot(struct efx_nic *efx)
793{
794 struct siena_nic_data *nic_data = efx->nic_data;
795 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
796 efx_dword_t reg;
797 u32 value;
798
799 efx_readd(efx, ®, addr);
800 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
801
802 if (value == 0)
803 return 0;
804
805 EFX_ZERO_DWORD(reg);
806 efx_writed(efx, ®, addr);
807
808 /* MAC statistics have been cleared on the NIC; clear the local
809 * copies that we update with efx_update_diff_stat().
810 */
811 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
812 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
813
814 if (value == MC_STATUS_DWORD_ASSERT)
815 return -EINTR;
816 else
817 return -EIO;
818}
819
820/**************************************************************************
821 *
822 * MTD
823 *
824 **************************************************************************
825 */
826
827#ifdef CONFIG_SFC_MTD
828
829struct siena_nvram_type_info {
830 int port;
831 const char *name;
832};
833
834static const struct siena_nvram_type_info siena_nvram_types[] = {
835 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
836 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
837 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
838 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
839 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
840 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
841 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
842 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
843 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
844 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
845 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
846 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
847 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
848};
849
850static int siena_mtd_probe_partition(struct efx_nic *efx,
851 struct efx_mcdi_mtd_partition *part,
852 unsigned int type)
853{
854 const struct siena_nvram_type_info *info;
855 size_t size, erase_size;
856 bool protected;
857 int rc;
858
859 if (type >= ARRAY_SIZE(siena_nvram_types) ||
860 siena_nvram_types[type].name == NULL)
861 return -ENODEV;
862
863 info = &siena_nvram_types[type];
864
865 if (info->port != efx_port_num(efx))
866 return -ENODEV;
867
868 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
869 if (rc)
870 return rc;
871 if (protected)
872 return -ENODEV; /* hide it */
873
874 part->nvram_type = type;
875 part->common.dev_type_name = "Siena NVRAM manager";
876 part->common.type_name = info->name;
877
878 part->common.mtd.type = MTD_NORFLASH;
879 part->common.mtd.flags = MTD_CAP_NORFLASH;
880 part->common.mtd.size = size;
881 part->common.mtd.erasesize = erase_size;
882
883 return 0;
884}
885
886static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
887 struct efx_mcdi_mtd_partition *parts,
888 size_t n_parts)
889{
890 uint16_t fw_subtype_list[
891 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
892 size_t i;
893 int rc;
894
895 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
896 if (rc)
897 return rc;
898
899 for (i = 0; i < n_parts; i++)
900 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
901
902 return 0;
903}
904
905static int siena_mtd_probe(struct efx_nic *efx)
906{
907 struct efx_mcdi_mtd_partition *parts;
908 u32 nvram_types;
909 unsigned int type;
910 size_t n_parts;
911 int rc;
912
913 ASSERT_RTNL();
914
915 rc = efx_mcdi_nvram_types(efx, &nvram_types);
916 if (rc)
917 return rc;
918
919 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
920 if (!parts)
921 return -ENOMEM;
922
923 type = 0;
924 n_parts = 0;
925
926 while (nvram_types != 0) {
927 if (nvram_types & 1) {
928 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
929 type);
930 if (rc == 0)
931 n_parts++;
932 else if (rc != -ENODEV)
933 goto fail;
934 }
935 type++;
936 nvram_types >>= 1;
937 }
938
939 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
940 if (rc)
941 goto fail;
942
943 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
944fail:
945 if (rc)
946 kfree(parts);
947 return rc;
948}
949
950#endif /* CONFIG_SFC_MTD */
951
952/**************************************************************************
953 *
954 * Revision-dependent attributes used by efx.c and nic.c
955 *
956 **************************************************************************
957 */
958
959const struct efx_nic_type siena_a0_nic_type = {
960 .is_vf = false,
961 .mem_bar = siena_mem_bar,
962 .mem_map_size = siena_mem_map_size,
963 .probe = siena_probe_nic,
964 .remove = siena_remove_nic,
965 .init = siena_init_nic,
966 .dimension_resources = siena_dimension_resources,
967 .fini = efx_port_dummy_op_void,
968#ifdef CONFIG_EEH
969 .monitor = siena_monitor,
970#else
971 .monitor = NULL,
972#endif
973 .map_reset_reason = efx_mcdi_map_reset_reason,
974 .map_reset_flags = siena_map_reset_flags,
975 .reset = efx_mcdi_reset,
976 .probe_port = efx_mcdi_port_probe,
977 .remove_port = efx_mcdi_port_remove,
978 .fini_dmaq = efx_farch_fini_dmaq,
979 .prepare_flush = siena_prepare_flush,
980 .finish_flush = siena_finish_flush,
981 .prepare_flr = efx_port_dummy_op_void,
982 .finish_flr = efx_farch_finish_flr,
983 .describe_stats = siena_describe_nic_stats,
984 .update_stats = siena_update_nic_stats,
985 .start_stats = efx_mcdi_mac_start_stats,
986 .pull_stats = efx_mcdi_mac_pull_stats,
987 .stop_stats = efx_mcdi_mac_stop_stats,
988 .set_id_led = efx_mcdi_set_id_led,
989 .push_irq_moderation = siena_push_irq_moderation,
990 .reconfigure_mac = siena_mac_reconfigure,
991 .check_mac_fault = efx_mcdi_mac_check_fault,
992 .reconfigure_port = efx_mcdi_port_reconfigure,
993 .get_wol = siena_get_wol,
994 .set_wol = siena_set_wol,
995 .resume_wol = siena_init_wol,
996 .test_chip = siena_test_chip,
997 .test_nvram = efx_mcdi_nvram_test_all,
998 .mcdi_request = siena_mcdi_request,
999 .mcdi_poll_response = siena_mcdi_poll_response,
1000 .mcdi_read_response = siena_mcdi_read_response,
1001 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
1002 .irq_enable_master = efx_farch_irq_enable_master,
1003 .irq_test_generate = efx_farch_irq_test_generate,
1004 .irq_disable_non_ev = efx_farch_irq_disable_master,
1005 .irq_handle_msi = efx_farch_msi_interrupt,
1006 .irq_handle_legacy = efx_farch_legacy_interrupt,
1007 .tx_probe = efx_farch_tx_probe,
1008 .tx_init = efx_farch_tx_init,
1009 .tx_remove = efx_farch_tx_remove,
1010 .tx_write = efx_farch_tx_write,
1011 .tx_limit_len = efx_farch_tx_limit_len,
1012 .rx_push_rss_config = siena_rx_push_rss_config,
1013 .rx_pull_rss_config = siena_rx_pull_rss_config,
1014 .rx_probe = efx_farch_rx_probe,
1015 .rx_init = efx_farch_rx_init,
1016 .rx_remove = efx_farch_rx_remove,
1017 .rx_write = efx_farch_rx_write,
1018 .rx_defer_refill = efx_farch_rx_defer_refill,
1019 .ev_probe = efx_farch_ev_probe,
1020 .ev_init = efx_farch_ev_init,
1021 .ev_fini = efx_farch_ev_fini,
1022 .ev_remove = efx_farch_ev_remove,
1023 .ev_process = efx_farch_ev_process,
1024 .ev_read_ack = efx_farch_ev_read_ack,
1025 .ev_test_generate = efx_farch_ev_test_generate,
1026 .filter_table_probe = efx_farch_filter_table_probe,
1027 .filter_table_restore = efx_farch_filter_table_restore,
1028 .filter_table_remove = efx_farch_filter_table_remove,
1029 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
1030 .filter_insert = efx_farch_filter_insert,
1031 .filter_remove_safe = efx_farch_filter_remove_safe,
1032 .filter_get_safe = efx_farch_filter_get_safe,
1033 .filter_clear_rx = efx_farch_filter_clear_rx,
1034 .filter_count_rx_used = efx_farch_filter_count_rx_used,
1035 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
1036 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
1037#ifdef CONFIG_RFS_ACCEL
1038 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
1039#endif
1040#ifdef CONFIG_SFC_MTD
1041 .mtd_probe = siena_mtd_probe,
1042 .mtd_rename = efx_mcdi_mtd_rename,
1043 .mtd_read = efx_mcdi_mtd_read,
1044 .mtd_erase = efx_mcdi_mtd_erase,
1045 .mtd_write = efx_mcdi_mtd_write,
1046 .mtd_sync = efx_mcdi_mtd_sync,
1047#endif
1048 .ptp_write_host_time = siena_ptp_write_host_time,
1049 .ptp_set_ts_config = siena_ptp_set_ts_config,
1050#ifdef CONFIG_SFC_SRIOV
1051 .sriov_configure = efx_siena_sriov_configure,
1052 .sriov_init = efx_siena_sriov_init,
1053 .sriov_fini = efx_siena_sriov_fini,
1054 .sriov_wanted = efx_siena_sriov_wanted,
1055 .sriov_reset = efx_siena_sriov_reset,
1056 .sriov_flr = efx_siena_sriov_flr,
1057 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1058 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1059 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1060 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1061 .vswitching_probe = efx_port_dummy_op_int,
1062 .vswitching_restore = efx_port_dummy_op_int,
1063 .vswitching_remove = efx_port_dummy_op_void,
1064 .set_mac_address = efx_siena_sriov_mac_address_changed,
1065#endif
1066
1067 .revision = EFX_REV_SIENA_A0,
1068 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1069 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1070 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1071 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1072 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1073 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1074 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1075 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1076 .rx_buffer_padding = 0,
1077 .can_rx_scatter = true,
1078 .option_descriptors = false,
1079 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
1080 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1081 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1082 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1083 NETIF_F_RXHASH | NETIF_F_NTUPLE),
1084 .mcdi_max_ver = 1,
1085 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1086 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1087 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1088 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
1089 .rx_hash_key_size = 16,
1090};