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1// SPDX-License-Identifier: GPL-2.0-only
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2007-2011 Solarflare Communications Inc.
5 */
6
7#include <linux/delay.h>
8#include <linux/rtnetlink.h>
9#include <linux/seq_file.h>
10#include <linux/slab.h>
11#include "efx.h"
12#include "mdio_10g.h"
13#include "nic.h"
14#include "phy.h"
15#include "workarounds.h"
16
17/* We expect these MMDs to be in the package. */
18#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
19 MDIO_DEVS_PCS | \
20 MDIO_DEVS_PHYXS | \
21 MDIO_DEVS_AN)
22
23#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
24 (1 << LOOPBACK_PCS) | \
25 (1 << LOOPBACK_PMAPMD) | \
26 (1 << LOOPBACK_PHYXS_WS))
27
28/* We complain if we fail to see the link partner as 10G capable this many
29 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
30 */
31#define MAX_BAD_LP_TRIES (5)
32
33/* Extended control register */
34#define PMA_PMD_XCONTROL_REG 49152
35#define PMA_PMD_EXT_GMII_EN_LBN 1
36#define PMA_PMD_EXT_GMII_EN_WIDTH 1
37#define PMA_PMD_EXT_CLK_OUT_LBN 2
38#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
39#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
40#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
41#define PMA_PMD_EXT_CLK312_WIDTH 1
42#define PMA_PMD_EXT_LPOWER_LBN 12
43#define PMA_PMD_EXT_LPOWER_WIDTH 1
44#define PMA_PMD_EXT_ROBUST_LBN 14
45#define PMA_PMD_EXT_ROBUST_WIDTH 1
46#define PMA_PMD_EXT_SSR_LBN 15
47#define PMA_PMD_EXT_SSR_WIDTH 1
48
49/* extended status register */
50#define PMA_PMD_XSTATUS_REG 49153
51#define PMA_PMD_XSTAT_MDIX_LBN 14
52#define PMA_PMD_XSTAT_FLP_LBN (12)
53
54/* LED control register */
55#define PMA_PMD_LED_CTRL_REG 49159
56#define PMA_PMA_LED_ACTIVITY_LBN (3)
57
58/* LED function override register */
59#define PMA_PMD_LED_OVERR_REG 49161
60/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
61#define PMA_PMD_LED_LINK_LBN (0)
62#define PMA_PMD_LED_SPEED_LBN (2)
63#define PMA_PMD_LED_TX_LBN (4)
64#define PMA_PMD_LED_RX_LBN (6)
65/* Override settings */
66#define PMA_PMD_LED_AUTO (0) /* H/W control */
67#define PMA_PMD_LED_ON (1)
68#define PMA_PMD_LED_OFF (2)
69#define PMA_PMD_LED_FLASH (3)
70#define PMA_PMD_LED_MASK 3
71/* All LEDs under hardware control */
72/* Green and Amber under hardware control, Red off */
73#define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
74
75#define PMA_PMD_SPEED_ENABLE_REG 49192
76#define PMA_PMD_100TX_ADV_LBN 1
77#define PMA_PMD_100TX_ADV_WIDTH 1
78#define PMA_PMD_1000T_ADV_LBN 2
79#define PMA_PMD_1000T_ADV_WIDTH 1
80#define PMA_PMD_10000T_ADV_LBN 3
81#define PMA_PMD_10000T_ADV_WIDTH 1
82#define PMA_PMD_SPEED_LBN 4
83#define PMA_PMD_SPEED_WIDTH 4
84
85/* Misc register defines */
86#define PCS_CLOCK_CTRL_REG 55297
87#define PLL312_RST_N_LBN 2
88
89#define PCS_SOFT_RST2_REG 55302
90#define SERDES_RST_N_LBN 13
91#define XGXS_RST_N_LBN 12
92
93#define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
94#define CLK312_EN_LBN 3
95
96/* PHYXS registers */
97#define PHYXS_XCONTROL_REG 49152
98#define PHYXS_RESET_LBN 15
99#define PHYXS_RESET_WIDTH 1
100
101#define PHYXS_TEST1 (49162)
102#define LOOPBACK_NEAR_LBN (8)
103#define LOOPBACK_NEAR_WIDTH (1)
104
105/* Boot status register */
106#define PCS_BOOT_STATUS_REG 53248
107#define PCS_BOOT_FATAL_ERROR_LBN 0
108#define PCS_BOOT_PROGRESS_LBN 1
109#define PCS_BOOT_PROGRESS_WIDTH 2
110#define PCS_BOOT_PROGRESS_INIT 0
111#define PCS_BOOT_PROGRESS_WAIT_MDIO 1
112#define PCS_BOOT_PROGRESS_CHECKSUM 2
113#define PCS_BOOT_PROGRESS_JUMP 3
114#define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
115#define PCS_BOOT_CODE_STARTED_LBN 4
116
117/* 100M/1G PHY registers */
118#define GPHY_XCONTROL_REG 49152
119#define GPHY_ISOLATE_LBN 10
120#define GPHY_ISOLATE_WIDTH 1
121#define GPHY_DUPLEX_LBN 8
122#define GPHY_DUPLEX_WIDTH 1
123#define GPHY_LOOPBACK_NEAR_LBN 14
124#define GPHY_LOOPBACK_NEAR_WIDTH 1
125
126#define C22EXT_STATUS_REG 49153
127#define C22EXT_STATUS_LINK_LBN 2
128#define C22EXT_STATUS_LINK_WIDTH 1
129
130#define C22EXT_MSTSLV_CTRL 49161
131#define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
132#define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
133
134#define C22EXT_MSTSLV_STATUS 49162
135#define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
136#define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
137
138/* Time to wait between powering down the LNPGA and turning off the power
139 * rails */
140#define LNPGA_PDOWN_WAIT (HZ / 5)
141
142struct tenxpress_phy_data {
143 enum ef4_loopback_mode loopback_mode;
144 enum ef4_phy_mode phy_mode;
145 int bad_lp_tries;
146};
147
148static int tenxpress_init(struct ef4_nic *efx)
149{
150 /* Enable 312.5 MHz clock */
151 ef4_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
152 1 << CLK312_EN_LBN);
153
154 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
155 ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
156 1 << PMA_PMA_LED_ACTIVITY_LBN, true);
157 ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
158 SFX7101_PMA_PMD_LED_DEFAULT);
159
160 return 0;
161}
162
163static int tenxpress_phy_probe(struct ef4_nic *efx)
164{
165 struct tenxpress_phy_data *phy_data;
166
167 /* Allocate phy private storage */
168 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
169 if (!phy_data)
170 return -ENOMEM;
171 efx->phy_data = phy_data;
172 phy_data->phy_mode = efx->phy_mode;
173
174 efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
175 efx->mdio.mode_support = MDIO_SUPPORTS_C45;
176
177 efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
178
179 efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg |
180 ADVERTISED_10000baseT_Full);
181
182 return 0;
183}
184
185static int tenxpress_phy_init(struct ef4_nic *efx)
186{
187 int rc;
188
189 falcon_board(efx)->type->init_phy(efx);
190
191 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
192 rc = ef4_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
193 if (rc < 0)
194 return rc;
195
196 rc = ef4_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS);
197 if (rc < 0)
198 return rc;
199 }
200
201 rc = tenxpress_init(efx);
202 if (rc < 0)
203 return rc;
204
205 /* Reinitialise flow control settings */
206 ef4_link_set_wanted_fc(efx, efx->wanted_fc);
207 ef4_mdio_an_reconfigure(efx);
208
209 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
210
211 /* Let XGXS and SerDes out of reset */
212 falcon_reset_xaui(efx);
213
214 return 0;
215}
216
217/* Perform a "special software reset" on the PHY. The caller is
218 * responsible for saving and restoring the PHY hardware registers
219 * properly, and masking/unmasking LASI */
220static int tenxpress_special_reset(struct ef4_nic *efx)
221{
222 int rc, reg;
223
224 /* The XGMAC clock is driven from the SFX7101 312MHz clock, so
225 * a special software reset can glitch the XGMAC sufficiently for stats
226 * requests to fail. */
227 falcon_stop_nic_stats(efx);
228
229 /* Initiate reset */
230 reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
231 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
232 ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
233
234 mdelay(200);
235
236 /* Wait for the blocks to come out of reset */
237 rc = ef4_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
238 if (rc < 0)
239 goto out;
240
241 /* Try and reconfigure the device */
242 rc = tenxpress_init(efx);
243 if (rc < 0)
244 goto out;
245
246 /* Wait for the XGXS state machine to churn */
247 mdelay(10);
248out:
249 falcon_start_nic_stats(efx);
250 return rc;
251}
252
253static void sfx7101_check_bad_lp(struct ef4_nic *efx, bool link_ok)
254{
255 struct tenxpress_phy_data *pd = efx->phy_data;
256 bool bad_lp;
257 int reg;
258
259 if (link_ok) {
260 bad_lp = false;
261 } else {
262 /* Check that AN has started but not completed. */
263 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
264 if (!(reg & MDIO_AN_STAT1_LPABLE))
265 return; /* LP status is unknown */
266 bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
267 if (bad_lp)
268 pd->bad_lp_tries++;
269 }
270
271 /* Nothing to do if all is well and was previously so. */
272 if (!pd->bad_lp_tries)
273 return;
274
275 /* Use the RX (red) LED as an error indicator once we've seen AN
276 * failure several times in a row, and also log a message. */
277 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
278 reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD,
279 PMA_PMD_LED_OVERR_REG);
280 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
281 if (!bad_lp) {
282 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
283 } else {
284 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
285 netif_err(efx, link, efx->net_dev,
286 "appears to be plugged into a port"
287 " that is not 10GBASE-T capable. The PHY"
288 " supports 10GBASE-T ONLY, so no link can"
289 " be established\n");
290 }
291 ef4_mdio_write(efx, MDIO_MMD_PMAPMD,
292 PMA_PMD_LED_OVERR_REG, reg);
293 pd->bad_lp_tries = bad_lp;
294 }
295}
296
297static bool sfx7101_link_ok(struct ef4_nic *efx)
298{
299 return ef4_mdio_links_ok(efx,
300 MDIO_DEVS_PMAPMD |
301 MDIO_DEVS_PCS |
302 MDIO_DEVS_PHYXS);
303}
304
305static void tenxpress_ext_loopback(struct ef4_nic *efx)
306{
307 ef4_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
308 1 << LOOPBACK_NEAR_LBN,
309 efx->loopback_mode == LOOPBACK_PHYXS);
310}
311
312static void tenxpress_low_power(struct ef4_nic *efx)
313{
314 ef4_mdio_set_mmds_lpower(
315 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
316 TENXPRESS_REQUIRED_DEVS);
317}
318
319static int tenxpress_phy_reconfigure(struct ef4_nic *efx)
320{
321 struct tenxpress_phy_data *phy_data = efx->phy_data;
322 bool phy_mode_change, loop_reset;
323
324 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
325 phy_data->phy_mode = efx->phy_mode;
326 return 0;
327 }
328
329 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
330 phy_data->phy_mode != PHY_MODE_NORMAL);
331 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) ||
332 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
333
334 if (loop_reset || phy_mode_change) {
335 tenxpress_special_reset(efx);
336 falcon_reset_xaui(efx);
337 }
338
339 tenxpress_low_power(efx);
340 ef4_mdio_transmit_disable(efx);
341 ef4_mdio_phy_reconfigure(efx);
342 tenxpress_ext_loopback(efx);
343 ef4_mdio_an_reconfigure(efx);
344
345 phy_data->loopback_mode = efx->loopback_mode;
346 phy_data->phy_mode = efx->phy_mode;
347
348 return 0;
349}
350
351/* Poll for link state changes */
352static bool tenxpress_phy_poll(struct ef4_nic *efx)
353{
354 struct ef4_link_state old_state = efx->link_state;
355
356 efx->link_state.up = sfx7101_link_ok(efx);
357 efx->link_state.speed = 10000;
358 efx->link_state.fd = true;
359 efx->link_state.fc = ef4_mdio_get_pause(efx);
360
361 sfx7101_check_bad_lp(efx, efx->link_state.up);
362
363 return !ef4_link_state_equal(&efx->link_state, &old_state);
364}
365
366static void sfx7101_phy_fini(struct ef4_nic *efx)
367{
368 int reg;
369
370 /* Power down the LNPGA */
371 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
372 ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
373
374 /* Waiting here ensures that the board fini, which can turn
375 * off the power to the PHY, won't get run until the LNPGA
376 * powerdown has been given long enough to complete. */
377 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
378}
379
380static void tenxpress_phy_remove(struct ef4_nic *efx)
381{
382 kfree(efx->phy_data);
383 efx->phy_data = NULL;
384}
385
386
387/* Override the RX, TX and link LEDs */
388void tenxpress_set_id_led(struct ef4_nic *efx, enum ef4_led_mode mode)
389{
390 int reg;
391
392 switch (mode) {
393 case EF4_LED_OFF:
394 reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) |
395 (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
396 (PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
397 break;
398 case EF4_LED_ON:
399 reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) |
400 (PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) |
401 (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
402 break;
403 default:
404 reg = SFX7101_PMA_PMD_LED_DEFAULT;
405 break;
406 }
407
408 ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
409}
410
411static const char *const sfx7101_test_names[] = {
412 "bist"
413};
414
415static const char *sfx7101_test_name(struct ef4_nic *efx, unsigned int index)
416{
417 if (index < ARRAY_SIZE(sfx7101_test_names))
418 return sfx7101_test_names[index];
419 return NULL;
420}
421
422static int
423sfx7101_run_tests(struct ef4_nic *efx, int *results, unsigned flags)
424{
425 int rc;
426
427 if (!(flags & ETH_TEST_FL_OFFLINE))
428 return 0;
429
430 /* BIST is automatically run after a special software reset */
431 rc = tenxpress_special_reset(efx);
432 results[0] = rc ? -1 : 1;
433
434 ef4_mdio_an_reconfigure(efx);
435
436 return rc;
437}
438
439static void
440tenxpress_get_link_ksettings(struct ef4_nic *efx,
441 struct ethtool_link_ksettings *cmd)
442{
443 u32 adv = 0, lpa = 0;
444 int reg;
445
446 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
447 if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
448 adv |= ADVERTISED_10000baseT_Full;
449 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
450 if (reg & MDIO_AN_10GBT_STAT_LP10G)
451 lpa |= ADVERTISED_10000baseT_Full;
452
453 mdio45_ethtool_ksettings_get_npage(&efx->mdio, cmd, adv, lpa);
454
455 /* In loopback, the PHY automatically brings up the correct interface,
456 * but doesn't advertise the correct speed. So override it */
457 if (LOOPBACK_EXTERNAL(efx))
458 cmd->base.speed = SPEED_10000;
459}
460
461static int
462tenxpress_set_link_ksettings(struct ef4_nic *efx,
463 const struct ethtool_link_ksettings *cmd)
464{
465 if (!cmd->base.autoneg)
466 return -EINVAL;
467
468 return ef4_mdio_set_link_ksettings(efx, cmd);
469}
470
471static void sfx7101_set_npage_adv(struct ef4_nic *efx, u32 advertising)
472{
473 ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
474 MDIO_AN_10GBT_CTRL_ADV10G,
475 advertising & ADVERTISED_10000baseT_Full);
476}
477
478const struct ef4_phy_operations falcon_sfx7101_phy_ops = {
479 .probe = tenxpress_phy_probe,
480 .init = tenxpress_phy_init,
481 .reconfigure = tenxpress_phy_reconfigure,
482 .poll = tenxpress_phy_poll,
483 .fini = sfx7101_phy_fini,
484 .remove = tenxpress_phy_remove,
485 .get_link_ksettings = tenxpress_get_link_ksettings,
486 .set_link_ksettings = tenxpress_set_link_ksettings,
487 .set_npage_adv = sfx7101_set_npage_adv,
488 .test_alive = ef4_mdio_test_alive,
489 .test_name = sfx7101_test_name,
490 .run_tests = sfx7101_run_tests,
491};
1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2007-2011 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include <linux/delay.h>
11#include <linux/rtnetlink.h>
12#include <linux/seq_file.h>
13#include <linux/slab.h>
14#include "efx.h"
15#include "mdio_10g.h"
16#include "nic.h"
17#include "phy.h"
18#include "workarounds.h"
19
20/* We expect these MMDs to be in the package. */
21#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
22 MDIO_DEVS_PCS | \
23 MDIO_DEVS_PHYXS | \
24 MDIO_DEVS_AN)
25
26#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
27 (1 << LOOPBACK_PCS) | \
28 (1 << LOOPBACK_PMAPMD) | \
29 (1 << LOOPBACK_PHYXS_WS))
30
31/* We complain if we fail to see the link partner as 10G capable this many
32 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
33 */
34#define MAX_BAD_LP_TRIES (5)
35
36/* Extended control register */
37#define PMA_PMD_XCONTROL_REG 49152
38#define PMA_PMD_EXT_GMII_EN_LBN 1
39#define PMA_PMD_EXT_GMII_EN_WIDTH 1
40#define PMA_PMD_EXT_CLK_OUT_LBN 2
41#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
42#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
43#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
44#define PMA_PMD_EXT_CLK312_WIDTH 1
45#define PMA_PMD_EXT_LPOWER_LBN 12
46#define PMA_PMD_EXT_LPOWER_WIDTH 1
47#define PMA_PMD_EXT_ROBUST_LBN 14
48#define PMA_PMD_EXT_ROBUST_WIDTH 1
49#define PMA_PMD_EXT_SSR_LBN 15
50#define PMA_PMD_EXT_SSR_WIDTH 1
51
52/* extended status register */
53#define PMA_PMD_XSTATUS_REG 49153
54#define PMA_PMD_XSTAT_MDIX_LBN 14
55#define PMA_PMD_XSTAT_FLP_LBN (12)
56
57/* LED control register */
58#define PMA_PMD_LED_CTRL_REG 49159
59#define PMA_PMA_LED_ACTIVITY_LBN (3)
60
61/* LED function override register */
62#define PMA_PMD_LED_OVERR_REG 49161
63/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
64#define PMA_PMD_LED_LINK_LBN (0)
65#define PMA_PMD_LED_SPEED_LBN (2)
66#define PMA_PMD_LED_TX_LBN (4)
67#define PMA_PMD_LED_RX_LBN (6)
68/* Override settings */
69#define PMA_PMD_LED_AUTO (0) /* H/W control */
70#define PMA_PMD_LED_ON (1)
71#define PMA_PMD_LED_OFF (2)
72#define PMA_PMD_LED_FLASH (3)
73#define PMA_PMD_LED_MASK 3
74/* All LEDs under hardware control */
75/* Green and Amber under hardware control, Red off */
76#define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
77
78#define PMA_PMD_SPEED_ENABLE_REG 49192
79#define PMA_PMD_100TX_ADV_LBN 1
80#define PMA_PMD_100TX_ADV_WIDTH 1
81#define PMA_PMD_1000T_ADV_LBN 2
82#define PMA_PMD_1000T_ADV_WIDTH 1
83#define PMA_PMD_10000T_ADV_LBN 3
84#define PMA_PMD_10000T_ADV_WIDTH 1
85#define PMA_PMD_SPEED_LBN 4
86#define PMA_PMD_SPEED_WIDTH 4
87
88/* Misc register defines */
89#define PCS_CLOCK_CTRL_REG 55297
90#define PLL312_RST_N_LBN 2
91
92#define PCS_SOFT_RST2_REG 55302
93#define SERDES_RST_N_LBN 13
94#define XGXS_RST_N_LBN 12
95
96#define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
97#define CLK312_EN_LBN 3
98
99/* PHYXS registers */
100#define PHYXS_XCONTROL_REG 49152
101#define PHYXS_RESET_LBN 15
102#define PHYXS_RESET_WIDTH 1
103
104#define PHYXS_TEST1 (49162)
105#define LOOPBACK_NEAR_LBN (8)
106#define LOOPBACK_NEAR_WIDTH (1)
107
108/* Boot status register */
109#define PCS_BOOT_STATUS_REG 53248
110#define PCS_BOOT_FATAL_ERROR_LBN 0
111#define PCS_BOOT_PROGRESS_LBN 1
112#define PCS_BOOT_PROGRESS_WIDTH 2
113#define PCS_BOOT_PROGRESS_INIT 0
114#define PCS_BOOT_PROGRESS_WAIT_MDIO 1
115#define PCS_BOOT_PROGRESS_CHECKSUM 2
116#define PCS_BOOT_PROGRESS_JUMP 3
117#define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
118#define PCS_BOOT_CODE_STARTED_LBN 4
119
120/* 100M/1G PHY registers */
121#define GPHY_XCONTROL_REG 49152
122#define GPHY_ISOLATE_LBN 10
123#define GPHY_ISOLATE_WIDTH 1
124#define GPHY_DUPLEX_LBN 8
125#define GPHY_DUPLEX_WIDTH 1
126#define GPHY_LOOPBACK_NEAR_LBN 14
127#define GPHY_LOOPBACK_NEAR_WIDTH 1
128
129#define C22EXT_STATUS_REG 49153
130#define C22EXT_STATUS_LINK_LBN 2
131#define C22EXT_STATUS_LINK_WIDTH 1
132
133#define C22EXT_MSTSLV_CTRL 49161
134#define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
135#define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
136
137#define C22EXT_MSTSLV_STATUS 49162
138#define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
139#define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
140
141/* Time to wait between powering down the LNPGA and turning off the power
142 * rails */
143#define LNPGA_PDOWN_WAIT (HZ / 5)
144
145struct tenxpress_phy_data {
146 enum ef4_loopback_mode loopback_mode;
147 enum ef4_phy_mode phy_mode;
148 int bad_lp_tries;
149};
150
151static int tenxpress_init(struct ef4_nic *efx)
152{
153 /* Enable 312.5 MHz clock */
154 ef4_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
155 1 << CLK312_EN_LBN);
156
157 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
158 ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
159 1 << PMA_PMA_LED_ACTIVITY_LBN, true);
160 ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
161 SFX7101_PMA_PMD_LED_DEFAULT);
162
163 return 0;
164}
165
166static int tenxpress_phy_probe(struct ef4_nic *efx)
167{
168 struct tenxpress_phy_data *phy_data;
169
170 /* Allocate phy private storage */
171 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
172 if (!phy_data)
173 return -ENOMEM;
174 efx->phy_data = phy_data;
175 phy_data->phy_mode = efx->phy_mode;
176
177 efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
178 efx->mdio.mode_support = MDIO_SUPPORTS_C45;
179
180 efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
181
182 efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg |
183 ADVERTISED_10000baseT_Full);
184
185 return 0;
186}
187
188static int tenxpress_phy_init(struct ef4_nic *efx)
189{
190 int rc;
191
192 falcon_board(efx)->type->init_phy(efx);
193
194 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
195 rc = ef4_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
196 if (rc < 0)
197 return rc;
198
199 rc = ef4_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS);
200 if (rc < 0)
201 return rc;
202 }
203
204 rc = tenxpress_init(efx);
205 if (rc < 0)
206 return rc;
207
208 /* Reinitialise flow control settings */
209 ef4_link_set_wanted_fc(efx, efx->wanted_fc);
210 ef4_mdio_an_reconfigure(efx);
211
212 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
213
214 /* Let XGXS and SerDes out of reset */
215 falcon_reset_xaui(efx);
216
217 return 0;
218}
219
220/* Perform a "special software reset" on the PHY. The caller is
221 * responsible for saving and restoring the PHY hardware registers
222 * properly, and masking/unmasking LASI */
223static int tenxpress_special_reset(struct ef4_nic *efx)
224{
225 int rc, reg;
226
227 /* The XGMAC clock is driven from the SFX7101 312MHz clock, so
228 * a special software reset can glitch the XGMAC sufficiently for stats
229 * requests to fail. */
230 falcon_stop_nic_stats(efx);
231
232 /* Initiate reset */
233 reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
234 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
235 ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
236
237 mdelay(200);
238
239 /* Wait for the blocks to come out of reset */
240 rc = ef4_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
241 if (rc < 0)
242 goto out;
243
244 /* Try and reconfigure the device */
245 rc = tenxpress_init(efx);
246 if (rc < 0)
247 goto out;
248
249 /* Wait for the XGXS state machine to churn */
250 mdelay(10);
251out:
252 falcon_start_nic_stats(efx);
253 return rc;
254}
255
256static void sfx7101_check_bad_lp(struct ef4_nic *efx, bool link_ok)
257{
258 struct tenxpress_phy_data *pd = efx->phy_data;
259 bool bad_lp;
260 int reg;
261
262 if (link_ok) {
263 bad_lp = false;
264 } else {
265 /* Check that AN has started but not completed. */
266 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
267 if (!(reg & MDIO_AN_STAT1_LPABLE))
268 return; /* LP status is unknown */
269 bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
270 if (bad_lp)
271 pd->bad_lp_tries++;
272 }
273
274 /* Nothing to do if all is well and was previously so. */
275 if (!pd->bad_lp_tries)
276 return;
277
278 /* Use the RX (red) LED as an error indicator once we've seen AN
279 * failure several times in a row, and also log a message. */
280 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
281 reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD,
282 PMA_PMD_LED_OVERR_REG);
283 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
284 if (!bad_lp) {
285 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
286 } else {
287 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
288 netif_err(efx, link, efx->net_dev,
289 "appears to be plugged into a port"
290 " that is not 10GBASE-T capable. The PHY"
291 " supports 10GBASE-T ONLY, so no link can"
292 " be established\n");
293 }
294 ef4_mdio_write(efx, MDIO_MMD_PMAPMD,
295 PMA_PMD_LED_OVERR_REG, reg);
296 pd->bad_lp_tries = bad_lp;
297 }
298}
299
300static bool sfx7101_link_ok(struct ef4_nic *efx)
301{
302 return ef4_mdio_links_ok(efx,
303 MDIO_DEVS_PMAPMD |
304 MDIO_DEVS_PCS |
305 MDIO_DEVS_PHYXS);
306}
307
308static void tenxpress_ext_loopback(struct ef4_nic *efx)
309{
310 ef4_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
311 1 << LOOPBACK_NEAR_LBN,
312 efx->loopback_mode == LOOPBACK_PHYXS);
313}
314
315static void tenxpress_low_power(struct ef4_nic *efx)
316{
317 ef4_mdio_set_mmds_lpower(
318 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
319 TENXPRESS_REQUIRED_DEVS);
320}
321
322static int tenxpress_phy_reconfigure(struct ef4_nic *efx)
323{
324 struct tenxpress_phy_data *phy_data = efx->phy_data;
325 bool phy_mode_change, loop_reset;
326
327 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
328 phy_data->phy_mode = efx->phy_mode;
329 return 0;
330 }
331
332 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
333 phy_data->phy_mode != PHY_MODE_NORMAL);
334 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) ||
335 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
336
337 if (loop_reset || phy_mode_change) {
338 tenxpress_special_reset(efx);
339 falcon_reset_xaui(efx);
340 }
341
342 tenxpress_low_power(efx);
343 ef4_mdio_transmit_disable(efx);
344 ef4_mdio_phy_reconfigure(efx);
345 tenxpress_ext_loopback(efx);
346 ef4_mdio_an_reconfigure(efx);
347
348 phy_data->loopback_mode = efx->loopback_mode;
349 phy_data->phy_mode = efx->phy_mode;
350
351 return 0;
352}
353
354/* Poll for link state changes */
355static bool tenxpress_phy_poll(struct ef4_nic *efx)
356{
357 struct ef4_link_state old_state = efx->link_state;
358
359 efx->link_state.up = sfx7101_link_ok(efx);
360 efx->link_state.speed = 10000;
361 efx->link_state.fd = true;
362 efx->link_state.fc = ef4_mdio_get_pause(efx);
363
364 sfx7101_check_bad_lp(efx, efx->link_state.up);
365
366 return !ef4_link_state_equal(&efx->link_state, &old_state);
367}
368
369static void sfx7101_phy_fini(struct ef4_nic *efx)
370{
371 int reg;
372
373 /* Power down the LNPGA */
374 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
375 ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
376
377 /* Waiting here ensures that the board fini, which can turn
378 * off the power to the PHY, won't get run until the LNPGA
379 * powerdown has been given long enough to complete. */
380 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
381}
382
383static void tenxpress_phy_remove(struct ef4_nic *efx)
384{
385 kfree(efx->phy_data);
386 efx->phy_data = NULL;
387}
388
389
390/* Override the RX, TX and link LEDs */
391void tenxpress_set_id_led(struct ef4_nic *efx, enum ef4_led_mode mode)
392{
393 int reg;
394
395 switch (mode) {
396 case EF4_LED_OFF:
397 reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) |
398 (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
399 (PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
400 break;
401 case EF4_LED_ON:
402 reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) |
403 (PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) |
404 (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
405 break;
406 default:
407 reg = SFX7101_PMA_PMD_LED_DEFAULT;
408 break;
409 }
410
411 ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
412}
413
414static const char *const sfx7101_test_names[] = {
415 "bist"
416};
417
418static const char *sfx7101_test_name(struct ef4_nic *efx, unsigned int index)
419{
420 if (index < ARRAY_SIZE(sfx7101_test_names))
421 return sfx7101_test_names[index];
422 return NULL;
423}
424
425static int
426sfx7101_run_tests(struct ef4_nic *efx, int *results, unsigned flags)
427{
428 int rc;
429
430 if (!(flags & ETH_TEST_FL_OFFLINE))
431 return 0;
432
433 /* BIST is automatically run after a special software reset */
434 rc = tenxpress_special_reset(efx);
435 results[0] = rc ? -1 : 1;
436
437 ef4_mdio_an_reconfigure(efx);
438
439 return rc;
440}
441
442static void
443tenxpress_get_link_ksettings(struct ef4_nic *efx,
444 struct ethtool_link_ksettings *cmd)
445{
446 u32 adv = 0, lpa = 0;
447 int reg;
448
449 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
450 if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
451 adv |= ADVERTISED_10000baseT_Full;
452 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
453 if (reg & MDIO_AN_10GBT_STAT_LP10G)
454 lpa |= ADVERTISED_10000baseT_Full;
455
456 mdio45_ethtool_ksettings_get_npage(&efx->mdio, cmd, adv, lpa);
457
458 /* In loopback, the PHY automatically brings up the correct interface,
459 * but doesn't advertise the correct speed. So override it */
460 if (LOOPBACK_EXTERNAL(efx))
461 cmd->base.speed = SPEED_10000;
462}
463
464static int
465tenxpress_set_link_ksettings(struct ef4_nic *efx,
466 const struct ethtool_link_ksettings *cmd)
467{
468 if (!cmd->base.autoneg)
469 return -EINVAL;
470
471 return ef4_mdio_set_link_ksettings(efx, cmd);
472}
473
474static void sfx7101_set_npage_adv(struct ef4_nic *efx, u32 advertising)
475{
476 ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
477 MDIO_AN_10GBT_CTRL_ADV10G,
478 advertising & ADVERTISED_10000baseT_Full);
479}
480
481const struct ef4_phy_operations falcon_sfx7101_phy_ops = {
482 .probe = tenxpress_phy_probe,
483 .init = tenxpress_phy_init,
484 .reconfigure = tenxpress_phy_reconfigure,
485 .poll = tenxpress_phy_poll,
486 .fini = sfx7101_phy_fini,
487 .remove = tenxpress_phy_remove,
488 .get_link_ksettings = tenxpress_get_link_ksettings,
489 .set_link_ksettings = tenxpress_set_link_ksettings,
490 .set_npage_adv = sfx7101_set_npage_adv,
491 .test_alive = ef4_mdio_test_alive,
492 .test_name = sfx7101_test_name,
493 .run_tests = sfx7101_run_tests,
494};