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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence MACB/GEM Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/crc32.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/circ_buf.h>
17#include <linux/slab.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/gpio/consumer.h>
22#include <linux/interrupt.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <linux/phylink.h>
28#include <linux/of.h>
29#include <linux/of_gpio.h>
30#include <linux/of_mdio.h>
31#include <linux/of_net.h>
32#include <linux/ip.h>
33#include <linux/udp.h>
34#include <linux/tcp.h>
35#include <linux/iopoll.h>
36#include <linux/phy/phy.h>
37#include <linux/pm_runtime.h>
38#include <linux/ptp_classify.h>
39#include <linux/reset.h>
40#include <linux/firmware/xlnx-zynqmp.h>
41#include "macb.h"
42
43/* This structure is only used for MACB on SiFive FU540 devices */
44struct sifive_fu540_macb_mgmt {
45 void __iomem *reg;
46 unsigned long rate;
47 struct clk_hw hw;
48};
49
50#define MACB_RX_BUFFER_SIZE 128
51#define RX_BUFFER_MULTIPLE 64 /* bytes */
52
53#define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
54#define MIN_RX_RING_SIZE 64
55#define MAX_RX_RING_SIZE 8192
56#define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
57 * (bp)->rx_ring_size)
58
59#define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
60#define MIN_TX_RING_SIZE 64
61#define MAX_TX_RING_SIZE 4096
62#define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
63 * (bp)->tx_ring_size)
64
65/* level of occupied TX descriptors under which we wake up TX process */
66#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
67
68#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
69#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
70 | MACB_BIT(ISR_RLE) \
71 | MACB_BIT(TXERR))
72#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
73 | MACB_BIT(TXUBR))
74
75/* Max length of transmit frame must be a multiple of 8 bytes */
76#define MACB_TX_LEN_ALIGN 8
77#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
78/* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
79 * false amba_error in TX path from the DMA assuming there is not enough
80 * space in the SRAM (16KB) even when there is.
81 */
82#define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
83
84#define GEM_MTU_MIN_SIZE ETH_MIN_MTU
85#define MACB_NETIF_LSO NETIF_F_TSO
86
87#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
88#define MACB_WOL_ENABLED (0x1 << 1)
89
90#define HS_SPEED_10000M 4
91#define MACB_SERDES_RATE_10G 1
92
93/* Graceful stop timeouts in us. We should allow up to
94 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
95 */
96#define MACB_HALT_TIMEOUT 14000
97#define MACB_PM_TIMEOUT 100 /* ms */
98
99#define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
100
101/* DMA buffer descriptor might be different size
102 * depends on hardware configuration:
103 *
104 * 1. dma address width 32 bits:
105 * word 1: 32 bit address of Data Buffer
106 * word 2: control
107 *
108 * 2. dma address width 64 bits:
109 * word 1: 32 bit address of Data Buffer
110 * word 2: control
111 * word 3: upper 32 bit address of Data Buffer
112 * word 4: unused
113 *
114 * 3. dma address width 32 bits with hardware timestamping:
115 * word 1: 32 bit address of Data Buffer
116 * word 2: control
117 * word 3: timestamp word 1
118 * word 4: timestamp word 2
119 *
120 * 4. dma address width 64 bits with hardware timestamping:
121 * word 1: 32 bit address of Data Buffer
122 * word 2: control
123 * word 3: upper 32 bit address of Data Buffer
124 * word 4: unused
125 * word 5: timestamp word 1
126 * word 6: timestamp word 2
127 */
128static unsigned int macb_dma_desc_get_size(struct macb *bp)
129{
130#ifdef MACB_EXT_DESC
131 unsigned int desc_size;
132
133 switch (bp->hw_dma_cap) {
134 case HW_DMA_CAP_64B:
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_64);
137 break;
138 case HW_DMA_CAP_PTP:
139 desc_size = sizeof(struct macb_dma_desc)
140 + sizeof(struct macb_dma_desc_ptp);
141 break;
142 case HW_DMA_CAP_64B_PTP:
143 desc_size = sizeof(struct macb_dma_desc)
144 + sizeof(struct macb_dma_desc_64)
145 + sizeof(struct macb_dma_desc_ptp);
146 break;
147 default:
148 desc_size = sizeof(struct macb_dma_desc);
149 }
150 return desc_size;
151#endif
152 return sizeof(struct macb_dma_desc);
153}
154
155static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
156{
157#ifdef MACB_EXT_DESC
158 switch (bp->hw_dma_cap) {
159 case HW_DMA_CAP_64B:
160 case HW_DMA_CAP_PTP:
161 desc_idx <<= 1;
162 break;
163 case HW_DMA_CAP_64B_PTP:
164 desc_idx *= 3;
165 break;
166 default:
167 break;
168 }
169#endif
170 return desc_idx;
171}
172
173#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
174static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
175{
176 return (struct macb_dma_desc_64 *)((void *)desc
177 + sizeof(struct macb_dma_desc));
178}
179#endif
180
181/* Ring buffer accessors */
182static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
183{
184 return index & (bp->tx_ring_size - 1);
185}
186
187static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
188 unsigned int index)
189{
190 index = macb_tx_ring_wrap(queue->bp, index);
191 index = macb_adj_dma_desc_idx(queue->bp, index);
192 return &queue->tx_ring[index];
193}
194
195static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
196 unsigned int index)
197{
198 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
199}
200
201static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
202{
203 dma_addr_t offset;
204
205 offset = macb_tx_ring_wrap(queue->bp, index) *
206 macb_dma_desc_get_size(queue->bp);
207
208 return queue->tx_ring_dma + offset;
209}
210
211static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
212{
213 return index & (bp->rx_ring_size - 1);
214}
215
216static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
217{
218 index = macb_rx_ring_wrap(queue->bp, index);
219 index = macb_adj_dma_desc_idx(queue->bp, index);
220 return &queue->rx_ring[index];
221}
222
223static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
224{
225 return queue->rx_buffers + queue->bp->rx_buffer_size *
226 macb_rx_ring_wrap(queue->bp, index);
227}
228
229/* I/O accessors */
230static u32 hw_readl_native(struct macb *bp, int offset)
231{
232 return __raw_readl(bp->regs + offset);
233}
234
235static void hw_writel_native(struct macb *bp, int offset, u32 value)
236{
237 __raw_writel(value, bp->regs + offset);
238}
239
240static u32 hw_readl(struct macb *bp, int offset)
241{
242 return readl_relaxed(bp->regs + offset);
243}
244
245static void hw_writel(struct macb *bp, int offset, u32 value)
246{
247 writel_relaxed(value, bp->regs + offset);
248}
249
250/* Find the CPU endianness by using the loopback bit of NCR register. When the
251 * CPU is in big endian we need to program swapped mode for management
252 * descriptor access.
253 */
254static bool hw_is_native_io(void __iomem *addr)
255{
256 u32 value = MACB_BIT(LLB);
257
258 __raw_writel(value, addr + MACB_NCR);
259 value = __raw_readl(addr + MACB_NCR);
260
261 /* Write 0 back to disable everything */
262 __raw_writel(0, addr + MACB_NCR);
263
264 return value == MACB_BIT(LLB);
265}
266
267static bool hw_is_gem(void __iomem *addr, bool native_io)
268{
269 u32 id;
270
271 if (native_io)
272 id = __raw_readl(addr + MACB_MID);
273 else
274 id = readl_relaxed(addr + MACB_MID);
275
276 return MACB_BFEXT(IDNUM, id) >= 0x2;
277}
278
279static void macb_set_hwaddr(struct macb *bp)
280{
281 u32 bottom;
282 u16 top;
283
284 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
285 macb_or_gem_writel(bp, SA1B, bottom);
286 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
287 macb_or_gem_writel(bp, SA1T, top);
288
289 if (gem_has_ptp(bp)) {
290 gem_writel(bp, RXPTPUNI, bottom);
291 gem_writel(bp, TXPTPUNI, bottom);
292 }
293
294 /* Clear unused address register sets */
295 macb_or_gem_writel(bp, SA2B, 0);
296 macb_or_gem_writel(bp, SA2T, 0);
297 macb_or_gem_writel(bp, SA3B, 0);
298 macb_or_gem_writel(bp, SA3T, 0);
299 macb_or_gem_writel(bp, SA4B, 0);
300 macb_or_gem_writel(bp, SA4T, 0);
301}
302
303static void macb_get_hwaddr(struct macb *bp)
304{
305 u32 bottom;
306 u16 top;
307 u8 addr[6];
308 int i;
309
310 /* Check all 4 address register for valid address */
311 for (i = 0; i < 4; i++) {
312 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
313 top = macb_or_gem_readl(bp, SA1T + i * 8);
314
315 addr[0] = bottom & 0xff;
316 addr[1] = (bottom >> 8) & 0xff;
317 addr[2] = (bottom >> 16) & 0xff;
318 addr[3] = (bottom >> 24) & 0xff;
319 addr[4] = top & 0xff;
320 addr[5] = (top >> 8) & 0xff;
321
322 if (is_valid_ether_addr(addr)) {
323 eth_hw_addr_set(bp->dev, addr);
324 return;
325 }
326 }
327
328 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
329 eth_hw_addr_random(bp->dev);
330}
331
332static int macb_mdio_wait_for_idle(struct macb *bp)
333{
334 u32 val;
335
336 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
337 1, MACB_MDIO_TIMEOUT);
338}
339
340static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
341{
342 struct macb *bp = bus->priv;
343 int status;
344
345 status = pm_runtime_resume_and_get(&bp->pdev->dev);
346 if (status < 0)
347 goto mdio_pm_exit;
348
349 status = macb_mdio_wait_for_idle(bp);
350 if (status < 0)
351 goto mdio_read_exit;
352
353 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
354 | MACB_BF(RW, MACB_MAN_C22_READ)
355 | MACB_BF(PHYA, mii_id)
356 | MACB_BF(REGA, regnum)
357 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
358
359 status = macb_mdio_wait_for_idle(bp);
360 if (status < 0)
361 goto mdio_read_exit;
362
363 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
364
365mdio_read_exit:
366 pm_runtime_mark_last_busy(&bp->pdev->dev);
367 pm_runtime_put_autosuspend(&bp->pdev->dev);
368mdio_pm_exit:
369 return status;
370}
371
372static int macb_mdio_read_c45(struct mii_bus *bus, int mii_id, int devad,
373 int regnum)
374{
375 struct macb *bp = bus->priv;
376 int status;
377
378 status = pm_runtime_get_sync(&bp->pdev->dev);
379 if (status < 0) {
380 pm_runtime_put_noidle(&bp->pdev->dev);
381 goto mdio_pm_exit;
382 }
383
384 status = macb_mdio_wait_for_idle(bp);
385 if (status < 0)
386 goto mdio_read_exit;
387
388 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
389 | MACB_BF(RW, MACB_MAN_C45_ADDR)
390 | MACB_BF(PHYA, mii_id)
391 | MACB_BF(REGA, devad & 0x1F)
392 | MACB_BF(DATA, regnum & 0xFFFF)
393 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
394
395 status = macb_mdio_wait_for_idle(bp);
396 if (status < 0)
397 goto mdio_read_exit;
398
399 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
400 | MACB_BF(RW, MACB_MAN_C45_READ)
401 | MACB_BF(PHYA, mii_id)
402 | MACB_BF(REGA, devad & 0x1F)
403 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
404
405 status = macb_mdio_wait_for_idle(bp);
406 if (status < 0)
407 goto mdio_read_exit;
408
409 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
410
411mdio_read_exit:
412 pm_runtime_mark_last_busy(&bp->pdev->dev);
413 pm_runtime_put_autosuspend(&bp->pdev->dev);
414mdio_pm_exit:
415 return status;
416}
417
418static int macb_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
419 u16 value)
420{
421 struct macb *bp = bus->priv;
422 int status;
423
424 status = pm_runtime_resume_and_get(&bp->pdev->dev);
425 if (status < 0)
426 goto mdio_pm_exit;
427
428 status = macb_mdio_wait_for_idle(bp);
429 if (status < 0)
430 goto mdio_write_exit;
431
432 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
433 | MACB_BF(RW, MACB_MAN_C22_WRITE)
434 | MACB_BF(PHYA, mii_id)
435 | MACB_BF(REGA, regnum)
436 | MACB_BF(CODE, MACB_MAN_C22_CODE)
437 | MACB_BF(DATA, value)));
438
439 status = macb_mdio_wait_for_idle(bp);
440 if (status < 0)
441 goto mdio_write_exit;
442
443mdio_write_exit:
444 pm_runtime_mark_last_busy(&bp->pdev->dev);
445 pm_runtime_put_autosuspend(&bp->pdev->dev);
446mdio_pm_exit:
447 return status;
448}
449
450static int macb_mdio_write_c45(struct mii_bus *bus, int mii_id,
451 int devad, int regnum,
452 u16 value)
453{
454 struct macb *bp = bus->priv;
455 int status;
456
457 status = pm_runtime_get_sync(&bp->pdev->dev);
458 if (status < 0) {
459 pm_runtime_put_noidle(&bp->pdev->dev);
460 goto mdio_pm_exit;
461 }
462
463 status = macb_mdio_wait_for_idle(bp);
464 if (status < 0)
465 goto mdio_write_exit;
466
467 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
468 | MACB_BF(RW, MACB_MAN_C45_ADDR)
469 | MACB_BF(PHYA, mii_id)
470 | MACB_BF(REGA, devad & 0x1F)
471 | MACB_BF(DATA, regnum & 0xFFFF)
472 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
473
474 status = macb_mdio_wait_for_idle(bp);
475 if (status < 0)
476 goto mdio_write_exit;
477
478 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
479 | MACB_BF(RW, MACB_MAN_C45_WRITE)
480 | MACB_BF(PHYA, mii_id)
481 | MACB_BF(REGA, devad & 0x1F)
482 | MACB_BF(CODE, MACB_MAN_C45_CODE)
483 | MACB_BF(DATA, value)));
484
485 status = macb_mdio_wait_for_idle(bp);
486 if (status < 0)
487 goto mdio_write_exit;
488
489mdio_write_exit:
490 pm_runtime_mark_last_busy(&bp->pdev->dev);
491 pm_runtime_put_autosuspend(&bp->pdev->dev);
492mdio_pm_exit:
493 return status;
494}
495
496static void macb_init_buffers(struct macb *bp)
497{
498 struct macb_queue *queue;
499 unsigned int q;
500
501 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
502 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
503#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
504 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
505 queue_writel(queue, RBQPH,
506 upper_32_bits(queue->rx_ring_dma));
507#endif
508 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
509#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
510 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
511 queue_writel(queue, TBQPH,
512 upper_32_bits(queue->tx_ring_dma));
513#endif
514 }
515}
516
517/**
518 * macb_set_tx_clk() - Set a clock to a new frequency
519 * @bp: pointer to struct macb
520 * @speed: New frequency in Hz
521 */
522static void macb_set_tx_clk(struct macb *bp, int speed)
523{
524 long ferr, rate, rate_rounded;
525
526 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
527 return;
528
529 /* In case of MII the PHY is the clock master */
530 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
531 return;
532
533 switch (speed) {
534 case SPEED_10:
535 rate = 2500000;
536 break;
537 case SPEED_100:
538 rate = 25000000;
539 break;
540 case SPEED_1000:
541 rate = 125000000;
542 break;
543 default:
544 return;
545 }
546
547 rate_rounded = clk_round_rate(bp->tx_clk, rate);
548 if (rate_rounded < 0)
549 return;
550
551 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
552 * is not satisfied.
553 */
554 ferr = abs(rate_rounded - rate);
555 ferr = DIV_ROUND_UP(ferr, rate / 100000);
556 if (ferr > 5)
557 netdev_warn(bp->dev,
558 "unable to generate target frequency: %ld Hz\n",
559 rate);
560
561 if (clk_set_rate(bp->tx_clk, rate_rounded))
562 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
563}
564
565static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
566 phy_interface_t interface, int speed,
567 int duplex)
568{
569 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
570 u32 config;
571
572 config = gem_readl(bp, USX_CONTROL);
573 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
574 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
575 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
576 config |= GEM_BIT(TX_EN);
577 gem_writel(bp, USX_CONTROL, config);
578}
579
580static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
581 struct phylink_link_state *state)
582{
583 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
584 u32 val;
585
586 state->speed = SPEED_10000;
587 state->duplex = 1;
588 state->an_complete = 1;
589
590 val = gem_readl(bp, USX_STATUS);
591 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
592 val = gem_readl(bp, NCFGR);
593 if (val & GEM_BIT(PAE))
594 state->pause = MLO_PAUSE_RX;
595}
596
597static int macb_usx_pcs_config(struct phylink_pcs *pcs,
598 unsigned int neg_mode,
599 phy_interface_t interface,
600 const unsigned long *advertising,
601 bool permit_pause_to_mac)
602{
603 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
604
605 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
606 GEM_BIT(SIGNAL_OK));
607
608 return 0;
609}
610
611static void macb_pcs_get_state(struct phylink_pcs *pcs,
612 struct phylink_link_state *state)
613{
614 state->link = 0;
615}
616
617static void macb_pcs_an_restart(struct phylink_pcs *pcs)
618{
619 /* Not supported */
620}
621
622static int macb_pcs_config(struct phylink_pcs *pcs,
623 unsigned int neg_mode,
624 phy_interface_t interface,
625 const unsigned long *advertising,
626 bool permit_pause_to_mac)
627{
628 return 0;
629}
630
631static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
632 .pcs_get_state = macb_usx_pcs_get_state,
633 .pcs_config = macb_usx_pcs_config,
634 .pcs_link_up = macb_usx_pcs_link_up,
635};
636
637static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
638 .pcs_get_state = macb_pcs_get_state,
639 .pcs_an_restart = macb_pcs_an_restart,
640 .pcs_config = macb_pcs_config,
641};
642
643static void macb_mac_config(struct phylink_config *config, unsigned int mode,
644 const struct phylink_link_state *state)
645{
646 struct net_device *ndev = to_net_dev(config->dev);
647 struct macb *bp = netdev_priv(ndev);
648 unsigned long flags;
649 u32 old_ctrl, ctrl;
650 u32 old_ncr, ncr;
651
652 spin_lock_irqsave(&bp->lock, flags);
653
654 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
655 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
656
657 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
658 if (state->interface == PHY_INTERFACE_MODE_RMII)
659 ctrl |= MACB_BIT(RM9200_RMII);
660 } else if (macb_is_gem(bp)) {
661 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
662 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
663
664 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
665 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
666 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
667 ctrl |= GEM_BIT(PCSSEL);
668 ncr |= GEM_BIT(ENABLE_HS_MAC);
669 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
670 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
671 ncr |= MACB_BIT(MIIONRGMII);
672 }
673 }
674
675 /* Apply the new configuration, if any */
676 if (old_ctrl ^ ctrl)
677 macb_or_gem_writel(bp, NCFGR, ctrl);
678
679 if (old_ncr ^ ncr)
680 macb_or_gem_writel(bp, NCR, ncr);
681
682 /* Disable AN for SGMII fixed link configuration, enable otherwise.
683 * Must be written after PCSSEL is set in NCFGR,
684 * otherwise writes will not take effect.
685 */
686 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
687 u32 pcsctrl, old_pcsctrl;
688
689 old_pcsctrl = gem_readl(bp, PCSCNTRL);
690 if (mode == MLO_AN_FIXED)
691 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
692 else
693 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
694 if (old_pcsctrl != pcsctrl)
695 gem_writel(bp, PCSCNTRL, pcsctrl);
696 }
697
698 spin_unlock_irqrestore(&bp->lock, flags);
699}
700
701static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
702 phy_interface_t interface)
703{
704 struct net_device *ndev = to_net_dev(config->dev);
705 struct macb *bp = netdev_priv(ndev);
706 struct macb_queue *queue;
707 unsigned int q;
708 u32 ctrl;
709
710 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
711 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
712 queue_writel(queue, IDR,
713 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
714
715 /* Disable Rx and Tx */
716 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
717 macb_writel(bp, NCR, ctrl);
718
719 netif_tx_stop_all_queues(ndev);
720}
721
722static void macb_mac_link_up(struct phylink_config *config,
723 struct phy_device *phy,
724 unsigned int mode, phy_interface_t interface,
725 int speed, int duplex,
726 bool tx_pause, bool rx_pause)
727{
728 struct net_device *ndev = to_net_dev(config->dev);
729 struct macb *bp = netdev_priv(ndev);
730 struct macb_queue *queue;
731 unsigned long flags;
732 unsigned int q;
733 u32 ctrl;
734
735 spin_lock_irqsave(&bp->lock, flags);
736
737 ctrl = macb_or_gem_readl(bp, NCFGR);
738
739 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
740
741 if (speed == SPEED_100)
742 ctrl |= MACB_BIT(SPD);
743
744 if (duplex)
745 ctrl |= MACB_BIT(FD);
746
747 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
748 ctrl &= ~MACB_BIT(PAE);
749 if (macb_is_gem(bp)) {
750 ctrl &= ~GEM_BIT(GBE);
751
752 if (speed == SPEED_1000)
753 ctrl |= GEM_BIT(GBE);
754 }
755
756 if (rx_pause)
757 ctrl |= MACB_BIT(PAE);
758
759 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
760 * cleared the pipeline and control registers.
761 */
762 bp->macbgem_ops.mog_init_rings(bp);
763 macb_init_buffers(bp);
764
765 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
766 queue_writel(queue, IER,
767 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
768 }
769
770 macb_or_gem_writel(bp, NCFGR, ctrl);
771
772 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
773 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
774 gem_readl(bp, HS_MAC_CONFIG)));
775
776 spin_unlock_irqrestore(&bp->lock, flags);
777
778 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
779 macb_set_tx_clk(bp, speed);
780
781 /* Enable Rx and Tx; Enable PTP unicast */
782 ctrl = macb_readl(bp, NCR);
783 if (gem_has_ptp(bp))
784 ctrl |= MACB_BIT(PTPUNI);
785
786 macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));
787
788 netif_tx_wake_all_queues(ndev);
789}
790
791static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
792 phy_interface_t interface)
793{
794 struct net_device *ndev = to_net_dev(config->dev);
795 struct macb *bp = netdev_priv(ndev);
796
797 if (interface == PHY_INTERFACE_MODE_10GBASER)
798 return &bp->phylink_usx_pcs;
799 else if (interface == PHY_INTERFACE_MODE_SGMII)
800 return &bp->phylink_sgmii_pcs;
801 else
802 return NULL;
803}
804
805static const struct phylink_mac_ops macb_phylink_ops = {
806 .mac_select_pcs = macb_mac_select_pcs,
807 .mac_config = macb_mac_config,
808 .mac_link_down = macb_mac_link_down,
809 .mac_link_up = macb_mac_link_up,
810};
811
812static bool macb_phy_handle_exists(struct device_node *dn)
813{
814 dn = of_parse_phandle(dn, "phy-handle", 0);
815 of_node_put(dn);
816 return dn != NULL;
817}
818
819static int macb_phylink_connect(struct macb *bp)
820{
821 struct device_node *dn = bp->pdev->dev.of_node;
822 struct net_device *dev = bp->dev;
823 struct phy_device *phydev;
824 int ret;
825
826 if (dn)
827 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
828
829 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
830 phydev = phy_find_first(bp->mii_bus);
831 if (!phydev) {
832 netdev_err(dev, "no PHY found\n");
833 return -ENXIO;
834 }
835
836 /* attach the mac to the phy */
837 ret = phylink_connect_phy(bp->phylink, phydev);
838 }
839
840 if (ret) {
841 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
842 return ret;
843 }
844
845 phylink_start(bp->phylink);
846
847 return 0;
848}
849
850static void macb_get_pcs_fixed_state(struct phylink_config *config,
851 struct phylink_link_state *state)
852{
853 struct net_device *ndev = to_net_dev(config->dev);
854 struct macb *bp = netdev_priv(ndev);
855
856 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
857}
858
859/* based on au1000_eth. c*/
860static int macb_mii_probe(struct net_device *dev)
861{
862 struct macb *bp = netdev_priv(dev);
863
864 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
865 bp->phylink_sgmii_pcs.neg_mode = true;
866 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
867 bp->phylink_usx_pcs.neg_mode = true;
868
869 bp->phylink_config.dev = &dev->dev;
870 bp->phylink_config.type = PHYLINK_NETDEV;
871 bp->phylink_config.mac_managed_pm = true;
872
873 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
874 bp->phylink_config.poll_fixed_state = true;
875 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
876 }
877
878 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
879 MAC_10 | MAC_100;
880
881 __set_bit(PHY_INTERFACE_MODE_MII,
882 bp->phylink_config.supported_interfaces);
883 __set_bit(PHY_INTERFACE_MODE_RMII,
884 bp->phylink_config.supported_interfaces);
885
886 /* Determine what modes are supported */
887 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
888 bp->phylink_config.mac_capabilities |= MAC_1000FD;
889 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
890 bp->phylink_config.mac_capabilities |= MAC_1000HD;
891
892 __set_bit(PHY_INTERFACE_MODE_GMII,
893 bp->phylink_config.supported_interfaces);
894 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
895
896 if (bp->caps & MACB_CAPS_PCS)
897 __set_bit(PHY_INTERFACE_MODE_SGMII,
898 bp->phylink_config.supported_interfaces);
899
900 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
901 __set_bit(PHY_INTERFACE_MODE_10GBASER,
902 bp->phylink_config.supported_interfaces);
903 bp->phylink_config.mac_capabilities |= MAC_10000FD;
904 }
905 }
906
907 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
908 bp->phy_interface, &macb_phylink_ops);
909 if (IS_ERR(bp->phylink)) {
910 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
911 PTR_ERR(bp->phylink));
912 return PTR_ERR(bp->phylink);
913 }
914
915 return 0;
916}
917
918static int macb_mdiobus_register(struct macb *bp)
919{
920 struct device_node *child, *np = bp->pdev->dev.of_node;
921
922 /* If we have a child named mdio, probe it instead of looking for PHYs
923 * directly under the MAC node
924 */
925 child = of_get_child_by_name(np, "mdio");
926 if (child) {
927 int ret = of_mdiobus_register(bp->mii_bus, child);
928
929 of_node_put(child);
930 return ret;
931 }
932
933 if (of_phy_is_fixed_link(np))
934 return mdiobus_register(bp->mii_bus);
935
936 /* Only create the PHY from the device tree if at least one PHY is
937 * described. Otherwise scan the entire MDIO bus. We do this to support
938 * old device tree that did not follow the best practices and did not
939 * describe their network PHYs.
940 */
941 for_each_available_child_of_node(np, child)
942 if (of_mdiobus_child_is_phy(child)) {
943 /* The loop increments the child refcount,
944 * decrement it before returning.
945 */
946 of_node_put(child);
947
948 return of_mdiobus_register(bp->mii_bus, np);
949 }
950
951 return mdiobus_register(bp->mii_bus);
952}
953
954static int macb_mii_init(struct macb *bp)
955{
956 int err = -ENXIO;
957
958 /* Enable management port */
959 macb_writel(bp, NCR, MACB_BIT(MPE));
960
961 bp->mii_bus = mdiobus_alloc();
962 if (!bp->mii_bus) {
963 err = -ENOMEM;
964 goto err_out;
965 }
966
967 bp->mii_bus->name = "MACB_mii_bus";
968 bp->mii_bus->read = &macb_mdio_read_c22;
969 bp->mii_bus->write = &macb_mdio_write_c22;
970 bp->mii_bus->read_c45 = &macb_mdio_read_c45;
971 bp->mii_bus->write_c45 = &macb_mdio_write_c45;
972 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
973 bp->pdev->name, bp->pdev->id);
974 bp->mii_bus->priv = bp;
975 bp->mii_bus->parent = &bp->pdev->dev;
976
977 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
978
979 err = macb_mdiobus_register(bp);
980 if (err)
981 goto err_out_free_mdiobus;
982
983 err = macb_mii_probe(bp->dev);
984 if (err)
985 goto err_out_unregister_bus;
986
987 return 0;
988
989err_out_unregister_bus:
990 mdiobus_unregister(bp->mii_bus);
991err_out_free_mdiobus:
992 mdiobus_free(bp->mii_bus);
993err_out:
994 return err;
995}
996
997static void macb_update_stats(struct macb *bp)
998{
999 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
1000 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
1001 int offset = MACB_PFR;
1002
1003 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
1004
1005 for (; p < end; p++, offset += 4)
1006 *p += bp->macb_reg_readl(bp, offset);
1007}
1008
1009static int macb_halt_tx(struct macb *bp)
1010{
1011 unsigned long halt_time, timeout;
1012 u32 status;
1013
1014 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
1015
1016 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
1017 do {
1018 halt_time = jiffies;
1019 status = macb_readl(bp, TSR);
1020 if (!(status & MACB_BIT(TGO)))
1021 return 0;
1022
1023 udelay(250);
1024 } while (time_before(halt_time, timeout));
1025
1026 return -ETIMEDOUT;
1027}
1028
1029static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget)
1030{
1031 if (tx_skb->mapping) {
1032 if (tx_skb->mapped_as_page)
1033 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
1034 tx_skb->size, DMA_TO_DEVICE);
1035 else
1036 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
1037 tx_skb->size, DMA_TO_DEVICE);
1038 tx_skb->mapping = 0;
1039 }
1040
1041 if (tx_skb->skb) {
1042 napi_consume_skb(tx_skb->skb, budget);
1043 tx_skb->skb = NULL;
1044 }
1045}
1046
1047static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
1048{
1049#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1050 struct macb_dma_desc_64 *desc_64;
1051
1052 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1053 desc_64 = macb_64b_desc(bp, desc);
1054 desc_64->addrh = upper_32_bits(addr);
1055 /* The low bits of RX address contain the RX_USED bit, clearing
1056 * of which allows packet RX. Make sure the high bits are also
1057 * visible to HW at that point.
1058 */
1059 dma_wmb();
1060 }
1061#endif
1062 desc->addr = lower_32_bits(addr);
1063}
1064
1065static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1066{
1067 dma_addr_t addr = 0;
1068#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1069 struct macb_dma_desc_64 *desc_64;
1070
1071 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1072 desc_64 = macb_64b_desc(bp, desc);
1073 addr = ((u64)(desc_64->addrh) << 32);
1074 }
1075#endif
1076 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1077#ifdef CONFIG_MACB_USE_HWSTAMP
1078 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
1079 addr &= ~GEM_BIT(DMA_RXVALID);
1080#endif
1081 return addr;
1082}
1083
1084static void macb_tx_error_task(struct work_struct *work)
1085{
1086 struct macb_queue *queue = container_of(work, struct macb_queue,
1087 tx_error_task);
1088 bool halt_timeout = false;
1089 struct macb *bp = queue->bp;
1090 struct macb_tx_skb *tx_skb;
1091 struct macb_dma_desc *desc;
1092 struct sk_buff *skb;
1093 unsigned int tail;
1094 unsigned long flags;
1095
1096 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1097 (unsigned int)(queue - bp->queues),
1098 queue->tx_tail, queue->tx_head);
1099
1100 /* Prevent the queue NAPI TX poll from running, as it calls
1101 * macb_tx_complete(), which in turn may call netif_wake_subqueue().
1102 * As explained below, we have to halt the transmission before updating
1103 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1104 * network engine about the macb/gem being halted.
1105 */
1106 napi_disable(&queue->napi_tx);
1107 spin_lock_irqsave(&bp->lock, flags);
1108
1109 /* Make sure nobody is trying to queue up new packets */
1110 netif_tx_stop_all_queues(bp->dev);
1111
1112 /* Stop transmission now
1113 * (in case we have just queued new packets)
1114 * macb/gem must be halted to write TBQP register
1115 */
1116 if (macb_halt_tx(bp)) {
1117 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1118 macb_writel(bp, NCR, macb_readl(bp, NCR) & (~MACB_BIT(TE)));
1119 halt_timeout = true;
1120 }
1121
1122 /* Treat frames in TX queue including the ones that caused the error.
1123 * Free transmit buffers in upper layer.
1124 */
1125 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1126 u32 ctrl;
1127
1128 desc = macb_tx_desc(queue, tail);
1129 ctrl = desc->ctrl;
1130 tx_skb = macb_tx_skb(queue, tail);
1131 skb = tx_skb->skb;
1132
1133 if (ctrl & MACB_BIT(TX_USED)) {
1134 /* skb is set for the last buffer of the frame */
1135 while (!skb) {
1136 macb_tx_unmap(bp, tx_skb, 0);
1137 tail++;
1138 tx_skb = macb_tx_skb(queue, tail);
1139 skb = tx_skb->skb;
1140 }
1141
1142 /* ctrl still refers to the first buffer descriptor
1143 * since it's the only one written back by the hardware
1144 */
1145 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1146 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1147 macb_tx_ring_wrap(bp, tail),
1148 skb->data);
1149 bp->dev->stats.tx_packets++;
1150 queue->stats.tx_packets++;
1151 bp->dev->stats.tx_bytes += skb->len;
1152 queue->stats.tx_bytes += skb->len;
1153 }
1154 } else {
1155 /* "Buffers exhausted mid-frame" errors may only happen
1156 * if the driver is buggy, so complain loudly about
1157 * those. Statistics are updated by hardware.
1158 */
1159 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1160 netdev_err(bp->dev,
1161 "BUG: TX buffers exhausted mid-frame\n");
1162
1163 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1164 }
1165
1166 macb_tx_unmap(bp, tx_skb, 0);
1167 }
1168
1169 /* Set end of TX queue */
1170 desc = macb_tx_desc(queue, 0);
1171 macb_set_addr(bp, desc, 0);
1172 desc->ctrl = MACB_BIT(TX_USED);
1173
1174 /* Make descriptor updates visible to hardware */
1175 wmb();
1176
1177 /* Reinitialize the TX desc queue */
1178 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1179#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1180 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1181 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1182#endif
1183 /* Make TX ring reflect state of hardware */
1184 queue->tx_head = 0;
1185 queue->tx_tail = 0;
1186
1187 /* Housework before enabling TX IRQ */
1188 macb_writel(bp, TSR, macb_readl(bp, TSR));
1189 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1190
1191 if (halt_timeout)
1192 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
1193
1194 /* Now we are ready to start transmission again */
1195 netif_tx_start_all_queues(bp->dev);
1196 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1197
1198 spin_unlock_irqrestore(&bp->lock, flags);
1199 napi_enable(&queue->napi_tx);
1200}
1201
1202static bool ptp_one_step_sync(struct sk_buff *skb)
1203{
1204 struct ptp_header *hdr;
1205 unsigned int ptp_class;
1206 u8 msgtype;
1207
1208 /* No need to parse packet if PTP TS is not involved */
1209 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
1210 goto not_oss;
1211
1212 /* Identify and return whether PTP one step sync is being processed */
1213 ptp_class = ptp_classify_raw(skb);
1214 if (ptp_class == PTP_CLASS_NONE)
1215 goto not_oss;
1216
1217 hdr = ptp_parse_header(skb, ptp_class);
1218 if (!hdr)
1219 goto not_oss;
1220
1221 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP)
1222 goto not_oss;
1223
1224 msgtype = ptp_get_msgtype(hdr, ptp_class);
1225 if (msgtype == PTP_MSGTYPE_SYNC)
1226 return true;
1227
1228not_oss:
1229 return false;
1230}
1231
1232static int macb_tx_complete(struct macb_queue *queue, int budget)
1233{
1234 struct macb *bp = queue->bp;
1235 u16 queue_index = queue - bp->queues;
1236 unsigned int tail;
1237 unsigned int head;
1238 int packets = 0;
1239
1240 spin_lock(&queue->tx_ptr_lock);
1241 head = queue->tx_head;
1242 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) {
1243 struct macb_tx_skb *tx_skb;
1244 struct sk_buff *skb;
1245 struct macb_dma_desc *desc;
1246 u32 ctrl;
1247
1248 desc = macb_tx_desc(queue, tail);
1249
1250 /* Make hw descriptor updates visible to CPU */
1251 rmb();
1252
1253 ctrl = desc->ctrl;
1254
1255 /* TX_USED bit is only set by hardware on the very first buffer
1256 * descriptor of the transmitted frame.
1257 */
1258 if (!(ctrl & MACB_BIT(TX_USED)))
1259 break;
1260
1261 /* Process all buffers of the current transmitted frame */
1262 for (;; tail++) {
1263 tx_skb = macb_tx_skb(queue, tail);
1264 skb = tx_skb->skb;
1265
1266 /* First, update TX stats if needed */
1267 if (skb) {
1268 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1269 !ptp_one_step_sync(skb))
1270 gem_ptp_do_txstamp(bp, skb, desc);
1271
1272 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1273 macb_tx_ring_wrap(bp, tail),
1274 skb->data);
1275 bp->dev->stats.tx_packets++;
1276 queue->stats.tx_packets++;
1277 bp->dev->stats.tx_bytes += skb->len;
1278 queue->stats.tx_bytes += skb->len;
1279 packets++;
1280 }
1281
1282 /* Now we can safely release resources */
1283 macb_tx_unmap(bp, tx_skb, budget);
1284
1285 /* skb is set only for the last buffer of the frame.
1286 * WARNING: at this point skb has been freed by
1287 * macb_tx_unmap().
1288 */
1289 if (skb)
1290 break;
1291 }
1292 }
1293
1294 queue->tx_tail = tail;
1295 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1296 CIRC_CNT(queue->tx_head, queue->tx_tail,
1297 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1298 netif_wake_subqueue(bp->dev, queue_index);
1299 spin_unlock(&queue->tx_ptr_lock);
1300
1301 return packets;
1302}
1303
1304static void gem_rx_refill(struct macb_queue *queue)
1305{
1306 unsigned int entry;
1307 struct sk_buff *skb;
1308 dma_addr_t paddr;
1309 struct macb *bp = queue->bp;
1310 struct macb_dma_desc *desc;
1311
1312 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1313 bp->rx_ring_size) > 0) {
1314 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1315
1316 /* Make hw descriptor updates visible to CPU */
1317 rmb();
1318
1319 desc = macb_rx_desc(queue, entry);
1320
1321 if (!queue->rx_skbuff[entry]) {
1322 /* allocate sk_buff for this free entry in ring */
1323 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1324 if (unlikely(!skb)) {
1325 netdev_err(bp->dev,
1326 "Unable to allocate sk_buff\n");
1327 break;
1328 }
1329
1330 /* now fill corresponding descriptor entry */
1331 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1332 bp->rx_buffer_size,
1333 DMA_FROM_DEVICE);
1334 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1335 dev_kfree_skb(skb);
1336 break;
1337 }
1338
1339 queue->rx_skbuff[entry] = skb;
1340
1341 if (entry == bp->rx_ring_size - 1)
1342 paddr |= MACB_BIT(RX_WRAP);
1343 desc->ctrl = 0;
1344 /* Setting addr clears RX_USED and allows reception,
1345 * make sure ctrl is cleared first to avoid a race.
1346 */
1347 dma_wmb();
1348 macb_set_addr(bp, desc, paddr);
1349
1350 /* properly align Ethernet header */
1351 skb_reserve(skb, NET_IP_ALIGN);
1352 } else {
1353 desc->ctrl = 0;
1354 dma_wmb();
1355 desc->addr &= ~MACB_BIT(RX_USED);
1356 }
1357 queue->rx_prepared_head++;
1358 }
1359
1360 /* Make descriptor updates visible to hardware */
1361 wmb();
1362
1363 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1364 queue, queue->rx_prepared_head, queue->rx_tail);
1365}
1366
1367/* Mark DMA descriptors from begin up to and not including end as unused */
1368static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1369 unsigned int end)
1370{
1371 unsigned int frag;
1372
1373 for (frag = begin; frag != end; frag++) {
1374 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1375
1376 desc->addr &= ~MACB_BIT(RX_USED);
1377 }
1378
1379 /* Make descriptor updates visible to hardware */
1380 wmb();
1381
1382 /* When this happens, the hardware stats registers for
1383 * whatever caused this is updated, so we don't have to record
1384 * anything.
1385 */
1386}
1387
1388static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1389 int budget)
1390{
1391 struct macb *bp = queue->bp;
1392 unsigned int len;
1393 unsigned int entry;
1394 struct sk_buff *skb;
1395 struct macb_dma_desc *desc;
1396 int count = 0;
1397
1398 while (count < budget) {
1399 u32 ctrl;
1400 dma_addr_t addr;
1401 bool rxused;
1402
1403 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1404 desc = macb_rx_desc(queue, entry);
1405
1406 /* Make hw descriptor updates visible to CPU */
1407 rmb();
1408
1409 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1410 addr = macb_get_addr(bp, desc);
1411
1412 if (!rxused)
1413 break;
1414
1415 /* Ensure ctrl is at least as up-to-date as rxused */
1416 dma_rmb();
1417
1418 ctrl = desc->ctrl;
1419
1420 queue->rx_tail++;
1421 count++;
1422
1423 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1424 netdev_err(bp->dev,
1425 "not whole frame pointed by descriptor\n");
1426 bp->dev->stats.rx_dropped++;
1427 queue->stats.rx_dropped++;
1428 break;
1429 }
1430 skb = queue->rx_skbuff[entry];
1431 if (unlikely(!skb)) {
1432 netdev_err(bp->dev,
1433 "inconsistent Rx descriptor chain\n");
1434 bp->dev->stats.rx_dropped++;
1435 queue->stats.rx_dropped++;
1436 break;
1437 }
1438 /* now everything is ready for receiving packet */
1439 queue->rx_skbuff[entry] = NULL;
1440 len = ctrl & bp->rx_frm_len_mask;
1441
1442 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1443
1444 skb_put(skb, len);
1445 dma_unmap_single(&bp->pdev->dev, addr,
1446 bp->rx_buffer_size, DMA_FROM_DEVICE);
1447
1448 skb->protocol = eth_type_trans(skb, bp->dev);
1449 skb_checksum_none_assert(skb);
1450 if (bp->dev->features & NETIF_F_RXCSUM &&
1451 !(bp->dev->flags & IFF_PROMISC) &&
1452 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1453 skb->ip_summed = CHECKSUM_UNNECESSARY;
1454
1455 bp->dev->stats.rx_packets++;
1456 queue->stats.rx_packets++;
1457 bp->dev->stats.rx_bytes += skb->len;
1458 queue->stats.rx_bytes += skb->len;
1459
1460 gem_ptp_do_rxstamp(bp, skb, desc);
1461
1462#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1463 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1464 skb->len, skb->csum);
1465 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1466 skb_mac_header(skb), 16, true);
1467 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1468 skb->data, 32, true);
1469#endif
1470
1471 napi_gro_receive(napi, skb);
1472 }
1473
1474 gem_rx_refill(queue);
1475
1476 return count;
1477}
1478
1479static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1480 unsigned int first_frag, unsigned int last_frag)
1481{
1482 unsigned int len;
1483 unsigned int frag;
1484 unsigned int offset;
1485 struct sk_buff *skb;
1486 struct macb_dma_desc *desc;
1487 struct macb *bp = queue->bp;
1488
1489 desc = macb_rx_desc(queue, last_frag);
1490 len = desc->ctrl & bp->rx_frm_len_mask;
1491
1492 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1493 macb_rx_ring_wrap(bp, first_frag),
1494 macb_rx_ring_wrap(bp, last_frag), len);
1495
1496 /* The ethernet header starts NET_IP_ALIGN bytes into the
1497 * first buffer. Since the header is 14 bytes, this makes the
1498 * payload word-aligned.
1499 *
1500 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1501 * the two padding bytes into the skb so that we avoid hitting
1502 * the slowpath in memcpy(), and pull them off afterwards.
1503 */
1504 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1505 if (!skb) {
1506 bp->dev->stats.rx_dropped++;
1507 for (frag = first_frag; ; frag++) {
1508 desc = macb_rx_desc(queue, frag);
1509 desc->addr &= ~MACB_BIT(RX_USED);
1510 if (frag == last_frag)
1511 break;
1512 }
1513
1514 /* Make descriptor updates visible to hardware */
1515 wmb();
1516
1517 return 1;
1518 }
1519
1520 offset = 0;
1521 len += NET_IP_ALIGN;
1522 skb_checksum_none_assert(skb);
1523 skb_put(skb, len);
1524
1525 for (frag = first_frag; ; frag++) {
1526 unsigned int frag_len = bp->rx_buffer_size;
1527
1528 if (offset + frag_len > len) {
1529 if (unlikely(frag != last_frag)) {
1530 dev_kfree_skb_any(skb);
1531 return -1;
1532 }
1533 frag_len = len - offset;
1534 }
1535 skb_copy_to_linear_data_offset(skb, offset,
1536 macb_rx_buffer(queue, frag),
1537 frag_len);
1538 offset += bp->rx_buffer_size;
1539 desc = macb_rx_desc(queue, frag);
1540 desc->addr &= ~MACB_BIT(RX_USED);
1541
1542 if (frag == last_frag)
1543 break;
1544 }
1545
1546 /* Make descriptor updates visible to hardware */
1547 wmb();
1548
1549 __skb_pull(skb, NET_IP_ALIGN);
1550 skb->protocol = eth_type_trans(skb, bp->dev);
1551
1552 bp->dev->stats.rx_packets++;
1553 bp->dev->stats.rx_bytes += skb->len;
1554 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1555 skb->len, skb->csum);
1556 napi_gro_receive(napi, skb);
1557
1558 return 0;
1559}
1560
1561static inline void macb_init_rx_ring(struct macb_queue *queue)
1562{
1563 struct macb *bp = queue->bp;
1564 dma_addr_t addr;
1565 struct macb_dma_desc *desc = NULL;
1566 int i;
1567
1568 addr = queue->rx_buffers_dma;
1569 for (i = 0; i < bp->rx_ring_size; i++) {
1570 desc = macb_rx_desc(queue, i);
1571 macb_set_addr(bp, desc, addr);
1572 desc->ctrl = 0;
1573 addr += bp->rx_buffer_size;
1574 }
1575 desc->addr |= MACB_BIT(RX_WRAP);
1576 queue->rx_tail = 0;
1577}
1578
1579static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1580 int budget)
1581{
1582 struct macb *bp = queue->bp;
1583 bool reset_rx_queue = false;
1584 int received = 0;
1585 unsigned int tail;
1586 int first_frag = -1;
1587
1588 for (tail = queue->rx_tail; budget > 0; tail++) {
1589 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1590 u32 ctrl;
1591
1592 /* Make hw descriptor updates visible to CPU */
1593 rmb();
1594
1595 if (!(desc->addr & MACB_BIT(RX_USED)))
1596 break;
1597
1598 /* Ensure ctrl is at least as up-to-date as addr */
1599 dma_rmb();
1600
1601 ctrl = desc->ctrl;
1602
1603 if (ctrl & MACB_BIT(RX_SOF)) {
1604 if (first_frag != -1)
1605 discard_partial_frame(queue, first_frag, tail);
1606 first_frag = tail;
1607 }
1608
1609 if (ctrl & MACB_BIT(RX_EOF)) {
1610 int dropped;
1611
1612 if (unlikely(first_frag == -1)) {
1613 reset_rx_queue = true;
1614 continue;
1615 }
1616
1617 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1618 first_frag = -1;
1619 if (unlikely(dropped < 0)) {
1620 reset_rx_queue = true;
1621 continue;
1622 }
1623 if (!dropped) {
1624 received++;
1625 budget--;
1626 }
1627 }
1628 }
1629
1630 if (unlikely(reset_rx_queue)) {
1631 unsigned long flags;
1632 u32 ctrl;
1633
1634 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1635
1636 spin_lock_irqsave(&bp->lock, flags);
1637
1638 ctrl = macb_readl(bp, NCR);
1639 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1640
1641 macb_init_rx_ring(queue);
1642 queue_writel(queue, RBQP, queue->rx_ring_dma);
1643
1644 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1645
1646 spin_unlock_irqrestore(&bp->lock, flags);
1647 return received;
1648 }
1649
1650 if (first_frag != -1)
1651 queue->rx_tail = first_frag;
1652 else
1653 queue->rx_tail = tail;
1654
1655 return received;
1656}
1657
1658static bool macb_rx_pending(struct macb_queue *queue)
1659{
1660 struct macb *bp = queue->bp;
1661 unsigned int entry;
1662 struct macb_dma_desc *desc;
1663
1664 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1665 desc = macb_rx_desc(queue, entry);
1666
1667 /* Make hw descriptor updates visible to CPU */
1668 rmb();
1669
1670 return (desc->addr & MACB_BIT(RX_USED)) != 0;
1671}
1672
1673static int macb_rx_poll(struct napi_struct *napi, int budget)
1674{
1675 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx);
1676 struct macb *bp = queue->bp;
1677 int work_done;
1678
1679 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1680
1681 netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n",
1682 (unsigned int)(queue - bp->queues), work_done, budget);
1683
1684 if (work_done < budget && napi_complete_done(napi, work_done)) {
1685 queue_writel(queue, IER, bp->rx_intr_mask);
1686
1687 /* Packet completions only seem to propagate to raise
1688 * interrupts when interrupts are enabled at the time, so if
1689 * packets were received while interrupts were disabled,
1690 * they will not cause another interrupt to be generated when
1691 * interrupts are re-enabled.
1692 * Check for this case here to avoid losing a wakeup. This can
1693 * potentially race with the interrupt handler doing the same
1694 * actions if an interrupt is raised just after enabling them,
1695 * but this should be harmless.
1696 */
1697 if (macb_rx_pending(queue)) {
1698 queue_writel(queue, IDR, bp->rx_intr_mask);
1699 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1700 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1701 netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n");
1702 napi_schedule(napi);
1703 }
1704 }
1705
1706 /* TODO: Handle errors */
1707
1708 return work_done;
1709}
1710
1711static void macb_tx_restart(struct macb_queue *queue)
1712{
1713 struct macb *bp = queue->bp;
1714 unsigned int head_idx, tbqp;
1715
1716 spin_lock(&queue->tx_ptr_lock);
1717
1718 if (queue->tx_head == queue->tx_tail)
1719 goto out_tx_ptr_unlock;
1720
1721 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1722 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1723 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head));
1724
1725 if (tbqp == head_idx)
1726 goto out_tx_ptr_unlock;
1727
1728 spin_lock_irq(&bp->lock);
1729 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1730 spin_unlock_irq(&bp->lock);
1731
1732out_tx_ptr_unlock:
1733 spin_unlock(&queue->tx_ptr_lock);
1734}
1735
1736static bool macb_tx_complete_pending(struct macb_queue *queue)
1737{
1738 bool retval = false;
1739
1740 spin_lock(&queue->tx_ptr_lock);
1741 if (queue->tx_head != queue->tx_tail) {
1742 /* Make hw descriptor updates visible to CPU */
1743 rmb();
1744
1745 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED))
1746 retval = true;
1747 }
1748 spin_unlock(&queue->tx_ptr_lock);
1749 return retval;
1750}
1751
1752static int macb_tx_poll(struct napi_struct *napi, int budget)
1753{
1754 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx);
1755 struct macb *bp = queue->bp;
1756 int work_done;
1757
1758 work_done = macb_tx_complete(queue, budget);
1759
1760 rmb(); // ensure txubr_pending is up to date
1761 if (queue->txubr_pending) {
1762 queue->txubr_pending = false;
1763 netdev_vdbg(bp->dev, "poll: tx restart\n");
1764 macb_tx_restart(queue);
1765 }
1766
1767 netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n",
1768 (unsigned int)(queue - bp->queues), work_done, budget);
1769
1770 if (work_done < budget && napi_complete_done(napi, work_done)) {
1771 queue_writel(queue, IER, MACB_BIT(TCOMP));
1772
1773 /* Packet completions only seem to propagate to raise
1774 * interrupts when interrupts are enabled at the time, so if
1775 * packets were sent while interrupts were disabled,
1776 * they will not cause another interrupt to be generated when
1777 * interrupts are re-enabled.
1778 * Check for this case here to avoid losing a wakeup. This can
1779 * potentially race with the interrupt handler doing the same
1780 * actions if an interrupt is raised just after enabling them,
1781 * but this should be harmless.
1782 */
1783 if (macb_tx_complete_pending(queue)) {
1784 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1785 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1786 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1787 netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n");
1788 napi_schedule(napi);
1789 }
1790 }
1791
1792 return work_done;
1793}
1794
1795static void macb_hresp_error_task(struct tasklet_struct *t)
1796{
1797 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1798 struct net_device *dev = bp->dev;
1799 struct macb_queue *queue;
1800 unsigned int q;
1801 u32 ctrl;
1802
1803 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1804 queue_writel(queue, IDR, bp->rx_intr_mask |
1805 MACB_TX_INT_FLAGS |
1806 MACB_BIT(HRESP));
1807 }
1808 ctrl = macb_readl(bp, NCR);
1809 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1810 macb_writel(bp, NCR, ctrl);
1811
1812 netif_tx_stop_all_queues(dev);
1813 netif_carrier_off(dev);
1814
1815 bp->macbgem_ops.mog_init_rings(bp);
1816
1817 /* Initialize TX and RX buffers */
1818 macb_init_buffers(bp);
1819
1820 /* Enable interrupts */
1821 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1822 queue_writel(queue, IER,
1823 bp->rx_intr_mask |
1824 MACB_TX_INT_FLAGS |
1825 MACB_BIT(HRESP));
1826
1827 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1828 macb_writel(bp, NCR, ctrl);
1829
1830 netif_carrier_on(dev);
1831 netif_tx_start_all_queues(dev);
1832}
1833
1834static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1835{
1836 struct macb_queue *queue = dev_id;
1837 struct macb *bp = queue->bp;
1838 u32 status;
1839
1840 status = queue_readl(queue, ISR);
1841
1842 if (unlikely(!status))
1843 return IRQ_NONE;
1844
1845 spin_lock(&bp->lock);
1846
1847 if (status & MACB_BIT(WOL)) {
1848 queue_writel(queue, IDR, MACB_BIT(WOL));
1849 macb_writel(bp, WOL, 0);
1850 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1851 (unsigned int)(queue - bp->queues),
1852 (unsigned long)status);
1853 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1854 queue_writel(queue, ISR, MACB_BIT(WOL));
1855 pm_wakeup_event(&bp->pdev->dev, 0);
1856 }
1857
1858 spin_unlock(&bp->lock);
1859
1860 return IRQ_HANDLED;
1861}
1862
1863static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1864{
1865 struct macb_queue *queue = dev_id;
1866 struct macb *bp = queue->bp;
1867 u32 status;
1868
1869 status = queue_readl(queue, ISR);
1870
1871 if (unlikely(!status))
1872 return IRQ_NONE;
1873
1874 spin_lock(&bp->lock);
1875
1876 if (status & GEM_BIT(WOL)) {
1877 queue_writel(queue, IDR, GEM_BIT(WOL));
1878 gem_writel(bp, WOL, 0);
1879 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1880 (unsigned int)(queue - bp->queues),
1881 (unsigned long)status);
1882 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1883 queue_writel(queue, ISR, GEM_BIT(WOL));
1884 pm_wakeup_event(&bp->pdev->dev, 0);
1885 }
1886
1887 spin_unlock(&bp->lock);
1888
1889 return IRQ_HANDLED;
1890}
1891
1892static irqreturn_t macb_interrupt(int irq, void *dev_id)
1893{
1894 struct macb_queue *queue = dev_id;
1895 struct macb *bp = queue->bp;
1896 struct net_device *dev = bp->dev;
1897 u32 status, ctrl;
1898
1899 status = queue_readl(queue, ISR);
1900
1901 if (unlikely(!status))
1902 return IRQ_NONE;
1903
1904 spin_lock(&bp->lock);
1905
1906 while (status) {
1907 /* close possible race with dev_close */
1908 if (unlikely(!netif_running(dev))) {
1909 queue_writel(queue, IDR, -1);
1910 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1911 queue_writel(queue, ISR, -1);
1912 break;
1913 }
1914
1915 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1916 (unsigned int)(queue - bp->queues),
1917 (unsigned long)status);
1918
1919 if (status & bp->rx_intr_mask) {
1920 /* There's no point taking any more interrupts
1921 * until we have processed the buffers. The
1922 * scheduling call may fail if the poll routine
1923 * is already scheduled, so disable interrupts
1924 * now.
1925 */
1926 queue_writel(queue, IDR, bp->rx_intr_mask);
1927 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1928 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1929
1930 if (napi_schedule_prep(&queue->napi_rx)) {
1931 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1932 __napi_schedule(&queue->napi_rx);
1933 }
1934 }
1935
1936 if (status & (MACB_BIT(TCOMP) |
1937 MACB_BIT(TXUBR))) {
1938 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1939 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1940 queue_writel(queue, ISR, MACB_BIT(TCOMP) |
1941 MACB_BIT(TXUBR));
1942
1943 if (status & MACB_BIT(TXUBR)) {
1944 queue->txubr_pending = true;
1945 wmb(); // ensure softirq can see update
1946 }
1947
1948 if (napi_schedule_prep(&queue->napi_tx)) {
1949 netdev_vdbg(bp->dev, "scheduling TX softirq\n");
1950 __napi_schedule(&queue->napi_tx);
1951 }
1952 }
1953
1954 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1955 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1956 schedule_work(&queue->tx_error_task);
1957
1958 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1959 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1960
1961 break;
1962 }
1963
1964 /* Link change detection isn't possible with RMII, so we'll
1965 * add that if/when we get our hands on a full-blown MII PHY.
1966 */
1967
1968 /* There is a hardware issue under heavy load where DMA can
1969 * stop, this causes endless "used buffer descriptor read"
1970 * interrupts but it can be cleared by re-enabling RX. See
1971 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1972 * section 16.7.4 for details. RXUBR is only enabled for
1973 * these two versions.
1974 */
1975 if (status & MACB_BIT(RXUBR)) {
1976 ctrl = macb_readl(bp, NCR);
1977 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1978 wmb();
1979 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1980
1981 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1982 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1983 }
1984
1985 if (status & MACB_BIT(ISR_ROVR)) {
1986 /* We missed at least one packet */
1987 if (macb_is_gem(bp))
1988 bp->hw_stats.gem.rx_overruns++;
1989 else
1990 bp->hw_stats.macb.rx_overruns++;
1991
1992 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1993 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1994 }
1995
1996 if (status & MACB_BIT(HRESP)) {
1997 tasklet_schedule(&bp->hresp_err_tasklet);
1998 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1999
2000 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2001 queue_writel(queue, ISR, MACB_BIT(HRESP));
2002 }
2003 status = queue_readl(queue, ISR);
2004 }
2005
2006 spin_unlock(&bp->lock);
2007
2008 return IRQ_HANDLED;
2009}
2010
2011#ifdef CONFIG_NET_POLL_CONTROLLER
2012/* Polling receive - used by netconsole and other diagnostic tools
2013 * to allow network i/o with interrupts disabled.
2014 */
2015static void macb_poll_controller(struct net_device *dev)
2016{
2017 struct macb *bp = netdev_priv(dev);
2018 struct macb_queue *queue;
2019 unsigned long flags;
2020 unsigned int q;
2021
2022 local_irq_save(flags);
2023 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2024 macb_interrupt(dev->irq, queue);
2025 local_irq_restore(flags);
2026}
2027#endif
2028
2029static unsigned int macb_tx_map(struct macb *bp,
2030 struct macb_queue *queue,
2031 struct sk_buff *skb,
2032 unsigned int hdrlen)
2033{
2034 dma_addr_t mapping;
2035 unsigned int len, entry, i, tx_head = queue->tx_head;
2036 struct macb_tx_skb *tx_skb = NULL;
2037 struct macb_dma_desc *desc;
2038 unsigned int offset, size, count = 0;
2039 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
2040 unsigned int eof = 1, mss_mfs = 0;
2041 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
2042
2043 /* LSO */
2044 if (skb_shinfo(skb)->gso_size != 0) {
2045 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2046 /* UDP - UFO */
2047 lso_ctrl = MACB_LSO_UFO_ENABLE;
2048 else
2049 /* TCP - TSO */
2050 lso_ctrl = MACB_LSO_TSO_ENABLE;
2051 }
2052
2053 /* First, map non-paged data */
2054 len = skb_headlen(skb);
2055
2056 /* first buffer length */
2057 size = hdrlen;
2058
2059 offset = 0;
2060 while (len) {
2061 entry = macb_tx_ring_wrap(bp, tx_head);
2062 tx_skb = &queue->tx_skb[entry];
2063
2064 mapping = dma_map_single(&bp->pdev->dev,
2065 skb->data + offset,
2066 size, DMA_TO_DEVICE);
2067 if (dma_mapping_error(&bp->pdev->dev, mapping))
2068 goto dma_error;
2069
2070 /* Save info to properly release resources */
2071 tx_skb->skb = NULL;
2072 tx_skb->mapping = mapping;
2073 tx_skb->size = size;
2074 tx_skb->mapped_as_page = false;
2075
2076 len -= size;
2077 offset += size;
2078 count++;
2079 tx_head++;
2080
2081 size = min(len, bp->max_tx_length);
2082 }
2083
2084 /* Then, map paged data from fragments */
2085 for (f = 0; f < nr_frags; f++) {
2086 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2087
2088 len = skb_frag_size(frag);
2089 offset = 0;
2090 while (len) {
2091 size = min(len, bp->max_tx_length);
2092 entry = macb_tx_ring_wrap(bp, tx_head);
2093 tx_skb = &queue->tx_skb[entry];
2094
2095 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
2096 offset, size, DMA_TO_DEVICE);
2097 if (dma_mapping_error(&bp->pdev->dev, mapping))
2098 goto dma_error;
2099
2100 /* Save info to properly release resources */
2101 tx_skb->skb = NULL;
2102 tx_skb->mapping = mapping;
2103 tx_skb->size = size;
2104 tx_skb->mapped_as_page = true;
2105
2106 len -= size;
2107 offset += size;
2108 count++;
2109 tx_head++;
2110 }
2111 }
2112
2113 /* Should never happen */
2114 if (unlikely(!tx_skb)) {
2115 netdev_err(bp->dev, "BUG! empty skb!\n");
2116 return 0;
2117 }
2118
2119 /* This is the last buffer of the frame: save socket buffer */
2120 tx_skb->skb = skb;
2121
2122 /* Update TX ring: update buffer descriptors in reverse order
2123 * to avoid race condition
2124 */
2125
2126 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
2127 * to set the end of TX queue
2128 */
2129 i = tx_head;
2130 entry = macb_tx_ring_wrap(bp, i);
2131 ctrl = MACB_BIT(TX_USED);
2132 desc = macb_tx_desc(queue, entry);
2133 desc->ctrl = ctrl;
2134
2135 if (lso_ctrl) {
2136 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
2137 /* include header and FCS in value given to h/w */
2138 mss_mfs = skb_shinfo(skb)->gso_size +
2139 skb_transport_offset(skb) +
2140 ETH_FCS_LEN;
2141 else /* TSO */ {
2142 mss_mfs = skb_shinfo(skb)->gso_size;
2143 /* TCP Sequence Number Source Select
2144 * can be set only for TSO
2145 */
2146 seq_ctrl = 0;
2147 }
2148 }
2149
2150 do {
2151 i--;
2152 entry = macb_tx_ring_wrap(bp, i);
2153 tx_skb = &queue->tx_skb[entry];
2154 desc = macb_tx_desc(queue, entry);
2155
2156 ctrl = (u32)tx_skb->size;
2157 if (eof) {
2158 ctrl |= MACB_BIT(TX_LAST);
2159 eof = 0;
2160 }
2161 if (unlikely(entry == (bp->tx_ring_size - 1)))
2162 ctrl |= MACB_BIT(TX_WRAP);
2163
2164 /* First descriptor is header descriptor */
2165 if (i == queue->tx_head) {
2166 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2167 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2168 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2169 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl &&
2170 !ptp_one_step_sync(skb))
2171 ctrl |= MACB_BIT(TX_NOCRC);
2172 } else
2173 /* Only set MSS/MFS on payload descriptors
2174 * (second or later descriptor)
2175 */
2176 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2177
2178 /* Set TX buffer descriptor */
2179 macb_set_addr(bp, desc, tx_skb->mapping);
2180 /* desc->addr must be visible to hardware before clearing
2181 * 'TX_USED' bit in desc->ctrl.
2182 */
2183 wmb();
2184 desc->ctrl = ctrl;
2185 } while (i != queue->tx_head);
2186
2187 queue->tx_head = tx_head;
2188
2189 return count;
2190
2191dma_error:
2192 netdev_err(bp->dev, "TX DMA map failed\n");
2193
2194 for (i = queue->tx_head; i != tx_head; i++) {
2195 tx_skb = macb_tx_skb(queue, i);
2196
2197 macb_tx_unmap(bp, tx_skb, 0);
2198 }
2199
2200 return 0;
2201}
2202
2203static netdev_features_t macb_features_check(struct sk_buff *skb,
2204 struct net_device *dev,
2205 netdev_features_t features)
2206{
2207 unsigned int nr_frags, f;
2208 unsigned int hdrlen;
2209
2210 /* Validate LSO compatibility */
2211
2212 /* there is only one buffer or protocol is not UDP */
2213 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2214 return features;
2215
2216 /* length of header */
2217 hdrlen = skb_transport_offset(skb);
2218
2219 /* For UFO only:
2220 * When software supplies two or more payload buffers all payload buffers
2221 * apart from the last must be a multiple of 8 bytes in size.
2222 */
2223 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2224 return features & ~MACB_NETIF_LSO;
2225
2226 nr_frags = skb_shinfo(skb)->nr_frags;
2227 /* No need to check last fragment */
2228 nr_frags--;
2229 for (f = 0; f < nr_frags; f++) {
2230 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2231
2232 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2233 return features & ~MACB_NETIF_LSO;
2234 }
2235 return features;
2236}
2237
2238static inline int macb_clear_csum(struct sk_buff *skb)
2239{
2240 /* no change for packets without checksum offloading */
2241 if (skb->ip_summed != CHECKSUM_PARTIAL)
2242 return 0;
2243
2244 /* make sure we can modify the header */
2245 if (unlikely(skb_cow_head(skb, 0)))
2246 return -1;
2247
2248 /* initialize checksum field
2249 * This is required - at least for Zynq, which otherwise calculates
2250 * wrong UDP header checksums for UDP packets with UDP data len <=2
2251 */
2252 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2253 return 0;
2254}
2255
2256static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2257{
2258 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2259 skb_is_nonlinear(*skb);
2260 int padlen = ETH_ZLEN - (*skb)->len;
2261 int tailroom = skb_tailroom(*skb);
2262 struct sk_buff *nskb;
2263 u32 fcs;
2264
2265 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2266 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2267 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb))
2268 return 0;
2269
2270 if (padlen <= 0) {
2271 /* FCS could be appeded to tailroom. */
2272 if (tailroom >= ETH_FCS_LEN)
2273 goto add_fcs;
2274 /* No room for FCS, need to reallocate skb. */
2275 else
2276 padlen = ETH_FCS_LEN;
2277 } else {
2278 /* Add room for FCS. */
2279 padlen += ETH_FCS_LEN;
2280 }
2281
2282 if (cloned || tailroom < padlen) {
2283 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2284 if (!nskb)
2285 return -ENOMEM;
2286
2287 dev_consume_skb_any(*skb);
2288 *skb = nskb;
2289 }
2290
2291 if (padlen > ETH_FCS_LEN)
2292 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2293
2294add_fcs:
2295 /* set FCS to packet */
2296 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2297 fcs = ~fcs;
2298
2299 skb_put_u8(*skb, fcs & 0xff);
2300 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2301 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2302 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2303
2304 return 0;
2305}
2306
2307static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2308{
2309 u16 queue_index = skb_get_queue_mapping(skb);
2310 struct macb *bp = netdev_priv(dev);
2311 struct macb_queue *queue = &bp->queues[queue_index];
2312 unsigned int desc_cnt, nr_frags, frag_size, f;
2313 unsigned int hdrlen;
2314 bool is_lso;
2315 netdev_tx_t ret = NETDEV_TX_OK;
2316
2317 if (macb_clear_csum(skb)) {
2318 dev_kfree_skb_any(skb);
2319 return ret;
2320 }
2321
2322 if (macb_pad_and_fcs(&skb, dev)) {
2323 dev_kfree_skb_any(skb);
2324 return ret;
2325 }
2326
2327#ifdef CONFIG_MACB_USE_HWSTAMP
2328 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2329 (bp->hw_dma_cap & HW_DMA_CAP_PTP))
2330 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2331#endif
2332
2333 is_lso = (skb_shinfo(skb)->gso_size != 0);
2334
2335 if (is_lso) {
2336 /* length of headers */
2337 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2338 /* only queue eth + ip headers separately for UDP */
2339 hdrlen = skb_transport_offset(skb);
2340 else
2341 hdrlen = skb_tcp_all_headers(skb);
2342 if (skb_headlen(skb) < hdrlen) {
2343 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2344 /* if this is required, would need to copy to single buffer */
2345 return NETDEV_TX_BUSY;
2346 }
2347 } else
2348 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2349
2350#if defined(DEBUG) && defined(VERBOSE_DEBUG)
2351 netdev_vdbg(bp->dev,
2352 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2353 queue_index, skb->len, skb->head, skb->data,
2354 skb_tail_pointer(skb), skb_end_pointer(skb));
2355 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2356 skb->data, 16, true);
2357#endif
2358
2359 /* Count how many TX buffer descriptors are needed to send this
2360 * socket buffer: skb fragments of jumbo frames may need to be
2361 * split into many buffer descriptors.
2362 */
2363 if (is_lso && (skb_headlen(skb) > hdrlen))
2364 /* extra header descriptor if also payload in first buffer */
2365 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2366 else
2367 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2368 nr_frags = skb_shinfo(skb)->nr_frags;
2369 for (f = 0; f < nr_frags; f++) {
2370 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2371 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2372 }
2373
2374 spin_lock_bh(&queue->tx_ptr_lock);
2375
2376 /* This is a hard error, log it. */
2377 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2378 bp->tx_ring_size) < desc_cnt) {
2379 netif_stop_subqueue(dev, queue_index);
2380 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2381 queue->tx_head, queue->tx_tail);
2382 ret = NETDEV_TX_BUSY;
2383 goto unlock;
2384 }
2385
2386 /* Map socket buffer for DMA transfer */
2387 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2388 dev_kfree_skb_any(skb);
2389 goto unlock;
2390 }
2391
2392 /* Make newly initialized descriptor visible to hardware */
2393 wmb();
2394 skb_tx_timestamp(skb);
2395
2396 spin_lock_irq(&bp->lock);
2397 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2398 spin_unlock_irq(&bp->lock);
2399
2400 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2401 netif_stop_subqueue(dev, queue_index);
2402
2403unlock:
2404 spin_unlock_bh(&queue->tx_ptr_lock);
2405
2406 return ret;
2407}
2408
2409static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2410{
2411 if (!macb_is_gem(bp)) {
2412 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2413 } else {
2414 bp->rx_buffer_size = size;
2415
2416 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2417 netdev_dbg(bp->dev,
2418 "RX buffer must be multiple of %d bytes, expanding\n",
2419 RX_BUFFER_MULTIPLE);
2420 bp->rx_buffer_size =
2421 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2422 }
2423 }
2424
2425 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2426 bp->dev->mtu, bp->rx_buffer_size);
2427}
2428
2429static void gem_free_rx_buffers(struct macb *bp)
2430{
2431 struct sk_buff *skb;
2432 struct macb_dma_desc *desc;
2433 struct macb_queue *queue;
2434 dma_addr_t addr;
2435 unsigned int q;
2436 int i;
2437
2438 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2439 if (!queue->rx_skbuff)
2440 continue;
2441
2442 for (i = 0; i < bp->rx_ring_size; i++) {
2443 skb = queue->rx_skbuff[i];
2444
2445 if (!skb)
2446 continue;
2447
2448 desc = macb_rx_desc(queue, i);
2449 addr = macb_get_addr(bp, desc);
2450
2451 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2452 DMA_FROM_DEVICE);
2453 dev_kfree_skb_any(skb);
2454 skb = NULL;
2455 }
2456
2457 kfree(queue->rx_skbuff);
2458 queue->rx_skbuff = NULL;
2459 }
2460}
2461
2462static void macb_free_rx_buffers(struct macb *bp)
2463{
2464 struct macb_queue *queue = &bp->queues[0];
2465
2466 if (queue->rx_buffers) {
2467 dma_free_coherent(&bp->pdev->dev,
2468 bp->rx_ring_size * bp->rx_buffer_size,
2469 queue->rx_buffers, queue->rx_buffers_dma);
2470 queue->rx_buffers = NULL;
2471 }
2472}
2473
2474static void macb_free_consistent(struct macb *bp)
2475{
2476 struct macb_queue *queue;
2477 unsigned int q;
2478 int size;
2479
2480 bp->macbgem_ops.mog_free_rx_buffers(bp);
2481
2482 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2483 kfree(queue->tx_skb);
2484 queue->tx_skb = NULL;
2485 if (queue->tx_ring) {
2486 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2487 dma_free_coherent(&bp->pdev->dev, size,
2488 queue->tx_ring, queue->tx_ring_dma);
2489 queue->tx_ring = NULL;
2490 }
2491 if (queue->rx_ring) {
2492 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2493 dma_free_coherent(&bp->pdev->dev, size,
2494 queue->rx_ring, queue->rx_ring_dma);
2495 queue->rx_ring = NULL;
2496 }
2497 }
2498}
2499
2500static int gem_alloc_rx_buffers(struct macb *bp)
2501{
2502 struct macb_queue *queue;
2503 unsigned int q;
2504 int size;
2505
2506 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2507 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2508 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2509 if (!queue->rx_skbuff)
2510 return -ENOMEM;
2511 else
2512 netdev_dbg(bp->dev,
2513 "Allocated %d RX struct sk_buff entries at %p\n",
2514 bp->rx_ring_size, queue->rx_skbuff);
2515 }
2516 return 0;
2517}
2518
2519static int macb_alloc_rx_buffers(struct macb *bp)
2520{
2521 struct macb_queue *queue = &bp->queues[0];
2522 int size;
2523
2524 size = bp->rx_ring_size * bp->rx_buffer_size;
2525 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2526 &queue->rx_buffers_dma, GFP_KERNEL);
2527 if (!queue->rx_buffers)
2528 return -ENOMEM;
2529
2530 netdev_dbg(bp->dev,
2531 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2532 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2533 return 0;
2534}
2535
2536static int macb_alloc_consistent(struct macb *bp)
2537{
2538 struct macb_queue *queue;
2539 unsigned int q;
2540 int size;
2541
2542 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2543 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2544 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2545 &queue->tx_ring_dma,
2546 GFP_KERNEL);
2547 if (!queue->tx_ring)
2548 goto out_err;
2549 netdev_dbg(bp->dev,
2550 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2551 q, size, (unsigned long)queue->tx_ring_dma,
2552 queue->tx_ring);
2553
2554 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2555 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2556 if (!queue->tx_skb)
2557 goto out_err;
2558
2559 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2560 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2561 &queue->rx_ring_dma, GFP_KERNEL);
2562 if (!queue->rx_ring)
2563 goto out_err;
2564 netdev_dbg(bp->dev,
2565 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2566 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2567 }
2568 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2569 goto out_err;
2570
2571 return 0;
2572
2573out_err:
2574 macb_free_consistent(bp);
2575 return -ENOMEM;
2576}
2577
2578static void gem_init_rings(struct macb *bp)
2579{
2580 struct macb_queue *queue;
2581 struct macb_dma_desc *desc = NULL;
2582 unsigned int q;
2583 int i;
2584
2585 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2586 for (i = 0; i < bp->tx_ring_size; i++) {
2587 desc = macb_tx_desc(queue, i);
2588 macb_set_addr(bp, desc, 0);
2589 desc->ctrl = MACB_BIT(TX_USED);
2590 }
2591 desc->ctrl |= MACB_BIT(TX_WRAP);
2592 queue->tx_head = 0;
2593 queue->tx_tail = 0;
2594
2595 queue->rx_tail = 0;
2596 queue->rx_prepared_head = 0;
2597
2598 gem_rx_refill(queue);
2599 }
2600
2601}
2602
2603static void macb_init_rings(struct macb *bp)
2604{
2605 int i;
2606 struct macb_dma_desc *desc = NULL;
2607
2608 macb_init_rx_ring(&bp->queues[0]);
2609
2610 for (i = 0; i < bp->tx_ring_size; i++) {
2611 desc = macb_tx_desc(&bp->queues[0], i);
2612 macb_set_addr(bp, desc, 0);
2613 desc->ctrl = MACB_BIT(TX_USED);
2614 }
2615 bp->queues[0].tx_head = 0;
2616 bp->queues[0].tx_tail = 0;
2617 desc->ctrl |= MACB_BIT(TX_WRAP);
2618}
2619
2620static void macb_reset_hw(struct macb *bp)
2621{
2622 struct macb_queue *queue;
2623 unsigned int q;
2624 u32 ctrl = macb_readl(bp, NCR);
2625
2626 /* Disable RX and TX (XXX: Should we halt the transmission
2627 * more gracefully?)
2628 */
2629 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2630
2631 /* Clear the stats registers (XXX: Update stats first?) */
2632 ctrl |= MACB_BIT(CLRSTAT);
2633
2634 macb_writel(bp, NCR, ctrl);
2635
2636 /* Clear all status flags */
2637 macb_writel(bp, TSR, -1);
2638 macb_writel(bp, RSR, -1);
2639
2640 /* Disable RX partial store and forward and reset watermark value */
2641 gem_writel(bp, PBUFRXCUT, 0);
2642
2643 /* Disable all interrupts */
2644 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2645 queue_writel(queue, IDR, -1);
2646 queue_readl(queue, ISR);
2647 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2648 queue_writel(queue, ISR, -1);
2649 }
2650}
2651
2652static u32 gem_mdc_clk_div(struct macb *bp)
2653{
2654 u32 config;
2655 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2656
2657 if (pclk_hz <= 20000000)
2658 config = GEM_BF(CLK, GEM_CLK_DIV8);
2659 else if (pclk_hz <= 40000000)
2660 config = GEM_BF(CLK, GEM_CLK_DIV16);
2661 else if (pclk_hz <= 80000000)
2662 config = GEM_BF(CLK, GEM_CLK_DIV32);
2663 else if (pclk_hz <= 120000000)
2664 config = GEM_BF(CLK, GEM_CLK_DIV48);
2665 else if (pclk_hz <= 160000000)
2666 config = GEM_BF(CLK, GEM_CLK_DIV64);
2667 else if (pclk_hz <= 240000000)
2668 config = GEM_BF(CLK, GEM_CLK_DIV96);
2669 else if (pclk_hz <= 320000000)
2670 config = GEM_BF(CLK, GEM_CLK_DIV128);
2671 else
2672 config = GEM_BF(CLK, GEM_CLK_DIV224);
2673
2674 return config;
2675}
2676
2677static u32 macb_mdc_clk_div(struct macb *bp)
2678{
2679 u32 config;
2680 unsigned long pclk_hz;
2681
2682 if (macb_is_gem(bp))
2683 return gem_mdc_clk_div(bp);
2684
2685 pclk_hz = clk_get_rate(bp->pclk);
2686 if (pclk_hz <= 20000000)
2687 config = MACB_BF(CLK, MACB_CLK_DIV8);
2688 else if (pclk_hz <= 40000000)
2689 config = MACB_BF(CLK, MACB_CLK_DIV16);
2690 else if (pclk_hz <= 80000000)
2691 config = MACB_BF(CLK, MACB_CLK_DIV32);
2692 else
2693 config = MACB_BF(CLK, MACB_CLK_DIV64);
2694
2695 return config;
2696}
2697
2698/* Get the DMA bus width field of the network configuration register that we
2699 * should program. We find the width from decoding the design configuration
2700 * register to find the maximum supported data bus width.
2701 */
2702static u32 macb_dbw(struct macb *bp)
2703{
2704 if (!macb_is_gem(bp))
2705 return 0;
2706
2707 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2708 case 4:
2709 return GEM_BF(DBW, GEM_DBW128);
2710 case 2:
2711 return GEM_BF(DBW, GEM_DBW64);
2712 case 1:
2713 default:
2714 return GEM_BF(DBW, GEM_DBW32);
2715 }
2716}
2717
2718/* Configure the receive DMA engine
2719 * - use the correct receive buffer size
2720 * - set best burst length for DMA operations
2721 * (if not supported by FIFO, it will fallback to default)
2722 * - set both rx/tx packet buffers to full memory size
2723 * These are configurable parameters for GEM.
2724 */
2725static void macb_configure_dma(struct macb *bp)
2726{
2727 struct macb_queue *queue;
2728 u32 buffer_size;
2729 unsigned int q;
2730 u32 dmacfg;
2731
2732 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2733 if (macb_is_gem(bp)) {
2734 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2735 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2736 if (q)
2737 queue_writel(queue, RBQS, buffer_size);
2738 else
2739 dmacfg |= GEM_BF(RXBS, buffer_size);
2740 }
2741 if (bp->dma_burst_length)
2742 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2743 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2744 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2745
2746 if (bp->native_io)
2747 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2748 else
2749 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2750
2751 if (bp->dev->features & NETIF_F_HW_CSUM)
2752 dmacfg |= GEM_BIT(TXCOEN);
2753 else
2754 dmacfg &= ~GEM_BIT(TXCOEN);
2755
2756 dmacfg &= ~GEM_BIT(ADDR64);
2757#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2758 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2759 dmacfg |= GEM_BIT(ADDR64);
2760#endif
2761#ifdef CONFIG_MACB_USE_HWSTAMP
2762 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2763 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2764#endif
2765 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2766 dmacfg);
2767 gem_writel(bp, DMACFG, dmacfg);
2768 }
2769}
2770
2771static void macb_init_hw(struct macb *bp)
2772{
2773 u32 config;
2774
2775 macb_reset_hw(bp);
2776 macb_set_hwaddr(bp);
2777
2778 config = macb_mdc_clk_div(bp);
2779 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2780 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2781 if (bp->caps & MACB_CAPS_JUMBO)
2782 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2783 else
2784 config |= MACB_BIT(BIG); /* Receive oversized frames */
2785 if (bp->dev->flags & IFF_PROMISC)
2786 config |= MACB_BIT(CAF); /* Copy All Frames */
2787 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2788 config |= GEM_BIT(RXCOEN);
2789 if (!(bp->dev->flags & IFF_BROADCAST))
2790 config |= MACB_BIT(NBC); /* No BroadCast */
2791 config |= macb_dbw(bp);
2792 macb_writel(bp, NCFGR, config);
2793 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2794 gem_writel(bp, JML, bp->jumbo_max_len);
2795 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2796 if (bp->caps & MACB_CAPS_JUMBO)
2797 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2798
2799 macb_configure_dma(bp);
2800
2801 /* Enable RX partial store and forward and set watermark */
2802 if (bp->rx_watermark)
2803 gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
2804}
2805
2806/* The hash address register is 64 bits long and takes up two
2807 * locations in the memory map. The least significant bits are stored
2808 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2809 *
2810 * The unicast hash enable and the multicast hash enable bits in the
2811 * network configuration register enable the reception of hash matched
2812 * frames. The destination address is reduced to a 6 bit index into
2813 * the 64 bit hash register using the following hash function. The
2814 * hash function is an exclusive or of every sixth bit of the
2815 * destination address.
2816 *
2817 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2818 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2819 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2820 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2821 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2822 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2823 *
2824 * da[0] represents the least significant bit of the first byte
2825 * received, that is, the multicast/unicast indicator, and da[47]
2826 * represents the most significant bit of the last byte received. If
2827 * the hash index, hi[n], points to a bit that is set in the hash
2828 * register then the frame will be matched according to whether the
2829 * frame is multicast or unicast. A multicast match will be signalled
2830 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2831 * index points to a bit set in the hash register. A unicast match
2832 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2833 * and the hash index points to a bit set in the hash register. To
2834 * receive all multicast frames, the hash register should be set with
2835 * all ones and the multicast hash enable bit should be set in the
2836 * network configuration register.
2837 */
2838
2839static inline int hash_bit_value(int bitnr, __u8 *addr)
2840{
2841 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2842 return 1;
2843 return 0;
2844}
2845
2846/* Return the hash index value for the specified address. */
2847static int hash_get_index(__u8 *addr)
2848{
2849 int i, j, bitval;
2850 int hash_index = 0;
2851
2852 for (j = 0; j < 6; j++) {
2853 for (i = 0, bitval = 0; i < 8; i++)
2854 bitval ^= hash_bit_value(i * 6 + j, addr);
2855
2856 hash_index |= (bitval << j);
2857 }
2858
2859 return hash_index;
2860}
2861
2862/* Add multicast addresses to the internal multicast-hash table. */
2863static void macb_sethashtable(struct net_device *dev)
2864{
2865 struct netdev_hw_addr *ha;
2866 unsigned long mc_filter[2];
2867 unsigned int bitnr;
2868 struct macb *bp = netdev_priv(dev);
2869
2870 mc_filter[0] = 0;
2871 mc_filter[1] = 0;
2872
2873 netdev_for_each_mc_addr(ha, dev) {
2874 bitnr = hash_get_index(ha->addr);
2875 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2876 }
2877
2878 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2879 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2880}
2881
2882/* Enable/Disable promiscuous and multicast modes. */
2883static void macb_set_rx_mode(struct net_device *dev)
2884{
2885 unsigned long cfg;
2886 struct macb *bp = netdev_priv(dev);
2887
2888 cfg = macb_readl(bp, NCFGR);
2889
2890 if (dev->flags & IFF_PROMISC) {
2891 /* Enable promiscuous mode */
2892 cfg |= MACB_BIT(CAF);
2893
2894 /* Disable RX checksum offload */
2895 if (macb_is_gem(bp))
2896 cfg &= ~GEM_BIT(RXCOEN);
2897 } else {
2898 /* Disable promiscuous mode */
2899 cfg &= ~MACB_BIT(CAF);
2900
2901 /* Enable RX checksum offload only if requested */
2902 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2903 cfg |= GEM_BIT(RXCOEN);
2904 }
2905
2906 if (dev->flags & IFF_ALLMULTI) {
2907 /* Enable all multicast mode */
2908 macb_or_gem_writel(bp, HRB, -1);
2909 macb_or_gem_writel(bp, HRT, -1);
2910 cfg |= MACB_BIT(NCFGR_MTI);
2911 } else if (!netdev_mc_empty(dev)) {
2912 /* Enable specific multicasts */
2913 macb_sethashtable(dev);
2914 cfg |= MACB_BIT(NCFGR_MTI);
2915 } else if (dev->flags & (~IFF_ALLMULTI)) {
2916 /* Disable all multicast mode */
2917 macb_or_gem_writel(bp, HRB, 0);
2918 macb_or_gem_writel(bp, HRT, 0);
2919 cfg &= ~MACB_BIT(NCFGR_MTI);
2920 }
2921
2922 macb_writel(bp, NCFGR, cfg);
2923}
2924
2925static int macb_open(struct net_device *dev)
2926{
2927 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2928 struct macb *bp = netdev_priv(dev);
2929 struct macb_queue *queue;
2930 unsigned int q;
2931 int err;
2932
2933 netdev_dbg(bp->dev, "open\n");
2934
2935 err = pm_runtime_resume_and_get(&bp->pdev->dev);
2936 if (err < 0)
2937 return err;
2938
2939 /* RX buffers initialization */
2940 macb_init_rx_buffer_size(bp, bufsz);
2941
2942 err = macb_alloc_consistent(bp);
2943 if (err) {
2944 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2945 err);
2946 goto pm_exit;
2947 }
2948
2949 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2950 napi_enable(&queue->napi_rx);
2951 napi_enable(&queue->napi_tx);
2952 }
2953
2954 macb_init_hw(bp);
2955
2956 err = phy_power_on(bp->sgmii_phy);
2957 if (err)
2958 goto reset_hw;
2959
2960 err = macb_phylink_connect(bp);
2961 if (err)
2962 goto phy_off;
2963
2964 netif_tx_start_all_queues(dev);
2965
2966 if (bp->ptp_info)
2967 bp->ptp_info->ptp_init(dev);
2968
2969 return 0;
2970
2971phy_off:
2972 phy_power_off(bp->sgmii_phy);
2973
2974reset_hw:
2975 macb_reset_hw(bp);
2976 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2977 napi_disable(&queue->napi_rx);
2978 napi_disable(&queue->napi_tx);
2979 }
2980 macb_free_consistent(bp);
2981pm_exit:
2982 pm_runtime_put_sync(&bp->pdev->dev);
2983 return err;
2984}
2985
2986static int macb_close(struct net_device *dev)
2987{
2988 struct macb *bp = netdev_priv(dev);
2989 struct macb_queue *queue;
2990 unsigned long flags;
2991 unsigned int q;
2992
2993 netif_tx_stop_all_queues(dev);
2994
2995 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2996 napi_disable(&queue->napi_rx);
2997 napi_disable(&queue->napi_tx);
2998 }
2999
3000 phylink_stop(bp->phylink);
3001 phylink_disconnect_phy(bp->phylink);
3002
3003 phy_power_off(bp->sgmii_phy);
3004
3005 spin_lock_irqsave(&bp->lock, flags);
3006 macb_reset_hw(bp);
3007 netif_carrier_off(dev);
3008 spin_unlock_irqrestore(&bp->lock, flags);
3009
3010 macb_free_consistent(bp);
3011
3012 if (bp->ptp_info)
3013 bp->ptp_info->ptp_remove(dev);
3014
3015 pm_runtime_put(&bp->pdev->dev);
3016
3017 return 0;
3018}
3019
3020static int macb_change_mtu(struct net_device *dev, int new_mtu)
3021{
3022 if (netif_running(dev))
3023 return -EBUSY;
3024
3025 dev->mtu = new_mtu;
3026
3027 return 0;
3028}
3029
3030static int macb_set_mac_addr(struct net_device *dev, void *addr)
3031{
3032 int err;
3033
3034 err = eth_mac_addr(dev, addr);
3035 if (err < 0)
3036 return err;
3037
3038 macb_set_hwaddr(netdev_priv(dev));
3039 return 0;
3040}
3041
3042static void gem_update_stats(struct macb *bp)
3043{
3044 struct macb_queue *queue;
3045 unsigned int i, q, idx;
3046 unsigned long *stat;
3047
3048 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
3049
3050 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
3051 u32 offset = gem_statistics[i].offset;
3052 u64 val = bp->macb_reg_readl(bp, offset);
3053
3054 bp->ethtool_stats[i] += val;
3055 *p += val;
3056
3057 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
3058 /* Add GEM_OCTTXH, GEM_OCTRXH */
3059 val = bp->macb_reg_readl(bp, offset + 4);
3060 bp->ethtool_stats[i] += ((u64)val) << 32;
3061 *(++p) += val;
3062 }
3063 }
3064
3065 idx = GEM_STATS_LEN;
3066 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
3067 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
3068 bp->ethtool_stats[idx++] = *stat;
3069}
3070
3071static struct net_device_stats *gem_get_stats(struct macb *bp)
3072{
3073 struct gem_stats *hwstat = &bp->hw_stats.gem;
3074 struct net_device_stats *nstat = &bp->dev->stats;
3075
3076 if (!netif_running(bp->dev))
3077 return nstat;
3078
3079 gem_update_stats(bp);
3080
3081 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
3082 hwstat->rx_alignment_errors +
3083 hwstat->rx_resource_errors +
3084 hwstat->rx_overruns +
3085 hwstat->rx_oversize_frames +
3086 hwstat->rx_jabbers +
3087 hwstat->rx_undersized_frames +
3088 hwstat->rx_length_field_frame_errors);
3089 nstat->tx_errors = (hwstat->tx_late_collisions +
3090 hwstat->tx_excessive_collisions +
3091 hwstat->tx_underrun +
3092 hwstat->tx_carrier_sense_errors);
3093 nstat->multicast = hwstat->rx_multicast_frames;
3094 nstat->collisions = (hwstat->tx_single_collision_frames +
3095 hwstat->tx_multiple_collision_frames +
3096 hwstat->tx_excessive_collisions);
3097 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
3098 hwstat->rx_jabbers +
3099 hwstat->rx_undersized_frames +
3100 hwstat->rx_length_field_frame_errors);
3101 nstat->rx_over_errors = hwstat->rx_resource_errors;
3102 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
3103 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
3104 nstat->rx_fifo_errors = hwstat->rx_overruns;
3105 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
3106 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
3107 nstat->tx_fifo_errors = hwstat->tx_underrun;
3108
3109 return nstat;
3110}
3111
3112static void gem_get_ethtool_stats(struct net_device *dev,
3113 struct ethtool_stats *stats, u64 *data)
3114{
3115 struct macb *bp;
3116
3117 bp = netdev_priv(dev);
3118 gem_update_stats(bp);
3119 memcpy(data, &bp->ethtool_stats, sizeof(u64)
3120 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
3121}
3122
3123static int gem_get_sset_count(struct net_device *dev, int sset)
3124{
3125 struct macb *bp = netdev_priv(dev);
3126
3127 switch (sset) {
3128 case ETH_SS_STATS:
3129 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
3130 default:
3131 return -EOPNOTSUPP;
3132 }
3133}
3134
3135static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
3136{
3137 char stat_string[ETH_GSTRING_LEN];
3138 struct macb *bp = netdev_priv(dev);
3139 struct macb_queue *queue;
3140 unsigned int i;
3141 unsigned int q;
3142
3143 switch (sset) {
3144 case ETH_SS_STATS:
3145 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
3146 memcpy(p, gem_statistics[i].stat_string,
3147 ETH_GSTRING_LEN);
3148
3149 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3150 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
3151 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
3152 q, queue_statistics[i].stat_string);
3153 memcpy(p, stat_string, ETH_GSTRING_LEN);
3154 }
3155 }
3156 break;
3157 }
3158}
3159
3160static struct net_device_stats *macb_get_stats(struct net_device *dev)
3161{
3162 struct macb *bp = netdev_priv(dev);
3163 struct net_device_stats *nstat = &bp->dev->stats;
3164 struct macb_stats *hwstat = &bp->hw_stats.macb;
3165
3166 if (macb_is_gem(bp))
3167 return gem_get_stats(bp);
3168
3169 /* read stats from hardware */
3170 macb_update_stats(bp);
3171
3172 /* Convert HW stats into netdevice stats */
3173 nstat->rx_errors = (hwstat->rx_fcs_errors +
3174 hwstat->rx_align_errors +
3175 hwstat->rx_resource_errors +
3176 hwstat->rx_overruns +
3177 hwstat->rx_oversize_pkts +
3178 hwstat->rx_jabbers +
3179 hwstat->rx_undersize_pkts +
3180 hwstat->rx_length_mismatch);
3181 nstat->tx_errors = (hwstat->tx_late_cols +
3182 hwstat->tx_excessive_cols +
3183 hwstat->tx_underruns +
3184 hwstat->tx_carrier_errors +
3185 hwstat->sqe_test_errors);
3186 nstat->collisions = (hwstat->tx_single_cols +
3187 hwstat->tx_multiple_cols +
3188 hwstat->tx_excessive_cols);
3189 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
3190 hwstat->rx_jabbers +
3191 hwstat->rx_undersize_pkts +
3192 hwstat->rx_length_mismatch);
3193 nstat->rx_over_errors = hwstat->rx_resource_errors +
3194 hwstat->rx_overruns;
3195 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
3196 nstat->rx_frame_errors = hwstat->rx_align_errors;
3197 nstat->rx_fifo_errors = hwstat->rx_overruns;
3198 /* XXX: What does "missed" mean? */
3199 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3200 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3201 nstat->tx_fifo_errors = hwstat->tx_underruns;
3202 /* Don't know about heartbeat or window errors... */
3203
3204 return nstat;
3205}
3206
3207static int macb_get_regs_len(struct net_device *netdev)
3208{
3209 return MACB_GREGS_NBR * sizeof(u32);
3210}
3211
3212static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3213 void *p)
3214{
3215 struct macb *bp = netdev_priv(dev);
3216 unsigned int tail, head;
3217 u32 *regs_buff = p;
3218
3219 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3220 | MACB_GREGS_VERSION;
3221
3222 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3223 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3224
3225 regs_buff[0] = macb_readl(bp, NCR);
3226 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3227 regs_buff[2] = macb_readl(bp, NSR);
3228 regs_buff[3] = macb_readl(bp, TSR);
3229 regs_buff[4] = macb_readl(bp, RBQP);
3230 regs_buff[5] = macb_readl(bp, TBQP);
3231 regs_buff[6] = macb_readl(bp, RSR);
3232 regs_buff[7] = macb_readl(bp, IMR);
3233
3234 regs_buff[8] = tail;
3235 regs_buff[9] = head;
3236 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3237 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3238
3239 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3240 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3241 if (macb_is_gem(bp))
3242 regs_buff[13] = gem_readl(bp, DMACFG);
3243}
3244
3245static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3246{
3247 struct macb *bp = netdev_priv(netdev);
3248
3249 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
3250 phylink_ethtool_get_wol(bp->phylink, wol);
3251 wol->supported |= WAKE_MAGIC;
3252
3253 if (bp->wol & MACB_WOL_ENABLED)
3254 wol->wolopts |= WAKE_MAGIC;
3255 }
3256}
3257
3258static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3259{
3260 struct macb *bp = netdev_priv(netdev);
3261 int ret;
3262
3263 /* Pass the order to phylink layer */
3264 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3265 /* Don't manage WoL on MAC if handled by the PHY
3266 * or if there's a failure in talking to the PHY
3267 */
3268 if (!ret || ret != -EOPNOTSUPP)
3269 return ret;
3270
3271 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3272 (wol->wolopts & ~WAKE_MAGIC))
3273 return -EOPNOTSUPP;
3274
3275 if (wol->wolopts & WAKE_MAGIC)
3276 bp->wol |= MACB_WOL_ENABLED;
3277 else
3278 bp->wol &= ~MACB_WOL_ENABLED;
3279
3280 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3281
3282 return 0;
3283}
3284
3285static int macb_get_link_ksettings(struct net_device *netdev,
3286 struct ethtool_link_ksettings *kset)
3287{
3288 struct macb *bp = netdev_priv(netdev);
3289
3290 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3291}
3292
3293static int macb_set_link_ksettings(struct net_device *netdev,
3294 const struct ethtool_link_ksettings *kset)
3295{
3296 struct macb *bp = netdev_priv(netdev);
3297
3298 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3299}
3300
3301static void macb_get_ringparam(struct net_device *netdev,
3302 struct ethtool_ringparam *ring,
3303 struct kernel_ethtool_ringparam *kernel_ring,
3304 struct netlink_ext_ack *extack)
3305{
3306 struct macb *bp = netdev_priv(netdev);
3307
3308 ring->rx_max_pending = MAX_RX_RING_SIZE;
3309 ring->tx_max_pending = MAX_TX_RING_SIZE;
3310
3311 ring->rx_pending = bp->rx_ring_size;
3312 ring->tx_pending = bp->tx_ring_size;
3313}
3314
3315static int macb_set_ringparam(struct net_device *netdev,
3316 struct ethtool_ringparam *ring,
3317 struct kernel_ethtool_ringparam *kernel_ring,
3318 struct netlink_ext_ack *extack)
3319{
3320 struct macb *bp = netdev_priv(netdev);
3321 u32 new_rx_size, new_tx_size;
3322 unsigned int reset = 0;
3323
3324 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3325 return -EINVAL;
3326
3327 new_rx_size = clamp_t(u32, ring->rx_pending,
3328 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3329 new_rx_size = roundup_pow_of_two(new_rx_size);
3330
3331 new_tx_size = clamp_t(u32, ring->tx_pending,
3332 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3333 new_tx_size = roundup_pow_of_two(new_tx_size);
3334
3335 if ((new_tx_size == bp->tx_ring_size) &&
3336 (new_rx_size == bp->rx_ring_size)) {
3337 /* nothing to do */
3338 return 0;
3339 }
3340
3341 if (netif_running(bp->dev)) {
3342 reset = 1;
3343 macb_close(bp->dev);
3344 }
3345
3346 bp->rx_ring_size = new_rx_size;
3347 bp->tx_ring_size = new_tx_size;
3348
3349 if (reset)
3350 macb_open(bp->dev);
3351
3352 return 0;
3353}
3354
3355#ifdef CONFIG_MACB_USE_HWSTAMP
3356static unsigned int gem_get_tsu_rate(struct macb *bp)
3357{
3358 struct clk *tsu_clk;
3359 unsigned int tsu_rate;
3360
3361 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3362 if (!IS_ERR(tsu_clk))
3363 tsu_rate = clk_get_rate(tsu_clk);
3364 /* try pclk instead */
3365 else if (!IS_ERR(bp->pclk)) {
3366 tsu_clk = bp->pclk;
3367 tsu_rate = clk_get_rate(tsu_clk);
3368 } else
3369 return -ENOTSUPP;
3370 return tsu_rate;
3371}
3372
3373static s32 gem_get_ptp_max_adj(void)
3374{
3375 return 64000000;
3376}
3377
3378static int gem_get_ts_info(struct net_device *dev,
3379 struct ethtool_ts_info *info)
3380{
3381 struct macb *bp = netdev_priv(dev);
3382
3383 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3384 ethtool_op_get_ts_info(dev, info);
3385 return 0;
3386 }
3387
3388 info->so_timestamping =
3389 SOF_TIMESTAMPING_TX_SOFTWARE |
3390 SOF_TIMESTAMPING_RX_SOFTWARE |
3391 SOF_TIMESTAMPING_SOFTWARE |
3392 SOF_TIMESTAMPING_TX_HARDWARE |
3393 SOF_TIMESTAMPING_RX_HARDWARE |
3394 SOF_TIMESTAMPING_RAW_HARDWARE;
3395 info->tx_types =
3396 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3397 (1 << HWTSTAMP_TX_OFF) |
3398 (1 << HWTSTAMP_TX_ON);
3399 info->rx_filters =
3400 (1 << HWTSTAMP_FILTER_NONE) |
3401 (1 << HWTSTAMP_FILTER_ALL);
3402
3403 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3404
3405 return 0;
3406}
3407
3408static struct macb_ptp_info gem_ptp_info = {
3409 .ptp_init = gem_ptp_init,
3410 .ptp_remove = gem_ptp_remove,
3411 .get_ptp_max_adj = gem_get_ptp_max_adj,
3412 .get_tsu_rate = gem_get_tsu_rate,
3413 .get_ts_info = gem_get_ts_info,
3414 .get_hwtst = gem_get_hwtst,
3415 .set_hwtst = gem_set_hwtst,
3416};
3417#endif
3418
3419static int macb_get_ts_info(struct net_device *netdev,
3420 struct ethtool_ts_info *info)
3421{
3422 struct macb *bp = netdev_priv(netdev);
3423
3424 if (bp->ptp_info)
3425 return bp->ptp_info->get_ts_info(netdev, info);
3426
3427 return ethtool_op_get_ts_info(netdev, info);
3428}
3429
3430static void gem_enable_flow_filters(struct macb *bp, bool enable)
3431{
3432 struct net_device *netdev = bp->dev;
3433 struct ethtool_rx_fs_item *item;
3434 u32 t2_scr;
3435 int num_t2_scr;
3436
3437 if (!(netdev->features & NETIF_F_NTUPLE))
3438 return;
3439
3440 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3441
3442 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3443 struct ethtool_rx_flow_spec *fs = &item->fs;
3444 struct ethtool_tcpip4_spec *tp4sp_m;
3445
3446 if (fs->location >= num_t2_scr)
3447 continue;
3448
3449 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3450
3451 /* enable/disable screener regs for the flow entry */
3452 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3453
3454 /* only enable fields with no masking */
3455 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3456
3457 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3458 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3459 else
3460 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3461
3462 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3463 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3464 else
3465 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3466
3467 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3468 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3469 else
3470 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3471
3472 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3473 }
3474}
3475
3476static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3477{
3478 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3479 uint16_t index = fs->location;
3480 u32 w0, w1, t2_scr;
3481 bool cmp_a = false;
3482 bool cmp_b = false;
3483 bool cmp_c = false;
3484
3485 if (!macb_is_gem(bp))
3486 return;
3487
3488 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3489 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3490
3491 /* ignore field if any masking set */
3492 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3493 /* 1st compare reg - IP source address */
3494 w0 = 0;
3495 w1 = 0;
3496 w0 = tp4sp_v->ip4src;
3497 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3498 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3499 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3500 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3501 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3502 cmp_a = true;
3503 }
3504
3505 /* ignore field if any masking set */
3506 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3507 /* 2nd compare reg - IP destination address */
3508 w0 = 0;
3509 w1 = 0;
3510 w0 = tp4sp_v->ip4dst;
3511 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3512 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3513 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3514 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3515 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3516 cmp_b = true;
3517 }
3518
3519 /* ignore both port fields if masking set in both */
3520 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3521 /* 3rd compare reg - source port, destination port */
3522 w0 = 0;
3523 w1 = 0;
3524 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3525 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3526 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3527 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3528 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3529 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3530 } else {
3531 /* only one port definition */
3532 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3533 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3534 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3535 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3536 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3537 } else { /* dst port */
3538 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3539 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3540 }
3541 }
3542 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3543 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3544 cmp_c = true;
3545 }
3546
3547 t2_scr = 0;
3548 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3549 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3550 if (cmp_a)
3551 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3552 if (cmp_b)
3553 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3554 if (cmp_c)
3555 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3556 gem_writel_n(bp, SCRT2, index, t2_scr);
3557}
3558
3559static int gem_add_flow_filter(struct net_device *netdev,
3560 struct ethtool_rxnfc *cmd)
3561{
3562 struct macb *bp = netdev_priv(netdev);
3563 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3564 struct ethtool_rx_fs_item *item, *newfs;
3565 unsigned long flags;
3566 int ret = -EINVAL;
3567 bool added = false;
3568
3569 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3570 if (newfs == NULL)
3571 return -ENOMEM;
3572 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3573
3574 netdev_dbg(netdev,
3575 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3576 fs->flow_type, (int)fs->ring_cookie, fs->location,
3577 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3578 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3579 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3580 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3581
3582 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3583
3584 /* find correct place to add in list */
3585 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3586 if (item->fs.location > newfs->fs.location) {
3587 list_add_tail(&newfs->list, &item->list);
3588 added = true;
3589 break;
3590 } else if (item->fs.location == fs->location) {
3591 netdev_err(netdev, "Rule not added: location %d not free!\n",
3592 fs->location);
3593 ret = -EBUSY;
3594 goto err;
3595 }
3596 }
3597 if (!added)
3598 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3599
3600 gem_prog_cmp_regs(bp, fs);
3601 bp->rx_fs_list.count++;
3602 /* enable filtering if NTUPLE on */
3603 gem_enable_flow_filters(bp, 1);
3604
3605 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3606 return 0;
3607
3608err:
3609 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3610 kfree(newfs);
3611 return ret;
3612}
3613
3614static int gem_del_flow_filter(struct net_device *netdev,
3615 struct ethtool_rxnfc *cmd)
3616{
3617 struct macb *bp = netdev_priv(netdev);
3618 struct ethtool_rx_fs_item *item;
3619 struct ethtool_rx_flow_spec *fs;
3620 unsigned long flags;
3621
3622 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3623
3624 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3625 if (item->fs.location == cmd->fs.location) {
3626 /* disable screener regs for the flow entry */
3627 fs = &(item->fs);
3628 netdev_dbg(netdev,
3629 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3630 fs->flow_type, (int)fs->ring_cookie, fs->location,
3631 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3632 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3633 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3634 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3635
3636 gem_writel_n(bp, SCRT2, fs->location, 0);
3637
3638 list_del(&item->list);
3639 bp->rx_fs_list.count--;
3640 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3641 kfree(item);
3642 return 0;
3643 }
3644 }
3645
3646 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3647 return -EINVAL;
3648}
3649
3650static int gem_get_flow_entry(struct net_device *netdev,
3651 struct ethtool_rxnfc *cmd)
3652{
3653 struct macb *bp = netdev_priv(netdev);
3654 struct ethtool_rx_fs_item *item;
3655
3656 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3657 if (item->fs.location == cmd->fs.location) {
3658 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3659 return 0;
3660 }
3661 }
3662 return -EINVAL;
3663}
3664
3665static int gem_get_all_flow_entries(struct net_device *netdev,
3666 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3667{
3668 struct macb *bp = netdev_priv(netdev);
3669 struct ethtool_rx_fs_item *item;
3670 uint32_t cnt = 0;
3671
3672 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3673 if (cnt == cmd->rule_cnt)
3674 return -EMSGSIZE;
3675 rule_locs[cnt] = item->fs.location;
3676 cnt++;
3677 }
3678 cmd->data = bp->max_tuples;
3679 cmd->rule_cnt = cnt;
3680
3681 return 0;
3682}
3683
3684static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3685 u32 *rule_locs)
3686{
3687 struct macb *bp = netdev_priv(netdev);
3688 int ret = 0;
3689
3690 switch (cmd->cmd) {
3691 case ETHTOOL_GRXRINGS:
3692 cmd->data = bp->num_queues;
3693 break;
3694 case ETHTOOL_GRXCLSRLCNT:
3695 cmd->rule_cnt = bp->rx_fs_list.count;
3696 break;
3697 case ETHTOOL_GRXCLSRULE:
3698 ret = gem_get_flow_entry(netdev, cmd);
3699 break;
3700 case ETHTOOL_GRXCLSRLALL:
3701 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3702 break;
3703 default:
3704 netdev_err(netdev,
3705 "Command parameter %d is not supported\n", cmd->cmd);
3706 ret = -EOPNOTSUPP;
3707 }
3708
3709 return ret;
3710}
3711
3712static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3713{
3714 struct macb *bp = netdev_priv(netdev);
3715 int ret;
3716
3717 switch (cmd->cmd) {
3718 case ETHTOOL_SRXCLSRLINS:
3719 if ((cmd->fs.location >= bp->max_tuples)
3720 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3721 ret = -EINVAL;
3722 break;
3723 }
3724 ret = gem_add_flow_filter(netdev, cmd);
3725 break;
3726 case ETHTOOL_SRXCLSRLDEL:
3727 ret = gem_del_flow_filter(netdev, cmd);
3728 break;
3729 default:
3730 netdev_err(netdev,
3731 "Command parameter %d is not supported\n", cmd->cmd);
3732 ret = -EOPNOTSUPP;
3733 }
3734
3735 return ret;
3736}
3737
3738static const struct ethtool_ops macb_ethtool_ops = {
3739 .get_regs_len = macb_get_regs_len,
3740 .get_regs = macb_get_regs,
3741 .get_link = ethtool_op_get_link,
3742 .get_ts_info = ethtool_op_get_ts_info,
3743 .get_wol = macb_get_wol,
3744 .set_wol = macb_set_wol,
3745 .get_link_ksettings = macb_get_link_ksettings,
3746 .set_link_ksettings = macb_set_link_ksettings,
3747 .get_ringparam = macb_get_ringparam,
3748 .set_ringparam = macb_set_ringparam,
3749};
3750
3751static const struct ethtool_ops gem_ethtool_ops = {
3752 .get_regs_len = macb_get_regs_len,
3753 .get_regs = macb_get_regs,
3754 .get_wol = macb_get_wol,
3755 .set_wol = macb_set_wol,
3756 .get_link = ethtool_op_get_link,
3757 .get_ts_info = macb_get_ts_info,
3758 .get_ethtool_stats = gem_get_ethtool_stats,
3759 .get_strings = gem_get_ethtool_strings,
3760 .get_sset_count = gem_get_sset_count,
3761 .get_link_ksettings = macb_get_link_ksettings,
3762 .set_link_ksettings = macb_set_link_ksettings,
3763 .get_ringparam = macb_get_ringparam,
3764 .set_ringparam = macb_set_ringparam,
3765 .get_rxnfc = gem_get_rxnfc,
3766 .set_rxnfc = gem_set_rxnfc,
3767};
3768
3769static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3770{
3771 struct macb *bp = netdev_priv(dev);
3772
3773 if (!netif_running(dev))
3774 return -EINVAL;
3775
3776 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3777}
3778
3779static int macb_hwtstamp_get(struct net_device *dev,
3780 struct kernel_hwtstamp_config *cfg)
3781{
3782 struct macb *bp = netdev_priv(dev);
3783
3784 if (!netif_running(dev))
3785 return -EINVAL;
3786
3787 if (!bp->ptp_info)
3788 return -EOPNOTSUPP;
3789
3790 return bp->ptp_info->get_hwtst(dev, cfg);
3791}
3792
3793static int macb_hwtstamp_set(struct net_device *dev,
3794 struct kernel_hwtstamp_config *cfg,
3795 struct netlink_ext_ack *extack)
3796{
3797 struct macb *bp = netdev_priv(dev);
3798
3799 if (!netif_running(dev))
3800 return -EINVAL;
3801
3802 if (!bp->ptp_info)
3803 return -EOPNOTSUPP;
3804
3805 return bp->ptp_info->set_hwtst(dev, cfg, extack);
3806}
3807
3808static inline void macb_set_txcsum_feature(struct macb *bp,
3809 netdev_features_t features)
3810{
3811 u32 val;
3812
3813 if (!macb_is_gem(bp))
3814 return;
3815
3816 val = gem_readl(bp, DMACFG);
3817 if (features & NETIF_F_HW_CSUM)
3818 val |= GEM_BIT(TXCOEN);
3819 else
3820 val &= ~GEM_BIT(TXCOEN);
3821
3822 gem_writel(bp, DMACFG, val);
3823}
3824
3825static inline void macb_set_rxcsum_feature(struct macb *bp,
3826 netdev_features_t features)
3827{
3828 struct net_device *netdev = bp->dev;
3829 u32 val;
3830
3831 if (!macb_is_gem(bp))
3832 return;
3833
3834 val = gem_readl(bp, NCFGR);
3835 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3836 val |= GEM_BIT(RXCOEN);
3837 else
3838 val &= ~GEM_BIT(RXCOEN);
3839
3840 gem_writel(bp, NCFGR, val);
3841}
3842
3843static inline void macb_set_rxflow_feature(struct macb *bp,
3844 netdev_features_t features)
3845{
3846 if (!macb_is_gem(bp))
3847 return;
3848
3849 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3850}
3851
3852static int macb_set_features(struct net_device *netdev,
3853 netdev_features_t features)
3854{
3855 struct macb *bp = netdev_priv(netdev);
3856 netdev_features_t changed = features ^ netdev->features;
3857
3858 /* TX checksum offload */
3859 if (changed & NETIF_F_HW_CSUM)
3860 macb_set_txcsum_feature(bp, features);
3861
3862 /* RX checksum offload */
3863 if (changed & NETIF_F_RXCSUM)
3864 macb_set_rxcsum_feature(bp, features);
3865
3866 /* RX Flow Filters */
3867 if (changed & NETIF_F_NTUPLE)
3868 macb_set_rxflow_feature(bp, features);
3869
3870 return 0;
3871}
3872
3873static void macb_restore_features(struct macb *bp)
3874{
3875 struct net_device *netdev = bp->dev;
3876 netdev_features_t features = netdev->features;
3877 struct ethtool_rx_fs_item *item;
3878
3879 /* TX checksum offload */
3880 macb_set_txcsum_feature(bp, features);
3881
3882 /* RX checksum offload */
3883 macb_set_rxcsum_feature(bp, features);
3884
3885 /* RX Flow Filters */
3886 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3887 gem_prog_cmp_regs(bp, &item->fs);
3888
3889 macb_set_rxflow_feature(bp, features);
3890}
3891
3892static const struct net_device_ops macb_netdev_ops = {
3893 .ndo_open = macb_open,
3894 .ndo_stop = macb_close,
3895 .ndo_start_xmit = macb_start_xmit,
3896 .ndo_set_rx_mode = macb_set_rx_mode,
3897 .ndo_get_stats = macb_get_stats,
3898 .ndo_eth_ioctl = macb_ioctl,
3899 .ndo_validate_addr = eth_validate_addr,
3900 .ndo_change_mtu = macb_change_mtu,
3901 .ndo_set_mac_address = macb_set_mac_addr,
3902#ifdef CONFIG_NET_POLL_CONTROLLER
3903 .ndo_poll_controller = macb_poll_controller,
3904#endif
3905 .ndo_set_features = macb_set_features,
3906 .ndo_features_check = macb_features_check,
3907 .ndo_hwtstamp_set = macb_hwtstamp_set,
3908 .ndo_hwtstamp_get = macb_hwtstamp_get,
3909};
3910
3911/* Configure peripheral capabilities according to device tree
3912 * and integration options used
3913 */
3914static void macb_configure_caps(struct macb *bp,
3915 const struct macb_config *dt_conf)
3916{
3917 u32 dcfg;
3918
3919 if (dt_conf)
3920 bp->caps = dt_conf->caps;
3921
3922 if (hw_is_gem(bp->regs, bp->native_io)) {
3923 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3924
3925 dcfg = gem_readl(bp, DCFG1);
3926 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3927 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3928 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3929 bp->caps |= MACB_CAPS_PCS;
3930 dcfg = gem_readl(bp, DCFG12);
3931 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3932 bp->caps |= MACB_CAPS_HIGH_SPEED;
3933 dcfg = gem_readl(bp, DCFG2);
3934 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3935 bp->caps |= MACB_CAPS_FIFO_MODE;
3936 if (gem_has_ptp(bp)) {
3937 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3938 dev_err(&bp->pdev->dev,
3939 "GEM doesn't support hardware ptp.\n");
3940 else {
3941#ifdef CONFIG_MACB_USE_HWSTAMP
3942 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3943 bp->ptp_info = &gem_ptp_info;
3944#endif
3945 }
3946 }
3947 }
3948
3949 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3950}
3951
3952static void macb_probe_queues(void __iomem *mem,
3953 bool native_io,
3954 unsigned int *queue_mask,
3955 unsigned int *num_queues)
3956{
3957 *queue_mask = 0x1;
3958 *num_queues = 1;
3959
3960 /* is it macb or gem ?
3961 *
3962 * We need to read directly from the hardware here because
3963 * we are early in the probe process and don't have the
3964 * MACB_CAPS_MACB_IS_GEM flag positioned
3965 */
3966 if (!hw_is_gem(mem, native_io))
3967 return;
3968
3969 /* bit 0 is never set but queue 0 always exists */
3970 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3971 *num_queues = hweight32(*queue_mask);
3972}
3973
3974static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3975 struct clk *rx_clk, struct clk *tsu_clk)
3976{
3977 struct clk_bulk_data clks[] = {
3978 { .clk = tsu_clk, },
3979 { .clk = rx_clk, },
3980 { .clk = pclk, },
3981 { .clk = hclk, },
3982 { .clk = tx_clk },
3983 };
3984
3985 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
3986}
3987
3988static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3989 struct clk **hclk, struct clk **tx_clk,
3990 struct clk **rx_clk, struct clk **tsu_clk)
3991{
3992 struct macb_platform_data *pdata;
3993 int err;
3994
3995 pdata = dev_get_platdata(&pdev->dev);
3996 if (pdata) {
3997 *pclk = pdata->pclk;
3998 *hclk = pdata->hclk;
3999 } else {
4000 *pclk = devm_clk_get(&pdev->dev, "pclk");
4001 *hclk = devm_clk_get(&pdev->dev, "hclk");
4002 }
4003
4004 if (IS_ERR_OR_NULL(*pclk))
4005 return dev_err_probe(&pdev->dev,
4006 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
4007 "failed to get pclk\n");
4008
4009 if (IS_ERR_OR_NULL(*hclk))
4010 return dev_err_probe(&pdev->dev,
4011 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
4012 "failed to get hclk\n");
4013
4014 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
4015 if (IS_ERR(*tx_clk))
4016 return PTR_ERR(*tx_clk);
4017
4018 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
4019 if (IS_ERR(*rx_clk))
4020 return PTR_ERR(*rx_clk);
4021
4022 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
4023 if (IS_ERR(*tsu_clk))
4024 return PTR_ERR(*tsu_clk);
4025
4026 err = clk_prepare_enable(*pclk);
4027 if (err) {
4028 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4029 return err;
4030 }
4031
4032 err = clk_prepare_enable(*hclk);
4033 if (err) {
4034 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
4035 goto err_disable_pclk;
4036 }
4037
4038 err = clk_prepare_enable(*tx_clk);
4039 if (err) {
4040 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
4041 goto err_disable_hclk;
4042 }
4043
4044 err = clk_prepare_enable(*rx_clk);
4045 if (err) {
4046 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
4047 goto err_disable_txclk;
4048 }
4049
4050 err = clk_prepare_enable(*tsu_clk);
4051 if (err) {
4052 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
4053 goto err_disable_rxclk;
4054 }
4055
4056 return 0;
4057
4058err_disable_rxclk:
4059 clk_disable_unprepare(*rx_clk);
4060
4061err_disable_txclk:
4062 clk_disable_unprepare(*tx_clk);
4063
4064err_disable_hclk:
4065 clk_disable_unprepare(*hclk);
4066
4067err_disable_pclk:
4068 clk_disable_unprepare(*pclk);
4069
4070 return err;
4071}
4072
4073static int macb_init(struct platform_device *pdev)
4074{
4075 struct net_device *dev = platform_get_drvdata(pdev);
4076 unsigned int hw_q, q;
4077 struct macb *bp = netdev_priv(dev);
4078 struct macb_queue *queue;
4079 int err;
4080 u32 val, reg;
4081
4082 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
4083 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
4084
4085 /* set the queue register mapping once for all: queue0 has a special
4086 * register mapping but we don't want to test the queue index then
4087 * compute the corresponding register offset at run time.
4088 */
4089 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
4090 if (!(bp->queue_mask & (1 << hw_q)))
4091 continue;
4092
4093 queue = &bp->queues[q];
4094 queue->bp = bp;
4095 spin_lock_init(&queue->tx_ptr_lock);
4096 netif_napi_add(dev, &queue->napi_rx, macb_rx_poll);
4097 netif_napi_add(dev, &queue->napi_tx, macb_tx_poll);
4098 if (hw_q) {
4099 queue->ISR = GEM_ISR(hw_q - 1);
4100 queue->IER = GEM_IER(hw_q - 1);
4101 queue->IDR = GEM_IDR(hw_q - 1);
4102 queue->IMR = GEM_IMR(hw_q - 1);
4103 queue->TBQP = GEM_TBQP(hw_q - 1);
4104 queue->RBQP = GEM_RBQP(hw_q - 1);
4105 queue->RBQS = GEM_RBQS(hw_q - 1);
4106#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4107 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4108 queue->TBQPH = GEM_TBQPH(hw_q - 1);
4109 queue->RBQPH = GEM_RBQPH(hw_q - 1);
4110 }
4111#endif
4112 } else {
4113 /* queue0 uses legacy registers */
4114 queue->ISR = MACB_ISR;
4115 queue->IER = MACB_IER;
4116 queue->IDR = MACB_IDR;
4117 queue->IMR = MACB_IMR;
4118 queue->TBQP = MACB_TBQP;
4119 queue->RBQP = MACB_RBQP;
4120#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4121 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4122 queue->TBQPH = MACB_TBQPH;
4123 queue->RBQPH = MACB_RBQPH;
4124 }
4125#endif
4126 }
4127
4128 /* get irq: here we use the linux queue index, not the hardware
4129 * queue index. the queue irq definitions in the device tree
4130 * must remove the optional gaps that could exist in the
4131 * hardware queue mask.
4132 */
4133 queue->irq = platform_get_irq(pdev, q);
4134 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
4135 IRQF_SHARED, dev->name, queue);
4136 if (err) {
4137 dev_err(&pdev->dev,
4138 "Unable to request IRQ %d (error %d)\n",
4139 queue->irq, err);
4140 return err;
4141 }
4142
4143 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
4144 q++;
4145 }
4146
4147 dev->netdev_ops = &macb_netdev_ops;
4148
4149 /* setup appropriated routines according to adapter type */
4150 if (macb_is_gem(bp)) {
4151 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
4152 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
4153 bp->macbgem_ops.mog_init_rings = gem_init_rings;
4154 bp->macbgem_ops.mog_rx = gem_rx;
4155 dev->ethtool_ops = &gem_ethtool_ops;
4156 } else {
4157 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
4158 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
4159 bp->macbgem_ops.mog_init_rings = macb_init_rings;
4160 bp->macbgem_ops.mog_rx = macb_rx;
4161 dev->ethtool_ops = &macb_ethtool_ops;
4162 }
4163
4164 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4165
4166 /* Set features */
4167 dev->hw_features = NETIF_F_SG;
4168
4169 /* Check LSO capability */
4170 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
4171 dev->hw_features |= MACB_NETIF_LSO;
4172
4173 /* Checksum offload is only available on gem with packet buffer */
4174 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
4175 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
4176 if (bp->caps & MACB_CAPS_SG_DISABLED)
4177 dev->hw_features &= ~NETIF_F_SG;
4178 dev->features = dev->hw_features;
4179
4180 /* Check RX Flow Filters support.
4181 * Max Rx flows set by availability of screeners & compare regs:
4182 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
4183 */
4184 reg = gem_readl(bp, DCFG8);
4185 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
4186 GEM_BFEXT(T2SCR, reg));
4187 INIT_LIST_HEAD(&bp->rx_fs_list.list);
4188 if (bp->max_tuples > 0) {
4189 /* also needs one ethtype match to check IPv4 */
4190 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
4191 /* program this reg now */
4192 reg = 0;
4193 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
4194 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
4195 /* Filtering is supported in hw but don't enable it in kernel now */
4196 dev->hw_features |= NETIF_F_NTUPLE;
4197 /* init Rx flow definitions */
4198 bp->rx_fs_list.count = 0;
4199 spin_lock_init(&bp->rx_fs_lock);
4200 } else
4201 bp->max_tuples = 0;
4202 }
4203
4204 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
4205 val = 0;
4206 if (phy_interface_mode_is_rgmii(bp->phy_interface))
4207 val = bp->usrio->rgmii;
4208 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
4209 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4210 val = bp->usrio->rmii;
4211 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4212 val = bp->usrio->mii;
4213
4214 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
4215 val |= bp->usrio->refclk;
4216
4217 macb_or_gem_writel(bp, USRIO, val);
4218 }
4219
4220 /* Set MII management clock divider */
4221 val = macb_mdc_clk_div(bp);
4222 val |= macb_dbw(bp);
4223 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4224 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4225 macb_writel(bp, NCFGR, val);
4226
4227 return 0;
4228}
4229
4230static const struct macb_usrio_config macb_default_usrio = {
4231 .mii = MACB_BIT(MII),
4232 .rmii = MACB_BIT(RMII),
4233 .rgmii = GEM_BIT(RGMII),
4234 .refclk = MACB_BIT(CLKEN),
4235};
4236
4237#if defined(CONFIG_OF)
4238/* 1518 rounded up */
4239#define AT91ETHER_MAX_RBUFF_SZ 0x600
4240/* max number of receive buffers */
4241#define AT91ETHER_MAX_RX_DESCR 9
4242
4243static struct sifive_fu540_macb_mgmt *mgmt;
4244
4245static int at91ether_alloc_coherent(struct macb *lp)
4246{
4247 struct macb_queue *q = &lp->queues[0];
4248
4249 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4250 (AT91ETHER_MAX_RX_DESCR *
4251 macb_dma_desc_get_size(lp)),
4252 &q->rx_ring_dma, GFP_KERNEL);
4253 if (!q->rx_ring)
4254 return -ENOMEM;
4255
4256 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4257 AT91ETHER_MAX_RX_DESCR *
4258 AT91ETHER_MAX_RBUFF_SZ,
4259 &q->rx_buffers_dma, GFP_KERNEL);
4260 if (!q->rx_buffers) {
4261 dma_free_coherent(&lp->pdev->dev,
4262 AT91ETHER_MAX_RX_DESCR *
4263 macb_dma_desc_get_size(lp),
4264 q->rx_ring, q->rx_ring_dma);
4265 q->rx_ring = NULL;
4266 return -ENOMEM;
4267 }
4268
4269 return 0;
4270}
4271
4272static void at91ether_free_coherent(struct macb *lp)
4273{
4274 struct macb_queue *q = &lp->queues[0];
4275
4276 if (q->rx_ring) {
4277 dma_free_coherent(&lp->pdev->dev,
4278 AT91ETHER_MAX_RX_DESCR *
4279 macb_dma_desc_get_size(lp),
4280 q->rx_ring, q->rx_ring_dma);
4281 q->rx_ring = NULL;
4282 }
4283
4284 if (q->rx_buffers) {
4285 dma_free_coherent(&lp->pdev->dev,
4286 AT91ETHER_MAX_RX_DESCR *
4287 AT91ETHER_MAX_RBUFF_SZ,
4288 q->rx_buffers, q->rx_buffers_dma);
4289 q->rx_buffers = NULL;
4290 }
4291}
4292
4293/* Initialize and start the Receiver and Transmit subsystems */
4294static int at91ether_start(struct macb *lp)
4295{
4296 struct macb_queue *q = &lp->queues[0];
4297 struct macb_dma_desc *desc;
4298 dma_addr_t addr;
4299 u32 ctl;
4300 int i, ret;
4301
4302 ret = at91ether_alloc_coherent(lp);
4303 if (ret)
4304 return ret;
4305
4306 addr = q->rx_buffers_dma;
4307 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4308 desc = macb_rx_desc(q, i);
4309 macb_set_addr(lp, desc, addr);
4310 desc->ctrl = 0;
4311 addr += AT91ETHER_MAX_RBUFF_SZ;
4312 }
4313
4314 /* Set the Wrap bit on the last descriptor */
4315 desc->addr |= MACB_BIT(RX_WRAP);
4316
4317 /* Reset buffer index */
4318 q->rx_tail = 0;
4319
4320 /* Program address of descriptor list in Rx Buffer Queue register */
4321 macb_writel(lp, RBQP, q->rx_ring_dma);
4322
4323 /* Enable Receive and Transmit */
4324 ctl = macb_readl(lp, NCR);
4325 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4326
4327 /* Enable MAC interrupts */
4328 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4329 MACB_BIT(RXUBR) |
4330 MACB_BIT(ISR_TUND) |
4331 MACB_BIT(ISR_RLE) |
4332 MACB_BIT(TCOMP) |
4333 MACB_BIT(ISR_ROVR) |
4334 MACB_BIT(HRESP));
4335
4336 return 0;
4337}
4338
4339static void at91ether_stop(struct macb *lp)
4340{
4341 u32 ctl;
4342
4343 /* Disable MAC interrupts */
4344 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4345 MACB_BIT(RXUBR) |
4346 MACB_BIT(ISR_TUND) |
4347 MACB_BIT(ISR_RLE) |
4348 MACB_BIT(TCOMP) |
4349 MACB_BIT(ISR_ROVR) |
4350 MACB_BIT(HRESP));
4351
4352 /* Disable Receiver and Transmitter */
4353 ctl = macb_readl(lp, NCR);
4354 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4355
4356 /* Free resources. */
4357 at91ether_free_coherent(lp);
4358}
4359
4360/* Open the ethernet interface */
4361static int at91ether_open(struct net_device *dev)
4362{
4363 struct macb *lp = netdev_priv(dev);
4364 u32 ctl;
4365 int ret;
4366
4367 ret = pm_runtime_resume_and_get(&lp->pdev->dev);
4368 if (ret < 0)
4369 return ret;
4370
4371 /* Clear internal statistics */
4372 ctl = macb_readl(lp, NCR);
4373 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4374
4375 macb_set_hwaddr(lp);
4376
4377 ret = at91ether_start(lp);
4378 if (ret)
4379 goto pm_exit;
4380
4381 ret = macb_phylink_connect(lp);
4382 if (ret)
4383 goto stop;
4384
4385 netif_start_queue(dev);
4386
4387 return 0;
4388
4389stop:
4390 at91ether_stop(lp);
4391pm_exit:
4392 pm_runtime_put_sync(&lp->pdev->dev);
4393 return ret;
4394}
4395
4396/* Close the interface */
4397static int at91ether_close(struct net_device *dev)
4398{
4399 struct macb *lp = netdev_priv(dev);
4400
4401 netif_stop_queue(dev);
4402
4403 phylink_stop(lp->phylink);
4404 phylink_disconnect_phy(lp->phylink);
4405
4406 at91ether_stop(lp);
4407
4408 return pm_runtime_put(&lp->pdev->dev);
4409}
4410
4411/* Transmit packet */
4412static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4413 struct net_device *dev)
4414{
4415 struct macb *lp = netdev_priv(dev);
4416
4417 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4418 int desc = 0;
4419
4420 netif_stop_queue(dev);
4421
4422 /* Store packet information (to free when Tx completed) */
4423 lp->rm9200_txq[desc].skb = skb;
4424 lp->rm9200_txq[desc].size = skb->len;
4425 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4426 skb->len, DMA_TO_DEVICE);
4427 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4428 dev_kfree_skb_any(skb);
4429 dev->stats.tx_dropped++;
4430 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4431 return NETDEV_TX_OK;
4432 }
4433
4434 /* Set address of the data in the Transmit Address register */
4435 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4436 /* Set length of the packet in the Transmit Control register */
4437 macb_writel(lp, TCR, skb->len);
4438
4439 } else {
4440 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4441 return NETDEV_TX_BUSY;
4442 }
4443
4444 return NETDEV_TX_OK;
4445}
4446
4447/* Extract received frame from buffer descriptors and sent to upper layers.
4448 * (Called from interrupt context)
4449 */
4450static void at91ether_rx(struct net_device *dev)
4451{
4452 struct macb *lp = netdev_priv(dev);
4453 struct macb_queue *q = &lp->queues[0];
4454 struct macb_dma_desc *desc;
4455 unsigned char *p_recv;
4456 struct sk_buff *skb;
4457 unsigned int pktlen;
4458
4459 desc = macb_rx_desc(q, q->rx_tail);
4460 while (desc->addr & MACB_BIT(RX_USED)) {
4461 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4462 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4463 skb = netdev_alloc_skb(dev, pktlen + 2);
4464 if (skb) {
4465 skb_reserve(skb, 2);
4466 skb_put_data(skb, p_recv, pktlen);
4467
4468 skb->protocol = eth_type_trans(skb, dev);
4469 dev->stats.rx_packets++;
4470 dev->stats.rx_bytes += pktlen;
4471 netif_rx(skb);
4472 } else {
4473 dev->stats.rx_dropped++;
4474 }
4475
4476 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4477 dev->stats.multicast++;
4478
4479 /* reset ownership bit */
4480 desc->addr &= ~MACB_BIT(RX_USED);
4481
4482 /* wrap after last buffer */
4483 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4484 q->rx_tail = 0;
4485 else
4486 q->rx_tail++;
4487
4488 desc = macb_rx_desc(q, q->rx_tail);
4489 }
4490}
4491
4492/* MAC interrupt handler */
4493static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4494{
4495 struct net_device *dev = dev_id;
4496 struct macb *lp = netdev_priv(dev);
4497 u32 intstatus, ctl;
4498 unsigned int desc;
4499
4500 /* MAC Interrupt Status register indicates what interrupts are pending.
4501 * It is automatically cleared once read.
4502 */
4503 intstatus = macb_readl(lp, ISR);
4504
4505 /* Receive complete */
4506 if (intstatus & MACB_BIT(RCOMP))
4507 at91ether_rx(dev);
4508
4509 /* Transmit complete */
4510 if (intstatus & MACB_BIT(TCOMP)) {
4511 /* The TCOM bit is set even if the transmission failed */
4512 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4513 dev->stats.tx_errors++;
4514
4515 desc = 0;
4516 if (lp->rm9200_txq[desc].skb) {
4517 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4518 lp->rm9200_txq[desc].skb = NULL;
4519 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4520 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4521 dev->stats.tx_packets++;
4522 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4523 }
4524 netif_wake_queue(dev);
4525 }
4526
4527 /* Work-around for EMAC Errata section 41.3.1 */
4528 if (intstatus & MACB_BIT(RXUBR)) {
4529 ctl = macb_readl(lp, NCR);
4530 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4531 wmb();
4532 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4533 }
4534
4535 if (intstatus & MACB_BIT(ISR_ROVR))
4536 netdev_err(dev, "ROVR error\n");
4537
4538 return IRQ_HANDLED;
4539}
4540
4541#ifdef CONFIG_NET_POLL_CONTROLLER
4542static void at91ether_poll_controller(struct net_device *dev)
4543{
4544 unsigned long flags;
4545
4546 local_irq_save(flags);
4547 at91ether_interrupt(dev->irq, dev);
4548 local_irq_restore(flags);
4549}
4550#endif
4551
4552static const struct net_device_ops at91ether_netdev_ops = {
4553 .ndo_open = at91ether_open,
4554 .ndo_stop = at91ether_close,
4555 .ndo_start_xmit = at91ether_start_xmit,
4556 .ndo_get_stats = macb_get_stats,
4557 .ndo_set_rx_mode = macb_set_rx_mode,
4558 .ndo_set_mac_address = eth_mac_addr,
4559 .ndo_eth_ioctl = macb_ioctl,
4560 .ndo_validate_addr = eth_validate_addr,
4561#ifdef CONFIG_NET_POLL_CONTROLLER
4562 .ndo_poll_controller = at91ether_poll_controller,
4563#endif
4564 .ndo_hwtstamp_set = macb_hwtstamp_set,
4565 .ndo_hwtstamp_get = macb_hwtstamp_get,
4566};
4567
4568static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4569 struct clk **hclk, struct clk **tx_clk,
4570 struct clk **rx_clk, struct clk **tsu_clk)
4571{
4572 int err;
4573
4574 *hclk = NULL;
4575 *tx_clk = NULL;
4576 *rx_clk = NULL;
4577 *tsu_clk = NULL;
4578
4579 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4580 if (IS_ERR(*pclk))
4581 return PTR_ERR(*pclk);
4582
4583 err = clk_prepare_enable(*pclk);
4584 if (err) {
4585 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4586 return err;
4587 }
4588
4589 return 0;
4590}
4591
4592static int at91ether_init(struct platform_device *pdev)
4593{
4594 struct net_device *dev = platform_get_drvdata(pdev);
4595 struct macb *bp = netdev_priv(dev);
4596 int err;
4597
4598 bp->queues[0].bp = bp;
4599
4600 dev->netdev_ops = &at91ether_netdev_ops;
4601 dev->ethtool_ops = &macb_ethtool_ops;
4602
4603 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4604 0, dev->name, dev);
4605 if (err)
4606 return err;
4607
4608 macb_writel(bp, NCR, 0);
4609
4610 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4611
4612 return 0;
4613}
4614
4615static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4616 unsigned long parent_rate)
4617{
4618 return mgmt->rate;
4619}
4620
4621static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4622 unsigned long *parent_rate)
4623{
4624 if (WARN_ON(rate < 2500000))
4625 return 2500000;
4626 else if (rate == 2500000)
4627 return 2500000;
4628 else if (WARN_ON(rate < 13750000))
4629 return 2500000;
4630 else if (WARN_ON(rate < 25000000))
4631 return 25000000;
4632 else if (rate == 25000000)
4633 return 25000000;
4634 else if (WARN_ON(rate < 75000000))
4635 return 25000000;
4636 else if (WARN_ON(rate < 125000000))
4637 return 125000000;
4638 else if (rate == 125000000)
4639 return 125000000;
4640
4641 WARN_ON(rate > 125000000);
4642
4643 return 125000000;
4644}
4645
4646static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4647 unsigned long parent_rate)
4648{
4649 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4650 if (rate != 125000000)
4651 iowrite32(1, mgmt->reg);
4652 else
4653 iowrite32(0, mgmt->reg);
4654 mgmt->rate = rate;
4655
4656 return 0;
4657}
4658
4659static const struct clk_ops fu540_c000_ops = {
4660 .recalc_rate = fu540_macb_tx_recalc_rate,
4661 .round_rate = fu540_macb_tx_round_rate,
4662 .set_rate = fu540_macb_tx_set_rate,
4663};
4664
4665static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4666 struct clk **hclk, struct clk **tx_clk,
4667 struct clk **rx_clk, struct clk **tsu_clk)
4668{
4669 struct clk_init_data init;
4670 int err = 0;
4671
4672 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4673 if (err)
4674 return err;
4675
4676 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4677 if (!mgmt) {
4678 err = -ENOMEM;
4679 goto err_disable_clks;
4680 }
4681
4682 init.name = "sifive-gemgxl-mgmt";
4683 init.ops = &fu540_c000_ops;
4684 init.flags = 0;
4685 init.num_parents = 0;
4686
4687 mgmt->rate = 0;
4688 mgmt->hw.init = &init;
4689
4690 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4691 if (IS_ERR(*tx_clk)) {
4692 err = PTR_ERR(*tx_clk);
4693 goto err_disable_clks;
4694 }
4695
4696 err = clk_prepare_enable(*tx_clk);
4697 if (err) {
4698 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4699 *tx_clk = NULL;
4700 goto err_disable_clks;
4701 } else {
4702 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4703 }
4704
4705 return 0;
4706
4707err_disable_clks:
4708 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4709
4710 return err;
4711}
4712
4713static int fu540_c000_init(struct platform_device *pdev)
4714{
4715 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4716 if (IS_ERR(mgmt->reg))
4717 return PTR_ERR(mgmt->reg);
4718
4719 return macb_init(pdev);
4720}
4721
4722static int init_reset_optional(struct platform_device *pdev)
4723{
4724 struct net_device *dev = platform_get_drvdata(pdev);
4725 struct macb *bp = netdev_priv(dev);
4726 int ret;
4727
4728 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4729 /* Ensure PHY device used in SGMII mode is ready */
4730 bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);
4731
4732 if (IS_ERR(bp->sgmii_phy))
4733 return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy),
4734 "failed to get SGMII PHY\n");
4735
4736 ret = phy_init(bp->sgmii_phy);
4737 if (ret)
4738 return dev_err_probe(&pdev->dev, ret,
4739 "failed to init SGMII PHY\n");
4740
4741 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG);
4742 if (!ret) {
4743 u32 pm_info[2];
4744
4745 ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
4746 pm_info, ARRAY_SIZE(pm_info));
4747 if (ret) {
4748 dev_err(&pdev->dev, "Failed to read power management information\n");
4749 goto err_out_phy_exit;
4750 }
4751 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0);
4752 if (ret)
4753 goto err_out_phy_exit;
4754
4755 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1);
4756 if (ret)
4757 goto err_out_phy_exit;
4758 }
4759
4760 }
4761
4762 /* Fully reset controller at hardware level if mapped in device tree */
4763 ret = device_reset_optional(&pdev->dev);
4764 if (ret) {
4765 phy_exit(bp->sgmii_phy);
4766 return dev_err_probe(&pdev->dev, ret, "failed to reset controller");
4767 }
4768
4769 ret = macb_init(pdev);
4770
4771err_out_phy_exit:
4772 if (ret)
4773 phy_exit(bp->sgmii_phy);
4774
4775 return ret;
4776}
4777
4778static const struct macb_usrio_config sama7g5_usrio = {
4779 .mii = 0,
4780 .rmii = 1,
4781 .rgmii = 2,
4782 .refclk = BIT(2),
4783 .hdfctlen = BIT(6),
4784};
4785
4786static const struct macb_config fu540_c000_config = {
4787 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4788 MACB_CAPS_GEM_HAS_PTP,
4789 .dma_burst_length = 16,
4790 .clk_init = fu540_c000_clk_init,
4791 .init = fu540_c000_init,
4792 .jumbo_max_len = 10240,
4793 .usrio = &macb_default_usrio,
4794};
4795
4796static const struct macb_config at91sam9260_config = {
4797 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4798 .clk_init = macb_clk_init,
4799 .init = macb_init,
4800 .usrio = &macb_default_usrio,
4801};
4802
4803static const struct macb_config sama5d3macb_config = {
4804 .caps = MACB_CAPS_SG_DISABLED |
4805 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4806 .clk_init = macb_clk_init,
4807 .init = macb_init,
4808 .usrio = &macb_default_usrio,
4809};
4810
4811static const struct macb_config pc302gem_config = {
4812 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4813 .dma_burst_length = 16,
4814 .clk_init = macb_clk_init,
4815 .init = macb_init,
4816 .usrio = &macb_default_usrio,
4817};
4818
4819static const struct macb_config sama5d2_config = {
4820 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4821 .dma_burst_length = 16,
4822 .clk_init = macb_clk_init,
4823 .init = macb_init,
4824 .usrio = &macb_default_usrio,
4825};
4826
4827static const struct macb_config sama5d29_config = {
4828 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
4829 .dma_burst_length = 16,
4830 .clk_init = macb_clk_init,
4831 .init = macb_init,
4832 .usrio = &macb_default_usrio,
4833};
4834
4835static const struct macb_config sama5d3_config = {
4836 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4837 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4838 .dma_burst_length = 16,
4839 .clk_init = macb_clk_init,
4840 .init = macb_init,
4841 .jumbo_max_len = 10240,
4842 .usrio = &macb_default_usrio,
4843};
4844
4845static const struct macb_config sama5d4_config = {
4846 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4847 .dma_burst_length = 4,
4848 .clk_init = macb_clk_init,
4849 .init = macb_init,
4850 .usrio = &macb_default_usrio,
4851};
4852
4853static const struct macb_config emac_config = {
4854 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4855 .clk_init = at91ether_clk_init,
4856 .init = at91ether_init,
4857 .usrio = &macb_default_usrio,
4858};
4859
4860static const struct macb_config np4_config = {
4861 .caps = MACB_CAPS_USRIO_DISABLED,
4862 .clk_init = macb_clk_init,
4863 .init = macb_init,
4864 .usrio = &macb_default_usrio,
4865};
4866
4867static const struct macb_config zynqmp_config = {
4868 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4869 MACB_CAPS_JUMBO |
4870 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4871 .dma_burst_length = 16,
4872 .clk_init = macb_clk_init,
4873 .init = init_reset_optional,
4874 .jumbo_max_len = 10240,
4875 .usrio = &macb_default_usrio,
4876};
4877
4878static const struct macb_config zynq_config = {
4879 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4880 MACB_CAPS_NEEDS_RSTONUBR,
4881 .dma_burst_length = 16,
4882 .clk_init = macb_clk_init,
4883 .init = macb_init,
4884 .usrio = &macb_default_usrio,
4885};
4886
4887static const struct macb_config mpfs_config = {
4888 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4889 MACB_CAPS_JUMBO |
4890 MACB_CAPS_GEM_HAS_PTP,
4891 .dma_burst_length = 16,
4892 .clk_init = macb_clk_init,
4893 .init = init_reset_optional,
4894 .usrio = &macb_default_usrio,
4895 .max_tx_length = 4040, /* Cadence Erratum 1686 */
4896 .jumbo_max_len = 4040,
4897};
4898
4899static const struct macb_config sama7g5_gem_config = {
4900 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
4901 MACB_CAPS_MIIONRGMII | MACB_CAPS_GEM_HAS_PTP,
4902 .dma_burst_length = 16,
4903 .clk_init = macb_clk_init,
4904 .init = macb_init,
4905 .usrio = &sama7g5_usrio,
4906};
4907
4908static const struct macb_config sama7g5_emac_config = {
4909 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
4910 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII |
4911 MACB_CAPS_GEM_HAS_PTP,
4912 .dma_burst_length = 16,
4913 .clk_init = macb_clk_init,
4914 .init = macb_init,
4915 .usrio = &sama7g5_usrio,
4916};
4917
4918static const struct macb_config versal_config = {
4919 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4920 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK,
4921 .dma_burst_length = 16,
4922 .clk_init = macb_clk_init,
4923 .init = init_reset_optional,
4924 .jumbo_max_len = 10240,
4925 .usrio = &macb_default_usrio,
4926};
4927
4928static const struct of_device_id macb_dt_ids[] = {
4929 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4930 { .compatible = "cdns,macb" },
4931 { .compatible = "cdns,np4-macb", .data = &np4_config },
4932 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4933 { .compatible = "cdns,gem", .data = &pc302gem_config },
4934 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4935 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4936 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4937 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4938 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4939 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4940 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4941 { .compatible = "cdns,emac", .data = &emac_config },
4942 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
4943 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
4944 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4945 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
4946 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4947 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4948 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
4949 { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
4950 { .compatible = "xlnx,versal-gem", .data = &versal_config},
4951 { /* sentinel */ }
4952};
4953MODULE_DEVICE_TABLE(of, macb_dt_ids);
4954#endif /* CONFIG_OF */
4955
4956static const struct macb_config default_gem_config = {
4957 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4958 MACB_CAPS_JUMBO |
4959 MACB_CAPS_GEM_HAS_PTP,
4960 .dma_burst_length = 16,
4961 .clk_init = macb_clk_init,
4962 .init = macb_init,
4963 .usrio = &macb_default_usrio,
4964 .jumbo_max_len = 10240,
4965};
4966
4967static int macb_probe(struct platform_device *pdev)
4968{
4969 const struct macb_config *macb_config = &default_gem_config;
4970 int (*clk_init)(struct platform_device *, struct clk **,
4971 struct clk **, struct clk **, struct clk **,
4972 struct clk **) = macb_config->clk_init;
4973 int (*init)(struct platform_device *) = macb_config->init;
4974 struct device_node *np = pdev->dev.of_node;
4975 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4976 struct clk *tsu_clk = NULL;
4977 unsigned int queue_mask, num_queues;
4978 bool native_io;
4979 phy_interface_t interface;
4980 struct net_device *dev;
4981 struct resource *regs;
4982 u32 wtrmrk_rst_val;
4983 void __iomem *mem;
4984 struct macb *bp;
4985 int err, val;
4986
4987 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
4988 if (IS_ERR(mem))
4989 return PTR_ERR(mem);
4990
4991 if (np) {
4992 const struct of_device_id *match;
4993
4994 match = of_match_node(macb_dt_ids, np);
4995 if (match && match->data) {
4996 macb_config = match->data;
4997 clk_init = macb_config->clk_init;
4998 init = macb_config->init;
4999 }
5000 }
5001
5002 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
5003 if (err)
5004 return err;
5005
5006 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
5007 pm_runtime_use_autosuspend(&pdev->dev);
5008 pm_runtime_get_noresume(&pdev->dev);
5009 pm_runtime_set_active(&pdev->dev);
5010 pm_runtime_enable(&pdev->dev);
5011 native_io = hw_is_native_io(mem);
5012
5013 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
5014 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
5015 if (!dev) {
5016 err = -ENOMEM;
5017 goto err_disable_clocks;
5018 }
5019
5020 dev->base_addr = regs->start;
5021
5022 SET_NETDEV_DEV(dev, &pdev->dev);
5023
5024 bp = netdev_priv(dev);
5025 bp->pdev = pdev;
5026 bp->dev = dev;
5027 bp->regs = mem;
5028 bp->native_io = native_io;
5029 if (native_io) {
5030 bp->macb_reg_readl = hw_readl_native;
5031 bp->macb_reg_writel = hw_writel_native;
5032 } else {
5033 bp->macb_reg_readl = hw_readl;
5034 bp->macb_reg_writel = hw_writel;
5035 }
5036 bp->num_queues = num_queues;
5037 bp->queue_mask = queue_mask;
5038 if (macb_config)
5039 bp->dma_burst_length = macb_config->dma_burst_length;
5040 bp->pclk = pclk;
5041 bp->hclk = hclk;
5042 bp->tx_clk = tx_clk;
5043 bp->rx_clk = rx_clk;
5044 bp->tsu_clk = tsu_clk;
5045 if (macb_config)
5046 bp->jumbo_max_len = macb_config->jumbo_max_len;
5047
5048 if (!hw_is_gem(bp->regs, bp->native_io))
5049 bp->max_tx_length = MACB_MAX_TX_LEN;
5050 else if (macb_config->max_tx_length)
5051 bp->max_tx_length = macb_config->max_tx_length;
5052 else
5053 bp->max_tx_length = GEM_MAX_TX_LEN;
5054
5055 bp->wol = 0;
5056 if (of_property_read_bool(np, "magic-packet"))
5057 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
5058 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
5059
5060 bp->usrio = macb_config->usrio;
5061
5062 /* By default we set to partial store and forward mode for zynqmp.
5063 * Disable if not set in devicetree.
5064 */
5065 if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
5066 err = of_property_read_u32(bp->pdev->dev.of_node,
5067 "cdns,rx-watermark",
5068 &bp->rx_watermark);
5069
5070 if (!err) {
5071 /* Disable partial store and forward in case of error or
5072 * invalid watermark value
5073 */
5074 wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
5075 if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
5076 dev_info(&bp->pdev->dev, "Invalid watermark value\n");
5077 bp->rx_watermark = 0;
5078 }
5079 }
5080 }
5081 spin_lock_init(&bp->lock);
5082
5083 /* setup capabilities */
5084 macb_configure_caps(bp, macb_config);
5085
5086#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5087 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
5088 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
5089 bp->hw_dma_cap |= HW_DMA_CAP_64B;
5090 }
5091#endif
5092 platform_set_drvdata(pdev, dev);
5093
5094 dev->irq = platform_get_irq(pdev, 0);
5095 if (dev->irq < 0) {
5096 err = dev->irq;
5097 goto err_out_free_netdev;
5098 }
5099
5100 /* MTU range: 68 - 1500 or 10240 */
5101 dev->min_mtu = GEM_MTU_MIN_SIZE;
5102 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
5103 dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN;
5104 else
5105 dev->max_mtu = ETH_DATA_LEN;
5106
5107 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
5108 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
5109 if (val)
5110 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
5111 macb_dma_desc_get_size(bp);
5112
5113 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
5114 if (val)
5115 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
5116 macb_dma_desc_get_size(bp);
5117 }
5118
5119 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
5120 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
5121 bp->rx_intr_mask |= MACB_BIT(RXUBR);
5122
5123 err = of_get_ethdev_address(np, bp->dev);
5124 if (err == -EPROBE_DEFER)
5125 goto err_out_free_netdev;
5126 else if (err)
5127 macb_get_hwaddr(bp);
5128
5129 err = of_get_phy_mode(np, &interface);
5130 if (err)
5131 /* not found in DT, MII by default */
5132 bp->phy_interface = PHY_INTERFACE_MODE_MII;
5133 else
5134 bp->phy_interface = interface;
5135
5136 /* IP specific init */
5137 err = init(pdev);
5138 if (err)
5139 goto err_out_free_netdev;
5140
5141 err = macb_mii_init(bp);
5142 if (err)
5143 goto err_out_phy_exit;
5144
5145 netif_carrier_off(dev);
5146
5147 err = register_netdev(dev);
5148 if (err) {
5149 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5150 goto err_out_unregister_mdio;
5151 }
5152
5153 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
5154
5155 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
5156 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
5157 dev->base_addr, dev->irq, dev->dev_addr);
5158
5159 pm_runtime_mark_last_busy(&bp->pdev->dev);
5160 pm_runtime_put_autosuspend(&bp->pdev->dev);
5161
5162 return 0;
5163
5164err_out_unregister_mdio:
5165 mdiobus_unregister(bp->mii_bus);
5166 mdiobus_free(bp->mii_bus);
5167
5168err_out_phy_exit:
5169 phy_exit(bp->sgmii_phy);
5170
5171err_out_free_netdev:
5172 free_netdev(dev);
5173
5174err_disable_clocks:
5175 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
5176 pm_runtime_disable(&pdev->dev);
5177 pm_runtime_set_suspended(&pdev->dev);
5178 pm_runtime_dont_use_autosuspend(&pdev->dev);
5179
5180 return err;
5181}
5182
5183static void macb_remove(struct platform_device *pdev)
5184{
5185 struct net_device *dev;
5186 struct macb *bp;
5187
5188 dev = platform_get_drvdata(pdev);
5189
5190 if (dev) {
5191 bp = netdev_priv(dev);
5192 phy_exit(bp->sgmii_phy);
5193 mdiobus_unregister(bp->mii_bus);
5194 mdiobus_free(bp->mii_bus);
5195
5196 unregister_netdev(dev);
5197 tasklet_kill(&bp->hresp_err_tasklet);
5198 pm_runtime_disable(&pdev->dev);
5199 pm_runtime_dont_use_autosuspend(&pdev->dev);
5200 if (!pm_runtime_suspended(&pdev->dev)) {
5201 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
5202 bp->rx_clk, bp->tsu_clk);
5203 pm_runtime_set_suspended(&pdev->dev);
5204 }
5205 phylink_destroy(bp->phylink);
5206 free_netdev(dev);
5207 }
5208}
5209
5210static int __maybe_unused macb_suspend(struct device *dev)
5211{
5212 struct net_device *netdev = dev_get_drvdata(dev);
5213 struct macb *bp = netdev_priv(netdev);
5214 struct macb_queue *queue;
5215 unsigned long flags;
5216 unsigned int q;
5217 int err;
5218
5219 if (!device_may_wakeup(&bp->dev->dev))
5220 phy_exit(bp->sgmii_phy);
5221
5222 if (!netif_running(netdev))
5223 return 0;
5224
5225 if (bp->wol & MACB_WOL_ENABLED) {
5226 spin_lock_irqsave(&bp->lock, flags);
5227 /* Flush all status bits */
5228 macb_writel(bp, TSR, -1);
5229 macb_writel(bp, RSR, -1);
5230 for (q = 0, queue = bp->queues; q < bp->num_queues;
5231 ++q, ++queue) {
5232 /* Disable all interrupts */
5233 queue_writel(queue, IDR, -1);
5234 queue_readl(queue, ISR);
5235 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5236 queue_writel(queue, ISR, -1);
5237 }
5238 /* Change interrupt handler and
5239 * Enable WoL IRQ on queue 0
5240 */
5241 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5242 if (macb_is_gem(bp)) {
5243 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
5244 IRQF_SHARED, netdev->name, bp->queues);
5245 if (err) {
5246 dev_err(dev,
5247 "Unable to request IRQ %d (error %d)\n",
5248 bp->queues[0].irq, err);
5249 spin_unlock_irqrestore(&bp->lock, flags);
5250 return err;
5251 }
5252 queue_writel(bp->queues, IER, GEM_BIT(WOL));
5253 gem_writel(bp, WOL, MACB_BIT(MAG));
5254 } else {
5255 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
5256 IRQF_SHARED, netdev->name, bp->queues);
5257 if (err) {
5258 dev_err(dev,
5259 "Unable to request IRQ %d (error %d)\n",
5260 bp->queues[0].irq, err);
5261 spin_unlock_irqrestore(&bp->lock, flags);
5262 return err;
5263 }
5264 queue_writel(bp->queues, IER, MACB_BIT(WOL));
5265 macb_writel(bp, WOL, MACB_BIT(MAG));
5266 }
5267 spin_unlock_irqrestore(&bp->lock, flags);
5268
5269 enable_irq_wake(bp->queues[0].irq);
5270 }
5271
5272 netif_device_detach(netdev);
5273 for (q = 0, queue = bp->queues; q < bp->num_queues;
5274 ++q, ++queue) {
5275 napi_disable(&queue->napi_rx);
5276 napi_disable(&queue->napi_tx);
5277 }
5278
5279 if (!(bp->wol & MACB_WOL_ENABLED)) {
5280 rtnl_lock();
5281 phylink_stop(bp->phylink);
5282 rtnl_unlock();
5283 spin_lock_irqsave(&bp->lock, flags);
5284 macb_reset_hw(bp);
5285 spin_unlock_irqrestore(&bp->lock, flags);
5286 }
5287
5288 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5289 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
5290
5291 if (netdev->hw_features & NETIF_F_NTUPLE)
5292 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5293
5294 if (bp->ptp_info)
5295 bp->ptp_info->ptp_remove(netdev);
5296 if (!device_may_wakeup(dev))
5297 pm_runtime_force_suspend(dev);
5298
5299 return 0;
5300}
5301
5302static int __maybe_unused macb_resume(struct device *dev)
5303{
5304 struct net_device *netdev = dev_get_drvdata(dev);
5305 struct macb *bp = netdev_priv(netdev);
5306 struct macb_queue *queue;
5307 unsigned long flags;
5308 unsigned int q;
5309 int err;
5310
5311 if (!device_may_wakeup(&bp->dev->dev))
5312 phy_init(bp->sgmii_phy);
5313
5314 if (!netif_running(netdev))
5315 return 0;
5316
5317 if (!device_may_wakeup(dev))
5318 pm_runtime_force_resume(dev);
5319
5320 if (bp->wol & MACB_WOL_ENABLED) {
5321 spin_lock_irqsave(&bp->lock, flags);
5322 /* Disable WoL */
5323 if (macb_is_gem(bp)) {
5324 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5325 gem_writel(bp, WOL, 0);
5326 } else {
5327 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5328 macb_writel(bp, WOL, 0);
5329 }
5330 /* Clear ISR on queue 0 */
5331 queue_readl(bp->queues, ISR);
5332 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5333 queue_writel(bp->queues, ISR, -1);
5334 /* Replace interrupt handler on queue 0 */
5335 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5336 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
5337 IRQF_SHARED, netdev->name, bp->queues);
5338 if (err) {
5339 dev_err(dev,
5340 "Unable to request IRQ %d (error %d)\n",
5341 bp->queues[0].irq, err);
5342 spin_unlock_irqrestore(&bp->lock, flags);
5343 return err;
5344 }
5345 spin_unlock_irqrestore(&bp->lock, flags);
5346
5347 disable_irq_wake(bp->queues[0].irq);
5348
5349 /* Now make sure we disable phy before moving
5350 * to common restore path
5351 */
5352 rtnl_lock();
5353 phylink_stop(bp->phylink);
5354 rtnl_unlock();
5355 }
5356
5357 for (q = 0, queue = bp->queues; q < bp->num_queues;
5358 ++q, ++queue) {
5359 napi_enable(&queue->napi_rx);
5360 napi_enable(&queue->napi_tx);
5361 }
5362
5363 if (netdev->hw_features & NETIF_F_NTUPLE)
5364 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5365
5366 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5367 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5368
5369 macb_writel(bp, NCR, MACB_BIT(MPE));
5370 macb_init_hw(bp);
5371 macb_set_rx_mode(netdev);
5372 macb_restore_features(bp);
5373 rtnl_lock();
5374
5375 phylink_start(bp->phylink);
5376 rtnl_unlock();
5377
5378 netif_device_attach(netdev);
5379 if (bp->ptp_info)
5380 bp->ptp_info->ptp_init(netdev);
5381
5382 return 0;
5383}
5384
5385static int __maybe_unused macb_runtime_suspend(struct device *dev)
5386{
5387 struct net_device *netdev = dev_get_drvdata(dev);
5388 struct macb *bp = netdev_priv(netdev);
5389
5390 if (!(device_may_wakeup(dev)))
5391 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5392 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK))
5393 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5394
5395 return 0;
5396}
5397
5398static int __maybe_unused macb_runtime_resume(struct device *dev)
5399{
5400 struct net_device *netdev = dev_get_drvdata(dev);
5401 struct macb *bp = netdev_priv(netdev);
5402
5403 if (!(device_may_wakeup(dev))) {
5404 clk_prepare_enable(bp->pclk);
5405 clk_prepare_enable(bp->hclk);
5406 clk_prepare_enable(bp->tx_clk);
5407 clk_prepare_enable(bp->rx_clk);
5408 clk_prepare_enable(bp->tsu_clk);
5409 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) {
5410 clk_prepare_enable(bp->tsu_clk);
5411 }
5412
5413 return 0;
5414}
5415
5416static const struct dev_pm_ops macb_pm_ops = {
5417 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5418 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5419};
5420
5421static struct platform_driver macb_driver = {
5422 .probe = macb_probe,
5423 .remove_new = macb_remove,
5424 .driver = {
5425 .name = "macb",
5426 .of_match_table = of_match_ptr(macb_dt_ids),
5427 .pm = &macb_pm_ops,
5428 },
5429};
5430
5431module_platform_driver(macb_driver);
5432
5433MODULE_LICENSE("GPL");
5434MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5435MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5436MODULE_ALIAS("platform:macb");
1/*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/circ_buf.h>
18#include <linux/slab.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/gpio/consumer.h>
23#include <linux/interrupt.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_data/macb.h>
28#include <linux/platform_device.h>
29#include <linux/phy.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/of_gpio.h>
33#include <linux/of_mdio.h>
34#include <linux/of_net.h>
35#include <linux/ip.h>
36#include <linux/udp.h>
37#include <linux/tcp.h>
38#include "macb.h"
39
40#define MACB_RX_BUFFER_SIZE 128
41#define RX_BUFFER_MULTIPLE 64 /* bytes */
42
43#define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
44#define MIN_RX_RING_SIZE 64
45#define MAX_RX_RING_SIZE 8192
46#define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
47 * (bp)->rx_ring_size)
48
49#define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
50#define MIN_TX_RING_SIZE 64
51#define MAX_TX_RING_SIZE 4096
52#define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
53 * (bp)->tx_ring_size)
54
55/* level of occupied TX descriptors under which we wake up TX process */
56#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
57
58#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
59 | MACB_BIT(ISR_ROVR))
60#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
61 | MACB_BIT(ISR_RLE) \
62 | MACB_BIT(TXERR))
63#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
64
65/* Max length of transmit frame must be a multiple of 8 bytes */
66#define MACB_TX_LEN_ALIGN 8
67#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
68#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
69
70#define GEM_MTU_MIN_SIZE ETH_MIN_MTU
71#define MACB_NETIF_LSO NETIF_F_TSO
72
73#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
74#define MACB_WOL_ENABLED (0x1 << 1)
75
76/* Graceful stop timeouts in us. We should allow up to
77 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
78 */
79#define MACB_HALT_TIMEOUT 1230
80
81/* DMA buffer descriptor might be different size
82 * depends on hardware configuration:
83 *
84 * 1. dma address width 32 bits:
85 * word 1: 32 bit address of Data Buffer
86 * word 2: control
87 *
88 * 2. dma address width 64 bits:
89 * word 1: 32 bit address of Data Buffer
90 * word 2: control
91 * word 3: upper 32 bit address of Data Buffer
92 * word 4: unused
93 *
94 * 3. dma address width 32 bits with hardware timestamping:
95 * word 1: 32 bit address of Data Buffer
96 * word 2: control
97 * word 3: timestamp word 1
98 * word 4: timestamp word 2
99 *
100 * 4. dma address width 64 bits with hardware timestamping:
101 * word 1: 32 bit address of Data Buffer
102 * word 2: control
103 * word 3: upper 32 bit address of Data Buffer
104 * word 4: unused
105 * word 5: timestamp word 1
106 * word 6: timestamp word 2
107 */
108static unsigned int macb_dma_desc_get_size(struct macb *bp)
109{
110#ifdef MACB_EXT_DESC
111 unsigned int desc_size;
112
113 switch (bp->hw_dma_cap) {
114 case HW_DMA_CAP_64B:
115 desc_size = sizeof(struct macb_dma_desc)
116 + sizeof(struct macb_dma_desc_64);
117 break;
118 case HW_DMA_CAP_PTP:
119 desc_size = sizeof(struct macb_dma_desc)
120 + sizeof(struct macb_dma_desc_ptp);
121 break;
122 case HW_DMA_CAP_64B_PTP:
123 desc_size = sizeof(struct macb_dma_desc)
124 + sizeof(struct macb_dma_desc_64)
125 + sizeof(struct macb_dma_desc_ptp);
126 break;
127 default:
128 desc_size = sizeof(struct macb_dma_desc);
129 }
130 return desc_size;
131#endif
132 return sizeof(struct macb_dma_desc);
133}
134
135static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
136{
137#ifdef MACB_EXT_DESC
138 switch (bp->hw_dma_cap) {
139 case HW_DMA_CAP_64B:
140 case HW_DMA_CAP_PTP:
141 desc_idx <<= 1;
142 break;
143 case HW_DMA_CAP_64B_PTP:
144 desc_idx *= 3;
145 break;
146 default:
147 break;
148 }
149#endif
150 return desc_idx;
151}
152
153#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
154static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
155{
156 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
157 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
158 return NULL;
159}
160#endif
161
162/* Ring buffer accessors */
163static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
164{
165 return index & (bp->tx_ring_size - 1);
166}
167
168static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
169 unsigned int index)
170{
171 index = macb_tx_ring_wrap(queue->bp, index);
172 index = macb_adj_dma_desc_idx(queue->bp, index);
173 return &queue->tx_ring[index];
174}
175
176static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
177 unsigned int index)
178{
179 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
180}
181
182static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
183{
184 dma_addr_t offset;
185
186 offset = macb_tx_ring_wrap(queue->bp, index) *
187 macb_dma_desc_get_size(queue->bp);
188
189 return queue->tx_ring_dma + offset;
190}
191
192static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
193{
194 return index & (bp->rx_ring_size - 1);
195}
196
197static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
198{
199 index = macb_rx_ring_wrap(queue->bp, index);
200 index = macb_adj_dma_desc_idx(queue->bp, index);
201 return &queue->rx_ring[index];
202}
203
204static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
205{
206 return queue->rx_buffers + queue->bp->rx_buffer_size *
207 macb_rx_ring_wrap(queue->bp, index);
208}
209
210/* I/O accessors */
211static u32 hw_readl_native(struct macb *bp, int offset)
212{
213 return __raw_readl(bp->regs + offset);
214}
215
216static void hw_writel_native(struct macb *bp, int offset, u32 value)
217{
218 __raw_writel(value, bp->regs + offset);
219}
220
221static u32 hw_readl(struct macb *bp, int offset)
222{
223 return readl_relaxed(bp->regs + offset);
224}
225
226static void hw_writel(struct macb *bp, int offset, u32 value)
227{
228 writel_relaxed(value, bp->regs + offset);
229}
230
231/* Find the CPU endianness by using the loopback bit of NCR register. When the
232 * CPU is in big endian we need to program swapped mode for management
233 * descriptor access.
234 */
235static bool hw_is_native_io(void __iomem *addr)
236{
237 u32 value = MACB_BIT(LLB);
238
239 __raw_writel(value, addr + MACB_NCR);
240 value = __raw_readl(addr + MACB_NCR);
241
242 /* Write 0 back to disable everything */
243 __raw_writel(0, addr + MACB_NCR);
244
245 return value == MACB_BIT(LLB);
246}
247
248static bool hw_is_gem(void __iomem *addr, bool native_io)
249{
250 u32 id;
251
252 if (native_io)
253 id = __raw_readl(addr + MACB_MID);
254 else
255 id = readl_relaxed(addr + MACB_MID);
256
257 return MACB_BFEXT(IDNUM, id) >= 0x2;
258}
259
260static void macb_set_hwaddr(struct macb *bp)
261{
262 u32 bottom;
263 u16 top;
264
265 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
266 macb_or_gem_writel(bp, SA1B, bottom);
267 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
268 macb_or_gem_writel(bp, SA1T, top);
269
270 /* Clear unused address register sets */
271 macb_or_gem_writel(bp, SA2B, 0);
272 macb_or_gem_writel(bp, SA2T, 0);
273 macb_or_gem_writel(bp, SA3B, 0);
274 macb_or_gem_writel(bp, SA3T, 0);
275 macb_or_gem_writel(bp, SA4B, 0);
276 macb_or_gem_writel(bp, SA4T, 0);
277}
278
279static void macb_get_hwaddr(struct macb *bp)
280{
281 struct macb_platform_data *pdata;
282 u32 bottom;
283 u16 top;
284 u8 addr[6];
285 int i;
286
287 pdata = dev_get_platdata(&bp->pdev->dev);
288
289 /* Check all 4 address register for valid address */
290 for (i = 0; i < 4; i++) {
291 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
292 top = macb_or_gem_readl(bp, SA1T + i * 8);
293
294 if (pdata && pdata->rev_eth_addr) {
295 addr[5] = bottom & 0xff;
296 addr[4] = (bottom >> 8) & 0xff;
297 addr[3] = (bottom >> 16) & 0xff;
298 addr[2] = (bottom >> 24) & 0xff;
299 addr[1] = top & 0xff;
300 addr[0] = (top & 0xff00) >> 8;
301 } else {
302 addr[0] = bottom & 0xff;
303 addr[1] = (bottom >> 8) & 0xff;
304 addr[2] = (bottom >> 16) & 0xff;
305 addr[3] = (bottom >> 24) & 0xff;
306 addr[4] = top & 0xff;
307 addr[5] = (top >> 8) & 0xff;
308 }
309
310 if (is_valid_ether_addr(addr)) {
311 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
312 return;
313 }
314 }
315
316 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
317 eth_hw_addr_random(bp->dev);
318}
319
320static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
321{
322 struct macb *bp = bus->priv;
323 int value;
324
325 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
326 | MACB_BF(RW, MACB_MAN_READ)
327 | MACB_BF(PHYA, mii_id)
328 | MACB_BF(REGA, regnum)
329 | MACB_BF(CODE, MACB_MAN_CODE)));
330
331 /* wait for end of transfer */
332 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
333 cpu_relax();
334
335 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
336
337 return value;
338}
339
340static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
341 u16 value)
342{
343 struct macb *bp = bus->priv;
344
345 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
346 | MACB_BF(RW, MACB_MAN_WRITE)
347 | MACB_BF(PHYA, mii_id)
348 | MACB_BF(REGA, regnum)
349 | MACB_BF(CODE, MACB_MAN_CODE)
350 | MACB_BF(DATA, value)));
351
352 /* wait for end of transfer */
353 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
354 cpu_relax();
355
356 return 0;
357}
358
359/**
360 * macb_set_tx_clk() - Set a clock to a new frequency
361 * @clk Pointer to the clock to change
362 * @rate New frequency in Hz
363 * @dev Pointer to the struct net_device
364 */
365static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
366{
367 long ferr, rate, rate_rounded;
368
369 if (!clk)
370 return;
371
372 switch (speed) {
373 case SPEED_10:
374 rate = 2500000;
375 break;
376 case SPEED_100:
377 rate = 25000000;
378 break;
379 case SPEED_1000:
380 rate = 125000000;
381 break;
382 default:
383 return;
384 }
385
386 rate_rounded = clk_round_rate(clk, rate);
387 if (rate_rounded < 0)
388 return;
389
390 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
391 * is not satisfied.
392 */
393 ferr = abs(rate_rounded - rate);
394 ferr = DIV_ROUND_UP(ferr, rate / 100000);
395 if (ferr > 5)
396 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
397 rate);
398
399 if (clk_set_rate(clk, rate_rounded))
400 netdev_err(dev, "adjusting tx_clk failed.\n");
401}
402
403static void macb_handle_link_change(struct net_device *dev)
404{
405 struct macb *bp = netdev_priv(dev);
406 struct phy_device *phydev = dev->phydev;
407 unsigned long flags;
408 int status_change = 0;
409
410 spin_lock_irqsave(&bp->lock, flags);
411
412 if (phydev->link) {
413 if ((bp->speed != phydev->speed) ||
414 (bp->duplex != phydev->duplex)) {
415 u32 reg;
416
417 reg = macb_readl(bp, NCFGR);
418 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
419 if (macb_is_gem(bp))
420 reg &= ~GEM_BIT(GBE);
421
422 if (phydev->duplex)
423 reg |= MACB_BIT(FD);
424 if (phydev->speed == SPEED_100)
425 reg |= MACB_BIT(SPD);
426 if (phydev->speed == SPEED_1000 &&
427 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
428 reg |= GEM_BIT(GBE);
429
430 macb_or_gem_writel(bp, NCFGR, reg);
431
432 bp->speed = phydev->speed;
433 bp->duplex = phydev->duplex;
434 status_change = 1;
435 }
436 }
437
438 if (phydev->link != bp->link) {
439 if (!phydev->link) {
440 bp->speed = 0;
441 bp->duplex = -1;
442 }
443 bp->link = phydev->link;
444
445 status_change = 1;
446 }
447
448 spin_unlock_irqrestore(&bp->lock, flags);
449
450 if (status_change) {
451 if (phydev->link) {
452 /* Update the TX clock rate if and only if the link is
453 * up and there has been a link change.
454 */
455 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
456
457 netif_carrier_on(dev);
458 netdev_info(dev, "link up (%d/%s)\n",
459 phydev->speed,
460 phydev->duplex == DUPLEX_FULL ?
461 "Full" : "Half");
462 } else {
463 netif_carrier_off(dev);
464 netdev_info(dev, "link down\n");
465 }
466 }
467}
468
469/* based on au1000_eth. c*/
470static int macb_mii_probe(struct net_device *dev)
471{
472 struct macb *bp = netdev_priv(dev);
473 struct macb_platform_data *pdata;
474 struct phy_device *phydev;
475 struct device_node *np;
476 int phy_irq, ret, i;
477
478 pdata = dev_get_platdata(&bp->pdev->dev);
479 np = bp->pdev->dev.of_node;
480 ret = 0;
481
482 if (np) {
483 if (of_phy_is_fixed_link(np)) {
484 if (of_phy_register_fixed_link(np) < 0) {
485 dev_err(&bp->pdev->dev,
486 "broken fixed-link specification\n");
487 return -ENODEV;
488 }
489 bp->phy_node = of_node_get(np);
490 } else {
491 bp->phy_node = of_parse_phandle(np, "phy-handle", 0);
492 /* fallback to standard phy registration if no
493 * phy-handle was found nor any phy found during
494 * dt phy registration
495 */
496 if (!bp->phy_node && !phy_find_first(bp->mii_bus)) {
497 for (i = 0; i < PHY_MAX_ADDR; i++) {
498 struct phy_device *phydev;
499
500 phydev = mdiobus_scan(bp->mii_bus, i);
501 if (IS_ERR(phydev) &&
502 PTR_ERR(phydev) != -ENODEV) {
503 ret = PTR_ERR(phydev);
504 break;
505 }
506 }
507
508 if (ret)
509 return -ENODEV;
510 }
511 }
512 }
513
514 if (bp->phy_node) {
515 phydev = of_phy_connect(dev, bp->phy_node,
516 &macb_handle_link_change, 0,
517 bp->phy_interface);
518 if (!phydev)
519 return -ENODEV;
520 } else {
521 phydev = phy_find_first(bp->mii_bus);
522 if (!phydev) {
523 netdev_err(dev, "no PHY found\n");
524 return -ENXIO;
525 }
526
527 if (pdata) {
528 if (gpio_is_valid(pdata->phy_irq_pin)) {
529 ret = devm_gpio_request(&bp->pdev->dev,
530 pdata->phy_irq_pin, "phy int");
531 if (!ret) {
532 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
533 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
534 }
535 } else {
536 phydev->irq = PHY_POLL;
537 }
538 }
539
540 /* attach the mac to the phy */
541 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
542 bp->phy_interface);
543 if (ret) {
544 netdev_err(dev, "Could not attach to PHY\n");
545 return ret;
546 }
547 }
548
549 /* mask with MAC supported features */
550 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
551 phydev->supported &= PHY_GBIT_FEATURES;
552 else
553 phydev->supported &= PHY_BASIC_FEATURES;
554
555 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
556 phydev->supported &= ~SUPPORTED_1000baseT_Half;
557
558 phydev->advertising = phydev->supported;
559
560 bp->link = 0;
561 bp->speed = 0;
562 bp->duplex = -1;
563
564 return 0;
565}
566
567static int macb_mii_init(struct macb *bp)
568{
569 struct macb_platform_data *pdata;
570 struct device_node *np;
571 int err;
572
573 /* Enable management port */
574 macb_writel(bp, NCR, MACB_BIT(MPE));
575
576 bp->mii_bus = mdiobus_alloc();
577 if (!bp->mii_bus) {
578 err = -ENOMEM;
579 goto err_out;
580 }
581
582 bp->mii_bus->name = "MACB_mii_bus";
583 bp->mii_bus->read = &macb_mdio_read;
584 bp->mii_bus->write = &macb_mdio_write;
585 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
586 bp->pdev->name, bp->pdev->id);
587 bp->mii_bus->priv = bp;
588 bp->mii_bus->parent = &bp->pdev->dev;
589 pdata = dev_get_platdata(&bp->pdev->dev);
590
591 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
592
593 np = bp->pdev->dev.of_node;
594
595 if (np) {
596 err = of_mdiobus_register(bp->mii_bus, np);
597 } else {
598 if (pdata)
599 bp->mii_bus->phy_mask = pdata->phy_mask;
600
601 err = mdiobus_register(bp->mii_bus);
602 }
603
604 if (err)
605 goto err_out_free_mdiobus;
606
607 err = macb_mii_probe(bp->dev);
608 if (err)
609 goto err_out_unregister_bus;
610
611 return 0;
612
613err_out_unregister_bus:
614 mdiobus_unregister(bp->mii_bus);
615 if (np && of_phy_is_fixed_link(np))
616 of_phy_deregister_fixed_link(np);
617err_out_free_mdiobus:
618 of_node_put(bp->phy_node);
619 mdiobus_free(bp->mii_bus);
620err_out:
621 return err;
622}
623
624static void macb_update_stats(struct macb *bp)
625{
626 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
627 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
628 int offset = MACB_PFR;
629
630 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
631
632 for (; p < end; p++, offset += 4)
633 *p += bp->macb_reg_readl(bp, offset);
634}
635
636static int macb_halt_tx(struct macb *bp)
637{
638 unsigned long halt_time, timeout;
639 u32 status;
640
641 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
642
643 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
644 do {
645 halt_time = jiffies;
646 status = macb_readl(bp, TSR);
647 if (!(status & MACB_BIT(TGO)))
648 return 0;
649
650 usleep_range(10, 250);
651 } while (time_before(halt_time, timeout));
652
653 return -ETIMEDOUT;
654}
655
656static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
657{
658 if (tx_skb->mapping) {
659 if (tx_skb->mapped_as_page)
660 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
661 tx_skb->size, DMA_TO_DEVICE);
662 else
663 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
664 tx_skb->size, DMA_TO_DEVICE);
665 tx_skb->mapping = 0;
666 }
667
668 if (tx_skb->skb) {
669 dev_kfree_skb_any(tx_skb->skb);
670 tx_skb->skb = NULL;
671 }
672}
673
674static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
675{
676#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
677 struct macb_dma_desc_64 *desc_64;
678
679 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
680 desc_64 = macb_64b_desc(bp, desc);
681 desc_64->addrh = upper_32_bits(addr);
682 }
683#endif
684 desc->addr = lower_32_bits(addr);
685}
686
687static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
688{
689 dma_addr_t addr = 0;
690#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
691 struct macb_dma_desc_64 *desc_64;
692
693 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
694 desc_64 = macb_64b_desc(bp, desc);
695 addr = ((u64)(desc_64->addrh) << 32);
696 }
697#endif
698 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
699 return addr;
700}
701
702static void macb_tx_error_task(struct work_struct *work)
703{
704 struct macb_queue *queue = container_of(work, struct macb_queue,
705 tx_error_task);
706 struct macb *bp = queue->bp;
707 struct macb_tx_skb *tx_skb;
708 struct macb_dma_desc *desc;
709 struct sk_buff *skb;
710 unsigned int tail;
711 unsigned long flags;
712
713 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
714 (unsigned int)(queue - bp->queues),
715 queue->tx_tail, queue->tx_head);
716
717 /* Prevent the queue IRQ handlers from running: each of them may call
718 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
719 * As explained below, we have to halt the transmission before updating
720 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
721 * network engine about the macb/gem being halted.
722 */
723 spin_lock_irqsave(&bp->lock, flags);
724
725 /* Make sure nobody is trying to queue up new packets */
726 netif_tx_stop_all_queues(bp->dev);
727
728 /* Stop transmission now
729 * (in case we have just queued new packets)
730 * macb/gem must be halted to write TBQP register
731 */
732 if (macb_halt_tx(bp))
733 /* Just complain for now, reinitializing TX path can be good */
734 netdev_err(bp->dev, "BUG: halt tx timed out\n");
735
736 /* Treat frames in TX queue including the ones that caused the error.
737 * Free transmit buffers in upper layer.
738 */
739 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
740 u32 ctrl;
741
742 desc = macb_tx_desc(queue, tail);
743 ctrl = desc->ctrl;
744 tx_skb = macb_tx_skb(queue, tail);
745 skb = tx_skb->skb;
746
747 if (ctrl & MACB_BIT(TX_USED)) {
748 /* skb is set for the last buffer of the frame */
749 while (!skb) {
750 macb_tx_unmap(bp, tx_skb);
751 tail++;
752 tx_skb = macb_tx_skb(queue, tail);
753 skb = tx_skb->skb;
754 }
755
756 /* ctrl still refers to the first buffer descriptor
757 * since it's the only one written back by the hardware
758 */
759 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
760 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
761 macb_tx_ring_wrap(bp, tail),
762 skb->data);
763 bp->dev->stats.tx_packets++;
764 queue->stats.tx_packets++;
765 bp->dev->stats.tx_bytes += skb->len;
766 queue->stats.tx_bytes += skb->len;
767 }
768 } else {
769 /* "Buffers exhausted mid-frame" errors may only happen
770 * if the driver is buggy, so complain loudly about
771 * those. Statistics are updated by hardware.
772 */
773 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
774 netdev_err(bp->dev,
775 "BUG: TX buffers exhausted mid-frame\n");
776
777 desc->ctrl = ctrl | MACB_BIT(TX_USED);
778 }
779
780 macb_tx_unmap(bp, tx_skb);
781 }
782
783 /* Set end of TX queue */
784 desc = macb_tx_desc(queue, 0);
785 macb_set_addr(bp, desc, 0);
786 desc->ctrl = MACB_BIT(TX_USED);
787
788 /* Make descriptor updates visible to hardware */
789 wmb();
790
791 /* Reinitialize the TX desc queue */
792 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
793#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
794 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
795 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
796#endif
797 /* Make TX ring reflect state of hardware */
798 queue->tx_head = 0;
799 queue->tx_tail = 0;
800
801 /* Housework before enabling TX IRQ */
802 macb_writel(bp, TSR, macb_readl(bp, TSR));
803 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
804
805 /* Now we are ready to start transmission again */
806 netif_tx_start_all_queues(bp->dev);
807 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
808
809 spin_unlock_irqrestore(&bp->lock, flags);
810}
811
812static void macb_tx_interrupt(struct macb_queue *queue)
813{
814 unsigned int tail;
815 unsigned int head;
816 u32 status;
817 struct macb *bp = queue->bp;
818 u16 queue_index = queue - bp->queues;
819
820 status = macb_readl(bp, TSR);
821 macb_writel(bp, TSR, status);
822
823 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
824 queue_writel(queue, ISR, MACB_BIT(TCOMP));
825
826 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
827 (unsigned long)status);
828
829 head = queue->tx_head;
830 for (tail = queue->tx_tail; tail != head; tail++) {
831 struct macb_tx_skb *tx_skb;
832 struct sk_buff *skb;
833 struct macb_dma_desc *desc;
834 u32 ctrl;
835
836 desc = macb_tx_desc(queue, tail);
837
838 /* Make hw descriptor updates visible to CPU */
839 rmb();
840
841 ctrl = desc->ctrl;
842
843 /* TX_USED bit is only set by hardware on the very first buffer
844 * descriptor of the transmitted frame.
845 */
846 if (!(ctrl & MACB_BIT(TX_USED)))
847 break;
848
849 /* Process all buffers of the current transmitted frame */
850 for (;; tail++) {
851 tx_skb = macb_tx_skb(queue, tail);
852 skb = tx_skb->skb;
853
854 /* First, update TX stats if needed */
855 if (skb) {
856 if (gem_ptp_do_txstamp(queue, skb, desc) == 0) {
857 /* skb now belongs to timestamp buffer
858 * and will be removed later
859 */
860 tx_skb->skb = NULL;
861 }
862 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
863 macb_tx_ring_wrap(bp, tail),
864 skb->data);
865 bp->dev->stats.tx_packets++;
866 queue->stats.tx_packets++;
867 bp->dev->stats.tx_bytes += skb->len;
868 queue->stats.tx_bytes += skb->len;
869 }
870
871 /* Now we can safely release resources */
872 macb_tx_unmap(bp, tx_skb);
873
874 /* skb is set only for the last buffer of the frame.
875 * WARNING: at this point skb has been freed by
876 * macb_tx_unmap().
877 */
878 if (skb)
879 break;
880 }
881 }
882
883 queue->tx_tail = tail;
884 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
885 CIRC_CNT(queue->tx_head, queue->tx_tail,
886 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
887 netif_wake_subqueue(bp->dev, queue_index);
888}
889
890static void gem_rx_refill(struct macb_queue *queue)
891{
892 unsigned int entry;
893 struct sk_buff *skb;
894 dma_addr_t paddr;
895 struct macb *bp = queue->bp;
896 struct macb_dma_desc *desc;
897
898 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
899 bp->rx_ring_size) > 0) {
900 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
901
902 /* Make hw descriptor updates visible to CPU */
903 rmb();
904
905 queue->rx_prepared_head++;
906 desc = macb_rx_desc(queue, entry);
907
908 if (!queue->rx_skbuff[entry]) {
909 /* allocate sk_buff for this free entry in ring */
910 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
911 if (unlikely(!skb)) {
912 netdev_err(bp->dev,
913 "Unable to allocate sk_buff\n");
914 break;
915 }
916
917 /* now fill corresponding descriptor entry */
918 paddr = dma_map_single(&bp->pdev->dev, skb->data,
919 bp->rx_buffer_size,
920 DMA_FROM_DEVICE);
921 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
922 dev_kfree_skb(skb);
923 break;
924 }
925
926 queue->rx_skbuff[entry] = skb;
927
928 if (entry == bp->rx_ring_size - 1)
929 paddr |= MACB_BIT(RX_WRAP);
930 macb_set_addr(bp, desc, paddr);
931 desc->ctrl = 0;
932
933 /* properly align Ethernet header */
934 skb_reserve(skb, NET_IP_ALIGN);
935 } else {
936 desc->addr &= ~MACB_BIT(RX_USED);
937 desc->ctrl = 0;
938 }
939 }
940
941 /* Make descriptor updates visible to hardware */
942 wmb();
943
944 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
945 queue, queue->rx_prepared_head, queue->rx_tail);
946}
947
948/* Mark DMA descriptors from begin up to and not including end as unused */
949static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
950 unsigned int end)
951{
952 unsigned int frag;
953
954 for (frag = begin; frag != end; frag++) {
955 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
956
957 desc->addr &= ~MACB_BIT(RX_USED);
958 }
959
960 /* Make descriptor updates visible to hardware */
961 wmb();
962
963 /* When this happens, the hardware stats registers for
964 * whatever caused this is updated, so we don't have to record
965 * anything.
966 */
967}
968
969static int gem_rx(struct macb_queue *queue, int budget)
970{
971 struct macb *bp = queue->bp;
972 unsigned int len;
973 unsigned int entry;
974 struct sk_buff *skb;
975 struct macb_dma_desc *desc;
976 int count = 0;
977
978 while (count < budget) {
979 u32 ctrl;
980 dma_addr_t addr;
981 bool rxused;
982
983 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
984 desc = macb_rx_desc(queue, entry);
985
986 /* Make hw descriptor updates visible to CPU */
987 rmb();
988
989 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
990 addr = macb_get_addr(bp, desc);
991 ctrl = desc->ctrl;
992
993 if (!rxused)
994 break;
995
996 queue->rx_tail++;
997 count++;
998
999 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1000 netdev_err(bp->dev,
1001 "not whole frame pointed by descriptor\n");
1002 bp->dev->stats.rx_dropped++;
1003 queue->stats.rx_dropped++;
1004 break;
1005 }
1006 skb = queue->rx_skbuff[entry];
1007 if (unlikely(!skb)) {
1008 netdev_err(bp->dev,
1009 "inconsistent Rx descriptor chain\n");
1010 bp->dev->stats.rx_dropped++;
1011 queue->stats.rx_dropped++;
1012 break;
1013 }
1014 /* now everything is ready for receiving packet */
1015 queue->rx_skbuff[entry] = NULL;
1016 len = ctrl & bp->rx_frm_len_mask;
1017
1018 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1019
1020 skb_put(skb, len);
1021 dma_unmap_single(&bp->pdev->dev, addr,
1022 bp->rx_buffer_size, DMA_FROM_DEVICE);
1023
1024 skb->protocol = eth_type_trans(skb, bp->dev);
1025 skb_checksum_none_assert(skb);
1026 if (bp->dev->features & NETIF_F_RXCSUM &&
1027 !(bp->dev->flags & IFF_PROMISC) &&
1028 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1029 skb->ip_summed = CHECKSUM_UNNECESSARY;
1030
1031 bp->dev->stats.rx_packets++;
1032 queue->stats.rx_packets++;
1033 bp->dev->stats.rx_bytes += skb->len;
1034 queue->stats.rx_bytes += skb->len;
1035
1036 gem_ptp_do_rxstamp(bp, skb, desc);
1037
1038#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1039 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1040 skb->len, skb->csum);
1041 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1042 skb_mac_header(skb), 16, true);
1043 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1044 skb->data, 32, true);
1045#endif
1046
1047 netif_receive_skb(skb);
1048 }
1049
1050 gem_rx_refill(queue);
1051
1052 return count;
1053}
1054
1055static int macb_rx_frame(struct macb_queue *queue, unsigned int first_frag,
1056 unsigned int last_frag)
1057{
1058 unsigned int len;
1059 unsigned int frag;
1060 unsigned int offset;
1061 struct sk_buff *skb;
1062 struct macb_dma_desc *desc;
1063 struct macb *bp = queue->bp;
1064
1065 desc = macb_rx_desc(queue, last_frag);
1066 len = desc->ctrl & bp->rx_frm_len_mask;
1067
1068 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1069 macb_rx_ring_wrap(bp, first_frag),
1070 macb_rx_ring_wrap(bp, last_frag), len);
1071
1072 /* The ethernet header starts NET_IP_ALIGN bytes into the
1073 * first buffer. Since the header is 14 bytes, this makes the
1074 * payload word-aligned.
1075 *
1076 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1077 * the two padding bytes into the skb so that we avoid hitting
1078 * the slowpath in memcpy(), and pull them off afterwards.
1079 */
1080 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1081 if (!skb) {
1082 bp->dev->stats.rx_dropped++;
1083 for (frag = first_frag; ; frag++) {
1084 desc = macb_rx_desc(queue, frag);
1085 desc->addr &= ~MACB_BIT(RX_USED);
1086 if (frag == last_frag)
1087 break;
1088 }
1089
1090 /* Make descriptor updates visible to hardware */
1091 wmb();
1092
1093 return 1;
1094 }
1095
1096 offset = 0;
1097 len += NET_IP_ALIGN;
1098 skb_checksum_none_assert(skb);
1099 skb_put(skb, len);
1100
1101 for (frag = first_frag; ; frag++) {
1102 unsigned int frag_len = bp->rx_buffer_size;
1103
1104 if (offset + frag_len > len) {
1105 if (unlikely(frag != last_frag)) {
1106 dev_kfree_skb_any(skb);
1107 return -1;
1108 }
1109 frag_len = len - offset;
1110 }
1111 skb_copy_to_linear_data_offset(skb, offset,
1112 macb_rx_buffer(queue, frag),
1113 frag_len);
1114 offset += bp->rx_buffer_size;
1115 desc = macb_rx_desc(queue, frag);
1116 desc->addr &= ~MACB_BIT(RX_USED);
1117
1118 if (frag == last_frag)
1119 break;
1120 }
1121
1122 /* Make descriptor updates visible to hardware */
1123 wmb();
1124
1125 __skb_pull(skb, NET_IP_ALIGN);
1126 skb->protocol = eth_type_trans(skb, bp->dev);
1127
1128 bp->dev->stats.rx_packets++;
1129 bp->dev->stats.rx_bytes += skb->len;
1130 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1131 skb->len, skb->csum);
1132 netif_receive_skb(skb);
1133
1134 return 0;
1135}
1136
1137static inline void macb_init_rx_ring(struct macb_queue *queue)
1138{
1139 struct macb *bp = queue->bp;
1140 dma_addr_t addr;
1141 struct macb_dma_desc *desc = NULL;
1142 int i;
1143
1144 addr = queue->rx_buffers_dma;
1145 for (i = 0; i < bp->rx_ring_size; i++) {
1146 desc = macb_rx_desc(queue, i);
1147 macb_set_addr(bp, desc, addr);
1148 desc->ctrl = 0;
1149 addr += bp->rx_buffer_size;
1150 }
1151 desc->addr |= MACB_BIT(RX_WRAP);
1152 queue->rx_tail = 0;
1153}
1154
1155static int macb_rx(struct macb_queue *queue, int budget)
1156{
1157 struct macb *bp = queue->bp;
1158 bool reset_rx_queue = false;
1159 int received = 0;
1160 unsigned int tail;
1161 int first_frag = -1;
1162
1163 for (tail = queue->rx_tail; budget > 0; tail++) {
1164 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1165 u32 ctrl;
1166
1167 /* Make hw descriptor updates visible to CPU */
1168 rmb();
1169
1170 ctrl = desc->ctrl;
1171
1172 if (!(desc->addr & MACB_BIT(RX_USED)))
1173 break;
1174
1175 if (ctrl & MACB_BIT(RX_SOF)) {
1176 if (first_frag != -1)
1177 discard_partial_frame(queue, first_frag, tail);
1178 first_frag = tail;
1179 }
1180
1181 if (ctrl & MACB_BIT(RX_EOF)) {
1182 int dropped;
1183
1184 if (unlikely(first_frag == -1)) {
1185 reset_rx_queue = true;
1186 continue;
1187 }
1188
1189 dropped = macb_rx_frame(queue, first_frag, tail);
1190 first_frag = -1;
1191 if (unlikely(dropped < 0)) {
1192 reset_rx_queue = true;
1193 continue;
1194 }
1195 if (!dropped) {
1196 received++;
1197 budget--;
1198 }
1199 }
1200 }
1201
1202 if (unlikely(reset_rx_queue)) {
1203 unsigned long flags;
1204 u32 ctrl;
1205
1206 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1207
1208 spin_lock_irqsave(&bp->lock, flags);
1209
1210 ctrl = macb_readl(bp, NCR);
1211 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1212
1213 macb_init_rx_ring(queue);
1214 queue_writel(queue, RBQP, queue->rx_ring_dma);
1215
1216 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1217
1218 spin_unlock_irqrestore(&bp->lock, flags);
1219 return received;
1220 }
1221
1222 if (first_frag != -1)
1223 queue->rx_tail = first_frag;
1224 else
1225 queue->rx_tail = tail;
1226
1227 return received;
1228}
1229
1230static int macb_poll(struct napi_struct *napi, int budget)
1231{
1232 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1233 struct macb *bp = queue->bp;
1234 int work_done;
1235 u32 status;
1236
1237 status = macb_readl(bp, RSR);
1238 macb_writel(bp, RSR, status);
1239
1240 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1241 (unsigned long)status, budget);
1242
1243 work_done = bp->macbgem_ops.mog_rx(queue, budget);
1244 if (work_done < budget) {
1245 napi_complete_done(napi, work_done);
1246
1247 /* Packets received while interrupts were disabled */
1248 status = macb_readl(bp, RSR);
1249 if (status) {
1250 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1251 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1252 napi_reschedule(napi);
1253 } else {
1254 queue_writel(queue, IER, MACB_RX_INT_FLAGS);
1255 }
1256 }
1257
1258 /* TODO: Handle errors */
1259
1260 return work_done;
1261}
1262
1263static void macb_hresp_error_task(unsigned long data)
1264{
1265 struct macb *bp = (struct macb *)data;
1266 struct net_device *dev = bp->dev;
1267 struct macb_queue *queue = bp->queues;
1268 unsigned int q;
1269 u32 ctrl;
1270
1271 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1272 queue_writel(queue, IDR, MACB_RX_INT_FLAGS |
1273 MACB_TX_INT_FLAGS |
1274 MACB_BIT(HRESP));
1275 }
1276 ctrl = macb_readl(bp, NCR);
1277 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1278 macb_writel(bp, NCR, ctrl);
1279
1280 netif_tx_stop_all_queues(dev);
1281 netif_carrier_off(dev);
1282
1283 bp->macbgem_ops.mog_init_rings(bp);
1284
1285 /* Initialize TX and RX buffers */
1286 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1287 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
1288#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1289 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1290 queue_writel(queue, RBQPH,
1291 upper_32_bits(queue->rx_ring_dma));
1292#endif
1293 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1294#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1295 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1296 queue_writel(queue, TBQPH,
1297 upper_32_bits(queue->tx_ring_dma));
1298#endif
1299
1300 /* Enable interrupts */
1301 queue_writel(queue, IER,
1302 MACB_RX_INT_FLAGS |
1303 MACB_TX_INT_FLAGS |
1304 MACB_BIT(HRESP));
1305 }
1306
1307 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1308 macb_writel(bp, NCR, ctrl);
1309
1310 netif_carrier_on(dev);
1311 netif_tx_start_all_queues(dev);
1312}
1313
1314static irqreturn_t macb_interrupt(int irq, void *dev_id)
1315{
1316 struct macb_queue *queue = dev_id;
1317 struct macb *bp = queue->bp;
1318 struct net_device *dev = bp->dev;
1319 u32 status, ctrl;
1320
1321 status = queue_readl(queue, ISR);
1322
1323 if (unlikely(!status))
1324 return IRQ_NONE;
1325
1326 spin_lock(&bp->lock);
1327
1328 while (status) {
1329 /* close possible race with dev_close */
1330 if (unlikely(!netif_running(dev))) {
1331 queue_writel(queue, IDR, -1);
1332 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1333 queue_writel(queue, ISR, -1);
1334 break;
1335 }
1336
1337 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1338 (unsigned int)(queue - bp->queues),
1339 (unsigned long)status);
1340
1341 if (status & MACB_RX_INT_FLAGS) {
1342 /* There's no point taking any more interrupts
1343 * until we have processed the buffers. The
1344 * scheduling call may fail if the poll routine
1345 * is already scheduled, so disable interrupts
1346 * now.
1347 */
1348 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1349 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1350 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1351
1352 if (napi_schedule_prep(&queue->napi)) {
1353 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1354 __napi_schedule(&queue->napi);
1355 }
1356 }
1357
1358 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1359 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1360 schedule_work(&queue->tx_error_task);
1361
1362 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1363 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1364
1365 break;
1366 }
1367
1368 if (status & MACB_BIT(TCOMP))
1369 macb_tx_interrupt(queue);
1370
1371 /* Link change detection isn't possible with RMII, so we'll
1372 * add that if/when we get our hands on a full-blown MII PHY.
1373 */
1374
1375 /* There is a hardware issue under heavy load where DMA can
1376 * stop, this causes endless "used buffer descriptor read"
1377 * interrupts but it can be cleared by re-enabling RX. See
1378 * the at91 manual, section 41.3.1 or the Zynq manual
1379 * section 16.7.4 for details.
1380 */
1381 if (status & MACB_BIT(RXUBR)) {
1382 ctrl = macb_readl(bp, NCR);
1383 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1384 wmb();
1385 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1386
1387 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1388 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1389 }
1390
1391 if (status & MACB_BIT(ISR_ROVR)) {
1392 /* We missed at least one packet */
1393 if (macb_is_gem(bp))
1394 bp->hw_stats.gem.rx_overruns++;
1395 else
1396 bp->hw_stats.macb.rx_overruns++;
1397
1398 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1399 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1400 }
1401
1402 if (status & MACB_BIT(HRESP)) {
1403 tasklet_schedule(&bp->hresp_err_tasklet);
1404 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1405
1406 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1407 queue_writel(queue, ISR, MACB_BIT(HRESP));
1408 }
1409 status = queue_readl(queue, ISR);
1410 }
1411
1412 spin_unlock(&bp->lock);
1413
1414 return IRQ_HANDLED;
1415}
1416
1417#ifdef CONFIG_NET_POLL_CONTROLLER
1418/* Polling receive - used by netconsole and other diagnostic tools
1419 * to allow network i/o with interrupts disabled.
1420 */
1421static void macb_poll_controller(struct net_device *dev)
1422{
1423 struct macb *bp = netdev_priv(dev);
1424 struct macb_queue *queue;
1425 unsigned long flags;
1426 unsigned int q;
1427
1428 local_irq_save(flags);
1429 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1430 macb_interrupt(dev->irq, queue);
1431 local_irq_restore(flags);
1432}
1433#endif
1434
1435static unsigned int macb_tx_map(struct macb *bp,
1436 struct macb_queue *queue,
1437 struct sk_buff *skb,
1438 unsigned int hdrlen)
1439{
1440 dma_addr_t mapping;
1441 unsigned int len, entry, i, tx_head = queue->tx_head;
1442 struct macb_tx_skb *tx_skb = NULL;
1443 struct macb_dma_desc *desc;
1444 unsigned int offset, size, count = 0;
1445 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1446 unsigned int eof = 1, mss_mfs = 0;
1447 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1448
1449 /* LSO */
1450 if (skb_shinfo(skb)->gso_size != 0) {
1451 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1452 /* UDP - UFO */
1453 lso_ctrl = MACB_LSO_UFO_ENABLE;
1454 else
1455 /* TCP - TSO */
1456 lso_ctrl = MACB_LSO_TSO_ENABLE;
1457 }
1458
1459 /* First, map non-paged data */
1460 len = skb_headlen(skb);
1461
1462 /* first buffer length */
1463 size = hdrlen;
1464
1465 offset = 0;
1466 while (len) {
1467 entry = macb_tx_ring_wrap(bp, tx_head);
1468 tx_skb = &queue->tx_skb[entry];
1469
1470 mapping = dma_map_single(&bp->pdev->dev,
1471 skb->data + offset,
1472 size, DMA_TO_DEVICE);
1473 if (dma_mapping_error(&bp->pdev->dev, mapping))
1474 goto dma_error;
1475
1476 /* Save info to properly release resources */
1477 tx_skb->skb = NULL;
1478 tx_skb->mapping = mapping;
1479 tx_skb->size = size;
1480 tx_skb->mapped_as_page = false;
1481
1482 len -= size;
1483 offset += size;
1484 count++;
1485 tx_head++;
1486
1487 size = min(len, bp->max_tx_length);
1488 }
1489
1490 /* Then, map paged data from fragments */
1491 for (f = 0; f < nr_frags; f++) {
1492 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1493
1494 len = skb_frag_size(frag);
1495 offset = 0;
1496 while (len) {
1497 size = min(len, bp->max_tx_length);
1498 entry = macb_tx_ring_wrap(bp, tx_head);
1499 tx_skb = &queue->tx_skb[entry];
1500
1501 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1502 offset, size, DMA_TO_DEVICE);
1503 if (dma_mapping_error(&bp->pdev->dev, mapping))
1504 goto dma_error;
1505
1506 /* Save info to properly release resources */
1507 tx_skb->skb = NULL;
1508 tx_skb->mapping = mapping;
1509 tx_skb->size = size;
1510 tx_skb->mapped_as_page = true;
1511
1512 len -= size;
1513 offset += size;
1514 count++;
1515 tx_head++;
1516 }
1517 }
1518
1519 /* Should never happen */
1520 if (unlikely(!tx_skb)) {
1521 netdev_err(bp->dev, "BUG! empty skb!\n");
1522 return 0;
1523 }
1524
1525 /* This is the last buffer of the frame: save socket buffer */
1526 tx_skb->skb = skb;
1527
1528 /* Update TX ring: update buffer descriptors in reverse order
1529 * to avoid race condition
1530 */
1531
1532 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1533 * to set the end of TX queue
1534 */
1535 i = tx_head;
1536 entry = macb_tx_ring_wrap(bp, i);
1537 ctrl = MACB_BIT(TX_USED);
1538 desc = macb_tx_desc(queue, entry);
1539 desc->ctrl = ctrl;
1540
1541 if (lso_ctrl) {
1542 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1543 /* include header and FCS in value given to h/w */
1544 mss_mfs = skb_shinfo(skb)->gso_size +
1545 skb_transport_offset(skb) +
1546 ETH_FCS_LEN;
1547 else /* TSO */ {
1548 mss_mfs = skb_shinfo(skb)->gso_size;
1549 /* TCP Sequence Number Source Select
1550 * can be set only for TSO
1551 */
1552 seq_ctrl = 0;
1553 }
1554 }
1555
1556 do {
1557 i--;
1558 entry = macb_tx_ring_wrap(bp, i);
1559 tx_skb = &queue->tx_skb[entry];
1560 desc = macb_tx_desc(queue, entry);
1561
1562 ctrl = (u32)tx_skb->size;
1563 if (eof) {
1564 ctrl |= MACB_BIT(TX_LAST);
1565 eof = 0;
1566 }
1567 if (unlikely(entry == (bp->tx_ring_size - 1)))
1568 ctrl |= MACB_BIT(TX_WRAP);
1569
1570 /* First descriptor is header descriptor */
1571 if (i == queue->tx_head) {
1572 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1573 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1574 } else
1575 /* Only set MSS/MFS on payload descriptors
1576 * (second or later descriptor)
1577 */
1578 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1579
1580 /* Set TX buffer descriptor */
1581 macb_set_addr(bp, desc, tx_skb->mapping);
1582 /* desc->addr must be visible to hardware before clearing
1583 * 'TX_USED' bit in desc->ctrl.
1584 */
1585 wmb();
1586 desc->ctrl = ctrl;
1587 } while (i != queue->tx_head);
1588
1589 queue->tx_head = tx_head;
1590
1591 return count;
1592
1593dma_error:
1594 netdev_err(bp->dev, "TX DMA map failed\n");
1595
1596 for (i = queue->tx_head; i != tx_head; i++) {
1597 tx_skb = macb_tx_skb(queue, i);
1598
1599 macb_tx_unmap(bp, tx_skb);
1600 }
1601
1602 return 0;
1603}
1604
1605static netdev_features_t macb_features_check(struct sk_buff *skb,
1606 struct net_device *dev,
1607 netdev_features_t features)
1608{
1609 unsigned int nr_frags, f;
1610 unsigned int hdrlen;
1611
1612 /* Validate LSO compatibility */
1613
1614 /* there is only one buffer */
1615 if (!skb_is_nonlinear(skb))
1616 return features;
1617
1618 /* length of header */
1619 hdrlen = skb_transport_offset(skb);
1620 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1621 hdrlen += tcp_hdrlen(skb);
1622
1623 /* For LSO:
1624 * When software supplies two or more payload buffers all payload buffers
1625 * apart from the last must be a multiple of 8 bytes in size.
1626 */
1627 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1628 return features & ~MACB_NETIF_LSO;
1629
1630 nr_frags = skb_shinfo(skb)->nr_frags;
1631 /* No need to check last fragment */
1632 nr_frags--;
1633 for (f = 0; f < nr_frags; f++) {
1634 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1635
1636 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1637 return features & ~MACB_NETIF_LSO;
1638 }
1639 return features;
1640}
1641
1642static inline int macb_clear_csum(struct sk_buff *skb)
1643{
1644 /* no change for packets without checksum offloading */
1645 if (skb->ip_summed != CHECKSUM_PARTIAL)
1646 return 0;
1647
1648 /* make sure we can modify the header */
1649 if (unlikely(skb_cow_head(skb, 0)))
1650 return -1;
1651
1652 /* initialize checksum field
1653 * This is required - at least for Zynq, which otherwise calculates
1654 * wrong UDP header checksums for UDP packets with UDP data len <=2
1655 */
1656 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1657 return 0;
1658}
1659
1660static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1661{
1662 u16 queue_index = skb_get_queue_mapping(skb);
1663 struct macb *bp = netdev_priv(dev);
1664 struct macb_queue *queue = &bp->queues[queue_index];
1665 unsigned long flags;
1666 unsigned int desc_cnt, nr_frags, frag_size, f;
1667 unsigned int hdrlen;
1668 bool is_lso, is_udp = 0;
1669
1670 is_lso = (skb_shinfo(skb)->gso_size != 0);
1671
1672 if (is_lso) {
1673 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1674
1675 /* length of headers */
1676 if (is_udp)
1677 /* only queue eth + ip headers separately for UDP */
1678 hdrlen = skb_transport_offset(skb);
1679 else
1680 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1681 if (skb_headlen(skb) < hdrlen) {
1682 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1683 /* if this is required, would need to copy to single buffer */
1684 return NETDEV_TX_BUSY;
1685 }
1686 } else
1687 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1688
1689#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1690 netdev_vdbg(bp->dev,
1691 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1692 queue_index, skb->len, skb->head, skb->data,
1693 skb_tail_pointer(skb), skb_end_pointer(skb));
1694 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1695 skb->data, 16, true);
1696#endif
1697
1698 /* Count how many TX buffer descriptors are needed to send this
1699 * socket buffer: skb fragments of jumbo frames may need to be
1700 * split into many buffer descriptors.
1701 */
1702 if (is_lso && (skb_headlen(skb) > hdrlen))
1703 /* extra header descriptor if also payload in first buffer */
1704 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1705 else
1706 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1707 nr_frags = skb_shinfo(skb)->nr_frags;
1708 for (f = 0; f < nr_frags; f++) {
1709 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1710 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1711 }
1712
1713 spin_lock_irqsave(&bp->lock, flags);
1714
1715 /* This is a hard error, log it. */
1716 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1717 bp->tx_ring_size) < desc_cnt) {
1718 netif_stop_subqueue(dev, queue_index);
1719 spin_unlock_irqrestore(&bp->lock, flags);
1720 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1721 queue->tx_head, queue->tx_tail);
1722 return NETDEV_TX_BUSY;
1723 }
1724
1725 if (macb_clear_csum(skb)) {
1726 dev_kfree_skb_any(skb);
1727 goto unlock;
1728 }
1729
1730 /* Map socket buffer for DMA transfer */
1731 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1732 dev_kfree_skb_any(skb);
1733 goto unlock;
1734 }
1735
1736 /* Make newly initialized descriptor visible to hardware */
1737 wmb();
1738 skb_tx_timestamp(skb);
1739
1740 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1741
1742 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1743 netif_stop_subqueue(dev, queue_index);
1744
1745unlock:
1746 spin_unlock_irqrestore(&bp->lock, flags);
1747
1748 return NETDEV_TX_OK;
1749}
1750
1751static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1752{
1753 if (!macb_is_gem(bp)) {
1754 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1755 } else {
1756 bp->rx_buffer_size = size;
1757
1758 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1759 netdev_dbg(bp->dev,
1760 "RX buffer must be multiple of %d bytes, expanding\n",
1761 RX_BUFFER_MULTIPLE);
1762 bp->rx_buffer_size =
1763 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1764 }
1765 }
1766
1767 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1768 bp->dev->mtu, bp->rx_buffer_size);
1769}
1770
1771static void gem_free_rx_buffers(struct macb *bp)
1772{
1773 struct sk_buff *skb;
1774 struct macb_dma_desc *desc;
1775 struct macb_queue *queue;
1776 dma_addr_t addr;
1777 unsigned int q;
1778 int i;
1779
1780 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1781 if (!queue->rx_skbuff)
1782 continue;
1783
1784 for (i = 0; i < bp->rx_ring_size; i++) {
1785 skb = queue->rx_skbuff[i];
1786
1787 if (!skb)
1788 continue;
1789
1790 desc = macb_rx_desc(queue, i);
1791 addr = macb_get_addr(bp, desc);
1792
1793 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1794 DMA_FROM_DEVICE);
1795 dev_kfree_skb_any(skb);
1796 skb = NULL;
1797 }
1798
1799 kfree(queue->rx_skbuff);
1800 queue->rx_skbuff = NULL;
1801 }
1802}
1803
1804static void macb_free_rx_buffers(struct macb *bp)
1805{
1806 struct macb_queue *queue = &bp->queues[0];
1807
1808 if (queue->rx_buffers) {
1809 dma_free_coherent(&bp->pdev->dev,
1810 bp->rx_ring_size * bp->rx_buffer_size,
1811 queue->rx_buffers, queue->rx_buffers_dma);
1812 queue->rx_buffers = NULL;
1813 }
1814}
1815
1816static void macb_free_consistent(struct macb *bp)
1817{
1818 struct macb_queue *queue;
1819 unsigned int q;
1820
1821 queue = &bp->queues[0];
1822 bp->macbgem_ops.mog_free_rx_buffers(bp);
1823 if (queue->rx_ring) {
1824 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES(bp),
1825 queue->rx_ring, queue->rx_ring_dma);
1826 queue->rx_ring = NULL;
1827 }
1828
1829 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1830 kfree(queue->tx_skb);
1831 queue->tx_skb = NULL;
1832 if (queue->tx_ring) {
1833 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES(bp),
1834 queue->tx_ring, queue->tx_ring_dma);
1835 queue->tx_ring = NULL;
1836 }
1837 }
1838}
1839
1840static int gem_alloc_rx_buffers(struct macb *bp)
1841{
1842 struct macb_queue *queue;
1843 unsigned int q;
1844 int size;
1845
1846 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1847 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1848 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
1849 if (!queue->rx_skbuff)
1850 return -ENOMEM;
1851 else
1852 netdev_dbg(bp->dev,
1853 "Allocated %d RX struct sk_buff entries at %p\n",
1854 bp->rx_ring_size, queue->rx_skbuff);
1855 }
1856 return 0;
1857}
1858
1859static int macb_alloc_rx_buffers(struct macb *bp)
1860{
1861 struct macb_queue *queue = &bp->queues[0];
1862 int size;
1863
1864 size = bp->rx_ring_size * bp->rx_buffer_size;
1865 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1866 &queue->rx_buffers_dma, GFP_KERNEL);
1867 if (!queue->rx_buffers)
1868 return -ENOMEM;
1869
1870 netdev_dbg(bp->dev,
1871 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1872 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
1873 return 0;
1874}
1875
1876static int macb_alloc_consistent(struct macb *bp)
1877{
1878 struct macb_queue *queue;
1879 unsigned int q;
1880 int size;
1881
1882 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1883 size = TX_RING_BYTES(bp);
1884 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1885 &queue->tx_ring_dma,
1886 GFP_KERNEL);
1887 if (!queue->tx_ring)
1888 goto out_err;
1889 netdev_dbg(bp->dev,
1890 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1891 q, size, (unsigned long)queue->tx_ring_dma,
1892 queue->tx_ring);
1893
1894 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
1895 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1896 if (!queue->tx_skb)
1897 goto out_err;
1898
1899 size = RX_RING_BYTES(bp);
1900 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1901 &queue->rx_ring_dma, GFP_KERNEL);
1902 if (!queue->rx_ring)
1903 goto out_err;
1904 netdev_dbg(bp->dev,
1905 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1906 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
1907 }
1908 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1909 goto out_err;
1910
1911 return 0;
1912
1913out_err:
1914 macb_free_consistent(bp);
1915 return -ENOMEM;
1916}
1917
1918static void gem_init_rings(struct macb *bp)
1919{
1920 struct macb_queue *queue;
1921 struct macb_dma_desc *desc = NULL;
1922 unsigned int q;
1923 int i;
1924
1925 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1926 for (i = 0; i < bp->tx_ring_size; i++) {
1927 desc = macb_tx_desc(queue, i);
1928 macb_set_addr(bp, desc, 0);
1929 desc->ctrl = MACB_BIT(TX_USED);
1930 }
1931 desc->ctrl |= MACB_BIT(TX_WRAP);
1932 queue->tx_head = 0;
1933 queue->tx_tail = 0;
1934
1935 queue->rx_tail = 0;
1936 queue->rx_prepared_head = 0;
1937
1938 gem_rx_refill(queue);
1939 }
1940
1941}
1942
1943static void macb_init_rings(struct macb *bp)
1944{
1945 int i;
1946 struct macb_dma_desc *desc = NULL;
1947
1948 macb_init_rx_ring(&bp->queues[0]);
1949
1950 for (i = 0; i < bp->tx_ring_size; i++) {
1951 desc = macb_tx_desc(&bp->queues[0], i);
1952 macb_set_addr(bp, desc, 0);
1953 desc->ctrl = MACB_BIT(TX_USED);
1954 }
1955 bp->queues[0].tx_head = 0;
1956 bp->queues[0].tx_tail = 0;
1957 desc->ctrl |= MACB_BIT(TX_WRAP);
1958}
1959
1960static void macb_reset_hw(struct macb *bp)
1961{
1962 struct macb_queue *queue;
1963 unsigned int q;
1964
1965 /* Disable RX and TX (XXX: Should we halt the transmission
1966 * more gracefully?)
1967 */
1968 macb_writel(bp, NCR, 0);
1969
1970 /* Clear the stats registers (XXX: Update stats first?) */
1971 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1972
1973 /* Clear all status flags */
1974 macb_writel(bp, TSR, -1);
1975 macb_writel(bp, RSR, -1);
1976
1977 /* Disable all interrupts */
1978 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1979 queue_writel(queue, IDR, -1);
1980 queue_readl(queue, ISR);
1981 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1982 queue_writel(queue, ISR, -1);
1983 }
1984}
1985
1986static u32 gem_mdc_clk_div(struct macb *bp)
1987{
1988 u32 config;
1989 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1990
1991 if (pclk_hz <= 20000000)
1992 config = GEM_BF(CLK, GEM_CLK_DIV8);
1993 else if (pclk_hz <= 40000000)
1994 config = GEM_BF(CLK, GEM_CLK_DIV16);
1995 else if (pclk_hz <= 80000000)
1996 config = GEM_BF(CLK, GEM_CLK_DIV32);
1997 else if (pclk_hz <= 120000000)
1998 config = GEM_BF(CLK, GEM_CLK_DIV48);
1999 else if (pclk_hz <= 160000000)
2000 config = GEM_BF(CLK, GEM_CLK_DIV64);
2001 else
2002 config = GEM_BF(CLK, GEM_CLK_DIV96);
2003
2004 return config;
2005}
2006
2007static u32 macb_mdc_clk_div(struct macb *bp)
2008{
2009 u32 config;
2010 unsigned long pclk_hz;
2011
2012 if (macb_is_gem(bp))
2013 return gem_mdc_clk_div(bp);
2014
2015 pclk_hz = clk_get_rate(bp->pclk);
2016 if (pclk_hz <= 20000000)
2017 config = MACB_BF(CLK, MACB_CLK_DIV8);
2018 else if (pclk_hz <= 40000000)
2019 config = MACB_BF(CLK, MACB_CLK_DIV16);
2020 else if (pclk_hz <= 80000000)
2021 config = MACB_BF(CLK, MACB_CLK_DIV32);
2022 else
2023 config = MACB_BF(CLK, MACB_CLK_DIV64);
2024
2025 return config;
2026}
2027
2028/* Get the DMA bus width field of the network configuration register that we
2029 * should program. We find the width from decoding the design configuration
2030 * register to find the maximum supported data bus width.
2031 */
2032static u32 macb_dbw(struct macb *bp)
2033{
2034 if (!macb_is_gem(bp))
2035 return 0;
2036
2037 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2038 case 4:
2039 return GEM_BF(DBW, GEM_DBW128);
2040 case 2:
2041 return GEM_BF(DBW, GEM_DBW64);
2042 case 1:
2043 default:
2044 return GEM_BF(DBW, GEM_DBW32);
2045 }
2046}
2047
2048/* Configure the receive DMA engine
2049 * - use the correct receive buffer size
2050 * - set best burst length for DMA operations
2051 * (if not supported by FIFO, it will fallback to default)
2052 * - set both rx/tx packet buffers to full memory size
2053 * These are configurable parameters for GEM.
2054 */
2055static void macb_configure_dma(struct macb *bp)
2056{
2057 struct macb_queue *queue;
2058 u32 buffer_size;
2059 unsigned int q;
2060 u32 dmacfg;
2061
2062 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2063 if (macb_is_gem(bp)) {
2064 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2065 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2066 if (q)
2067 queue_writel(queue, RBQS, buffer_size);
2068 else
2069 dmacfg |= GEM_BF(RXBS, buffer_size);
2070 }
2071 if (bp->dma_burst_length)
2072 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2073 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2074 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2075
2076 if (bp->native_io)
2077 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2078 else
2079 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2080
2081 if (bp->dev->features & NETIF_F_HW_CSUM)
2082 dmacfg |= GEM_BIT(TXCOEN);
2083 else
2084 dmacfg &= ~GEM_BIT(TXCOEN);
2085
2086#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2087 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2088 dmacfg |= GEM_BIT(ADDR64);
2089#endif
2090#ifdef CONFIG_MACB_USE_HWSTAMP
2091 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2092 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2093#endif
2094 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2095 dmacfg);
2096 gem_writel(bp, DMACFG, dmacfg);
2097 }
2098}
2099
2100static void macb_init_hw(struct macb *bp)
2101{
2102 struct macb_queue *queue;
2103 unsigned int q;
2104
2105 u32 config;
2106
2107 macb_reset_hw(bp);
2108 macb_set_hwaddr(bp);
2109
2110 config = macb_mdc_clk_div(bp);
2111 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2112 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2113 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2114 config |= MACB_BIT(PAE); /* PAuse Enable */
2115 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2116 if (bp->caps & MACB_CAPS_JUMBO)
2117 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2118 else
2119 config |= MACB_BIT(BIG); /* Receive oversized frames */
2120 if (bp->dev->flags & IFF_PROMISC)
2121 config |= MACB_BIT(CAF); /* Copy All Frames */
2122 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2123 config |= GEM_BIT(RXCOEN);
2124 if (!(bp->dev->flags & IFF_BROADCAST))
2125 config |= MACB_BIT(NBC); /* No BroadCast */
2126 config |= macb_dbw(bp);
2127 macb_writel(bp, NCFGR, config);
2128 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2129 gem_writel(bp, JML, bp->jumbo_max_len);
2130 bp->speed = SPEED_10;
2131 bp->duplex = DUPLEX_HALF;
2132 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2133 if (bp->caps & MACB_CAPS_JUMBO)
2134 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2135
2136 macb_configure_dma(bp);
2137
2138 /* Initialize TX and RX buffers */
2139 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2140 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
2141#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2142 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2143 queue_writel(queue, RBQPH, upper_32_bits(queue->rx_ring_dma));
2144#endif
2145 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2146#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2147 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2148 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2149#endif
2150
2151 /* Enable interrupts */
2152 queue_writel(queue, IER,
2153 MACB_RX_INT_FLAGS |
2154 MACB_TX_INT_FLAGS |
2155 MACB_BIT(HRESP));
2156 }
2157
2158 /* Enable TX and RX */
2159 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
2160}
2161
2162/* The hash address register is 64 bits long and takes up two
2163 * locations in the memory map. The least significant bits are stored
2164 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2165 *
2166 * The unicast hash enable and the multicast hash enable bits in the
2167 * network configuration register enable the reception of hash matched
2168 * frames. The destination address is reduced to a 6 bit index into
2169 * the 64 bit hash register using the following hash function. The
2170 * hash function is an exclusive or of every sixth bit of the
2171 * destination address.
2172 *
2173 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2174 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2175 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2176 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2177 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2178 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2179 *
2180 * da[0] represents the least significant bit of the first byte
2181 * received, that is, the multicast/unicast indicator, and da[47]
2182 * represents the most significant bit of the last byte received. If
2183 * the hash index, hi[n], points to a bit that is set in the hash
2184 * register then the frame will be matched according to whether the
2185 * frame is multicast or unicast. A multicast match will be signalled
2186 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2187 * index points to a bit set in the hash register. A unicast match
2188 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2189 * and the hash index points to a bit set in the hash register. To
2190 * receive all multicast frames, the hash register should be set with
2191 * all ones and the multicast hash enable bit should be set in the
2192 * network configuration register.
2193 */
2194
2195static inline int hash_bit_value(int bitnr, __u8 *addr)
2196{
2197 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2198 return 1;
2199 return 0;
2200}
2201
2202/* Return the hash index value for the specified address. */
2203static int hash_get_index(__u8 *addr)
2204{
2205 int i, j, bitval;
2206 int hash_index = 0;
2207
2208 for (j = 0; j < 6; j++) {
2209 for (i = 0, bitval = 0; i < 8; i++)
2210 bitval ^= hash_bit_value(i * 6 + j, addr);
2211
2212 hash_index |= (bitval << j);
2213 }
2214
2215 return hash_index;
2216}
2217
2218/* Add multicast addresses to the internal multicast-hash table. */
2219static void macb_sethashtable(struct net_device *dev)
2220{
2221 struct netdev_hw_addr *ha;
2222 unsigned long mc_filter[2];
2223 unsigned int bitnr;
2224 struct macb *bp = netdev_priv(dev);
2225
2226 mc_filter[0] = 0;
2227 mc_filter[1] = 0;
2228
2229 netdev_for_each_mc_addr(ha, dev) {
2230 bitnr = hash_get_index(ha->addr);
2231 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2232 }
2233
2234 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2235 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2236}
2237
2238/* Enable/Disable promiscuous and multicast modes. */
2239static void macb_set_rx_mode(struct net_device *dev)
2240{
2241 unsigned long cfg;
2242 struct macb *bp = netdev_priv(dev);
2243
2244 cfg = macb_readl(bp, NCFGR);
2245
2246 if (dev->flags & IFF_PROMISC) {
2247 /* Enable promiscuous mode */
2248 cfg |= MACB_BIT(CAF);
2249
2250 /* Disable RX checksum offload */
2251 if (macb_is_gem(bp))
2252 cfg &= ~GEM_BIT(RXCOEN);
2253 } else {
2254 /* Disable promiscuous mode */
2255 cfg &= ~MACB_BIT(CAF);
2256
2257 /* Enable RX checksum offload only if requested */
2258 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2259 cfg |= GEM_BIT(RXCOEN);
2260 }
2261
2262 if (dev->flags & IFF_ALLMULTI) {
2263 /* Enable all multicast mode */
2264 macb_or_gem_writel(bp, HRB, -1);
2265 macb_or_gem_writel(bp, HRT, -1);
2266 cfg |= MACB_BIT(NCFGR_MTI);
2267 } else if (!netdev_mc_empty(dev)) {
2268 /* Enable specific multicasts */
2269 macb_sethashtable(dev);
2270 cfg |= MACB_BIT(NCFGR_MTI);
2271 } else if (dev->flags & (~IFF_ALLMULTI)) {
2272 /* Disable all multicast mode */
2273 macb_or_gem_writel(bp, HRB, 0);
2274 macb_or_gem_writel(bp, HRT, 0);
2275 cfg &= ~MACB_BIT(NCFGR_MTI);
2276 }
2277
2278 macb_writel(bp, NCFGR, cfg);
2279}
2280
2281static int macb_open(struct net_device *dev)
2282{
2283 struct macb *bp = netdev_priv(dev);
2284 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2285 struct macb_queue *queue;
2286 unsigned int q;
2287 int err;
2288
2289 netdev_dbg(bp->dev, "open\n");
2290
2291 /* carrier starts down */
2292 netif_carrier_off(dev);
2293
2294 /* if the phy is not yet register, retry later*/
2295 if (!dev->phydev)
2296 return -EAGAIN;
2297
2298 /* RX buffers initialization */
2299 macb_init_rx_buffer_size(bp, bufsz);
2300
2301 err = macb_alloc_consistent(bp);
2302 if (err) {
2303 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2304 err);
2305 return err;
2306 }
2307
2308 bp->macbgem_ops.mog_init_rings(bp);
2309 macb_init_hw(bp);
2310
2311 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2312 napi_enable(&queue->napi);
2313
2314 /* schedule a link state check */
2315 phy_start(dev->phydev);
2316
2317 netif_tx_start_all_queues(dev);
2318
2319 if (bp->ptp_info)
2320 bp->ptp_info->ptp_init(dev);
2321
2322 return 0;
2323}
2324
2325static int macb_close(struct net_device *dev)
2326{
2327 struct macb *bp = netdev_priv(dev);
2328 struct macb_queue *queue;
2329 unsigned long flags;
2330 unsigned int q;
2331
2332 netif_tx_stop_all_queues(dev);
2333
2334 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2335 napi_disable(&queue->napi);
2336
2337 if (dev->phydev)
2338 phy_stop(dev->phydev);
2339
2340 spin_lock_irqsave(&bp->lock, flags);
2341 macb_reset_hw(bp);
2342 netif_carrier_off(dev);
2343 spin_unlock_irqrestore(&bp->lock, flags);
2344
2345 macb_free_consistent(bp);
2346
2347 if (bp->ptp_info)
2348 bp->ptp_info->ptp_remove(dev);
2349
2350 return 0;
2351}
2352
2353static int macb_change_mtu(struct net_device *dev, int new_mtu)
2354{
2355 if (netif_running(dev))
2356 return -EBUSY;
2357
2358 dev->mtu = new_mtu;
2359
2360 return 0;
2361}
2362
2363static void gem_update_stats(struct macb *bp)
2364{
2365 struct macb_queue *queue;
2366 unsigned int i, q, idx;
2367 unsigned long *stat;
2368
2369 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2370
2371 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2372 u32 offset = gem_statistics[i].offset;
2373 u64 val = bp->macb_reg_readl(bp, offset);
2374
2375 bp->ethtool_stats[i] += val;
2376 *p += val;
2377
2378 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2379 /* Add GEM_OCTTXH, GEM_OCTRXH */
2380 val = bp->macb_reg_readl(bp, offset + 4);
2381 bp->ethtool_stats[i] += ((u64)val) << 32;
2382 *(++p) += val;
2383 }
2384 }
2385
2386 idx = GEM_STATS_LEN;
2387 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2388 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2389 bp->ethtool_stats[idx++] = *stat;
2390}
2391
2392static struct net_device_stats *gem_get_stats(struct macb *bp)
2393{
2394 struct gem_stats *hwstat = &bp->hw_stats.gem;
2395 struct net_device_stats *nstat = &bp->dev->stats;
2396
2397 gem_update_stats(bp);
2398
2399 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2400 hwstat->rx_alignment_errors +
2401 hwstat->rx_resource_errors +
2402 hwstat->rx_overruns +
2403 hwstat->rx_oversize_frames +
2404 hwstat->rx_jabbers +
2405 hwstat->rx_undersized_frames +
2406 hwstat->rx_length_field_frame_errors);
2407 nstat->tx_errors = (hwstat->tx_late_collisions +
2408 hwstat->tx_excessive_collisions +
2409 hwstat->tx_underrun +
2410 hwstat->tx_carrier_sense_errors);
2411 nstat->multicast = hwstat->rx_multicast_frames;
2412 nstat->collisions = (hwstat->tx_single_collision_frames +
2413 hwstat->tx_multiple_collision_frames +
2414 hwstat->tx_excessive_collisions);
2415 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2416 hwstat->rx_jabbers +
2417 hwstat->rx_undersized_frames +
2418 hwstat->rx_length_field_frame_errors);
2419 nstat->rx_over_errors = hwstat->rx_resource_errors;
2420 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2421 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2422 nstat->rx_fifo_errors = hwstat->rx_overruns;
2423 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2424 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2425 nstat->tx_fifo_errors = hwstat->tx_underrun;
2426
2427 return nstat;
2428}
2429
2430static void gem_get_ethtool_stats(struct net_device *dev,
2431 struct ethtool_stats *stats, u64 *data)
2432{
2433 struct macb *bp;
2434
2435 bp = netdev_priv(dev);
2436 gem_update_stats(bp);
2437 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2438 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2439}
2440
2441static int gem_get_sset_count(struct net_device *dev, int sset)
2442{
2443 struct macb *bp = netdev_priv(dev);
2444
2445 switch (sset) {
2446 case ETH_SS_STATS:
2447 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2448 default:
2449 return -EOPNOTSUPP;
2450 }
2451}
2452
2453static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2454{
2455 char stat_string[ETH_GSTRING_LEN];
2456 struct macb *bp = netdev_priv(dev);
2457 struct macb_queue *queue;
2458 unsigned int i;
2459 unsigned int q;
2460
2461 switch (sset) {
2462 case ETH_SS_STATS:
2463 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2464 memcpy(p, gem_statistics[i].stat_string,
2465 ETH_GSTRING_LEN);
2466
2467 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2468 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2469 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2470 q, queue_statistics[i].stat_string);
2471 memcpy(p, stat_string, ETH_GSTRING_LEN);
2472 }
2473 }
2474 break;
2475 }
2476}
2477
2478static struct net_device_stats *macb_get_stats(struct net_device *dev)
2479{
2480 struct macb *bp = netdev_priv(dev);
2481 struct net_device_stats *nstat = &bp->dev->stats;
2482 struct macb_stats *hwstat = &bp->hw_stats.macb;
2483
2484 if (macb_is_gem(bp))
2485 return gem_get_stats(bp);
2486
2487 /* read stats from hardware */
2488 macb_update_stats(bp);
2489
2490 /* Convert HW stats into netdevice stats */
2491 nstat->rx_errors = (hwstat->rx_fcs_errors +
2492 hwstat->rx_align_errors +
2493 hwstat->rx_resource_errors +
2494 hwstat->rx_overruns +
2495 hwstat->rx_oversize_pkts +
2496 hwstat->rx_jabbers +
2497 hwstat->rx_undersize_pkts +
2498 hwstat->rx_length_mismatch);
2499 nstat->tx_errors = (hwstat->tx_late_cols +
2500 hwstat->tx_excessive_cols +
2501 hwstat->tx_underruns +
2502 hwstat->tx_carrier_errors +
2503 hwstat->sqe_test_errors);
2504 nstat->collisions = (hwstat->tx_single_cols +
2505 hwstat->tx_multiple_cols +
2506 hwstat->tx_excessive_cols);
2507 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2508 hwstat->rx_jabbers +
2509 hwstat->rx_undersize_pkts +
2510 hwstat->rx_length_mismatch);
2511 nstat->rx_over_errors = hwstat->rx_resource_errors +
2512 hwstat->rx_overruns;
2513 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2514 nstat->rx_frame_errors = hwstat->rx_align_errors;
2515 nstat->rx_fifo_errors = hwstat->rx_overruns;
2516 /* XXX: What does "missed" mean? */
2517 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2518 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2519 nstat->tx_fifo_errors = hwstat->tx_underruns;
2520 /* Don't know about heartbeat or window errors... */
2521
2522 return nstat;
2523}
2524
2525static int macb_get_regs_len(struct net_device *netdev)
2526{
2527 return MACB_GREGS_NBR * sizeof(u32);
2528}
2529
2530static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2531 void *p)
2532{
2533 struct macb *bp = netdev_priv(dev);
2534 unsigned int tail, head;
2535 u32 *regs_buff = p;
2536
2537 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2538 | MACB_GREGS_VERSION;
2539
2540 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2541 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2542
2543 regs_buff[0] = macb_readl(bp, NCR);
2544 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2545 regs_buff[2] = macb_readl(bp, NSR);
2546 regs_buff[3] = macb_readl(bp, TSR);
2547 regs_buff[4] = macb_readl(bp, RBQP);
2548 regs_buff[5] = macb_readl(bp, TBQP);
2549 regs_buff[6] = macb_readl(bp, RSR);
2550 regs_buff[7] = macb_readl(bp, IMR);
2551
2552 regs_buff[8] = tail;
2553 regs_buff[9] = head;
2554 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2555 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2556
2557 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2558 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2559 if (macb_is_gem(bp))
2560 regs_buff[13] = gem_readl(bp, DMACFG);
2561}
2562
2563static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2564{
2565 struct macb *bp = netdev_priv(netdev);
2566
2567 wol->supported = 0;
2568 wol->wolopts = 0;
2569
2570 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2571 wol->supported = WAKE_MAGIC;
2572
2573 if (bp->wol & MACB_WOL_ENABLED)
2574 wol->wolopts |= WAKE_MAGIC;
2575 }
2576}
2577
2578static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2579{
2580 struct macb *bp = netdev_priv(netdev);
2581
2582 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2583 (wol->wolopts & ~WAKE_MAGIC))
2584 return -EOPNOTSUPP;
2585
2586 if (wol->wolopts & WAKE_MAGIC)
2587 bp->wol |= MACB_WOL_ENABLED;
2588 else
2589 bp->wol &= ~MACB_WOL_ENABLED;
2590
2591 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2592
2593 return 0;
2594}
2595
2596static void macb_get_ringparam(struct net_device *netdev,
2597 struct ethtool_ringparam *ring)
2598{
2599 struct macb *bp = netdev_priv(netdev);
2600
2601 ring->rx_max_pending = MAX_RX_RING_SIZE;
2602 ring->tx_max_pending = MAX_TX_RING_SIZE;
2603
2604 ring->rx_pending = bp->rx_ring_size;
2605 ring->tx_pending = bp->tx_ring_size;
2606}
2607
2608static int macb_set_ringparam(struct net_device *netdev,
2609 struct ethtool_ringparam *ring)
2610{
2611 struct macb *bp = netdev_priv(netdev);
2612 u32 new_rx_size, new_tx_size;
2613 unsigned int reset = 0;
2614
2615 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2616 return -EINVAL;
2617
2618 new_rx_size = clamp_t(u32, ring->rx_pending,
2619 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2620 new_rx_size = roundup_pow_of_two(new_rx_size);
2621
2622 new_tx_size = clamp_t(u32, ring->tx_pending,
2623 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2624 new_tx_size = roundup_pow_of_two(new_tx_size);
2625
2626 if ((new_tx_size == bp->tx_ring_size) &&
2627 (new_rx_size == bp->rx_ring_size)) {
2628 /* nothing to do */
2629 return 0;
2630 }
2631
2632 if (netif_running(bp->dev)) {
2633 reset = 1;
2634 macb_close(bp->dev);
2635 }
2636
2637 bp->rx_ring_size = new_rx_size;
2638 bp->tx_ring_size = new_tx_size;
2639
2640 if (reset)
2641 macb_open(bp->dev);
2642
2643 return 0;
2644}
2645
2646#ifdef CONFIG_MACB_USE_HWSTAMP
2647static unsigned int gem_get_tsu_rate(struct macb *bp)
2648{
2649 struct clk *tsu_clk;
2650 unsigned int tsu_rate;
2651
2652 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2653 if (!IS_ERR(tsu_clk))
2654 tsu_rate = clk_get_rate(tsu_clk);
2655 /* try pclk instead */
2656 else if (!IS_ERR(bp->pclk)) {
2657 tsu_clk = bp->pclk;
2658 tsu_rate = clk_get_rate(tsu_clk);
2659 } else
2660 return -ENOTSUPP;
2661 return tsu_rate;
2662}
2663
2664static s32 gem_get_ptp_max_adj(void)
2665{
2666 return 64000000;
2667}
2668
2669static int gem_get_ts_info(struct net_device *dev,
2670 struct ethtool_ts_info *info)
2671{
2672 struct macb *bp = netdev_priv(dev);
2673
2674 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2675 ethtool_op_get_ts_info(dev, info);
2676 return 0;
2677 }
2678
2679 info->so_timestamping =
2680 SOF_TIMESTAMPING_TX_SOFTWARE |
2681 SOF_TIMESTAMPING_RX_SOFTWARE |
2682 SOF_TIMESTAMPING_SOFTWARE |
2683 SOF_TIMESTAMPING_TX_HARDWARE |
2684 SOF_TIMESTAMPING_RX_HARDWARE |
2685 SOF_TIMESTAMPING_RAW_HARDWARE;
2686 info->tx_types =
2687 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2688 (1 << HWTSTAMP_TX_OFF) |
2689 (1 << HWTSTAMP_TX_ON);
2690 info->rx_filters =
2691 (1 << HWTSTAMP_FILTER_NONE) |
2692 (1 << HWTSTAMP_FILTER_ALL);
2693
2694 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2695
2696 return 0;
2697}
2698
2699static struct macb_ptp_info gem_ptp_info = {
2700 .ptp_init = gem_ptp_init,
2701 .ptp_remove = gem_ptp_remove,
2702 .get_ptp_max_adj = gem_get_ptp_max_adj,
2703 .get_tsu_rate = gem_get_tsu_rate,
2704 .get_ts_info = gem_get_ts_info,
2705 .get_hwtst = gem_get_hwtst,
2706 .set_hwtst = gem_set_hwtst,
2707};
2708#endif
2709
2710static int macb_get_ts_info(struct net_device *netdev,
2711 struct ethtool_ts_info *info)
2712{
2713 struct macb *bp = netdev_priv(netdev);
2714
2715 if (bp->ptp_info)
2716 return bp->ptp_info->get_ts_info(netdev, info);
2717
2718 return ethtool_op_get_ts_info(netdev, info);
2719}
2720
2721static void gem_enable_flow_filters(struct macb *bp, bool enable)
2722{
2723 struct ethtool_rx_fs_item *item;
2724 u32 t2_scr;
2725 int num_t2_scr;
2726
2727 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2728
2729 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2730 struct ethtool_rx_flow_spec *fs = &item->fs;
2731 struct ethtool_tcpip4_spec *tp4sp_m;
2732
2733 if (fs->location >= num_t2_scr)
2734 continue;
2735
2736 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2737
2738 /* enable/disable screener regs for the flow entry */
2739 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2740
2741 /* only enable fields with no masking */
2742 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2743
2744 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2745 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2746 else
2747 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2748
2749 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2750 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2751 else
2752 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2753
2754 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
2755 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
2756 else
2757 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
2758
2759 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
2760 }
2761}
2762
2763static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
2764{
2765 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
2766 uint16_t index = fs->location;
2767 u32 w0, w1, t2_scr;
2768 bool cmp_a = false;
2769 bool cmp_b = false;
2770 bool cmp_c = false;
2771
2772 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
2773 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2774
2775 /* ignore field if any masking set */
2776 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
2777 /* 1st compare reg - IP source address */
2778 w0 = 0;
2779 w1 = 0;
2780 w0 = tp4sp_v->ip4src;
2781 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2782 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2783 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
2784 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
2785 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
2786 cmp_a = true;
2787 }
2788
2789 /* ignore field if any masking set */
2790 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
2791 /* 2nd compare reg - IP destination address */
2792 w0 = 0;
2793 w1 = 0;
2794 w0 = tp4sp_v->ip4dst;
2795 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2796 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2797 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
2798 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
2799 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
2800 cmp_b = true;
2801 }
2802
2803 /* ignore both port fields if masking set in both */
2804 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
2805 /* 3rd compare reg - source port, destination port */
2806 w0 = 0;
2807 w1 = 0;
2808 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
2809 if (tp4sp_m->psrc == tp4sp_m->pdst) {
2810 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
2811 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2812 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2813 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2814 } else {
2815 /* only one port definition */
2816 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
2817 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
2818 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
2819 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
2820 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2821 } else { /* dst port */
2822 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2823 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
2824 }
2825 }
2826 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
2827 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
2828 cmp_c = true;
2829 }
2830
2831 t2_scr = 0;
2832 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
2833 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
2834 if (cmp_a)
2835 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
2836 if (cmp_b)
2837 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
2838 if (cmp_c)
2839 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
2840 gem_writel_n(bp, SCRT2, index, t2_scr);
2841}
2842
2843static int gem_add_flow_filter(struct net_device *netdev,
2844 struct ethtool_rxnfc *cmd)
2845{
2846 struct macb *bp = netdev_priv(netdev);
2847 struct ethtool_rx_flow_spec *fs = &cmd->fs;
2848 struct ethtool_rx_fs_item *item, *newfs;
2849 unsigned long flags;
2850 int ret = -EINVAL;
2851 bool added = false;
2852
2853 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
2854 if (newfs == NULL)
2855 return -ENOMEM;
2856 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
2857
2858 netdev_dbg(netdev,
2859 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
2860 fs->flow_type, (int)fs->ring_cookie, fs->location,
2861 htonl(fs->h_u.tcp_ip4_spec.ip4src),
2862 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
2863 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
2864
2865 spin_lock_irqsave(&bp->rx_fs_lock, flags);
2866
2867 /* find correct place to add in list */
2868 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2869 if (item->fs.location > newfs->fs.location) {
2870 list_add_tail(&newfs->list, &item->list);
2871 added = true;
2872 break;
2873 } else if (item->fs.location == fs->location) {
2874 netdev_err(netdev, "Rule not added: location %d not free!\n",
2875 fs->location);
2876 ret = -EBUSY;
2877 goto err;
2878 }
2879 }
2880 if (!added)
2881 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
2882
2883 gem_prog_cmp_regs(bp, fs);
2884 bp->rx_fs_list.count++;
2885 /* enable filtering if NTUPLE on */
2886 if (netdev->features & NETIF_F_NTUPLE)
2887 gem_enable_flow_filters(bp, 1);
2888
2889 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
2890 return 0;
2891
2892err:
2893 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
2894 kfree(newfs);
2895 return ret;
2896}
2897
2898static int gem_del_flow_filter(struct net_device *netdev,
2899 struct ethtool_rxnfc *cmd)
2900{
2901 struct macb *bp = netdev_priv(netdev);
2902 struct ethtool_rx_fs_item *item;
2903 struct ethtool_rx_flow_spec *fs;
2904 unsigned long flags;
2905
2906 spin_lock_irqsave(&bp->rx_fs_lock, flags);
2907
2908 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2909 if (item->fs.location == cmd->fs.location) {
2910 /* disable screener regs for the flow entry */
2911 fs = &(item->fs);
2912 netdev_dbg(netdev,
2913 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
2914 fs->flow_type, (int)fs->ring_cookie, fs->location,
2915 htonl(fs->h_u.tcp_ip4_spec.ip4src),
2916 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
2917 htons(fs->h_u.tcp_ip4_spec.psrc),
2918 htons(fs->h_u.tcp_ip4_spec.pdst));
2919
2920 gem_writel_n(bp, SCRT2, fs->location, 0);
2921
2922 list_del(&item->list);
2923 bp->rx_fs_list.count--;
2924 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
2925 kfree(item);
2926 return 0;
2927 }
2928 }
2929
2930 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
2931 return -EINVAL;
2932}
2933
2934static int gem_get_flow_entry(struct net_device *netdev,
2935 struct ethtool_rxnfc *cmd)
2936{
2937 struct macb *bp = netdev_priv(netdev);
2938 struct ethtool_rx_fs_item *item;
2939
2940 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2941 if (item->fs.location == cmd->fs.location) {
2942 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
2943 return 0;
2944 }
2945 }
2946 return -EINVAL;
2947}
2948
2949static int gem_get_all_flow_entries(struct net_device *netdev,
2950 struct ethtool_rxnfc *cmd, u32 *rule_locs)
2951{
2952 struct macb *bp = netdev_priv(netdev);
2953 struct ethtool_rx_fs_item *item;
2954 uint32_t cnt = 0;
2955
2956 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2957 if (cnt == cmd->rule_cnt)
2958 return -EMSGSIZE;
2959 rule_locs[cnt] = item->fs.location;
2960 cnt++;
2961 }
2962 cmd->data = bp->max_tuples;
2963 cmd->rule_cnt = cnt;
2964
2965 return 0;
2966}
2967
2968static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
2969 u32 *rule_locs)
2970{
2971 struct macb *bp = netdev_priv(netdev);
2972 int ret = 0;
2973
2974 switch (cmd->cmd) {
2975 case ETHTOOL_GRXRINGS:
2976 cmd->data = bp->num_queues;
2977 break;
2978 case ETHTOOL_GRXCLSRLCNT:
2979 cmd->rule_cnt = bp->rx_fs_list.count;
2980 break;
2981 case ETHTOOL_GRXCLSRULE:
2982 ret = gem_get_flow_entry(netdev, cmd);
2983 break;
2984 case ETHTOOL_GRXCLSRLALL:
2985 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
2986 break;
2987 default:
2988 netdev_err(netdev,
2989 "Command parameter %d is not supported\n", cmd->cmd);
2990 ret = -EOPNOTSUPP;
2991 }
2992
2993 return ret;
2994}
2995
2996static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
2997{
2998 struct macb *bp = netdev_priv(netdev);
2999 int ret;
3000
3001 switch (cmd->cmd) {
3002 case ETHTOOL_SRXCLSRLINS:
3003 if ((cmd->fs.location >= bp->max_tuples)
3004 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3005 ret = -EINVAL;
3006 break;
3007 }
3008 ret = gem_add_flow_filter(netdev, cmd);
3009 break;
3010 case ETHTOOL_SRXCLSRLDEL:
3011 ret = gem_del_flow_filter(netdev, cmd);
3012 break;
3013 default:
3014 netdev_err(netdev,
3015 "Command parameter %d is not supported\n", cmd->cmd);
3016 ret = -EOPNOTSUPP;
3017 }
3018
3019 return ret;
3020}
3021
3022static const struct ethtool_ops macb_ethtool_ops = {
3023 .get_regs_len = macb_get_regs_len,
3024 .get_regs = macb_get_regs,
3025 .get_link = ethtool_op_get_link,
3026 .get_ts_info = ethtool_op_get_ts_info,
3027 .get_wol = macb_get_wol,
3028 .set_wol = macb_set_wol,
3029 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3030 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3031 .get_ringparam = macb_get_ringparam,
3032 .set_ringparam = macb_set_ringparam,
3033};
3034
3035static const struct ethtool_ops gem_ethtool_ops = {
3036 .get_regs_len = macb_get_regs_len,
3037 .get_regs = macb_get_regs,
3038 .get_link = ethtool_op_get_link,
3039 .get_ts_info = macb_get_ts_info,
3040 .get_ethtool_stats = gem_get_ethtool_stats,
3041 .get_strings = gem_get_ethtool_strings,
3042 .get_sset_count = gem_get_sset_count,
3043 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3044 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3045 .get_ringparam = macb_get_ringparam,
3046 .set_ringparam = macb_set_ringparam,
3047 .get_rxnfc = gem_get_rxnfc,
3048 .set_rxnfc = gem_set_rxnfc,
3049};
3050
3051static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3052{
3053 struct phy_device *phydev = dev->phydev;
3054 struct macb *bp = netdev_priv(dev);
3055
3056 if (!netif_running(dev))
3057 return -EINVAL;
3058
3059 if (!phydev)
3060 return -ENODEV;
3061
3062 if (!bp->ptp_info)
3063 return phy_mii_ioctl(phydev, rq, cmd);
3064
3065 switch (cmd) {
3066 case SIOCSHWTSTAMP:
3067 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3068 case SIOCGHWTSTAMP:
3069 return bp->ptp_info->get_hwtst(dev, rq);
3070 default:
3071 return phy_mii_ioctl(phydev, rq, cmd);
3072 }
3073}
3074
3075static int macb_set_features(struct net_device *netdev,
3076 netdev_features_t features)
3077{
3078 struct macb *bp = netdev_priv(netdev);
3079 netdev_features_t changed = features ^ netdev->features;
3080
3081 /* TX checksum offload */
3082 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
3083 u32 dmacfg;
3084
3085 dmacfg = gem_readl(bp, DMACFG);
3086 if (features & NETIF_F_HW_CSUM)
3087 dmacfg |= GEM_BIT(TXCOEN);
3088 else
3089 dmacfg &= ~GEM_BIT(TXCOEN);
3090 gem_writel(bp, DMACFG, dmacfg);
3091 }
3092
3093 /* RX checksum offload */
3094 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
3095 u32 netcfg;
3096
3097 netcfg = gem_readl(bp, NCFGR);
3098 if (features & NETIF_F_RXCSUM &&
3099 !(netdev->flags & IFF_PROMISC))
3100 netcfg |= GEM_BIT(RXCOEN);
3101 else
3102 netcfg &= ~GEM_BIT(RXCOEN);
3103 gem_writel(bp, NCFGR, netcfg);
3104 }
3105
3106 /* RX Flow Filters */
3107 if ((changed & NETIF_F_NTUPLE) && macb_is_gem(bp)) {
3108 bool turn_on = features & NETIF_F_NTUPLE;
3109
3110 gem_enable_flow_filters(bp, turn_on);
3111 }
3112 return 0;
3113}
3114
3115static const struct net_device_ops macb_netdev_ops = {
3116 .ndo_open = macb_open,
3117 .ndo_stop = macb_close,
3118 .ndo_start_xmit = macb_start_xmit,
3119 .ndo_set_rx_mode = macb_set_rx_mode,
3120 .ndo_get_stats = macb_get_stats,
3121 .ndo_do_ioctl = macb_ioctl,
3122 .ndo_validate_addr = eth_validate_addr,
3123 .ndo_change_mtu = macb_change_mtu,
3124 .ndo_set_mac_address = eth_mac_addr,
3125#ifdef CONFIG_NET_POLL_CONTROLLER
3126 .ndo_poll_controller = macb_poll_controller,
3127#endif
3128 .ndo_set_features = macb_set_features,
3129 .ndo_features_check = macb_features_check,
3130};
3131
3132/* Configure peripheral capabilities according to device tree
3133 * and integration options used
3134 */
3135static void macb_configure_caps(struct macb *bp,
3136 const struct macb_config *dt_conf)
3137{
3138 u32 dcfg;
3139
3140 if (dt_conf)
3141 bp->caps = dt_conf->caps;
3142
3143 if (hw_is_gem(bp->regs, bp->native_io)) {
3144 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3145
3146 dcfg = gem_readl(bp, DCFG1);
3147 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3148 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3149 dcfg = gem_readl(bp, DCFG2);
3150 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3151 bp->caps |= MACB_CAPS_FIFO_MODE;
3152#ifdef CONFIG_MACB_USE_HWSTAMP
3153 if (gem_has_ptp(bp)) {
3154 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3155 pr_err("GEM doesn't support hardware ptp.\n");
3156 else {
3157 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3158 bp->ptp_info = &gem_ptp_info;
3159 }
3160 }
3161#endif
3162 }
3163
3164 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3165}
3166
3167static void macb_probe_queues(void __iomem *mem,
3168 bool native_io,
3169 unsigned int *queue_mask,
3170 unsigned int *num_queues)
3171{
3172 unsigned int hw_q;
3173
3174 *queue_mask = 0x1;
3175 *num_queues = 1;
3176
3177 /* is it macb or gem ?
3178 *
3179 * We need to read directly from the hardware here because
3180 * we are early in the probe process and don't have the
3181 * MACB_CAPS_MACB_IS_GEM flag positioned
3182 */
3183 if (!hw_is_gem(mem, native_io))
3184 return;
3185
3186 /* bit 0 is never set but queue 0 always exists */
3187 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3188
3189 *queue_mask |= 0x1;
3190
3191 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3192 if (*queue_mask & (1 << hw_q))
3193 (*num_queues)++;
3194}
3195
3196static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3197 struct clk **hclk, struct clk **tx_clk,
3198 struct clk **rx_clk)
3199{
3200 struct macb_platform_data *pdata;
3201 int err;
3202
3203 pdata = dev_get_platdata(&pdev->dev);
3204 if (pdata) {
3205 *pclk = pdata->pclk;
3206 *hclk = pdata->hclk;
3207 } else {
3208 *pclk = devm_clk_get(&pdev->dev, "pclk");
3209 *hclk = devm_clk_get(&pdev->dev, "hclk");
3210 }
3211
3212 if (IS_ERR(*pclk)) {
3213 err = PTR_ERR(*pclk);
3214 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
3215 return err;
3216 }
3217
3218 if (IS_ERR(*hclk)) {
3219 err = PTR_ERR(*hclk);
3220 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
3221 return err;
3222 }
3223
3224 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
3225 if (IS_ERR(*tx_clk))
3226 *tx_clk = NULL;
3227
3228 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
3229 if (IS_ERR(*rx_clk))
3230 *rx_clk = NULL;
3231
3232 err = clk_prepare_enable(*pclk);
3233 if (err) {
3234 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3235 return err;
3236 }
3237
3238 err = clk_prepare_enable(*hclk);
3239 if (err) {
3240 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
3241 goto err_disable_pclk;
3242 }
3243
3244 err = clk_prepare_enable(*tx_clk);
3245 if (err) {
3246 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
3247 goto err_disable_hclk;
3248 }
3249
3250 err = clk_prepare_enable(*rx_clk);
3251 if (err) {
3252 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
3253 goto err_disable_txclk;
3254 }
3255
3256 return 0;
3257
3258err_disable_txclk:
3259 clk_disable_unprepare(*tx_clk);
3260
3261err_disable_hclk:
3262 clk_disable_unprepare(*hclk);
3263
3264err_disable_pclk:
3265 clk_disable_unprepare(*pclk);
3266
3267 return err;
3268}
3269
3270static int macb_init(struct platform_device *pdev)
3271{
3272 struct net_device *dev = platform_get_drvdata(pdev);
3273 unsigned int hw_q, q;
3274 struct macb *bp = netdev_priv(dev);
3275 struct macb_queue *queue;
3276 int err;
3277 u32 val, reg;
3278
3279 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3280 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3281
3282 /* set the queue register mapping once for all: queue0 has a special
3283 * register mapping but we don't want to test the queue index then
3284 * compute the corresponding register offset at run time.
3285 */
3286 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3287 if (!(bp->queue_mask & (1 << hw_q)))
3288 continue;
3289
3290 queue = &bp->queues[q];
3291 queue->bp = bp;
3292 netif_napi_add(dev, &queue->napi, macb_poll, 64);
3293 if (hw_q) {
3294 queue->ISR = GEM_ISR(hw_q - 1);
3295 queue->IER = GEM_IER(hw_q - 1);
3296 queue->IDR = GEM_IDR(hw_q - 1);
3297 queue->IMR = GEM_IMR(hw_q - 1);
3298 queue->TBQP = GEM_TBQP(hw_q - 1);
3299 queue->RBQP = GEM_RBQP(hw_q - 1);
3300 queue->RBQS = GEM_RBQS(hw_q - 1);
3301#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3302 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3303 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3304 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3305 }
3306#endif
3307 } else {
3308 /* queue0 uses legacy registers */
3309 queue->ISR = MACB_ISR;
3310 queue->IER = MACB_IER;
3311 queue->IDR = MACB_IDR;
3312 queue->IMR = MACB_IMR;
3313 queue->TBQP = MACB_TBQP;
3314 queue->RBQP = MACB_RBQP;
3315#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3316 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3317 queue->TBQPH = MACB_TBQPH;
3318 queue->RBQPH = MACB_RBQPH;
3319 }
3320#endif
3321 }
3322
3323 /* get irq: here we use the linux queue index, not the hardware
3324 * queue index. the queue irq definitions in the device tree
3325 * must remove the optional gaps that could exist in the
3326 * hardware queue mask.
3327 */
3328 queue->irq = platform_get_irq(pdev, q);
3329 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3330 IRQF_SHARED, dev->name, queue);
3331 if (err) {
3332 dev_err(&pdev->dev,
3333 "Unable to request IRQ %d (error %d)\n",
3334 queue->irq, err);
3335 return err;
3336 }
3337
3338 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3339 q++;
3340 }
3341
3342 dev->netdev_ops = &macb_netdev_ops;
3343
3344 /* setup appropriated routines according to adapter type */
3345 if (macb_is_gem(bp)) {
3346 bp->max_tx_length = GEM_MAX_TX_LEN;
3347 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3348 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3349 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3350 bp->macbgem_ops.mog_rx = gem_rx;
3351 dev->ethtool_ops = &gem_ethtool_ops;
3352 } else {
3353 bp->max_tx_length = MACB_MAX_TX_LEN;
3354 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3355 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3356 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3357 bp->macbgem_ops.mog_rx = macb_rx;
3358 dev->ethtool_ops = &macb_ethtool_ops;
3359 }
3360
3361 /* Set features */
3362 dev->hw_features = NETIF_F_SG;
3363
3364 /* Check LSO capability */
3365 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3366 dev->hw_features |= MACB_NETIF_LSO;
3367
3368 /* Checksum offload is only available on gem with packet buffer */
3369 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3370 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3371 if (bp->caps & MACB_CAPS_SG_DISABLED)
3372 dev->hw_features &= ~NETIF_F_SG;
3373 dev->features = dev->hw_features;
3374
3375 /* Check RX Flow Filters support.
3376 * Max Rx flows set by availability of screeners & compare regs:
3377 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3378 */
3379 reg = gem_readl(bp, DCFG8);
3380 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3381 GEM_BFEXT(T2SCR, reg));
3382 if (bp->max_tuples > 0) {
3383 /* also needs one ethtype match to check IPv4 */
3384 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3385 /* program this reg now */
3386 reg = 0;
3387 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3388 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3389 /* Filtering is supported in hw but don't enable it in kernel now */
3390 dev->hw_features |= NETIF_F_NTUPLE;
3391 /* init Rx flow definitions */
3392 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3393 bp->rx_fs_list.count = 0;
3394 spin_lock_init(&bp->rx_fs_lock);
3395 } else
3396 bp->max_tuples = 0;
3397 }
3398
3399 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3400 val = 0;
3401 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3402 val = GEM_BIT(RGMII);
3403 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3404 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3405 val = MACB_BIT(RMII);
3406 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3407 val = MACB_BIT(MII);
3408
3409 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3410 val |= MACB_BIT(CLKEN);
3411
3412 macb_or_gem_writel(bp, USRIO, val);
3413 }
3414
3415 /* Set MII management clock divider */
3416 val = macb_mdc_clk_div(bp);
3417 val |= macb_dbw(bp);
3418 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3419 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3420 macb_writel(bp, NCFGR, val);
3421
3422 return 0;
3423}
3424
3425#if defined(CONFIG_OF)
3426/* 1518 rounded up */
3427#define AT91ETHER_MAX_RBUFF_SZ 0x600
3428/* max number of receive buffers */
3429#define AT91ETHER_MAX_RX_DESCR 9
3430
3431/* Initialize and start the Receiver and Transmit subsystems */
3432static int at91ether_start(struct net_device *dev)
3433{
3434 struct macb *lp = netdev_priv(dev);
3435 struct macb_queue *q = &lp->queues[0];
3436 struct macb_dma_desc *desc;
3437 dma_addr_t addr;
3438 u32 ctl;
3439 int i;
3440
3441 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3442 (AT91ETHER_MAX_RX_DESCR *
3443 macb_dma_desc_get_size(lp)),
3444 &q->rx_ring_dma, GFP_KERNEL);
3445 if (!q->rx_ring)
3446 return -ENOMEM;
3447
3448 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3449 AT91ETHER_MAX_RX_DESCR *
3450 AT91ETHER_MAX_RBUFF_SZ,
3451 &q->rx_buffers_dma, GFP_KERNEL);
3452 if (!q->rx_buffers) {
3453 dma_free_coherent(&lp->pdev->dev,
3454 AT91ETHER_MAX_RX_DESCR *
3455 macb_dma_desc_get_size(lp),
3456 q->rx_ring, q->rx_ring_dma);
3457 q->rx_ring = NULL;
3458 return -ENOMEM;
3459 }
3460
3461 addr = q->rx_buffers_dma;
3462 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3463 desc = macb_rx_desc(q, i);
3464 macb_set_addr(lp, desc, addr);
3465 desc->ctrl = 0;
3466 addr += AT91ETHER_MAX_RBUFF_SZ;
3467 }
3468
3469 /* Set the Wrap bit on the last descriptor */
3470 desc->addr |= MACB_BIT(RX_WRAP);
3471
3472 /* Reset buffer index */
3473 q->rx_tail = 0;
3474
3475 /* Program address of descriptor list in Rx Buffer Queue register */
3476 macb_writel(lp, RBQP, q->rx_ring_dma);
3477
3478 /* Enable Receive and Transmit */
3479 ctl = macb_readl(lp, NCR);
3480 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3481
3482 return 0;
3483}
3484
3485/* Open the ethernet interface */
3486static int at91ether_open(struct net_device *dev)
3487{
3488 struct macb *lp = netdev_priv(dev);
3489 u32 ctl;
3490 int ret;
3491
3492 /* Clear internal statistics */
3493 ctl = macb_readl(lp, NCR);
3494 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3495
3496 macb_set_hwaddr(lp);
3497
3498 ret = at91ether_start(dev);
3499 if (ret)
3500 return ret;
3501
3502 /* Enable MAC interrupts */
3503 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3504 MACB_BIT(RXUBR) |
3505 MACB_BIT(ISR_TUND) |
3506 MACB_BIT(ISR_RLE) |
3507 MACB_BIT(TCOMP) |
3508 MACB_BIT(ISR_ROVR) |
3509 MACB_BIT(HRESP));
3510
3511 /* schedule a link state check */
3512 phy_start(dev->phydev);
3513
3514 netif_start_queue(dev);
3515
3516 return 0;
3517}
3518
3519/* Close the interface */
3520static int at91ether_close(struct net_device *dev)
3521{
3522 struct macb *lp = netdev_priv(dev);
3523 struct macb_queue *q = &lp->queues[0];
3524 u32 ctl;
3525
3526 /* Disable Receiver and Transmitter */
3527 ctl = macb_readl(lp, NCR);
3528 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3529
3530 /* Disable MAC interrupts */
3531 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3532 MACB_BIT(RXUBR) |
3533 MACB_BIT(ISR_TUND) |
3534 MACB_BIT(ISR_RLE) |
3535 MACB_BIT(TCOMP) |
3536 MACB_BIT(ISR_ROVR) |
3537 MACB_BIT(HRESP));
3538
3539 netif_stop_queue(dev);
3540
3541 dma_free_coherent(&lp->pdev->dev,
3542 AT91ETHER_MAX_RX_DESCR *
3543 macb_dma_desc_get_size(lp),
3544 q->rx_ring, q->rx_ring_dma);
3545 q->rx_ring = NULL;
3546
3547 dma_free_coherent(&lp->pdev->dev,
3548 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3549 q->rx_buffers, q->rx_buffers_dma);
3550 q->rx_buffers = NULL;
3551
3552 return 0;
3553}
3554
3555/* Transmit packet */
3556static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
3557{
3558 struct macb *lp = netdev_priv(dev);
3559
3560 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3561 netif_stop_queue(dev);
3562
3563 /* Store packet information (to free when Tx completed) */
3564 lp->skb = skb;
3565 lp->skb_length = skb->len;
3566 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3567 DMA_TO_DEVICE);
3568 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3569 dev_kfree_skb_any(skb);
3570 dev->stats.tx_dropped++;
3571 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3572 return NETDEV_TX_OK;
3573 }
3574
3575 /* Set address of the data in the Transmit Address register */
3576 macb_writel(lp, TAR, lp->skb_physaddr);
3577 /* Set length of the packet in the Transmit Control register */
3578 macb_writel(lp, TCR, skb->len);
3579
3580 } else {
3581 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3582 return NETDEV_TX_BUSY;
3583 }
3584
3585 return NETDEV_TX_OK;
3586}
3587
3588/* Extract received frame from buffer descriptors and sent to upper layers.
3589 * (Called from interrupt context)
3590 */
3591static void at91ether_rx(struct net_device *dev)
3592{
3593 struct macb *lp = netdev_priv(dev);
3594 struct macb_queue *q = &lp->queues[0];
3595 struct macb_dma_desc *desc;
3596 unsigned char *p_recv;
3597 struct sk_buff *skb;
3598 unsigned int pktlen;
3599
3600 desc = macb_rx_desc(q, q->rx_tail);
3601 while (desc->addr & MACB_BIT(RX_USED)) {
3602 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3603 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3604 skb = netdev_alloc_skb(dev, pktlen + 2);
3605 if (skb) {
3606 skb_reserve(skb, 2);
3607 skb_put_data(skb, p_recv, pktlen);
3608
3609 skb->protocol = eth_type_trans(skb, dev);
3610 dev->stats.rx_packets++;
3611 dev->stats.rx_bytes += pktlen;
3612 netif_rx(skb);
3613 } else {
3614 dev->stats.rx_dropped++;
3615 }
3616
3617 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3618 dev->stats.multicast++;
3619
3620 /* reset ownership bit */
3621 desc->addr &= ~MACB_BIT(RX_USED);
3622
3623 /* wrap after last buffer */
3624 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3625 q->rx_tail = 0;
3626 else
3627 q->rx_tail++;
3628
3629 desc = macb_rx_desc(q, q->rx_tail);
3630 }
3631}
3632
3633/* MAC interrupt handler */
3634static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3635{
3636 struct net_device *dev = dev_id;
3637 struct macb *lp = netdev_priv(dev);
3638 u32 intstatus, ctl;
3639
3640 /* MAC Interrupt Status register indicates what interrupts are pending.
3641 * It is automatically cleared once read.
3642 */
3643 intstatus = macb_readl(lp, ISR);
3644
3645 /* Receive complete */
3646 if (intstatus & MACB_BIT(RCOMP))
3647 at91ether_rx(dev);
3648
3649 /* Transmit complete */
3650 if (intstatus & MACB_BIT(TCOMP)) {
3651 /* The TCOM bit is set even if the transmission failed */
3652 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3653 dev->stats.tx_errors++;
3654
3655 if (lp->skb) {
3656 dev_kfree_skb_irq(lp->skb);
3657 lp->skb = NULL;
3658 dma_unmap_single(NULL, lp->skb_physaddr,
3659 lp->skb_length, DMA_TO_DEVICE);
3660 dev->stats.tx_packets++;
3661 dev->stats.tx_bytes += lp->skb_length;
3662 }
3663 netif_wake_queue(dev);
3664 }
3665
3666 /* Work-around for EMAC Errata section 41.3.1 */
3667 if (intstatus & MACB_BIT(RXUBR)) {
3668 ctl = macb_readl(lp, NCR);
3669 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3670 wmb();
3671 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3672 }
3673
3674 if (intstatus & MACB_BIT(ISR_ROVR))
3675 netdev_err(dev, "ROVR error\n");
3676
3677 return IRQ_HANDLED;
3678}
3679
3680#ifdef CONFIG_NET_POLL_CONTROLLER
3681static void at91ether_poll_controller(struct net_device *dev)
3682{
3683 unsigned long flags;
3684
3685 local_irq_save(flags);
3686 at91ether_interrupt(dev->irq, dev);
3687 local_irq_restore(flags);
3688}
3689#endif
3690
3691static const struct net_device_ops at91ether_netdev_ops = {
3692 .ndo_open = at91ether_open,
3693 .ndo_stop = at91ether_close,
3694 .ndo_start_xmit = at91ether_start_xmit,
3695 .ndo_get_stats = macb_get_stats,
3696 .ndo_set_rx_mode = macb_set_rx_mode,
3697 .ndo_set_mac_address = eth_mac_addr,
3698 .ndo_do_ioctl = macb_ioctl,
3699 .ndo_validate_addr = eth_validate_addr,
3700#ifdef CONFIG_NET_POLL_CONTROLLER
3701 .ndo_poll_controller = at91ether_poll_controller,
3702#endif
3703};
3704
3705static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3706 struct clk **hclk, struct clk **tx_clk,
3707 struct clk **rx_clk)
3708{
3709 int err;
3710
3711 *hclk = NULL;
3712 *tx_clk = NULL;
3713 *rx_clk = NULL;
3714
3715 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3716 if (IS_ERR(*pclk))
3717 return PTR_ERR(*pclk);
3718
3719 err = clk_prepare_enable(*pclk);
3720 if (err) {
3721 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3722 return err;
3723 }
3724
3725 return 0;
3726}
3727
3728static int at91ether_init(struct platform_device *pdev)
3729{
3730 struct net_device *dev = platform_get_drvdata(pdev);
3731 struct macb *bp = netdev_priv(dev);
3732 int err;
3733 u32 reg;
3734
3735 dev->netdev_ops = &at91ether_netdev_ops;
3736 dev->ethtool_ops = &macb_ethtool_ops;
3737
3738 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3739 0, dev->name, dev);
3740 if (err)
3741 return err;
3742
3743 macb_writel(bp, NCR, 0);
3744
3745 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3746 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3747 reg |= MACB_BIT(RM9200_RMII);
3748
3749 macb_writel(bp, NCFGR, reg);
3750
3751 return 0;
3752}
3753
3754static const struct macb_config at91sam9260_config = {
3755 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3756 .clk_init = macb_clk_init,
3757 .init = macb_init,
3758};
3759
3760static const struct macb_config pc302gem_config = {
3761 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3762 .dma_burst_length = 16,
3763 .clk_init = macb_clk_init,
3764 .init = macb_init,
3765};
3766
3767static const struct macb_config sama5d2_config = {
3768 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3769 .dma_burst_length = 16,
3770 .clk_init = macb_clk_init,
3771 .init = macb_init,
3772};
3773
3774static const struct macb_config sama5d3_config = {
3775 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3776 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3777 .dma_burst_length = 16,
3778 .clk_init = macb_clk_init,
3779 .init = macb_init,
3780 .jumbo_max_len = 10240,
3781};
3782
3783static const struct macb_config sama5d4_config = {
3784 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3785 .dma_burst_length = 4,
3786 .clk_init = macb_clk_init,
3787 .init = macb_init,
3788};
3789
3790static const struct macb_config emac_config = {
3791 .clk_init = at91ether_clk_init,
3792 .init = at91ether_init,
3793};
3794
3795static const struct macb_config np4_config = {
3796 .caps = MACB_CAPS_USRIO_DISABLED,
3797 .clk_init = macb_clk_init,
3798 .init = macb_init,
3799};
3800
3801static const struct macb_config zynqmp_config = {
3802 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3803 MACB_CAPS_JUMBO |
3804 MACB_CAPS_GEM_HAS_PTP,
3805 .dma_burst_length = 16,
3806 .clk_init = macb_clk_init,
3807 .init = macb_init,
3808 .jumbo_max_len = 10240,
3809};
3810
3811static const struct macb_config zynq_config = {
3812 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
3813 .dma_burst_length = 16,
3814 .clk_init = macb_clk_init,
3815 .init = macb_init,
3816};
3817
3818static const struct of_device_id macb_dt_ids[] = {
3819 { .compatible = "cdns,at32ap7000-macb" },
3820 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3821 { .compatible = "cdns,macb" },
3822 { .compatible = "cdns,np4-macb", .data = &np4_config },
3823 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3824 { .compatible = "cdns,gem", .data = &pc302gem_config },
3825 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3826 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3827 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3828 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3829 { .compatible = "cdns,emac", .data = &emac_config },
3830 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
3831 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
3832 { /* sentinel */ }
3833};
3834MODULE_DEVICE_TABLE(of, macb_dt_ids);
3835#endif /* CONFIG_OF */
3836
3837static const struct macb_config default_gem_config = {
3838 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3839 MACB_CAPS_JUMBO |
3840 MACB_CAPS_GEM_HAS_PTP,
3841 .dma_burst_length = 16,
3842 .clk_init = macb_clk_init,
3843 .init = macb_init,
3844 .jumbo_max_len = 10240,
3845};
3846
3847static int macb_probe(struct platform_device *pdev)
3848{
3849 const struct macb_config *macb_config = &default_gem_config;
3850 int (*clk_init)(struct platform_device *, struct clk **,
3851 struct clk **, struct clk **, struct clk **)
3852 = macb_config->clk_init;
3853 int (*init)(struct platform_device *) = macb_config->init;
3854 struct device_node *np = pdev->dev.of_node;
3855 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
3856 unsigned int queue_mask, num_queues;
3857 struct macb_platform_data *pdata;
3858 bool native_io;
3859 struct phy_device *phydev;
3860 struct net_device *dev;
3861 struct resource *regs;
3862 void __iomem *mem;
3863 const char *mac;
3864 struct macb *bp;
3865 int err;
3866
3867 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3868 mem = devm_ioremap_resource(&pdev->dev, regs);
3869 if (IS_ERR(mem))
3870 return PTR_ERR(mem);
3871
3872 if (np) {
3873 const struct of_device_id *match;
3874
3875 match = of_match_node(macb_dt_ids, np);
3876 if (match && match->data) {
3877 macb_config = match->data;
3878 clk_init = macb_config->clk_init;
3879 init = macb_config->init;
3880 }
3881 }
3882
3883 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
3884 if (err)
3885 return err;
3886
3887 native_io = hw_is_native_io(mem);
3888
3889 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
3890 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
3891 if (!dev) {
3892 err = -ENOMEM;
3893 goto err_disable_clocks;
3894 }
3895
3896 dev->base_addr = regs->start;
3897
3898 SET_NETDEV_DEV(dev, &pdev->dev);
3899
3900 bp = netdev_priv(dev);
3901 bp->pdev = pdev;
3902 bp->dev = dev;
3903 bp->regs = mem;
3904 bp->native_io = native_io;
3905 if (native_io) {
3906 bp->macb_reg_readl = hw_readl_native;
3907 bp->macb_reg_writel = hw_writel_native;
3908 } else {
3909 bp->macb_reg_readl = hw_readl;
3910 bp->macb_reg_writel = hw_writel;
3911 }
3912 bp->num_queues = num_queues;
3913 bp->queue_mask = queue_mask;
3914 if (macb_config)
3915 bp->dma_burst_length = macb_config->dma_burst_length;
3916 bp->pclk = pclk;
3917 bp->hclk = hclk;
3918 bp->tx_clk = tx_clk;
3919 bp->rx_clk = rx_clk;
3920 if (macb_config)
3921 bp->jumbo_max_len = macb_config->jumbo_max_len;
3922
3923 bp->wol = 0;
3924 if (of_get_property(np, "magic-packet", NULL))
3925 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
3926 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
3927
3928 spin_lock_init(&bp->lock);
3929
3930 /* setup capabilities */
3931 macb_configure_caps(bp, macb_config);
3932
3933#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3934 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
3935 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
3936 bp->hw_dma_cap |= HW_DMA_CAP_64B;
3937 }
3938#endif
3939 platform_set_drvdata(pdev, dev);
3940
3941 dev->irq = platform_get_irq(pdev, 0);
3942 if (dev->irq < 0) {
3943 err = dev->irq;
3944 goto err_out_free_netdev;
3945 }
3946
3947 /* MTU range: 68 - 1500 or 10240 */
3948 dev->min_mtu = GEM_MTU_MIN_SIZE;
3949 if (bp->caps & MACB_CAPS_JUMBO)
3950 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
3951 else
3952 dev->max_mtu = ETH_DATA_LEN;
3953
3954 mac = of_get_mac_address(np);
3955 if (mac) {
3956 ether_addr_copy(bp->dev->dev_addr, mac);
3957 } else {
3958 err = of_get_nvmem_mac_address(np, bp->dev->dev_addr);
3959 if (err) {
3960 if (err == -EPROBE_DEFER)
3961 goto err_out_free_netdev;
3962 macb_get_hwaddr(bp);
3963 }
3964 }
3965
3966 err = of_get_phy_mode(np);
3967 if (err < 0) {
3968 pdata = dev_get_platdata(&pdev->dev);
3969 if (pdata && pdata->is_rmii)
3970 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
3971 else
3972 bp->phy_interface = PHY_INTERFACE_MODE_MII;
3973 } else {
3974 bp->phy_interface = err;
3975 }
3976
3977 /* IP specific init */
3978 err = init(pdev);
3979 if (err)
3980 goto err_out_free_netdev;
3981
3982 err = macb_mii_init(bp);
3983 if (err)
3984 goto err_out_free_netdev;
3985
3986 phydev = dev->phydev;
3987
3988 netif_carrier_off(dev);
3989
3990 err = register_netdev(dev);
3991 if (err) {
3992 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
3993 goto err_out_unregister_mdio;
3994 }
3995
3996 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
3997 (unsigned long)bp);
3998
3999 phy_attached_info(phydev);
4000
4001 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4002 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4003 dev->base_addr, dev->irq, dev->dev_addr);
4004
4005 return 0;
4006
4007err_out_unregister_mdio:
4008 phy_disconnect(dev->phydev);
4009 mdiobus_unregister(bp->mii_bus);
4010 of_node_put(bp->phy_node);
4011 if (np && of_phy_is_fixed_link(np))
4012 of_phy_deregister_fixed_link(np);
4013 mdiobus_free(bp->mii_bus);
4014
4015err_out_free_netdev:
4016 free_netdev(dev);
4017
4018err_disable_clocks:
4019 clk_disable_unprepare(tx_clk);
4020 clk_disable_unprepare(hclk);
4021 clk_disable_unprepare(pclk);
4022 clk_disable_unprepare(rx_clk);
4023
4024 return err;
4025}
4026
4027static int macb_remove(struct platform_device *pdev)
4028{
4029 struct net_device *dev;
4030 struct macb *bp;
4031 struct device_node *np = pdev->dev.of_node;
4032
4033 dev = platform_get_drvdata(pdev);
4034
4035 if (dev) {
4036 bp = netdev_priv(dev);
4037 if (dev->phydev)
4038 phy_disconnect(dev->phydev);
4039 mdiobus_unregister(bp->mii_bus);
4040 if (np && of_phy_is_fixed_link(np))
4041 of_phy_deregister_fixed_link(np);
4042 dev->phydev = NULL;
4043 mdiobus_free(bp->mii_bus);
4044
4045 unregister_netdev(dev);
4046 clk_disable_unprepare(bp->tx_clk);
4047 clk_disable_unprepare(bp->hclk);
4048 clk_disable_unprepare(bp->pclk);
4049 clk_disable_unprepare(bp->rx_clk);
4050 of_node_put(bp->phy_node);
4051 free_netdev(dev);
4052 }
4053
4054 return 0;
4055}
4056
4057static int __maybe_unused macb_suspend(struct device *dev)
4058{
4059 struct platform_device *pdev = to_platform_device(dev);
4060 struct net_device *netdev = platform_get_drvdata(pdev);
4061 struct macb *bp = netdev_priv(netdev);
4062
4063 netif_carrier_off(netdev);
4064 netif_device_detach(netdev);
4065
4066 if (bp->wol & MACB_WOL_ENABLED) {
4067 macb_writel(bp, IER, MACB_BIT(WOL));
4068 macb_writel(bp, WOL, MACB_BIT(MAG));
4069 enable_irq_wake(bp->queues[0].irq);
4070 } else {
4071 clk_disable_unprepare(bp->tx_clk);
4072 clk_disable_unprepare(bp->hclk);
4073 clk_disable_unprepare(bp->pclk);
4074 clk_disable_unprepare(bp->rx_clk);
4075 }
4076
4077 return 0;
4078}
4079
4080static int __maybe_unused macb_resume(struct device *dev)
4081{
4082 struct platform_device *pdev = to_platform_device(dev);
4083 struct net_device *netdev = platform_get_drvdata(pdev);
4084 struct macb *bp = netdev_priv(netdev);
4085
4086 if (bp->wol & MACB_WOL_ENABLED) {
4087 macb_writel(bp, IDR, MACB_BIT(WOL));
4088 macb_writel(bp, WOL, 0);
4089 disable_irq_wake(bp->queues[0].irq);
4090 } else {
4091 clk_prepare_enable(bp->pclk);
4092 clk_prepare_enable(bp->hclk);
4093 clk_prepare_enable(bp->tx_clk);
4094 clk_prepare_enable(bp->rx_clk);
4095 }
4096
4097 netif_device_attach(netdev);
4098
4099 return 0;
4100}
4101
4102static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
4103
4104static struct platform_driver macb_driver = {
4105 .probe = macb_probe,
4106 .remove = macb_remove,
4107 .driver = {
4108 .name = "macb",
4109 .of_match_table = of_match_ptr(macb_dt_ids),
4110 .pm = &macb_pm_ops,
4111 },
4112};
4113
4114module_platform_driver(macb_driver);
4115
4116MODULE_LICENSE("GPL");
4117MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4118MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4119MODULE_ALIAS("platform:macb");