Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Network device driver for the MACE ethernet controller on
4 * Apple Powermacs. Assumes it's under a DBDMA controller.
5 *
6 * Copyright (C) 1996 Paul Mackerras.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/netdevice.h>
12#include <linux/etherdevice.h>
13#include <linux/delay.h>
14#include <linux/string.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/crc32.h>
19#include <linux/spinlock.h>
20#include <linux/bitrev.h>
21#include <linux/slab.h>
22#include <linux/pgtable.h>
23#include <asm/dbdma.h>
24#include <asm/io.h>
25#include <asm/macio.h>
26
27#include "mace.h"
28
29static int port_aaui = -1;
30
31#define N_RX_RING 8
32#define N_TX_RING 6
33#define MAX_TX_ACTIVE 1
34#define NCMDS_TX 1 /* dma commands per element in tx ring */
35#define RX_BUFLEN (ETH_FRAME_LEN + 8)
36#define TX_TIMEOUT HZ /* 1 second */
37
38/* Chip rev needs workaround on HW & multicast addr change */
39#define BROKEN_ADDRCHG_REV 0x0941
40
41/* Bits in transmit DMA status */
42#define TX_DMA_ERR 0x80
43
44struct mace_data {
45 volatile struct mace __iomem *mace;
46 volatile struct dbdma_regs __iomem *tx_dma;
47 int tx_dma_intr;
48 volatile struct dbdma_regs __iomem *rx_dma;
49 int rx_dma_intr;
50 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
51 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
52 struct sk_buff *rx_bufs[N_RX_RING];
53 int rx_fill;
54 int rx_empty;
55 struct sk_buff *tx_bufs[N_TX_RING];
56 int tx_fill;
57 int tx_empty;
58 unsigned char maccc;
59 unsigned char tx_fullup;
60 unsigned char tx_active;
61 unsigned char tx_bad_runt;
62 struct timer_list tx_timeout;
63 int timeout_active;
64 int port_aaui;
65 int chipid;
66 struct macio_dev *mdev;
67 spinlock_t lock;
68};
69
70/*
71 * Number of bytes of private data per MACE: allow enough for
72 * the rx and tx dma commands plus a branch dma command each,
73 * and another 16 bytes to allow us to align the dma command
74 * buffers on a 16 byte boundary.
75 */
76#define PRIV_BYTES (sizeof(struct mace_data) \
77 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
78
79static int mace_open(struct net_device *dev);
80static int mace_close(struct net_device *dev);
81static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
82static void mace_set_multicast(struct net_device *dev);
83static void mace_reset(struct net_device *dev);
84static int mace_set_address(struct net_device *dev, void *addr);
85static irqreturn_t mace_interrupt(int irq, void *dev_id);
86static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
87static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
88static void mace_set_timeout(struct net_device *dev);
89static void mace_tx_timeout(struct timer_list *t);
90static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
91static inline void mace_clean_rings(struct mace_data *mp);
92static void __mace_set_address(struct net_device *dev, const void *addr);
93
94/*
95 * If we can't get a skbuff when we need it, we use this area for DMA.
96 */
97static unsigned char *dummy_buf;
98
99static const struct net_device_ops mace_netdev_ops = {
100 .ndo_open = mace_open,
101 .ndo_stop = mace_close,
102 .ndo_start_xmit = mace_xmit_start,
103 .ndo_set_rx_mode = mace_set_multicast,
104 .ndo_set_mac_address = mace_set_address,
105 .ndo_validate_addr = eth_validate_addr,
106};
107
108static int mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
109{
110 struct device_node *mace = macio_get_of_node(mdev);
111 struct net_device *dev;
112 struct mace_data *mp;
113 const unsigned char *addr;
114 u8 macaddr[ETH_ALEN];
115 int j, rev, rc = -EBUSY;
116
117 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
118 printk(KERN_ERR "can't use MACE %pOF: need 3 addrs and 3 irqs\n",
119 mace);
120 return -ENODEV;
121 }
122
123 addr = of_get_property(mace, "mac-address", NULL);
124 if (addr == NULL) {
125 addr = of_get_property(mace, "local-mac-address", NULL);
126 if (addr == NULL) {
127 printk(KERN_ERR "Can't get mac-address for MACE %pOF\n",
128 mace);
129 return -ENODEV;
130 }
131 }
132
133 /*
134 * lazy allocate the driver-wide dummy buffer. (Note that we
135 * never have more than one MACE in the system anyway)
136 */
137 if (dummy_buf == NULL) {
138 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
139 if (dummy_buf == NULL)
140 return -ENOMEM;
141 }
142
143 if (macio_request_resources(mdev, "mace")) {
144 printk(KERN_ERR "MACE: can't request IO resources !\n");
145 return -EBUSY;
146 }
147
148 dev = alloc_etherdev(PRIV_BYTES);
149 if (!dev) {
150 rc = -ENOMEM;
151 goto err_release;
152 }
153 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
154
155 mp = netdev_priv(dev);
156 mp->mdev = mdev;
157 macio_set_drvdata(mdev, dev);
158
159 dev->base_addr = macio_resource_start(mdev, 0);
160 mp->mace = ioremap(dev->base_addr, 0x1000);
161 if (mp->mace == NULL) {
162 printk(KERN_ERR "MACE: can't map IO resources !\n");
163 rc = -ENOMEM;
164 goto err_free;
165 }
166 dev->irq = macio_irq(mdev, 0);
167
168 rev = addr[0] == 0 && addr[1] == 0xA0;
169 for (j = 0; j < 6; ++j) {
170 macaddr[j] = rev ? bitrev8(addr[j]): addr[j];
171 }
172 eth_hw_addr_set(dev, macaddr);
173 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
174 in_8(&mp->mace->chipid_lo);
175
176
177 mp = netdev_priv(dev);
178 mp->maccc = ENXMT | ENRCV;
179
180 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
181 if (mp->tx_dma == NULL) {
182 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
183 rc = -ENOMEM;
184 goto err_unmap_io;
185 }
186 mp->tx_dma_intr = macio_irq(mdev, 1);
187
188 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
189 if (mp->rx_dma == NULL) {
190 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
191 rc = -ENOMEM;
192 goto err_unmap_tx_dma;
193 }
194 mp->rx_dma_intr = macio_irq(mdev, 2);
195
196 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
197 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
198
199 memset((char *) mp->tx_cmds, 0,
200 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
201 timer_setup(&mp->tx_timeout, mace_tx_timeout, 0);
202 spin_lock_init(&mp->lock);
203 mp->timeout_active = 0;
204
205 if (port_aaui >= 0)
206 mp->port_aaui = port_aaui;
207 else {
208 /* Apple Network Server uses the AAUI port */
209 if (of_machine_is_compatible("AAPL,ShinerESB"))
210 mp->port_aaui = 1;
211 else {
212#ifdef CONFIG_MACE_AAUI_PORT
213 mp->port_aaui = 1;
214#else
215 mp->port_aaui = 0;
216#endif
217 }
218 }
219
220 dev->netdev_ops = &mace_netdev_ops;
221
222 /*
223 * Most of what is below could be moved to mace_open()
224 */
225 mace_reset(dev);
226
227 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
228 if (rc) {
229 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
230 goto err_unmap_rx_dma;
231 }
232 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
233 if (rc) {
234 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
235 goto err_free_irq;
236 }
237 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
238 if (rc) {
239 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
240 goto err_free_tx_irq;
241 }
242
243 rc = register_netdev(dev);
244 if (rc) {
245 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
246 goto err_free_rx_irq;
247 }
248
249 printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n",
250 dev->name, dev->dev_addr,
251 mp->chipid >> 8, mp->chipid & 0xff);
252
253 return 0;
254
255 err_free_rx_irq:
256 free_irq(macio_irq(mdev, 2), dev);
257 err_free_tx_irq:
258 free_irq(macio_irq(mdev, 1), dev);
259 err_free_irq:
260 free_irq(macio_irq(mdev, 0), dev);
261 err_unmap_rx_dma:
262 iounmap(mp->rx_dma);
263 err_unmap_tx_dma:
264 iounmap(mp->tx_dma);
265 err_unmap_io:
266 iounmap(mp->mace);
267 err_free:
268 free_netdev(dev);
269 err_release:
270 macio_release_resources(mdev);
271
272 return rc;
273}
274
275static int mace_remove(struct macio_dev *mdev)
276{
277 struct net_device *dev = macio_get_drvdata(mdev);
278 struct mace_data *mp;
279
280 BUG_ON(dev == NULL);
281
282 macio_set_drvdata(mdev, NULL);
283
284 mp = netdev_priv(dev);
285
286 unregister_netdev(dev);
287
288 free_irq(dev->irq, dev);
289 free_irq(mp->tx_dma_intr, dev);
290 free_irq(mp->rx_dma_intr, dev);
291
292 iounmap(mp->rx_dma);
293 iounmap(mp->tx_dma);
294 iounmap(mp->mace);
295
296 free_netdev(dev);
297
298 macio_release_resources(mdev);
299
300 return 0;
301}
302
303static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
304{
305 int i;
306
307 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
308
309 /*
310 * Yes this looks peculiar, but apparently it needs to be this
311 * way on some machines.
312 */
313 for (i = 200; i > 0; --i)
314 if (le32_to_cpu(dma->control) & RUN)
315 udelay(1);
316}
317
318static void mace_reset(struct net_device *dev)
319{
320 struct mace_data *mp = netdev_priv(dev);
321 volatile struct mace __iomem *mb = mp->mace;
322 int i;
323
324 /* soft-reset the chip */
325 i = 200;
326 while (--i) {
327 out_8(&mb->biucc, SWRST);
328 if (in_8(&mb->biucc) & SWRST) {
329 udelay(10);
330 continue;
331 }
332 break;
333 }
334 if (!i) {
335 printk(KERN_ERR "mace: cannot reset chip!\n");
336 return;
337 }
338
339 out_8(&mb->imr, 0xff); /* disable all intrs for now */
340 i = in_8(&mb->ir);
341 out_8(&mb->maccc, 0); /* turn off tx, rx */
342
343 out_8(&mb->biucc, XMTSP_64);
344 out_8(&mb->utr, RTRD);
345 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
346 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
347 out_8(&mb->rcvfc, 0);
348
349 /* load up the hardware address */
350 __mace_set_address(dev, dev->dev_addr);
351
352 /* clear the multicast filter */
353 if (mp->chipid == BROKEN_ADDRCHG_REV)
354 out_8(&mb->iac, LOGADDR);
355 else {
356 out_8(&mb->iac, ADDRCHG | LOGADDR);
357 while ((in_8(&mb->iac) & ADDRCHG) != 0)
358 ;
359 }
360 for (i = 0; i < 8; ++i)
361 out_8(&mb->ladrf, 0);
362
363 /* done changing address */
364 if (mp->chipid != BROKEN_ADDRCHG_REV)
365 out_8(&mb->iac, 0);
366
367 if (mp->port_aaui)
368 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
369 else
370 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
371}
372
373static void __mace_set_address(struct net_device *dev, const void *addr)
374{
375 struct mace_data *mp = netdev_priv(dev);
376 volatile struct mace __iomem *mb = mp->mace;
377 const unsigned char *p = addr;
378 u8 macaddr[ETH_ALEN];
379 int i;
380
381 /* load up the hardware address */
382 if (mp->chipid == BROKEN_ADDRCHG_REV)
383 out_8(&mb->iac, PHYADDR);
384 else {
385 out_8(&mb->iac, ADDRCHG | PHYADDR);
386 while ((in_8(&mb->iac) & ADDRCHG) != 0)
387 ;
388 }
389 for (i = 0; i < 6; ++i)
390 out_8(&mb->padr, macaddr[i] = p[i]);
391
392 eth_hw_addr_set(dev, macaddr);
393
394 if (mp->chipid != BROKEN_ADDRCHG_REV)
395 out_8(&mb->iac, 0);
396}
397
398static int mace_set_address(struct net_device *dev, void *addr)
399{
400 struct mace_data *mp = netdev_priv(dev);
401 volatile struct mace __iomem *mb = mp->mace;
402 unsigned long flags;
403
404 spin_lock_irqsave(&mp->lock, flags);
405
406 __mace_set_address(dev, addr);
407
408 /* note: setting ADDRCHG clears ENRCV */
409 out_8(&mb->maccc, mp->maccc);
410
411 spin_unlock_irqrestore(&mp->lock, flags);
412 return 0;
413}
414
415static inline void mace_clean_rings(struct mace_data *mp)
416{
417 int i;
418
419 /* free some skb's */
420 for (i = 0; i < N_RX_RING; ++i) {
421 if (mp->rx_bufs[i] != NULL) {
422 dev_kfree_skb(mp->rx_bufs[i]);
423 mp->rx_bufs[i] = NULL;
424 }
425 }
426 for (i = mp->tx_empty; i != mp->tx_fill; ) {
427 dev_kfree_skb(mp->tx_bufs[i]);
428 if (++i >= N_TX_RING)
429 i = 0;
430 }
431}
432
433static int mace_open(struct net_device *dev)
434{
435 struct mace_data *mp = netdev_priv(dev);
436 volatile struct mace __iomem *mb = mp->mace;
437 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
438 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
439 volatile struct dbdma_cmd *cp;
440 int i;
441 struct sk_buff *skb;
442 unsigned char *data;
443
444 /* reset the chip */
445 mace_reset(dev);
446
447 /* initialize list of sk_buffs for receiving and set up recv dma */
448 mace_clean_rings(mp);
449 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
450 cp = mp->rx_cmds;
451 for (i = 0; i < N_RX_RING - 1; ++i) {
452 skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
453 if (!skb) {
454 data = dummy_buf;
455 } else {
456 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
457 data = skb->data;
458 }
459 mp->rx_bufs[i] = skb;
460 cp->req_count = cpu_to_le16(RX_BUFLEN);
461 cp->command = cpu_to_le16(INPUT_LAST + INTR_ALWAYS);
462 cp->phy_addr = cpu_to_le32(virt_to_bus(data));
463 cp->xfer_status = 0;
464 ++cp;
465 }
466 mp->rx_bufs[i] = NULL;
467 cp->command = cpu_to_le16(DBDMA_STOP);
468 mp->rx_fill = i;
469 mp->rx_empty = 0;
470
471 /* Put a branch back to the beginning of the receive command list */
472 ++cp;
473 cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
474 cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->rx_cmds));
475
476 /* start rx dma */
477 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
478 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
479 out_le32(&rd->control, (RUN << 16) | RUN);
480
481 /* put a branch at the end of the tx command list */
482 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
483 cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
484 cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->tx_cmds));
485
486 /* reset tx dma */
487 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
488 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
489 mp->tx_fill = 0;
490 mp->tx_empty = 0;
491 mp->tx_fullup = 0;
492 mp->tx_active = 0;
493 mp->tx_bad_runt = 0;
494
495 /* turn it on! */
496 out_8(&mb->maccc, mp->maccc);
497 /* enable all interrupts except receive interrupts */
498 out_8(&mb->imr, RCVINT);
499
500 return 0;
501}
502
503static int mace_close(struct net_device *dev)
504{
505 struct mace_data *mp = netdev_priv(dev);
506 volatile struct mace __iomem *mb = mp->mace;
507 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
508 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
509
510 /* disable rx and tx */
511 out_8(&mb->maccc, 0);
512 out_8(&mb->imr, 0xff); /* disable all intrs */
513
514 /* disable rx and tx dma */
515 rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
516 td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
517
518 mace_clean_rings(mp);
519
520 return 0;
521}
522
523static inline void mace_set_timeout(struct net_device *dev)
524{
525 struct mace_data *mp = netdev_priv(dev);
526
527 if (mp->timeout_active)
528 del_timer(&mp->tx_timeout);
529 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
530 add_timer(&mp->tx_timeout);
531 mp->timeout_active = 1;
532}
533
534static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
535{
536 struct mace_data *mp = netdev_priv(dev);
537 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
538 volatile struct dbdma_cmd *cp, *np;
539 unsigned long flags;
540 int fill, next, len;
541
542 /* see if there's a free slot in the tx ring */
543 spin_lock_irqsave(&mp->lock, flags);
544 fill = mp->tx_fill;
545 next = fill + 1;
546 if (next >= N_TX_RING)
547 next = 0;
548 if (next == mp->tx_empty) {
549 netif_stop_queue(dev);
550 mp->tx_fullup = 1;
551 spin_unlock_irqrestore(&mp->lock, flags);
552 return NETDEV_TX_BUSY; /* can't take it at the moment */
553 }
554 spin_unlock_irqrestore(&mp->lock, flags);
555
556 /* partially fill in the dma command block */
557 len = skb->len;
558 if (len > ETH_FRAME_LEN) {
559 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
560 len = ETH_FRAME_LEN;
561 }
562 mp->tx_bufs[fill] = skb;
563 cp = mp->tx_cmds + NCMDS_TX * fill;
564 cp->req_count = cpu_to_le16(len);
565 cp->phy_addr = cpu_to_le32(virt_to_bus(skb->data));
566
567 np = mp->tx_cmds + NCMDS_TX * next;
568 out_le16(&np->command, DBDMA_STOP);
569
570 /* poke the tx dma channel */
571 spin_lock_irqsave(&mp->lock, flags);
572 mp->tx_fill = next;
573 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
574 out_le16(&cp->xfer_status, 0);
575 out_le16(&cp->command, OUTPUT_LAST);
576 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
577 ++mp->tx_active;
578 mace_set_timeout(dev);
579 }
580 if (++next >= N_TX_RING)
581 next = 0;
582 if (next == mp->tx_empty)
583 netif_stop_queue(dev);
584 spin_unlock_irqrestore(&mp->lock, flags);
585
586 return NETDEV_TX_OK;
587}
588
589static void mace_set_multicast(struct net_device *dev)
590{
591 struct mace_data *mp = netdev_priv(dev);
592 volatile struct mace __iomem *mb = mp->mace;
593 int i;
594 u32 crc;
595 unsigned long flags;
596
597 spin_lock_irqsave(&mp->lock, flags);
598 mp->maccc &= ~PROM;
599 if (dev->flags & IFF_PROMISC) {
600 mp->maccc |= PROM;
601 } else {
602 unsigned char multicast_filter[8];
603 struct netdev_hw_addr *ha;
604
605 if (dev->flags & IFF_ALLMULTI) {
606 for (i = 0; i < 8; i++)
607 multicast_filter[i] = 0xff;
608 } else {
609 for (i = 0; i < 8; i++)
610 multicast_filter[i] = 0;
611 netdev_for_each_mc_addr(ha, dev) {
612 crc = ether_crc_le(6, ha->addr);
613 i = crc >> 26; /* bit number in multicast_filter */
614 multicast_filter[i >> 3] |= 1 << (i & 7);
615 }
616 }
617#if 0
618 printk("Multicast filter :");
619 for (i = 0; i < 8; i++)
620 printk("%02x ", multicast_filter[i]);
621 printk("\n");
622#endif
623
624 if (mp->chipid == BROKEN_ADDRCHG_REV)
625 out_8(&mb->iac, LOGADDR);
626 else {
627 out_8(&mb->iac, ADDRCHG | LOGADDR);
628 while ((in_8(&mb->iac) & ADDRCHG) != 0)
629 ;
630 }
631 for (i = 0; i < 8; ++i)
632 out_8(&mb->ladrf, multicast_filter[i]);
633 if (mp->chipid != BROKEN_ADDRCHG_REV)
634 out_8(&mb->iac, 0);
635 }
636 /* reset maccc */
637 out_8(&mb->maccc, mp->maccc);
638 spin_unlock_irqrestore(&mp->lock, flags);
639}
640
641static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev)
642{
643 volatile struct mace __iomem *mb = mp->mace;
644 static int mace_babbles, mace_jabbers;
645
646 if (intr & MPCO)
647 dev->stats.rx_missed_errors += 256;
648 dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
649 if (intr & RNTPCO)
650 dev->stats.rx_length_errors += 256;
651 dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
652 if (intr & CERR)
653 ++dev->stats.tx_heartbeat_errors;
654 if (intr & BABBLE)
655 if (mace_babbles++ < 4)
656 printk(KERN_DEBUG "mace: babbling transmitter\n");
657 if (intr & JABBER)
658 if (mace_jabbers++ < 4)
659 printk(KERN_DEBUG "mace: jabbering transceiver\n");
660}
661
662static irqreturn_t mace_interrupt(int irq, void *dev_id)
663{
664 struct net_device *dev = (struct net_device *) dev_id;
665 struct mace_data *mp = netdev_priv(dev);
666 volatile struct mace __iomem *mb = mp->mace;
667 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
668 volatile struct dbdma_cmd *cp;
669 int intr, fs, i, stat, x;
670 int xcount, dstat;
671 unsigned long flags;
672 /* static int mace_last_fs, mace_last_xcount; */
673
674 spin_lock_irqsave(&mp->lock, flags);
675 intr = in_8(&mb->ir); /* read interrupt register */
676 in_8(&mb->xmtrc); /* get retries */
677 mace_handle_misc_intrs(mp, intr, dev);
678
679 i = mp->tx_empty;
680 while (in_8(&mb->pr) & XMTSV) {
681 del_timer(&mp->tx_timeout);
682 mp->timeout_active = 0;
683 /*
684 * Clear any interrupt indication associated with this status
685 * word. This appears to unlatch any error indication from
686 * the DMA controller.
687 */
688 intr = in_8(&mb->ir);
689 if (intr != 0)
690 mace_handle_misc_intrs(mp, intr, dev);
691 if (mp->tx_bad_runt) {
692 fs = in_8(&mb->xmtfs);
693 mp->tx_bad_runt = 0;
694 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
695 continue;
696 }
697 dstat = le32_to_cpu(td->status);
698 /* stop DMA controller */
699 out_le32(&td->control, RUN << 16);
700 /*
701 * xcount is the number of complete frames which have been
702 * written to the fifo but for which status has not been read.
703 */
704 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
705 if (xcount == 0 || (dstat & DEAD)) {
706 /*
707 * If a packet was aborted before the DMA controller has
708 * finished transferring it, it seems that there are 2 bytes
709 * which are stuck in some buffer somewhere. These will get
710 * transmitted as soon as we read the frame status (which
711 * reenables the transmit data transfer request). Turning
712 * off the DMA controller and/or resetting the MACE doesn't
713 * help. So we disable auto-padding and FCS transmission
714 * so the two bytes will only be a runt packet which should
715 * be ignored by other stations.
716 */
717 out_8(&mb->xmtfc, DXMTFCS);
718 }
719 fs = in_8(&mb->xmtfs);
720 if ((fs & XMTSV) == 0) {
721 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
722 fs, xcount, dstat);
723 mace_reset(dev);
724 /*
725 * XXX mace likes to hang the machine after a xmtfs error.
726 * This is hard to reproduce, resetting *may* help
727 */
728 }
729 cp = mp->tx_cmds + NCMDS_TX * i;
730 stat = le16_to_cpu(cp->xfer_status);
731 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
732 /*
733 * Check whether there were in fact 2 bytes written to
734 * the transmit FIFO.
735 */
736 udelay(1);
737 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
738 if (x != 0) {
739 /* there were two bytes with an end-of-packet indication */
740 mp->tx_bad_runt = 1;
741 mace_set_timeout(dev);
742 } else {
743 /*
744 * Either there weren't the two bytes buffered up, or they
745 * didn't have an end-of-packet indication.
746 * We flush the transmit FIFO just in case (by setting the
747 * XMTFWU bit with the transmitter disabled).
748 */
749 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
750 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
751 udelay(1);
752 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
753 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
754 }
755 }
756 /* dma should have finished */
757 if (i == mp->tx_fill) {
758 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
759 fs, xcount, dstat);
760 continue;
761 }
762 /* Update stats */
763 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
764 ++dev->stats.tx_errors;
765 if (fs & LCAR)
766 ++dev->stats.tx_carrier_errors;
767 if (fs & (UFLO|LCOL|RTRY))
768 ++dev->stats.tx_aborted_errors;
769 } else {
770 dev->stats.tx_bytes += mp->tx_bufs[i]->len;
771 ++dev->stats.tx_packets;
772 }
773 dev_consume_skb_irq(mp->tx_bufs[i]);
774 --mp->tx_active;
775 if (++i >= N_TX_RING)
776 i = 0;
777#if 0
778 mace_last_fs = fs;
779 mace_last_xcount = xcount;
780#endif
781 }
782
783 if (i != mp->tx_empty) {
784 mp->tx_fullup = 0;
785 netif_wake_queue(dev);
786 }
787 mp->tx_empty = i;
788 i += mp->tx_active;
789 if (i >= N_TX_RING)
790 i -= N_TX_RING;
791 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
792 do {
793 /* set up the next one */
794 cp = mp->tx_cmds + NCMDS_TX * i;
795 out_le16(&cp->xfer_status, 0);
796 out_le16(&cp->command, OUTPUT_LAST);
797 ++mp->tx_active;
798 if (++i >= N_TX_RING)
799 i = 0;
800 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
801 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
802 mace_set_timeout(dev);
803 }
804 spin_unlock_irqrestore(&mp->lock, flags);
805 return IRQ_HANDLED;
806}
807
808static void mace_tx_timeout(struct timer_list *t)
809{
810 struct mace_data *mp = from_timer(mp, t, tx_timeout);
811 struct net_device *dev = macio_get_drvdata(mp->mdev);
812 volatile struct mace __iomem *mb = mp->mace;
813 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
814 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
815 volatile struct dbdma_cmd *cp;
816 unsigned long flags;
817 int i;
818
819 spin_lock_irqsave(&mp->lock, flags);
820 mp->timeout_active = 0;
821 if (mp->tx_active == 0 && !mp->tx_bad_runt)
822 goto out;
823
824 /* update various counters */
825 mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);
826
827 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
828
829 /* turn off both tx and rx and reset the chip */
830 out_8(&mb->maccc, 0);
831 printk(KERN_ERR "mace: transmit timeout - resetting\n");
832 dbdma_reset(td);
833 mace_reset(dev);
834
835 /* restart rx dma */
836 cp = bus_to_virt(le32_to_cpu(rd->cmdptr));
837 dbdma_reset(rd);
838 out_le16(&cp->xfer_status, 0);
839 out_le32(&rd->cmdptr, virt_to_bus(cp));
840 out_le32(&rd->control, (RUN << 16) | RUN);
841
842 /* fix up the transmit side */
843 i = mp->tx_empty;
844 mp->tx_active = 0;
845 ++dev->stats.tx_errors;
846 if (mp->tx_bad_runt) {
847 mp->tx_bad_runt = 0;
848 } else if (i != mp->tx_fill) {
849 dev_kfree_skb_irq(mp->tx_bufs[i]);
850 if (++i >= N_TX_RING)
851 i = 0;
852 mp->tx_empty = i;
853 }
854 mp->tx_fullup = 0;
855 netif_wake_queue(dev);
856 if (i != mp->tx_fill) {
857 cp = mp->tx_cmds + NCMDS_TX * i;
858 out_le16(&cp->xfer_status, 0);
859 out_le16(&cp->command, OUTPUT_LAST);
860 out_le32(&td->cmdptr, virt_to_bus(cp));
861 out_le32(&td->control, (RUN << 16) | RUN);
862 ++mp->tx_active;
863 mace_set_timeout(dev);
864 }
865
866 /* turn it back on */
867 out_8(&mb->imr, RCVINT);
868 out_8(&mb->maccc, mp->maccc);
869
870out:
871 spin_unlock_irqrestore(&mp->lock, flags);
872}
873
874static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
875{
876 return IRQ_HANDLED;
877}
878
879static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
880{
881 struct net_device *dev = (struct net_device *) dev_id;
882 struct mace_data *mp = netdev_priv(dev);
883 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
884 volatile struct dbdma_cmd *cp, *np;
885 int i, nb, stat, next;
886 struct sk_buff *skb;
887 unsigned frame_status;
888 static int mace_lost_status;
889 unsigned char *data;
890 unsigned long flags;
891
892 spin_lock_irqsave(&mp->lock, flags);
893 for (i = mp->rx_empty; i != mp->rx_fill; ) {
894 cp = mp->rx_cmds + i;
895 stat = le16_to_cpu(cp->xfer_status);
896 if ((stat & ACTIVE) == 0) {
897 next = i + 1;
898 if (next >= N_RX_RING)
899 next = 0;
900 np = mp->rx_cmds + next;
901 if (next != mp->rx_fill &&
902 (le16_to_cpu(np->xfer_status) & ACTIVE) != 0) {
903 printk(KERN_DEBUG "mace: lost a status word\n");
904 ++mace_lost_status;
905 } else
906 break;
907 }
908 nb = le16_to_cpu(cp->req_count) - le16_to_cpu(cp->res_count);
909 out_le16(&cp->command, DBDMA_STOP);
910 /* got a packet, have a look at it */
911 skb = mp->rx_bufs[i];
912 if (!skb) {
913 ++dev->stats.rx_dropped;
914 } else if (nb > 8) {
915 data = skb->data;
916 frame_status = (data[nb-3] << 8) + data[nb-4];
917 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
918 ++dev->stats.rx_errors;
919 if (frame_status & RS_OFLO)
920 ++dev->stats.rx_over_errors;
921 if (frame_status & RS_FRAMERR)
922 ++dev->stats.rx_frame_errors;
923 if (frame_status & RS_FCSERR)
924 ++dev->stats.rx_crc_errors;
925 } else {
926 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
927 * FCS on frames with 802.3 headers. This means that Ethernet
928 * frames have 8 extra octets at the end, while 802.3 frames
929 * have only 4. We need to correctly account for this. */
930 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
931 nb -= 4;
932 else /* Ethernet header; mace includes FCS */
933 nb -= 8;
934 skb_put(skb, nb);
935 skb->protocol = eth_type_trans(skb, dev);
936 dev->stats.rx_bytes += skb->len;
937 netif_rx(skb);
938 mp->rx_bufs[i] = NULL;
939 ++dev->stats.rx_packets;
940 }
941 } else {
942 ++dev->stats.rx_errors;
943 ++dev->stats.rx_length_errors;
944 }
945
946 /* advance to next */
947 if (++i >= N_RX_RING)
948 i = 0;
949 }
950 mp->rx_empty = i;
951
952 i = mp->rx_fill;
953 for (;;) {
954 next = i + 1;
955 if (next >= N_RX_RING)
956 next = 0;
957 if (next == mp->rx_empty)
958 break;
959 cp = mp->rx_cmds + i;
960 skb = mp->rx_bufs[i];
961 if (!skb) {
962 skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
963 if (skb) {
964 skb_reserve(skb, 2);
965 mp->rx_bufs[i] = skb;
966 }
967 }
968 cp->req_count = cpu_to_le16(RX_BUFLEN);
969 data = skb? skb->data: dummy_buf;
970 cp->phy_addr = cpu_to_le32(virt_to_bus(data));
971 out_le16(&cp->xfer_status, 0);
972 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
973#if 0
974 if ((le32_to_cpu(rd->status) & ACTIVE) != 0) {
975 out_le32(&rd->control, (PAUSE << 16) | PAUSE);
976 while ((in_le32(&rd->status) & ACTIVE) != 0)
977 ;
978 }
979#endif
980 i = next;
981 }
982 if (i != mp->rx_fill) {
983 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
984 mp->rx_fill = i;
985 }
986 spin_unlock_irqrestore(&mp->lock, flags);
987 return IRQ_HANDLED;
988}
989
990static const struct of_device_id mace_match[] =
991{
992 {
993 .name = "mace",
994 },
995 {},
996};
997MODULE_DEVICE_TABLE (of, mace_match);
998
999static struct macio_driver mace_driver =
1000{
1001 .driver = {
1002 .name = "mace",
1003 .owner = THIS_MODULE,
1004 .of_match_table = mace_match,
1005 },
1006 .probe = mace_probe,
1007 .remove = mace_remove,
1008};
1009
1010
1011static int __init mace_init(void)
1012{
1013 return macio_register_driver(&mace_driver);
1014}
1015
1016static void __exit mace_cleanup(void)
1017{
1018 macio_unregister_driver(&mace_driver);
1019
1020 kfree(dummy_buf);
1021 dummy_buf = NULL;
1022}
1023
1024MODULE_AUTHOR("Paul Mackerras");
1025MODULE_DESCRIPTION("PowerMac MACE driver.");
1026module_param(port_aaui, int, 0);
1027MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1028MODULE_LICENSE("GPL");
1029
1030module_init(mace_init);
1031module_exit(mace_cleanup);
1/*
2 * Network device driver for the MACE ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/netdevice.h>
11#include <linux/etherdevice.h>
12#include <linux/delay.h>
13#include <linux/string.h>
14#include <linux/timer.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/crc32.h>
18#include <linux/spinlock.h>
19#include <linux/bitrev.h>
20#include <linux/slab.h>
21#include <asm/prom.h>
22#include <asm/dbdma.h>
23#include <asm/io.h>
24#include <asm/pgtable.h>
25#include <asm/macio.h>
26
27#include "mace.h"
28
29static int port_aaui = -1;
30
31#define N_RX_RING 8
32#define N_TX_RING 6
33#define MAX_TX_ACTIVE 1
34#define NCMDS_TX 1 /* dma commands per element in tx ring */
35#define RX_BUFLEN (ETH_FRAME_LEN + 8)
36#define TX_TIMEOUT HZ /* 1 second */
37
38/* Chip rev needs workaround on HW & multicast addr change */
39#define BROKEN_ADDRCHG_REV 0x0941
40
41/* Bits in transmit DMA status */
42#define TX_DMA_ERR 0x80
43
44struct mace_data {
45 volatile struct mace __iomem *mace;
46 volatile struct dbdma_regs __iomem *tx_dma;
47 int tx_dma_intr;
48 volatile struct dbdma_regs __iomem *rx_dma;
49 int rx_dma_intr;
50 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
51 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
52 struct sk_buff *rx_bufs[N_RX_RING];
53 int rx_fill;
54 int rx_empty;
55 struct sk_buff *tx_bufs[N_TX_RING];
56 int tx_fill;
57 int tx_empty;
58 unsigned char maccc;
59 unsigned char tx_fullup;
60 unsigned char tx_active;
61 unsigned char tx_bad_runt;
62 struct timer_list tx_timeout;
63 int timeout_active;
64 int port_aaui;
65 int chipid;
66 struct macio_dev *mdev;
67 spinlock_t lock;
68};
69
70/*
71 * Number of bytes of private data per MACE: allow enough for
72 * the rx and tx dma commands plus a branch dma command each,
73 * and another 16 bytes to allow us to align the dma command
74 * buffers on a 16 byte boundary.
75 */
76#define PRIV_BYTES (sizeof(struct mace_data) \
77 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
78
79static int mace_open(struct net_device *dev);
80static int mace_close(struct net_device *dev);
81static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
82static void mace_set_multicast(struct net_device *dev);
83static void mace_reset(struct net_device *dev);
84static int mace_set_address(struct net_device *dev, void *addr);
85static irqreturn_t mace_interrupt(int irq, void *dev_id);
86static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
87static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
88static void mace_set_timeout(struct net_device *dev);
89static void mace_tx_timeout(struct timer_list *t);
90static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
91static inline void mace_clean_rings(struct mace_data *mp);
92static void __mace_set_address(struct net_device *dev, void *addr);
93
94/*
95 * If we can't get a skbuff when we need it, we use this area for DMA.
96 */
97static unsigned char *dummy_buf;
98
99static const struct net_device_ops mace_netdev_ops = {
100 .ndo_open = mace_open,
101 .ndo_stop = mace_close,
102 .ndo_start_xmit = mace_xmit_start,
103 .ndo_set_rx_mode = mace_set_multicast,
104 .ndo_set_mac_address = mace_set_address,
105 .ndo_validate_addr = eth_validate_addr,
106};
107
108static int mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
109{
110 struct device_node *mace = macio_get_of_node(mdev);
111 struct net_device *dev;
112 struct mace_data *mp;
113 const unsigned char *addr;
114 int j, rev, rc = -EBUSY;
115
116 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
117 printk(KERN_ERR "can't use MACE %pOF: need 3 addrs and 3 irqs\n",
118 mace);
119 return -ENODEV;
120 }
121
122 addr = of_get_property(mace, "mac-address", NULL);
123 if (addr == NULL) {
124 addr = of_get_property(mace, "local-mac-address", NULL);
125 if (addr == NULL) {
126 printk(KERN_ERR "Can't get mac-address for MACE %pOF\n",
127 mace);
128 return -ENODEV;
129 }
130 }
131
132 /*
133 * lazy allocate the driver-wide dummy buffer. (Note that we
134 * never have more than one MACE in the system anyway)
135 */
136 if (dummy_buf == NULL) {
137 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
138 if (dummy_buf == NULL)
139 return -ENOMEM;
140 }
141
142 if (macio_request_resources(mdev, "mace")) {
143 printk(KERN_ERR "MACE: can't request IO resources !\n");
144 return -EBUSY;
145 }
146
147 dev = alloc_etherdev(PRIV_BYTES);
148 if (!dev) {
149 rc = -ENOMEM;
150 goto err_release;
151 }
152 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
153
154 mp = netdev_priv(dev);
155 mp->mdev = mdev;
156 macio_set_drvdata(mdev, dev);
157
158 dev->base_addr = macio_resource_start(mdev, 0);
159 mp->mace = ioremap(dev->base_addr, 0x1000);
160 if (mp->mace == NULL) {
161 printk(KERN_ERR "MACE: can't map IO resources !\n");
162 rc = -ENOMEM;
163 goto err_free;
164 }
165 dev->irq = macio_irq(mdev, 0);
166
167 rev = addr[0] == 0 && addr[1] == 0xA0;
168 for (j = 0; j < 6; ++j) {
169 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
170 }
171 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
172 in_8(&mp->mace->chipid_lo);
173
174
175 mp = netdev_priv(dev);
176 mp->maccc = ENXMT | ENRCV;
177
178 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
179 if (mp->tx_dma == NULL) {
180 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
181 rc = -ENOMEM;
182 goto err_unmap_io;
183 }
184 mp->tx_dma_intr = macio_irq(mdev, 1);
185
186 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
187 if (mp->rx_dma == NULL) {
188 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
189 rc = -ENOMEM;
190 goto err_unmap_tx_dma;
191 }
192 mp->rx_dma_intr = macio_irq(mdev, 2);
193
194 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
195 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
196
197 memset((char *) mp->tx_cmds, 0,
198 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
199 timer_setup(&mp->tx_timeout, mace_tx_timeout, 0);
200 spin_lock_init(&mp->lock);
201 mp->timeout_active = 0;
202
203 if (port_aaui >= 0)
204 mp->port_aaui = port_aaui;
205 else {
206 /* Apple Network Server uses the AAUI port */
207 if (of_machine_is_compatible("AAPL,ShinerESB"))
208 mp->port_aaui = 1;
209 else {
210#ifdef CONFIG_MACE_AAUI_PORT
211 mp->port_aaui = 1;
212#else
213 mp->port_aaui = 0;
214#endif
215 }
216 }
217
218 dev->netdev_ops = &mace_netdev_ops;
219
220 /*
221 * Most of what is below could be moved to mace_open()
222 */
223 mace_reset(dev);
224
225 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
226 if (rc) {
227 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
228 goto err_unmap_rx_dma;
229 }
230 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
231 if (rc) {
232 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
233 goto err_free_irq;
234 }
235 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
236 if (rc) {
237 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
238 goto err_free_tx_irq;
239 }
240
241 rc = register_netdev(dev);
242 if (rc) {
243 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
244 goto err_free_rx_irq;
245 }
246
247 printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n",
248 dev->name, dev->dev_addr,
249 mp->chipid >> 8, mp->chipid & 0xff);
250
251 return 0;
252
253 err_free_rx_irq:
254 free_irq(macio_irq(mdev, 2), dev);
255 err_free_tx_irq:
256 free_irq(macio_irq(mdev, 1), dev);
257 err_free_irq:
258 free_irq(macio_irq(mdev, 0), dev);
259 err_unmap_rx_dma:
260 iounmap(mp->rx_dma);
261 err_unmap_tx_dma:
262 iounmap(mp->tx_dma);
263 err_unmap_io:
264 iounmap(mp->mace);
265 err_free:
266 free_netdev(dev);
267 err_release:
268 macio_release_resources(mdev);
269
270 return rc;
271}
272
273static int mace_remove(struct macio_dev *mdev)
274{
275 struct net_device *dev = macio_get_drvdata(mdev);
276 struct mace_data *mp;
277
278 BUG_ON(dev == NULL);
279
280 macio_set_drvdata(mdev, NULL);
281
282 mp = netdev_priv(dev);
283
284 unregister_netdev(dev);
285
286 free_irq(dev->irq, dev);
287 free_irq(mp->tx_dma_intr, dev);
288 free_irq(mp->rx_dma_intr, dev);
289
290 iounmap(mp->rx_dma);
291 iounmap(mp->tx_dma);
292 iounmap(mp->mace);
293
294 free_netdev(dev);
295
296 macio_release_resources(mdev);
297
298 return 0;
299}
300
301static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
302{
303 int i;
304
305 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
306
307 /*
308 * Yes this looks peculiar, but apparently it needs to be this
309 * way on some machines.
310 */
311 for (i = 200; i > 0; --i)
312 if (le32_to_cpu(dma->control) & RUN)
313 udelay(1);
314}
315
316static void mace_reset(struct net_device *dev)
317{
318 struct mace_data *mp = netdev_priv(dev);
319 volatile struct mace __iomem *mb = mp->mace;
320 int i;
321
322 /* soft-reset the chip */
323 i = 200;
324 while (--i) {
325 out_8(&mb->biucc, SWRST);
326 if (in_8(&mb->biucc) & SWRST) {
327 udelay(10);
328 continue;
329 }
330 break;
331 }
332 if (!i) {
333 printk(KERN_ERR "mace: cannot reset chip!\n");
334 return;
335 }
336
337 out_8(&mb->imr, 0xff); /* disable all intrs for now */
338 i = in_8(&mb->ir);
339 out_8(&mb->maccc, 0); /* turn off tx, rx */
340
341 out_8(&mb->biucc, XMTSP_64);
342 out_8(&mb->utr, RTRD);
343 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
344 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
345 out_8(&mb->rcvfc, 0);
346
347 /* load up the hardware address */
348 __mace_set_address(dev, dev->dev_addr);
349
350 /* clear the multicast filter */
351 if (mp->chipid == BROKEN_ADDRCHG_REV)
352 out_8(&mb->iac, LOGADDR);
353 else {
354 out_8(&mb->iac, ADDRCHG | LOGADDR);
355 while ((in_8(&mb->iac) & ADDRCHG) != 0)
356 ;
357 }
358 for (i = 0; i < 8; ++i)
359 out_8(&mb->ladrf, 0);
360
361 /* done changing address */
362 if (mp->chipid != BROKEN_ADDRCHG_REV)
363 out_8(&mb->iac, 0);
364
365 if (mp->port_aaui)
366 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
367 else
368 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
369}
370
371static void __mace_set_address(struct net_device *dev, void *addr)
372{
373 struct mace_data *mp = netdev_priv(dev);
374 volatile struct mace __iomem *mb = mp->mace;
375 unsigned char *p = addr;
376 int i;
377
378 /* load up the hardware address */
379 if (mp->chipid == BROKEN_ADDRCHG_REV)
380 out_8(&mb->iac, PHYADDR);
381 else {
382 out_8(&mb->iac, ADDRCHG | PHYADDR);
383 while ((in_8(&mb->iac) & ADDRCHG) != 0)
384 ;
385 }
386 for (i = 0; i < 6; ++i)
387 out_8(&mb->padr, dev->dev_addr[i] = p[i]);
388 if (mp->chipid != BROKEN_ADDRCHG_REV)
389 out_8(&mb->iac, 0);
390}
391
392static int mace_set_address(struct net_device *dev, void *addr)
393{
394 struct mace_data *mp = netdev_priv(dev);
395 volatile struct mace __iomem *mb = mp->mace;
396 unsigned long flags;
397
398 spin_lock_irqsave(&mp->lock, flags);
399
400 __mace_set_address(dev, addr);
401
402 /* note: setting ADDRCHG clears ENRCV */
403 out_8(&mb->maccc, mp->maccc);
404
405 spin_unlock_irqrestore(&mp->lock, flags);
406 return 0;
407}
408
409static inline void mace_clean_rings(struct mace_data *mp)
410{
411 int i;
412
413 /* free some skb's */
414 for (i = 0; i < N_RX_RING; ++i) {
415 if (mp->rx_bufs[i] != NULL) {
416 dev_kfree_skb(mp->rx_bufs[i]);
417 mp->rx_bufs[i] = NULL;
418 }
419 }
420 for (i = mp->tx_empty; i != mp->tx_fill; ) {
421 dev_kfree_skb(mp->tx_bufs[i]);
422 if (++i >= N_TX_RING)
423 i = 0;
424 }
425}
426
427static int mace_open(struct net_device *dev)
428{
429 struct mace_data *mp = netdev_priv(dev);
430 volatile struct mace __iomem *mb = mp->mace;
431 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
432 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
433 volatile struct dbdma_cmd *cp;
434 int i;
435 struct sk_buff *skb;
436 unsigned char *data;
437
438 /* reset the chip */
439 mace_reset(dev);
440
441 /* initialize list of sk_buffs for receiving and set up recv dma */
442 mace_clean_rings(mp);
443 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
444 cp = mp->rx_cmds;
445 for (i = 0; i < N_RX_RING - 1; ++i) {
446 skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
447 if (!skb) {
448 data = dummy_buf;
449 } else {
450 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
451 data = skb->data;
452 }
453 mp->rx_bufs[i] = skb;
454 cp->req_count = cpu_to_le16(RX_BUFLEN);
455 cp->command = cpu_to_le16(INPUT_LAST + INTR_ALWAYS);
456 cp->phy_addr = cpu_to_le32(virt_to_bus(data));
457 cp->xfer_status = 0;
458 ++cp;
459 }
460 mp->rx_bufs[i] = NULL;
461 cp->command = cpu_to_le16(DBDMA_STOP);
462 mp->rx_fill = i;
463 mp->rx_empty = 0;
464
465 /* Put a branch back to the beginning of the receive command list */
466 ++cp;
467 cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
468 cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->rx_cmds));
469
470 /* start rx dma */
471 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
472 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
473 out_le32(&rd->control, (RUN << 16) | RUN);
474
475 /* put a branch at the end of the tx command list */
476 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
477 cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
478 cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->tx_cmds));
479
480 /* reset tx dma */
481 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
482 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
483 mp->tx_fill = 0;
484 mp->tx_empty = 0;
485 mp->tx_fullup = 0;
486 mp->tx_active = 0;
487 mp->tx_bad_runt = 0;
488
489 /* turn it on! */
490 out_8(&mb->maccc, mp->maccc);
491 /* enable all interrupts except receive interrupts */
492 out_8(&mb->imr, RCVINT);
493
494 return 0;
495}
496
497static int mace_close(struct net_device *dev)
498{
499 struct mace_data *mp = netdev_priv(dev);
500 volatile struct mace __iomem *mb = mp->mace;
501 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
502 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
503
504 /* disable rx and tx */
505 out_8(&mb->maccc, 0);
506 out_8(&mb->imr, 0xff); /* disable all intrs */
507
508 /* disable rx and tx dma */
509 rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
510 td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
511
512 mace_clean_rings(mp);
513
514 return 0;
515}
516
517static inline void mace_set_timeout(struct net_device *dev)
518{
519 struct mace_data *mp = netdev_priv(dev);
520
521 if (mp->timeout_active)
522 del_timer(&mp->tx_timeout);
523 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
524 add_timer(&mp->tx_timeout);
525 mp->timeout_active = 1;
526}
527
528static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
529{
530 struct mace_data *mp = netdev_priv(dev);
531 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
532 volatile struct dbdma_cmd *cp, *np;
533 unsigned long flags;
534 int fill, next, len;
535
536 /* see if there's a free slot in the tx ring */
537 spin_lock_irqsave(&mp->lock, flags);
538 fill = mp->tx_fill;
539 next = fill + 1;
540 if (next >= N_TX_RING)
541 next = 0;
542 if (next == mp->tx_empty) {
543 netif_stop_queue(dev);
544 mp->tx_fullup = 1;
545 spin_unlock_irqrestore(&mp->lock, flags);
546 return NETDEV_TX_BUSY; /* can't take it at the moment */
547 }
548 spin_unlock_irqrestore(&mp->lock, flags);
549
550 /* partially fill in the dma command block */
551 len = skb->len;
552 if (len > ETH_FRAME_LEN) {
553 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
554 len = ETH_FRAME_LEN;
555 }
556 mp->tx_bufs[fill] = skb;
557 cp = mp->tx_cmds + NCMDS_TX * fill;
558 cp->req_count = cpu_to_le16(len);
559 cp->phy_addr = cpu_to_le32(virt_to_bus(skb->data));
560
561 np = mp->tx_cmds + NCMDS_TX * next;
562 out_le16(&np->command, DBDMA_STOP);
563
564 /* poke the tx dma channel */
565 spin_lock_irqsave(&mp->lock, flags);
566 mp->tx_fill = next;
567 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
568 out_le16(&cp->xfer_status, 0);
569 out_le16(&cp->command, OUTPUT_LAST);
570 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
571 ++mp->tx_active;
572 mace_set_timeout(dev);
573 }
574 if (++next >= N_TX_RING)
575 next = 0;
576 if (next == mp->tx_empty)
577 netif_stop_queue(dev);
578 spin_unlock_irqrestore(&mp->lock, flags);
579
580 return NETDEV_TX_OK;
581}
582
583static void mace_set_multicast(struct net_device *dev)
584{
585 struct mace_data *mp = netdev_priv(dev);
586 volatile struct mace __iomem *mb = mp->mace;
587 int i;
588 u32 crc;
589 unsigned long flags;
590
591 spin_lock_irqsave(&mp->lock, flags);
592 mp->maccc &= ~PROM;
593 if (dev->flags & IFF_PROMISC) {
594 mp->maccc |= PROM;
595 } else {
596 unsigned char multicast_filter[8];
597 struct netdev_hw_addr *ha;
598
599 if (dev->flags & IFF_ALLMULTI) {
600 for (i = 0; i < 8; i++)
601 multicast_filter[i] = 0xff;
602 } else {
603 for (i = 0; i < 8; i++)
604 multicast_filter[i] = 0;
605 netdev_for_each_mc_addr(ha, dev) {
606 crc = ether_crc_le(6, ha->addr);
607 i = crc >> 26; /* bit number in multicast_filter */
608 multicast_filter[i >> 3] |= 1 << (i & 7);
609 }
610 }
611#if 0
612 printk("Multicast filter :");
613 for (i = 0; i < 8; i++)
614 printk("%02x ", multicast_filter[i]);
615 printk("\n");
616#endif
617
618 if (mp->chipid == BROKEN_ADDRCHG_REV)
619 out_8(&mb->iac, LOGADDR);
620 else {
621 out_8(&mb->iac, ADDRCHG | LOGADDR);
622 while ((in_8(&mb->iac) & ADDRCHG) != 0)
623 ;
624 }
625 for (i = 0; i < 8; ++i)
626 out_8(&mb->ladrf, multicast_filter[i]);
627 if (mp->chipid != BROKEN_ADDRCHG_REV)
628 out_8(&mb->iac, 0);
629 }
630 /* reset maccc */
631 out_8(&mb->maccc, mp->maccc);
632 spin_unlock_irqrestore(&mp->lock, flags);
633}
634
635static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev)
636{
637 volatile struct mace __iomem *mb = mp->mace;
638 static int mace_babbles, mace_jabbers;
639
640 if (intr & MPCO)
641 dev->stats.rx_missed_errors += 256;
642 dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
643 if (intr & RNTPCO)
644 dev->stats.rx_length_errors += 256;
645 dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
646 if (intr & CERR)
647 ++dev->stats.tx_heartbeat_errors;
648 if (intr & BABBLE)
649 if (mace_babbles++ < 4)
650 printk(KERN_DEBUG "mace: babbling transmitter\n");
651 if (intr & JABBER)
652 if (mace_jabbers++ < 4)
653 printk(KERN_DEBUG "mace: jabbering transceiver\n");
654}
655
656static irqreturn_t mace_interrupt(int irq, void *dev_id)
657{
658 struct net_device *dev = (struct net_device *) dev_id;
659 struct mace_data *mp = netdev_priv(dev);
660 volatile struct mace __iomem *mb = mp->mace;
661 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
662 volatile struct dbdma_cmd *cp;
663 int intr, fs, i, stat, x;
664 int xcount, dstat;
665 unsigned long flags;
666 /* static int mace_last_fs, mace_last_xcount; */
667
668 spin_lock_irqsave(&mp->lock, flags);
669 intr = in_8(&mb->ir); /* read interrupt register */
670 in_8(&mb->xmtrc); /* get retries */
671 mace_handle_misc_intrs(mp, intr, dev);
672
673 i = mp->tx_empty;
674 while (in_8(&mb->pr) & XMTSV) {
675 del_timer(&mp->tx_timeout);
676 mp->timeout_active = 0;
677 /*
678 * Clear any interrupt indication associated with this status
679 * word. This appears to unlatch any error indication from
680 * the DMA controller.
681 */
682 intr = in_8(&mb->ir);
683 if (intr != 0)
684 mace_handle_misc_intrs(mp, intr, dev);
685 if (mp->tx_bad_runt) {
686 fs = in_8(&mb->xmtfs);
687 mp->tx_bad_runt = 0;
688 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
689 continue;
690 }
691 dstat = le32_to_cpu(td->status);
692 /* stop DMA controller */
693 out_le32(&td->control, RUN << 16);
694 /*
695 * xcount is the number of complete frames which have been
696 * written to the fifo but for which status has not been read.
697 */
698 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
699 if (xcount == 0 || (dstat & DEAD)) {
700 /*
701 * If a packet was aborted before the DMA controller has
702 * finished transferring it, it seems that there are 2 bytes
703 * which are stuck in some buffer somewhere. These will get
704 * transmitted as soon as we read the frame status (which
705 * reenables the transmit data transfer request). Turning
706 * off the DMA controller and/or resetting the MACE doesn't
707 * help. So we disable auto-padding and FCS transmission
708 * so the two bytes will only be a runt packet which should
709 * be ignored by other stations.
710 */
711 out_8(&mb->xmtfc, DXMTFCS);
712 }
713 fs = in_8(&mb->xmtfs);
714 if ((fs & XMTSV) == 0) {
715 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
716 fs, xcount, dstat);
717 mace_reset(dev);
718 /*
719 * XXX mace likes to hang the machine after a xmtfs error.
720 * This is hard to reproduce, resetting *may* help
721 */
722 }
723 cp = mp->tx_cmds + NCMDS_TX * i;
724 stat = le16_to_cpu(cp->xfer_status);
725 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
726 /*
727 * Check whether there were in fact 2 bytes written to
728 * the transmit FIFO.
729 */
730 udelay(1);
731 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
732 if (x != 0) {
733 /* there were two bytes with an end-of-packet indication */
734 mp->tx_bad_runt = 1;
735 mace_set_timeout(dev);
736 } else {
737 /*
738 * Either there weren't the two bytes buffered up, or they
739 * didn't have an end-of-packet indication.
740 * We flush the transmit FIFO just in case (by setting the
741 * XMTFWU bit with the transmitter disabled).
742 */
743 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
744 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
745 udelay(1);
746 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
747 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
748 }
749 }
750 /* dma should have finished */
751 if (i == mp->tx_fill) {
752 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
753 fs, xcount, dstat);
754 continue;
755 }
756 /* Update stats */
757 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
758 ++dev->stats.tx_errors;
759 if (fs & LCAR)
760 ++dev->stats.tx_carrier_errors;
761 if (fs & (UFLO|LCOL|RTRY))
762 ++dev->stats.tx_aborted_errors;
763 } else {
764 dev->stats.tx_bytes += mp->tx_bufs[i]->len;
765 ++dev->stats.tx_packets;
766 }
767 dev_kfree_skb_irq(mp->tx_bufs[i]);
768 --mp->tx_active;
769 if (++i >= N_TX_RING)
770 i = 0;
771#if 0
772 mace_last_fs = fs;
773 mace_last_xcount = xcount;
774#endif
775 }
776
777 if (i != mp->tx_empty) {
778 mp->tx_fullup = 0;
779 netif_wake_queue(dev);
780 }
781 mp->tx_empty = i;
782 i += mp->tx_active;
783 if (i >= N_TX_RING)
784 i -= N_TX_RING;
785 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
786 do {
787 /* set up the next one */
788 cp = mp->tx_cmds + NCMDS_TX * i;
789 out_le16(&cp->xfer_status, 0);
790 out_le16(&cp->command, OUTPUT_LAST);
791 ++mp->tx_active;
792 if (++i >= N_TX_RING)
793 i = 0;
794 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
795 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
796 mace_set_timeout(dev);
797 }
798 spin_unlock_irqrestore(&mp->lock, flags);
799 return IRQ_HANDLED;
800}
801
802static void mace_tx_timeout(struct timer_list *t)
803{
804 struct mace_data *mp = from_timer(mp, t, tx_timeout);
805 struct net_device *dev = macio_get_drvdata(mp->mdev);
806 volatile struct mace __iomem *mb = mp->mace;
807 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
808 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
809 volatile struct dbdma_cmd *cp;
810 unsigned long flags;
811 int i;
812
813 spin_lock_irqsave(&mp->lock, flags);
814 mp->timeout_active = 0;
815 if (mp->tx_active == 0 && !mp->tx_bad_runt)
816 goto out;
817
818 /* update various counters */
819 mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);
820
821 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
822
823 /* turn off both tx and rx and reset the chip */
824 out_8(&mb->maccc, 0);
825 printk(KERN_ERR "mace: transmit timeout - resetting\n");
826 dbdma_reset(td);
827 mace_reset(dev);
828
829 /* restart rx dma */
830 cp = bus_to_virt(le32_to_cpu(rd->cmdptr));
831 dbdma_reset(rd);
832 out_le16(&cp->xfer_status, 0);
833 out_le32(&rd->cmdptr, virt_to_bus(cp));
834 out_le32(&rd->control, (RUN << 16) | RUN);
835
836 /* fix up the transmit side */
837 i = mp->tx_empty;
838 mp->tx_active = 0;
839 ++dev->stats.tx_errors;
840 if (mp->tx_bad_runt) {
841 mp->tx_bad_runt = 0;
842 } else if (i != mp->tx_fill) {
843 dev_kfree_skb(mp->tx_bufs[i]);
844 if (++i >= N_TX_RING)
845 i = 0;
846 mp->tx_empty = i;
847 }
848 mp->tx_fullup = 0;
849 netif_wake_queue(dev);
850 if (i != mp->tx_fill) {
851 cp = mp->tx_cmds + NCMDS_TX * i;
852 out_le16(&cp->xfer_status, 0);
853 out_le16(&cp->command, OUTPUT_LAST);
854 out_le32(&td->cmdptr, virt_to_bus(cp));
855 out_le32(&td->control, (RUN << 16) | RUN);
856 ++mp->tx_active;
857 mace_set_timeout(dev);
858 }
859
860 /* turn it back on */
861 out_8(&mb->imr, RCVINT);
862 out_8(&mb->maccc, mp->maccc);
863
864out:
865 spin_unlock_irqrestore(&mp->lock, flags);
866}
867
868static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
869{
870 return IRQ_HANDLED;
871}
872
873static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
874{
875 struct net_device *dev = (struct net_device *) dev_id;
876 struct mace_data *mp = netdev_priv(dev);
877 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
878 volatile struct dbdma_cmd *cp, *np;
879 int i, nb, stat, next;
880 struct sk_buff *skb;
881 unsigned frame_status;
882 static int mace_lost_status;
883 unsigned char *data;
884 unsigned long flags;
885
886 spin_lock_irqsave(&mp->lock, flags);
887 for (i = mp->rx_empty; i != mp->rx_fill; ) {
888 cp = mp->rx_cmds + i;
889 stat = le16_to_cpu(cp->xfer_status);
890 if ((stat & ACTIVE) == 0) {
891 next = i + 1;
892 if (next >= N_RX_RING)
893 next = 0;
894 np = mp->rx_cmds + next;
895 if (next != mp->rx_fill &&
896 (le16_to_cpu(np->xfer_status) & ACTIVE) != 0) {
897 printk(KERN_DEBUG "mace: lost a status word\n");
898 ++mace_lost_status;
899 } else
900 break;
901 }
902 nb = le16_to_cpu(cp->req_count) - le16_to_cpu(cp->res_count);
903 out_le16(&cp->command, DBDMA_STOP);
904 /* got a packet, have a look at it */
905 skb = mp->rx_bufs[i];
906 if (!skb) {
907 ++dev->stats.rx_dropped;
908 } else if (nb > 8) {
909 data = skb->data;
910 frame_status = (data[nb-3] << 8) + data[nb-4];
911 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
912 ++dev->stats.rx_errors;
913 if (frame_status & RS_OFLO)
914 ++dev->stats.rx_over_errors;
915 if (frame_status & RS_FRAMERR)
916 ++dev->stats.rx_frame_errors;
917 if (frame_status & RS_FCSERR)
918 ++dev->stats.rx_crc_errors;
919 } else {
920 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
921 * FCS on frames with 802.3 headers. This means that Ethernet
922 * frames have 8 extra octets at the end, while 802.3 frames
923 * have only 4. We need to correctly account for this. */
924 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
925 nb -= 4;
926 else /* Ethernet header; mace includes FCS */
927 nb -= 8;
928 skb_put(skb, nb);
929 skb->protocol = eth_type_trans(skb, dev);
930 dev->stats.rx_bytes += skb->len;
931 netif_rx(skb);
932 mp->rx_bufs[i] = NULL;
933 ++dev->stats.rx_packets;
934 }
935 } else {
936 ++dev->stats.rx_errors;
937 ++dev->stats.rx_length_errors;
938 }
939
940 /* advance to next */
941 if (++i >= N_RX_RING)
942 i = 0;
943 }
944 mp->rx_empty = i;
945
946 i = mp->rx_fill;
947 for (;;) {
948 next = i + 1;
949 if (next >= N_RX_RING)
950 next = 0;
951 if (next == mp->rx_empty)
952 break;
953 cp = mp->rx_cmds + i;
954 skb = mp->rx_bufs[i];
955 if (!skb) {
956 skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
957 if (skb) {
958 skb_reserve(skb, 2);
959 mp->rx_bufs[i] = skb;
960 }
961 }
962 cp->req_count = cpu_to_le16(RX_BUFLEN);
963 data = skb? skb->data: dummy_buf;
964 cp->phy_addr = cpu_to_le32(virt_to_bus(data));
965 out_le16(&cp->xfer_status, 0);
966 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
967#if 0
968 if ((le32_to_cpu(rd->status) & ACTIVE) != 0) {
969 out_le32(&rd->control, (PAUSE << 16) | PAUSE);
970 while ((in_le32(&rd->status) & ACTIVE) != 0)
971 ;
972 }
973#endif
974 i = next;
975 }
976 if (i != mp->rx_fill) {
977 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
978 mp->rx_fill = i;
979 }
980 spin_unlock_irqrestore(&mp->lock, flags);
981 return IRQ_HANDLED;
982}
983
984static const struct of_device_id mace_match[] =
985{
986 {
987 .name = "mace",
988 },
989 {},
990};
991MODULE_DEVICE_TABLE (of, mace_match);
992
993static struct macio_driver mace_driver =
994{
995 .driver = {
996 .name = "mace",
997 .owner = THIS_MODULE,
998 .of_match_table = mace_match,
999 },
1000 .probe = mace_probe,
1001 .remove = mace_remove,
1002};
1003
1004
1005static int __init mace_init(void)
1006{
1007 return macio_register_driver(&mace_driver);
1008}
1009
1010static void __exit mace_cleanup(void)
1011{
1012 macio_unregister_driver(&mace_driver);
1013
1014 kfree(dummy_buf);
1015 dummy_buf = NULL;
1016}
1017
1018MODULE_AUTHOR("Paul Mackerras");
1019MODULE_DESCRIPTION("PowerMac MACE driver.");
1020module_param(port_aaui, int, 0);
1021MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1022MODULE_LICENSE("GPL");
1023
1024module_init(mace_init);
1025module_exit(mace_cleanup);