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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13#include <linux/bitfield.h>
14#include <linux/delay.h>
15#include <linux/dsa/mv88e6xxx.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/if_bridge.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/jiffies.h>
23#include <linux/list.h>
24#include <linux/mdio.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/of_irq.h>
28#include <linux/of_mdio.h>
29#include <linux/platform_data/mv88e6xxx.h>
30#include <linux/netdevice.h>
31#include <linux/gpio/consumer.h>
32#include <linux/phylink.h>
33#include <net/dsa.h>
34
35#include "chip.h"
36#include "devlink.h"
37#include "global1.h"
38#include "global2.h"
39#include "hwtstamp.h"
40#include "phy.h"
41#include "port.h"
42#include "ptp.h"
43#include "serdes.h"
44#include "smi.h"
45
46static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47{
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
50 dump_stack();
51 }
52}
53
54int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55{
56 int err;
57
58 assert_reg_lock(chip);
59
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
61 if (err)
62 return err;
63
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65 addr, reg, *val);
66
67 return 0;
68}
69
70int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71{
72 int err;
73
74 assert_reg_lock(chip);
75
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
77 if (err)
78 return err;
79
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81 addr, reg, val);
82
83 return 0;
84}
85
86int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88{
89 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
90 u16 data;
91 int err;
92 int i;
93
94 /* There's no bus specific operation to wait for a mask. Even
95 * if the initial poll takes longer than 50ms, always do at
96 * least one more attempt.
97 */
98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99 err = mv88e6xxx_read(chip, addr, reg, &data);
100 if (err)
101 return err;
102
103 if ((data & mask) == val)
104 return 0;
105
106 if (i < 2)
107 cpu_relax();
108 else
109 usleep_range(1000, 2000);
110 }
111
112 err = mv88e6xxx_read(chip, addr, reg, &data);
113 if (err)
114 return err;
115
116 if ((data & mask) == val)
117 return 0;
118
119 dev_err(chip->dev, "Timeout while waiting for switch\n");
120 return -ETIMEDOUT;
121}
122
123int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
124 int bit, int val)
125{
126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
127 val ? BIT(bit) : 0x0000);
128}
129
130struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
131{
132 struct mv88e6xxx_mdio_bus *mdio_bus;
133
134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
135 list);
136 if (!mdio_bus)
137 return NULL;
138
139 return mdio_bus->bus;
140}
141
142static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
143{
144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
145 unsigned int n = d->hwirq;
146
147 chip->g1_irq.masked |= (1 << n);
148}
149
150static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
151{
152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
153 unsigned int n = d->hwirq;
154
155 chip->g1_irq.masked &= ~(1 << n);
156}
157
158static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
159{
160 unsigned int nhandled = 0;
161 unsigned int sub_irq;
162 unsigned int n;
163 u16 reg;
164 u16 ctl1;
165 int err;
166
167 mv88e6xxx_reg_lock(chip);
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
169 mv88e6xxx_reg_unlock(chip);
170
171 if (err)
172 goto out;
173
174 do {
175 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
176 if (reg & (1 << n)) {
177 sub_irq = irq_find_mapping(chip->g1_irq.domain,
178 n);
179 handle_nested_irq(sub_irq);
180 ++nhandled;
181 }
182 }
183
184 mv88e6xxx_reg_lock(chip);
185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
186 if (err)
187 goto unlock;
188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
189unlock:
190 mv88e6xxx_reg_unlock(chip);
191 if (err)
192 goto out;
193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
194 } while (reg & ctl1);
195
196out:
197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
198}
199
200static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
201{
202 struct mv88e6xxx_chip *chip = dev_id;
203
204 return mv88e6xxx_g1_irq_thread_work(chip);
205}
206
207static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
208{
209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210
211 mv88e6xxx_reg_lock(chip);
212}
213
214static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
215{
216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
218 u16 reg;
219 int err;
220
221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
222 if (err)
223 goto out;
224
225 reg &= ~mask;
226 reg |= (~chip->g1_irq.masked & mask);
227
228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
229 if (err)
230 goto out;
231
232out:
233 mv88e6xxx_reg_unlock(chip);
234}
235
236static const struct irq_chip mv88e6xxx_g1_irq_chip = {
237 .name = "mv88e6xxx-g1",
238 .irq_mask = mv88e6xxx_g1_irq_mask,
239 .irq_unmask = mv88e6xxx_g1_irq_unmask,
240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
242};
243
244static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
245 unsigned int irq,
246 irq_hw_number_t hwirq)
247{
248 struct mv88e6xxx_chip *chip = d->host_data;
249
250 irq_set_chip_data(irq, d->host_data);
251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
252 irq_set_noprobe(irq);
253
254 return 0;
255}
256
257static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
258 .map = mv88e6xxx_g1_irq_domain_map,
259 .xlate = irq_domain_xlate_twocell,
260};
261
262/* To be called with reg_lock held */
263static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
264{
265 int irq, virq;
266 u16 mask;
267
268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
271
272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
273 virq = irq_find_mapping(chip->g1_irq.domain, irq);
274 irq_dispose_mapping(virq);
275 }
276
277 irq_domain_remove(chip->g1_irq.domain);
278}
279
280static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
281{
282 /*
283 * free_irq must be called without reg_lock taken because the irq
284 * handler takes this lock, too.
285 */
286 free_irq(chip->irq, chip);
287
288 mv88e6xxx_reg_lock(chip);
289 mv88e6xxx_g1_irq_free_common(chip);
290 mv88e6xxx_reg_unlock(chip);
291}
292
293static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
294{
295 int err, irq, virq;
296 u16 reg, mask;
297
298 chip->g1_irq.nirqs = chip->info->g1_irqs;
299 chip->g1_irq.domain = irq_domain_add_simple(
300 NULL, chip->g1_irq.nirqs, 0,
301 &mv88e6xxx_g1_irq_domain_ops, chip);
302 if (!chip->g1_irq.domain)
303 return -ENOMEM;
304
305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
306 irq_create_mapping(chip->g1_irq.domain, irq);
307
308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
309 chip->g1_irq.masked = ~0;
310
311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
312 if (err)
313 goto out_mapping;
314
315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
316
317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
318 if (err)
319 goto out_disable;
320
321 /* Reading the interrupt status clears (most of) them */
322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
323 if (err)
324 goto out_disable;
325
326 return 0;
327
328out_disable:
329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
331
332out_mapping:
333 for (irq = 0; irq < 16; irq++) {
334 virq = irq_find_mapping(chip->g1_irq.domain, irq);
335 irq_dispose_mapping(virq);
336 }
337
338 irq_domain_remove(chip->g1_irq.domain);
339
340 return err;
341}
342
343static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
344{
345 static struct lock_class_key lock_key;
346 static struct lock_class_key request_key;
347 int err;
348
349 err = mv88e6xxx_g1_irq_setup_common(chip);
350 if (err)
351 return err;
352
353 /* These lock classes tells lockdep that global 1 irqs are in
354 * a different category than their parent GPIO, so it won't
355 * report false recursion.
356 */
357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
358
359 snprintf(chip->irq_name, sizeof(chip->irq_name),
360 "mv88e6xxx-%s", dev_name(chip->dev));
361
362 mv88e6xxx_reg_unlock(chip);
363 err = request_threaded_irq(chip->irq, NULL,
364 mv88e6xxx_g1_irq_thread_fn,
365 IRQF_ONESHOT | IRQF_SHARED,
366 chip->irq_name, chip);
367 mv88e6xxx_reg_lock(chip);
368 if (err)
369 mv88e6xxx_g1_irq_free_common(chip);
370
371 return err;
372}
373
374static void mv88e6xxx_irq_poll(struct kthread_work *work)
375{
376 struct mv88e6xxx_chip *chip = container_of(work,
377 struct mv88e6xxx_chip,
378 irq_poll_work.work);
379 mv88e6xxx_g1_irq_thread_work(chip);
380
381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
382 msecs_to_jiffies(100));
383}
384
385static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
386{
387 int err;
388
389 err = mv88e6xxx_g1_irq_setup_common(chip);
390 if (err)
391 return err;
392
393 kthread_init_delayed_work(&chip->irq_poll_work,
394 mv88e6xxx_irq_poll);
395
396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
397 if (IS_ERR(chip->kworker))
398 return PTR_ERR(chip->kworker);
399
400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
401 msecs_to_jiffies(100));
402
403 return 0;
404}
405
406static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
407{
408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
409 kthread_destroy_worker(chip->kworker);
410
411 mv88e6xxx_reg_lock(chip);
412 mv88e6xxx_g1_irq_free_common(chip);
413 mv88e6xxx_reg_unlock(chip);
414}
415
416static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
417 int port, phy_interface_t interface)
418{
419 int err;
420
421 if (chip->info->ops->port_set_rgmii_delay) {
422 err = chip->info->ops->port_set_rgmii_delay(chip, port,
423 interface);
424 if (err && err != -EOPNOTSUPP)
425 return err;
426 }
427
428 if (chip->info->ops->port_set_cmode) {
429 err = chip->info->ops->port_set_cmode(chip, port,
430 interface);
431 if (err && err != -EOPNOTSUPP)
432 return err;
433 }
434
435 return 0;
436}
437
438static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
439 int link, int speed, int duplex, int pause,
440 phy_interface_t mode)
441{
442 int err;
443
444 if (!chip->info->ops->port_set_link)
445 return 0;
446
447 /* Port's MAC control must not be changed unless the link is down */
448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
449 if (err)
450 return err;
451
452 if (chip->info->ops->port_set_speed_duplex) {
453 err = chip->info->ops->port_set_speed_duplex(chip, port,
454 speed, duplex);
455 if (err && err != -EOPNOTSUPP)
456 goto restore_link;
457 }
458
459 if (chip->info->ops->port_set_pause) {
460 err = chip->info->ops->port_set_pause(chip, port, pause);
461 if (err)
462 goto restore_link;
463 }
464
465 err = mv88e6xxx_port_config_interface(chip, port, mode);
466restore_link:
467 if (chip->info->ops->port_set_link(chip, port, link))
468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
469
470 return err;
471}
472
473static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
474{
475 return port >= chip->info->internal_phys_offset &&
476 port < chip->info->num_internal_phys +
477 chip->info->internal_phys_offset;
478}
479
480static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
481{
482 u16 reg;
483 int err;
484
485 /* The 88e6250 family does not have the PHY detect bit. Instead,
486 * report whether the port is internal.
487 */
488 if (chip->info->family == MV88E6XXX_FAMILY_6250)
489 return mv88e6xxx_phy_is_internal(chip, port);
490
491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
492 if (err) {
493 dev_err(chip->dev,
494 "p%d: %s: failed to read port status\n",
495 port, __func__);
496 return err;
497 }
498
499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
500}
501
502static const u8 mv88e6185_phy_interface_modes[] = {
503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
510};
511
512static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
513 struct phylink_config *config)
514{
515 u8 cmode = chip->ports[port].cmode;
516
517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
518
519 if (mv88e6xxx_phy_is_internal(chip, port)) {
520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
521 } else {
522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
523 mv88e6185_phy_interface_modes[cmode])
524 __set_bit(mv88e6185_phy_interface_modes[cmode],
525 config->supported_interfaces);
526
527 config->mac_capabilities |= MAC_1000FD;
528 }
529}
530
531static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
532 struct phylink_config *config)
533{
534 u8 cmode = chip->ports[port].cmode;
535
536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
537 mv88e6185_phy_interface_modes[cmode])
538 __set_bit(mv88e6185_phy_interface_modes[cmode],
539 config->supported_interfaces);
540
541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
542 MAC_1000FD;
543}
544
545static const u8 mv88e6xxx_phy_interface_modes[] = {
546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
554 /* higher interface modes are not needed here, since ports supporting
555 * them are writable, and so the supported interfaces are filled in the
556 * corresponding .phylink_set_interfaces() implementation below
557 */
558};
559
560static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
561{
562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
563 mv88e6xxx_phy_interface_modes[cmode])
564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
566 phy_interface_set_rgmii(supported);
567}
568
569static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
570 struct phylink_config *config)
571{
572 unsigned long *supported = config->supported_interfaces;
573
574 /* Translate the default cmode */
575 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
576
577 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
578}
579
580static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
581 struct phylink_config *config)
582{
583 unsigned long *supported = config->supported_interfaces;
584
585 /* Translate the default cmode */
586 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
587
588 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
589 MAC_1000FD;
590}
591
592static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
593{
594 u16 reg, val;
595 int err;
596
597 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®);
598 if (err)
599 return err;
600
601 /* If PHY_DETECT is zero, then we are not in auto-media mode */
602 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
603 return 0xf;
604
605 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
606 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
607 if (err)
608 return err;
609
610 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
611 if (err)
612 return err;
613
614 /* Restore PHY_DETECT value */
615 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
616 if (err)
617 return err;
618
619 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
620}
621
622static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
623 struct phylink_config *config)
624{
625 unsigned long *supported = config->supported_interfaces;
626 int err, cmode;
627
628 /* Translate the default cmode */
629 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
630
631 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
632 MAC_1000FD;
633
634 /* Port 4 supports automedia if the serdes is associated with it. */
635 if (port == 4) {
636 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
637 if (err < 0)
638 dev_err(chip->dev, "p%d: failed to read scratch\n",
639 port);
640 if (err <= 0)
641 return;
642
643 cmode = mv88e6352_get_port4_serdes_cmode(chip);
644 if (cmode < 0)
645 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
646 port);
647 else
648 mv88e6xxx_translate_cmode(cmode, supported);
649 }
650}
651
652static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
653 struct phylink_config *config)
654{
655 unsigned long *supported = config->supported_interfaces;
656
657 /* Translate the default cmode */
658 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
659
660 /* No ethtool bits for 200Mbps */
661 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
662 MAC_1000FD;
663
664 /* The C_Mode field is programmable on port 5 */
665 if (port == 5) {
666 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
667 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
668 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
669
670 config->mac_capabilities |= MAC_2500FD;
671 }
672}
673
674static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
675 struct phylink_config *config)
676{
677 unsigned long *supported = config->supported_interfaces;
678
679 /* Translate the default cmode */
680 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
681
682 /* No ethtool bits for 200Mbps */
683 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
684 MAC_1000FD;
685
686 /* The C_Mode field is programmable on ports 9 and 10 */
687 if (port == 9 || port == 10) {
688 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
689 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
690 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
691
692 config->mac_capabilities |= MAC_2500FD;
693 }
694}
695
696static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
697 struct phylink_config *config)
698{
699 unsigned long *supported = config->supported_interfaces;
700
701 mv88e6390_phylink_get_caps(chip, port, config);
702
703 /* For the 6x90X, ports 2-7 can be in automedia mode.
704 * (Note that 6x90 doesn't support RXAUI nor XAUI).
705 *
706 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
707 * configured for 1000BASE-X, SGMII or 2500BASE-X.
708 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
709 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
710 *
711 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
712 * configured for 1000BASE-X, SGMII or 2500BASE-X.
713 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
714 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
715 *
716 * For now, be permissive (as the old code was) and allow 1000BASE-X
717 * on ports 2..7.
718 */
719 if (port >= 2 && port <= 7)
720 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
721
722 /* The C_Mode field can also be programmed for 10G speeds */
723 if (port == 9 || port == 10) {
724 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
725 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
726
727 config->mac_capabilities |= MAC_10000FD;
728 }
729}
730
731static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
732 struct phylink_config *config)
733{
734 unsigned long *supported = config->supported_interfaces;
735 bool is_6191x =
736 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
737 bool is_6361 =
738 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
739
740 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
741
742 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
743 MAC_1000FD;
744
745 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
746 if (port == 0 || port == 9 || port == 10) {
747 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
748 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
749
750 /* 6191X supports >1G modes only on port 10 */
751 if (!is_6191x || port == 10) {
752 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
753 config->mac_capabilities |= MAC_2500FD;
754
755 /* 6361 only supports up to 2500BaseX */
756 if (!is_6361) {
757 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
758 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
759 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
760 config->mac_capabilities |= MAC_5000FD |
761 MAC_10000FD;
762 }
763 }
764 }
765
766 if (port == 0) {
767 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
768 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
769 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
770 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
771 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
772 }
773}
774
775static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
776 struct phylink_config *config)
777{
778 struct mv88e6xxx_chip *chip = ds->priv;
779
780 mv88e6xxx_reg_lock(chip);
781 chip->info->ops->phylink_get_caps(chip, port, config);
782 mv88e6xxx_reg_unlock(chip);
783
784 if (mv88e6xxx_phy_is_internal(chip, port)) {
785 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
786 config->supported_interfaces);
787 /* Internal ports with no phy-mode need GMII for PHYLIB */
788 __set_bit(PHY_INTERFACE_MODE_GMII,
789 config->supported_interfaces);
790 }
791}
792
793static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds,
794 int port,
795 phy_interface_t interface)
796{
797 struct mv88e6xxx_chip *chip = ds->priv;
798 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
799
800 if (chip->info->ops->pcs_ops)
801 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
802 interface);
803
804 return pcs;
805}
806
807static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port,
808 unsigned int mode, phy_interface_t interface)
809{
810 struct mv88e6xxx_chip *chip = ds->priv;
811 int err = 0;
812
813 /* In inband mode, the link may come up at any time while the link
814 * is not forced down. Force the link down while we reconfigure the
815 * interface mode.
816 */
817 if (mode == MLO_AN_INBAND &&
818 chip->ports[port].interface != interface &&
819 chip->info->ops->port_set_link) {
820 mv88e6xxx_reg_lock(chip);
821 err = chip->info->ops->port_set_link(chip, port,
822 LINK_FORCED_DOWN);
823 mv88e6xxx_reg_unlock(chip);
824 }
825
826 return err;
827}
828
829static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
830 unsigned int mode,
831 const struct phylink_link_state *state)
832{
833 struct mv88e6xxx_chip *chip = ds->priv;
834 int err = 0;
835
836 mv88e6xxx_reg_lock(chip);
837
838 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
839 err = mv88e6xxx_port_config_interface(chip, port,
840 state->interface);
841 if (err && err != -EOPNOTSUPP)
842 goto err_unlock;
843 }
844
845err_unlock:
846 mv88e6xxx_reg_unlock(chip);
847
848 if (err && err != -EOPNOTSUPP)
849 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
850}
851
852static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port,
853 unsigned int mode, phy_interface_t interface)
854{
855 struct mv88e6xxx_chip *chip = ds->priv;
856 int err = 0;
857
858 /* Undo the forced down state above after completing configuration
859 * irrespective of its state on entry, which allows the link to come
860 * up in the in-band case where there is no separate SERDES. Also
861 * ensure that the link can come up if the PPU is in use and we are
862 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
863 */
864 mv88e6xxx_reg_lock(chip);
865
866 if (chip->info->ops->port_set_link &&
867 ((mode == MLO_AN_INBAND &&
868 chip->ports[port].interface != interface) ||
869 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
870 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
871
872 mv88e6xxx_reg_unlock(chip);
873
874 chip->ports[port].interface = interface;
875
876 return err;
877}
878
879static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
880 unsigned int mode,
881 phy_interface_t interface)
882{
883 struct mv88e6xxx_chip *chip = ds->priv;
884 const struct mv88e6xxx_ops *ops;
885 int err = 0;
886
887 ops = chip->info->ops;
888
889 mv88e6xxx_reg_lock(chip);
890 /* Force the link down if we know the port may not be automatically
891 * updated by the switch or if we are using fixed-link mode.
892 */
893 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
894 mode == MLO_AN_FIXED) && ops->port_sync_link)
895 err = ops->port_sync_link(chip, port, mode, false);
896
897 if (!err && ops->port_set_speed_duplex)
898 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
899 DUPLEX_UNFORCED);
900 mv88e6xxx_reg_unlock(chip);
901
902 if (err)
903 dev_err(chip->dev,
904 "p%d: failed to force MAC link down\n", port);
905}
906
907static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
908 unsigned int mode, phy_interface_t interface,
909 struct phy_device *phydev,
910 int speed, int duplex,
911 bool tx_pause, bool rx_pause)
912{
913 struct mv88e6xxx_chip *chip = ds->priv;
914 const struct mv88e6xxx_ops *ops;
915 int err = 0;
916
917 ops = chip->info->ops;
918
919 mv88e6xxx_reg_lock(chip);
920 /* Configure and force the link up if we know that the port may not
921 * automatically updated by the switch or if we are using fixed-link
922 * mode.
923 */
924 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
925 mode == MLO_AN_FIXED) {
926 if (ops->port_set_speed_duplex) {
927 err = ops->port_set_speed_duplex(chip, port,
928 speed, duplex);
929 if (err && err != -EOPNOTSUPP)
930 goto error;
931 }
932
933 if (ops->port_sync_link)
934 err = ops->port_sync_link(chip, port, mode, true);
935 }
936error:
937 mv88e6xxx_reg_unlock(chip);
938
939 if (err && err != -EOPNOTSUPP)
940 dev_err(ds->dev,
941 "p%d: failed to configure MAC link up\n", port);
942}
943
944static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
945{
946 int err;
947
948 if (!chip->info->ops->stats_snapshot)
949 return -EOPNOTSUPP;
950
951 mv88e6xxx_reg_lock(chip);
952 err = chip->info->ops->stats_snapshot(chip, port);
953 mv88e6xxx_reg_unlock(chip);
954
955 return err;
956}
957
958#define MV88E6XXX_HW_STAT_MAPPER(_fn) \
959 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \
960 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \
961 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \
962 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \
963 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \
964 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \
965 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \
966 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \
967 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \
968 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \
969 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \
970 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \
971 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \
972 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \
973 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \
974 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \
975 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \
976 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \
977 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \
978 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \
979 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \
980 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \
981 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \
982 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \
983 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \
984 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \
985 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \
986 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \
987 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \
988 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \
989 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \
990 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \
991 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \
992 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \
993 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \
994 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \
995 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \
996 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \
997 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \
998 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \
999 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \
1000 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \
1001 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \
1002 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \
1003 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \
1004 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \
1005 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \
1006 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \
1007 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \
1008 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \
1009 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \
1010 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \
1011 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \
1012 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \
1013 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \
1014 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \
1015 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \
1016 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \
1017 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \
1018 /* */
1019
1020#define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1021 { #_string, _size, _reg, _type }
1022static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1023 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1024};
1025
1026#define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1027 MV88E6XXX_HW_STAT_ID_ ## _string
1028enum mv88e6xxx_hw_stat_id {
1029 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1030};
1031
1032static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1033 const struct mv88e6xxx_hw_stat *s,
1034 int port, u16 bank1_select,
1035 u16 histogram)
1036{
1037 u32 low;
1038 u32 high = 0;
1039 u16 reg = 0;
1040 int err;
1041 u64 value;
1042
1043 switch (s->type) {
1044 case STATS_TYPE_PORT:
1045 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1046 if (err)
1047 return U64_MAX;
1048
1049 low = reg;
1050 if (s->size == 4) {
1051 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1052 if (err)
1053 return U64_MAX;
1054 low |= ((u32)reg) << 16;
1055 }
1056 break;
1057 case STATS_TYPE_BANK1:
1058 reg = bank1_select;
1059 fallthrough;
1060 case STATS_TYPE_BANK0:
1061 reg |= s->reg | histogram;
1062 mv88e6xxx_g1_stats_read(chip, reg, &low);
1063 if (s->size == 8)
1064 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1065 break;
1066 default:
1067 return U64_MAX;
1068 }
1069 value = (((u64)high) << 32) | low;
1070 return value;
1071}
1072
1073static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1074 uint8_t *data, int types)
1075{
1076 const struct mv88e6xxx_hw_stat *stat;
1077 int i, j;
1078
1079 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1080 stat = &mv88e6xxx_hw_stats[i];
1081 if (stat->type & types) {
1082 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1083 ETH_GSTRING_LEN);
1084 j++;
1085 }
1086 }
1087
1088 return j;
1089}
1090
1091static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1092 uint8_t *data)
1093{
1094 return mv88e6xxx_stats_get_strings(chip, data,
1095 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1096}
1097
1098static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1099 uint8_t *data)
1100{
1101 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1102}
1103
1104static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1105 uint8_t *data)
1106{
1107 return mv88e6xxx_stats_get_strings(chip, data,
1108 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1109}
1110
1111static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1112 "atu_member_violation",
1113 "atu_miss_violation",
1114 "atu_full_violation",
1115 "vtu_member_violation",
1116 "vtu_miss_violation",
1117};
1118
1119static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1120{
1121 unsigned int i;
1122
1123 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1124 strscpy(data + i * ETH_GSTRING_LEN,
1125 mv88e6xxx_atu_vtu_stats_strings[i],
1126 ETH_GSTRING_LEN);
1127}
1128
1129static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1130 u32 stringset, uint8_t *data)
1131{
1132 struct mv88e6xxx_chip *chip = ds->priv;
1133 int count = 0;
1134
1135 if (stringset != ETH_SS_STATS)
1136 return;
1137
1138 mv88e6xxx_reg_lock(chip);
1139
1140 if (chip->info->ops->stats_get_strings)
1141 count = chip->info->ops->stats_get_strings(chip, data);
1142
1143 if (chip->info->ops->serdes_get_strings) {
1144 data += count * ETH_GSTRING_LEN;
1145 count = chip->info->ops->serdes_get_strings(chip, port, data);
1146 }
1147
1148 data += count * ETH_GSTRING_LEN;
1149 mv88e6xxx_atu_vtu_get_strings(data);
1150
1151 mv88e6xxx_reg_unlock(chip);
1152}
1153
1154static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1155 int types)
1156{
1157 const struct mv88e6xxx_hw_stat *stat;
1158 int i, j;
1159
1160 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1161 stat = &mv88e6xxx_hw_stats[i];
1162 if (stat->type & types)
1163 j++;
1164 }
1165 return j;
1166}
1167
1168static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1169{
1170 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1171 STATS_TYPE_PORT);
1172}
1173
1174static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1175{
1176 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1177}
1178
1179static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1180{
1181 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1182 STATS_TYPE_BANK1);
1183}
1184
1185static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1186{
1187 struct mv88e6xxx_chip *chip = ds->priv;
1188 int serdes_count = 0;
1189 int count = 0;
1190
1191 if (sset != ETH_SS_STATS)
1192 return 0;
1193
1194 mv88e6xxx_reg_lock(chip);
1195 if (chip->info->ops->stats_get_sset_count)
1196 count = chip->info->ops->stats_get_sset_count(chip);
1197 if (count < 0)
1198 goto out;
1199
1200 if (chip->info->ops->serdes_get_sset_count)
1201 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1202 port);
1203 if (serdes_count < 0) {
1204 count = serdes_count;
1205 goto out;
1206 }
1207 count += serdes_count;
1208 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1209
1210out:
1211 mv88e6xxx_reg_unlock(chip);
1212
1213 return count;
1214}
1215
1216static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1217 const struct mv88e6xxx_hw_stat *stat,
1218 uint64_t *data)
1219{
1220 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))
1221 return 0;
1222
1223 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1224 MV88E6XXX_G1_STATS_OP_HIST_RX);
1225 return 1;
1226}
1227
1228static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1229 const struct mv88e6xxx_hw_stat *stat,
1230 uint64_t *data)
1231{
1232 if (!(stat->type & STATS_TYPE_BANK0))
1233 return 0;
1234
1235 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1236 MV88E6XXX_G1_STATS_OP_HIST_RX);
1237 return 1;
1238}
1239
1240static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1241 const struct mv88e6xxx_hw_stat *stat,
1242 uint64_t *data)
1243{
1244 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1245 return 0;
1246
1247 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1248 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1249 MV88E6XXX_G1_STATS_OP_HIST_RX);
1250 return 1;
1251}
1252
1253static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1254 const struct mv88e6xxx_hw_stat *stat,
1255 uint64_t *data)
1256{
1257 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1258 return 0;
1259
1260 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1261 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1262 0);
1263 return 1;
1264}
1265
1266static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1267 const struct mv88e6xxx_hw_stat *stat,
1268 uint64_t *data)
1269{
1270 int ret = 0;
1271
1272 if (chip->info->ops->stats_get_stat) {
1273 mv88e6xxx_reg_lock(chip);
1274 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1275 mv88e6xxx_reg_unlock(chip);
1276 }
1277
1278 return ret;
1279}
1280
1281static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1282 uint64_t *data)
1283{
1284 const struct mv88e6xxx_hw_stat *stat;
1285 size_t i, j;
1286
1287 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1288 stat = &mv88e6xxx_hw_stats[i];
1289 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1290 }
1291 return j;
1292}
1293
1294static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1295 uint64_t *data)
1296{
1297 *data++ = chip->ports[port].atu_member_violation;
1298 *data++ = chip->ports[port].atu_miss_violation;
1299 *data++ = chip->ports[port].atu_full_violation;
1300 *data++ = chip->ports[port].vtu_member_violation;
1301 *data++ = chip->ports[port].vtu_miss_violation;
1302}
1303
1304static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1305 uint64_t *data)
1306{
1307 size_t count;
1308
1309 count = mv88e6xxx_stats_get_stats(chip, port, data);
1310
1311 mv88e6xxx_reg_lock(chip);
1312 if (chip->info->ops->serdes_get_stats) {
1313 data += count;
1314 count = chip->info->ops->serdes_get_stats(chip, port, data);
1315 }
1316 data += count;
1317 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1318 mv88e6xxx_reg_unlock(chip);
1319}
1320
1321static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1322 uint64_t *data)
1323{
1324 struct mv88e6xxx_chip *chip = ds->priv;
1325 int ret;
1326
1327 ret = mv88e6xxx_stats_snapshot(chip, port);
1328 if (ret < 0)
1329 return;
1330
1331 mv88e6xxx_get_stats(chip, port, data);
1332}
1333
1334static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1335 struct ethtool_eth_mac_stats *mac_stats)
1336{
1337 struct mv88e6xxx_chip *chip = ds->priv;
1338 int ret;
1339
1340 ret = mv88e6xxx_stats_snapshot(chip, port);
1341 if (ret < 0)
1342 return;
1343
1344#define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \
1345 mv88e6xxx_stats_get_stat(chip, port, \
1346 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1347 &mac_stats->stats._member)
1348
1349 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1350 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1351 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1352 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1353 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1354 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1355 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1356 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1357 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1358 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1359 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1360 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1361 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1362 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1363
1364#undef MV88E6XXX_ETH_MAC_STAT_MAP
1365
1366 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1367 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1368 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1369 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1370}
1371
1372static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1373 struct ethtool_rmon_stats *rmon_stats,
1374 const struct ethtool_rmon_hist_range **ranges)
1375{
1376 static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1377 { 64, 64 },
1378 { 65, 127 },
1379 { 128, 255 },
1380 { 256, 511 },
1381 { 512, 1023 },
1382 { 1024, 65535 },
1383 {}
1384 };
1385 struct mv88e6xxx_chip *chip = ds->priv;
1386 int ret;
1387
1388 ret = mv88e6xxx_stats_snapshot(chip, port);
1389 if (ret < 0)
1390 return;
1391
1392#define MV88E6XXX_RMON_STAT_MAP(_id, _member) \
1393 mv88e6xxx_stats_get_stat(chip, port, \
1394 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1395 &rmon_stats->stats._member)
1396
1397 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1398 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1399 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1400 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1401 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1402 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1403 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1404 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1405 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1406 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1407
1408#undef MV88E6XXX_RMON_STAT_MAP
1409
1410 *ranges = rmon_ranges;
1411}
1412
1413static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1414{
1415 struct mv88e6xxx_chip *chip = ds->priv;
1416 int len;
1417
1418 len = 32 * sizeof(u16);
1419 if (chip->info->ops->serdes_get_regs_len)
1420 len += chip->info->ops->serdes_get_regs_len(chip, port);
1421
1422 return len;
1423}
1424
1425static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1426 struct ethtool_regs *regs, void *_p)
1427{
1428 struct mv88e6xxx_chip *chip = ds->priv;
1429 int err;
1430 u16 reg;
1431 u16 *p = _p;
1432 int i;
1433
1434 regs->version = chip->info->prod_num;
1435
1436 memset(p, 0xff, 32 * sizeof(u16));
1437
1438 mv88e6xxx_reg_lock(chip);
1439
1440 for (i = 0; i < 32; i++) {
1441
1442 err = mv88e6xxx_port_read(chip, port, i, ®);
1443 if (!err)
1444 p[i] = reg;
1445 }
1446
1447 if (chip->info->ops->serdes_get_regs)
1448 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1449
1450 mv88e6xxx_reg_unlock(chip);
1451}
1452
1453static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1454 struct ethtool_eee *e)
1455{
1456 /* Nothing to do on the port's MAC */
1457 return 0;
1458}
1459
1460static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1461 struct ethtool_eee *e)
1462{
1463 /* Nothing to do on the port's MAC */
1464 return 0;
1465}
1466
1467/* Mask of the local ports allowed to receive frames from a given fabric port */
1468static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1469{
1470 struct dsa_switch *ds = chip->ds;
1471 struct dsa_switch_tree *dst = ds->dst;
1472 struct dsa_port *dp, *other_dp;
1473 bool found = false;
1474 u16 pvlan;
1475
1476 /* dev is a physical switch */
1477 if (dev <= dst->last_switch) {
1478 list_for_each_entry(dp, &dst->ports, list) {
1479 if (dp->ds->index == dev && dp->index == port) {
1480 /* dp might be a DSA link or a user port, so it
1481 * might or might not have a bridge.
1482 * Use the "found" variable for both cases.
1483 */
1484 found = true;
1485 break;
1486 }
1487 }
1488 /* dev is a virtual bridge */
1489 } else {
1490 list_for_each_entry(dp, &dst->ports, list) {
1491 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1492
1493 if (!bridge_num)
1494 continue;
1495
1496 if (bridge_num + dst->last_switch != dev)
1497 continue;
1498
1499 found = true;
1500 break;
1501 }
1502 }
1503
1504 /* Prevent frames from unknown switch or virtual bridge */
1505 if (!found)
1506 return 0;
1507
1508 /* Frames from DSA links and CPU ports can egress any local port */
1509 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1510 return mv88e6xxx_port_mask(chip);
1511
1512 pvlan = 0;
1513
1514 /* Frames from standalone user ports can only egress on the
1515 * upstream port.
1516 */
1517 if (!dsa_port_bridge_dev_get(dp))
1518 return BIT(dsa_switch_upstream_port(ds));
1519
1520 /* Frames from bridged user ports can egress any local DSA
1521 * links and CPU ports, as well as any local member of their
1522 * bridge group.
1523 */
1524 dsa_switch_for_each_port(other_dp, ds)
1525 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1526 other_dp->type == DSA_PORT_TYPE_DSA ||
1527 dsa_port_bridge_same(dp, other_dp))
1528 pvlan |= BIT(other_dp->index);
1529
1530 return pvlan;
1531}
1532
1533static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1534{
1535 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1536
1537 /* prevent frames from going back out of the port they came in on */
1538 output_ports &= ~BIT(port);
1539
1540 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1541}
1542
1543static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1544 u8 state)
1545{
1546 struct mv88e6xxx_chip *chip = ds->priv;
1547 int err;
1548
1549 mv88e6xxx_reg_lock(chip);
1550 err = mv88e6xxx_port_set_state(chip, port, state);
1551 mv88e6xxx_reg_unlock(chip);
1552
1553 if (err)
1554 dev_err(ds->dev, "p%d: failed to update state\n", port);
1555}
1556
1557static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1558{
1559 int err;
1560
1561 if (chip->info->ops->ieee_pri_map) {
1562 err = chip->info->ops->ieee_pri_map(chip);
1563 if (err)
1564 return err;
1565 }
1566
1567 if (chip->info->ops->ip_pri_map) {
1568 err = chip->info->ops->ip_pri_map(chip);
1569 if (err)
1570 return err;
1571 }
1572
1573 return 0;
1574}
1575
1576static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1577{
1578 struct dsa_switch *ds = chip->ds;
1579 int target, port;
1580 int err;
1581
1582 if (!chip->info->global2_addr)
1583 return 0;
1584
1585 /* Initialize the routing port to the 32 possible target devices */
1586 for (target = 0; target < 32; target++) {
1587 port = dsa_routing_port(ds, target);
1588 if (port == ds->num_ports)
1589 port = 0x1f;
1590
1591 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1592 if (err)
1593 return err;
1594 }
1595
1596 if (chip->info->ops->set_cascade_port) {
1597 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1598 err = chip->info->ops->set_cascade_port(chip, port);
1599 if (err)
1600 return err;
1601 }
1602
1603 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1604 if (err)
1605 return err;
1606
1607 return 0;
1608}
1609
1610static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1611{
1612 /* Clear all trunk masks and mapping */
1613 if (chip->info->global2_addr)
1614 return mv88e6xxx_g2_trunk_clear(chip);
1615
1616 return 0;
1617}
1618
1619static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1620{
1621 if (chip->info->ops->rmu_disable)
1622 return chip->info->ops->rmu_disable(chip);
1623
1624 return 0;
1625}
1626
1627static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1628{
1629 if (chip->info->ops->pot_clear)
1630 return chip->info->ops->pot_clear(chip);
1631
1632 return 0;
1633}
1634
1635static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1636{
1637 if (chip->info->ops->mgmt_rsvd2cpu)
1638 return chip->info->ops->mgmt_rsvd2cpu(chip);
1639
1640 return 0;
1641}
1642
1643static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1644{
1645 int err;
1646
1647 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1648 if (err)
1649 return err;
1650
1651 /* The chips that have a "learn2all" bit in Global1, ATU
1652 * Control are precisely those whose port registers have a
1653 * Message Port bit in Port Control 1 and hence implement
1654 * ->port_setup_message_port.
1655 */
1656 if (chip->info->ops->port_setup_message_port) {
1657 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1658 if (err)
1659 return err;
1660 }
1661
1662 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1663}
1664
1665static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1666{
1667 int port;
1668 int err;
1669
1670 if (!chip->info->ops->irl_init_all)
1671 return 0;
1672
1673 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1674 /* Disable ingress rate limiting by resetting all per port
1675 * ingress rate limit resources to their initial state.
1676 */
1677 err = chip->info->ops->irl_init_all(chip, port);
1678 if (err)
1679 return err;
1680 }
1681
1682 return 0;
1683}
1684
1685static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1686{
1687 if (chip->info->ops->set_switch_mac) {
1688 u8 addr[ETH_ALEN];
1689
1690 eth_random_addr(addr);
1691
1692 return chip->info->ops->set_switch_mac(chip, addr);
1693 }
1694
1695 return 0;
1696}
1697
1698static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1699{
1700 struct dsa_switch_tree *dst = chip->ds->dst;
1701 struct dsa_switch *ds;
1702 struct dsa_port *dp;
1703 u16 pvlan = 0;
1704
1705 if (!mv88e6xxx_has_pvt(chip))
1706 return 0;
1707
1708 /* Skip the local source device, which uses in-chip port VLAN */
1709 if (dev != chip->ds->index) {
1710 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1711
1712 ds = dsa_switch_find(dst->index, dev);
1713 dp = ds ? dsa_to_port(ds, port) : NULL;
1714 if (dp && dp->lag) {
1715 /* As the PVT is used to limit flooding of
1716 * FORWARD frames, which use the LAG ID as the
1717 * source port, we must translate dev/port to
1718 * the special "LAG device" in the PVT, using
1719 * the LAG ID (one-based) as the port number
1720 * (zero-based).
1721 */
1722 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1723 port = dsa_port_lag_id_get(dp) - 1;
1724 }
1725 }
1726
1727 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1728}
1729
1730static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1731{
1732 int dev, port;
1733 int err;
1734
1735 if (!mv88e6xxx_has_pvt(chip))
1736 return 0;
1737
1738 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1739 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1740 */
1741 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1742 if (err)
1743 return err;
1744
1745 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1746 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1747 err = mv88e6xxx_pvt_map(chip, dev, port);
1748 if (err)
1749 return err;
1750 }
1751 }
1752
1753 return 0;
1754}
1755
1756static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1757 u16 fid)
1758{
1759 if (dsa_to_port(chip->ds, port)->lag)
1760 /* Hardware is incapable of fast-aging a LAG through a
1761 * regular ATU move operation. Until we have something
1762 * more fancy in place this is a no-op.
1763 */
1764 return -EOPNOTSUPP;
1765
1766 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1767}
1768
1769static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1770{
1771 struct mv88e6xxx_chip *chip = ds->priv;
1772 int err;
1773
1774 mv88e6xxx_reg_lock(chip);
1775 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1776 mv88e6xxx_reg_unlock(chip);
1777
1778 if (err)
1779 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1780 port, err);
1781}
1782
1783static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1784{
1785 if (!mv88e6xxx_max_vid(chip))
1786 return 0;
1787
1788 return mv88e6xxx_g1_vtu_flush(chip);
1789}
1790
1791static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1792 struct mv88e6xxx_vtu_entry *entry)
1793{
1794 int err;
1795
1796 if (!chip->info->ops->vtu_getnext)
1797 return -EOPNOTSUPP;
1798
1799 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1800 entry->valid = false;
1801
1802 err = chip->info->ops->vtu_getnext(chip, entry);
1803
1804 if (entry->vid != vid)
1805 entry->valid = false;
1806
1807 return err;
1808}
1809
1810int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1811 int (*cb)(struct mv88e6xxx_chip *chip,
1812 const struct mv88e6xxx_vtu_entry *entry,
1813 void *priv),
1814 void *priv)
1815{
1816 struct mv88e6xxx_vtu_entry entry = {
1817 .vid = mv88e6xxx_max_vid(chip),
1818 .valid = false,
1819 };
1820 int err;
1821
1822 if (!chip->info->ops->vtu_getnext)
1823 return -EOPNOTSUPP;
1824
1825 do {
1826 err = chip->info->ops->vtu_getnext(chip, &entry);
1827 if (err)
1828 return err;
1829
1830 if (!entry.valid)
1831 break;
1832
1833 err = cb(chip, &entry, priv);
1834 if (err)
1835 return err;
1836 } while (entry.vid < mv88e6xxx_max_vid(chip));
1837
1838 return 0;
1839}
1840
1841static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1842 struct mv88e6xxx_vtu_entry *entry)
1843{
1844 if (!chip->info->ops->vtu_loadpurge)
1845 return -EOPNOTSUPP;
1846
1847 return chip->info->ops->vtu_loadpurge(chip, entry);
1848}
1849
1850static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1851 const struct mv88e6xxx_vtu_entry *entry,
1852 void *_fid_bitmap)
1853{
1854 unsigned long *fid_bitmap = _fid_bitmap;
1855
1856 set_bit(entry->fid, fid_bitmap);
1857 return 0;
1858}
1859
1860int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1861{
1862 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1863
1864 /* Every FID has an associated VID, so walking the VTU
1865 * will discover the full set of FIDs in use.
1866 */
1867 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1868}
1869
1870static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1871{
1872 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1873 int err;
1874
1875 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1876 if (err)
1877 return err;
1878
1879 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1880 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1881 return -ENOSPC;
1882
1883 /* Clear the database */
1884 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1885}
1886
1887static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1888 struct mv88e6xxx_stu_entry *entry)
1889{
1890 if (!chip->info->ops->stu_loadpurge)
1891 return -EOPNOTSUPP;
1892
1893 return chip->info->ops->stu_loadpurge(chip, entry);
1894}
1895
1896static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1897{
1898 struct mv88e6xxx_stu_entry stu = {
1899 .valid = true,
1900 .sid = 0
1901 };
1902
1903 if (!mv88e6xxx_has_stu(chip))
1904 return 0;
1905
1906 /* Make sure that SID 0 is always valid. This is used by VTU
1907 * entries that do not make use of the STU, e.g. when creating
1908 * a VLAN upper on a port that is also part of a VLAN
1909 * filtering bridge.
1910 */
1911 return mv88e6xxx_stu_loadpurge(chip, &stu);
1912}
1913
1914static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1915{
1916 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1917 struct mv88e6xxx_mst *mst;
1918
1919 __set_bit(0, busy);
1920
1921 list_for_each_entry(mst, &chip->msts, node)
1922 __set_bit(mst->stu.sid, busy);
1923
1924 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1925
1926 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1927}
1928
1929static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1930{
1931 struct mv88e6xxx_mst *mst, *tmp;
1932 int err;
1933
1934 if (!sid)
1935 return 0;
1936
1937 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1938 if (mst->stu.sid != sid)
1939 continue;
1940
1941 if (!refcount_dec_and_test(&mst->refcnt))
1942 return 0;
1943
1944 mst->stu.valid = false;
1945 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1946 if (err) {
1947 refcount_set(&mst->refcnt, 1);
1948 return err;
1949 }
1950
1951 list_del(&mst->node);
1952 kfree(mst);
1953 return 0;
1954 }
1955
1956 return -ENOENT;
1957}
1958
1959static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1960 u16 msti, u8 *sid)
1961{
1962 struct mv88e6xxx_mst *mst;
1963 int err, i;
1964
1965 if (!mv88e6xxx_has_stu(chip)) {
1966 err = -EOPNOTSUPP;
1967 goto err;
1968 }
1969
1970 if (!msti) {
1971 *sid = 0;
1972 return 0;
1973 }
1974
1975 list_for_each_entry(mst, &chip->msts, node) {
1976 if (mst->br == br && mst->msti == msti) {
1977 refcount_inc(&mst->refcnt);
1978 *sid = mst->stu.sid;
1979 return 0;
1980 }
1981 }
1982
1983 err = mv88e6xxx_sid_get(chip, sid);
1984 if (err)
1985 goto err;
1986
1987 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1988 if (!mst) {
1989 err = -ENOMEM;
1990 goto err;
1991 }
1992
1993 INIT_LIST_HEAD(&mst->node);
1994 refcount_set(&mst->refcnt, 1);
1995 mst->br = br;
1996 mst->msti = msti;
1997 mst->stu.valid = true;
1998 mst->stu.sid = *sid;
1999
2000 /* The bridge starts out all ports in the disabled state. But
2001 * a STU state of disabled means to go by the port-global
2002 * state. So we set all user port's initial state to blocking,
2003 * to match the bridge's behavior.
2004 */
2005 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2006 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2007 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2008 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2009
2010 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2011 if (err)
2012 goto err_free;
2013
2014 list_add_tail(&mst->node, &chip->msts);
2015 return 0;
2016
2017err_free:
2018 kfree(mst);
2019err:
2020 return err;
2021}
2022
2023static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2024 const struct switchdev_mst_state *st)
2025{
2026 struct dsa_port *dp = dsa_to_port(ds, port);
2027 struct mv88e6xxx_chip *chip = ds->priv;
2028 struct mv88e6xxx_mst *mst;
2029 u8 state;
2030 int err;
2031
2032 if (!mv88e6xxx_has_stu(chip))
2033 return -EOPNOTSUPP;
2034
2035 switch (st->state) {
2036 case BR_STATE_DISABLED:
2037 case BR_STATE_BLOCKING:
2038 case BR_STATE_LISTENING:
2039 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2040 break;
2041 case BR_STATE_LEARNING:
2042 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2043 break;
2044 case BR_STATE_FORWARDING:
2045 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2046 break;
2047 default:
2048 return -EINVAL;
2049 }
2050
2051 list_for_each_entry(mst, &chip->msts, node) {
2052 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2053 mst->msti == st->msti) {
2054 if (mst->stu.state[port] == state)
2055 return 0;
2056
2057 mst->stu.state[port] = state;
2058 mv88e6xxx_reg_lock(chip);
2059 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2060 mv88e6xxx_reg_unlock(chip);
2061 return err;
2062 }
2063 }
2064
2065 return -ENOENT;
2066}
2067
2068static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2069 u16 vid)
2070{
2071 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2072 struct mv88e6xxx_chip *chip = ds->priv;
2073 struct mv88e6xxx_vtu_entry vlan;
2074 int err;
2075
2076 /* DSA and CPU ports have to be members of multiple vlans */
2077 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2078 return 0;
2079
2080 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2081 if (err)
2082 return err;
2083
2084 if (!vlan.valid)
2085 return 0;
2086
2087 dsa_switch_for_each_user_port(other_dp, ds) {
2088 struct net_device *other_br;
2089
2090 if (vlan.member[other_dp->index] ==
2091 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2092 continue;
2093
2094 if (dsa_port_bridge_same(dp, other_dp))
2095 break; /* same bridge, check next VLAN */
2096
2097 other_br = dsa_port_bridge_dev_get(other_dp);
2098 if (!other_br)
2099 continue;
2100
2101 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2102 port, vlan.vid, other_dp->index, netdev_name(other_br));
2103 return -EOPNOTSUPP;
2104 }
2105
2106 return 0;
2107}
2108
2109static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2110{
2111 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2112 struct net_device *br = dsa_port_bridge_dev_get(dp);
2113 struct mv88e6xxx_port *p = &chip->ports[port];
2114 u16 pvid = MV88E6XXX_VID_STANDALONE;
2115 bool drop_untagged = false;
2116 int err;
2117
2118 if (br) {
2119 if (br_vlan_enabled(br)) {
2120 pvid = p->bridge_pvid.vid;
2121 drop_untagged = !p->bridge_pvid.valid;
2122 } else {
2123 pvid = MV88E6XXX_VID_BRIDGED;
2124 }
2125 }
2126
2127 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2128 if (err)
2129 return err;
2130
2131 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2132}
2133
2134static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2135 bool vlan_filtering,
2136 struct netlink_ext_ack *extack)
2137{
2138 struct mv88e6xxx_chip *chip = ds->priv;
2139 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2140 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2141 int err;
2142
2143 if (!mv88e6xxx_max_vid(chip))
2144 return -EOPNOTSUPP;
2145
2146 mv88e6xxx_reg_lock(chip);
2147
2148 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2149 if (err)
2150 goto unlock;
2151
2152 err = mv88e6xxx_port_commit_pvid(chip, port);
2153 if (err)
2154 goto unlock;
2155
2156unlock:
2157 mv88e6xxx_reg_unlock(chip);
2158
2159 return err;
2160}
2161
2162static int
2163mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2164 const struct switchdev_obj_port_vlan *vlan)
2165{
2166 struct mv88e6xxx_chip *chip = ds->priv;
2167 int err;
2168
2169 if (!mv88e6xxx_max_vid(chip))
2170 return -EOPNOTSUPP;
2171
2172 /* If the requested port doesn't belong to the same bridge as the VLAN
2173 * members, do not support it (yet) and fallback to software VLAN.
2174 */
2175 mv88e6xxx_reg_lock(chip);
2176 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2177 mv88e6xxx_reg_unlock(chip);
2178
2179 return err;
2180}
2181
2182static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2183 const unsigned char *addr, u16 vid,
2184 u8 state)
2185{
2186 struct mv88e6xxx_atu_entry entry;
2187 struct mv88e6xxx_vtu_entry vlan;
2188 u16 fid;
2189 int err;
2190
2191 /* Ports have two private address databases: one for when the port is
2192 * standalone and one for when the port is under a bridge and the
2193 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2194 * address database to remain 100% empty, so we never load an ATU entry
2195 * into a standalone port's database. Therefore, translate the null
2196 * VLAN ID into the port's database used for VLAN-unaware bridging.
2197 */
2198 if (vid == 0) {
2199 fid = MV88E6XXX_FID_BRIDGED;
2200 } else {
2201 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2202 if (err)
2203 return err;
2204
2205 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2206 if (!vlan.valid)
2207 return -EOPNOTSUPP;
2208
2209 fid = vlan.fid;
2210 }
2211
2212 entry.state = 0;
2213 ether_addr_copy(entry.mac, addr);
2214 eth_addr_dec(entry.mac);
2215
2216 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2217 if (err)
2218 return err;
2219
2220 /* Initialize a fresh ATU entry if it isn't found */
2221 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2222 memset(&entry, 0, sizeof(entry));
2223 ether_addr_copy(entry.mac, addr);
2224 }
2225
2226 /* Purge the ATU entry only if no port is using it anymore */
2227 if (!state) {
2228 entry.portvec &= ~BIT(port);
2229 if (!entry.portvec)
2230 entry.state = 0;
2231 } else {
2232 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2233 entry.portvec = BIT(port);
2234 else
2235 entry.portvec |= BIT(port);
2236
2237 entry.state = state;
2238 }
2239
2240 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2241}
2242
2243static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2244 const struct mv88e6xxx_policy *policy)
2245{
2246 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2247 enum mv88e6xxx_policy_action action = policy->action;
2248 const u8 *addr = policy->addr;
2249 u16 vid = policy->vid;
2250 u8 state;
2251 int err;
2252 int id;
2253
2254 if (!chip->info->ops->port_set_policy)
2255 return -EOPNOTSUPP;
2256
2257 switch (mapping) {
2258 case MV88E6XXX_POLICY_MAPPING_DA:
2259 case MV88E6XXX_POLICY_MAPPING_SA:
2260 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2261 state = 0; /* Dissociate the port and address */
2262 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2263 is_multicast_ether_addr(addr))
2264 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2265 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2266 is_unicast_ether_addr(addr))
2267 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2268 else
2269 return -EOPNOTSUPP;
2270
2271 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2272 state);
2273 if (err)
2274 return err;
2275 break;
2276 default:
2277 return -EOPNOTSUPP;
2278 }
2279
2280 /* Skip the port's policy clearing if the mapping is still in use */
2281 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2282 idr_for_each_entry(&chip->policies, policy, id)
2283 if (policy->port == port &&
2284 policy->mapping == mapping &&
2285 policy->action != action)
2286 return 0;
2287
2288 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2289}
2290
2291static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2292 struct ethtool_rx_flow_spec *fs)
2293{
2294 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2295 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2296 enum mv88e6xxx_policy_mapping mapping;
2297 enum mv88e6xxx_policy_action action;
2298 struct mv88e6xxx_policy *policy;
2299 u16 vid = 0;
2300 u8 *addr;
2301 int err;
2302 int id;
2303
2304 if (fs->location != RX_CLS_LOC_ANY)
2305 return -EINVAL;
2306
2307 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2308 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2309 else
2310 return -EOPNOTSUPP;
2311
2312 switch (fs->flow_type & ~FLOW_EXT) {
2313 case ETHER_FLOW:
2314 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2315 is_zero_ether_addr(mac_mask->h_source)) {
2316 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2317 addr = mac_entry->h_dest;
2318 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2319 !is_zero_ether_addr(mac_mask->h_source)) {
2320 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2321 addr = mac_entry->h_source;
2322 } else {
2323 /* Cannot support DA and SA mapping in the same rule */
2324 return -EOPNOTSUPP;
2325 }
2326 break;
2327 default:
2328 return -EOPNOTSUPP;
2329 }
2330
2331 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2332 if (fs->m_ext.vlan_tci != htons(0xffff))
2333 return -EOPNOTSUPP;
2334 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2335 }
2336
2337 idr_for_each_entry(&chip->policies, policy, id) {
2338 if (policy->port == port && policy->mapping == mapping &&
2339 policy->action == action && policy->vid == vid &&
2340 ether_addr_equal(policy->addr, addr))
2341 return -EEXIST;
2342 }
2343
2344 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2345 if (!policy)
2346 return -ENOMEM;
2347
2348 fs->location = 0;
2349 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2350 GFP_KERNEL);
2351 if (err) {
2352 devm_kfree(chip->dev, policy);
2353 return err;
2354 }
2355
2356 memcpy(&policy->fs, fs, sizeof(*fs));
2357 ether_addr_copy(policy->addr, addr);
2358 policy->mapping = mapping;
2359 policy->action = action;
2360 policy->port = port;
2361 policy->vid = vid;
2362
2363 err = mv88e6xxx_policy_apply(chip, port, policy);
2364 if (err) {
2365 idr_remove(&chip->policies, fs->location);
2366 devm_kfree(chip->dev, policy);
2367 return err;
2368 }
2369
2370 return 0;
2371}
2372
2373static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2374 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2375{
2376 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2377 struct mv88e6xxx_chip *chip = ds->priv;
2378 struct mv88e6xxx_policy *policy;
2379 int err;
2380 int id;
2381
2382 mv88e6xxx_reg_lock(chip);
2383
2384 switch (rxnfc->cmd) {
2385 case ETHTOOL_GRXCLSRLCNT:
2386 rxnfc->data = 0;
2387 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2388 rxnfc->rule_cnt = 0;
2389 idr_for_each_entry(&chip->policies, policy, id)
2390 if (policy->port == port)
2391 rxnfc->rule_cnt++;
2392 err = 0;
2393 break;
2394 case ETHTOOL_GRXCLSRULE:
2395 err = -ENOENT;
2396 policy = idr_find(&chip->policies, fs->location);
2397 if (policy) {
2398 memcpy(fs, &policy->fs, sizeof(*fs));
2399 err = 0;
2400 }
2401 break;
2402 case ETHTOOL_GRXCLSRLALL:
2403 rxnfc->data = 0;
2404 rxnfc->rule_cnt = 0;
2405 idr_for_each_entry(&chip->policies, policy, id)
2406 if (policy->port == port)
2407 rule_locs[rxnfc->rule_cnt++] = id;
2408 err = 0;
2409 break;
2410 default:
2411 err = -EOPNOTSUPP;
2412 break;
2413 }
2414
2415 mv88e6xxx_reg_unlock(chip);
2416
2417 return err;
2418}
2419
2420static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2421 struct ethtool_rxnfc *rxnfc)
2422{
2423 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2424 struct mv88e6xxx_chip *chip = ds->priv;
2425 struct mv88e6xxx_policy *policy;
2426 int err;
2427
2428 mv88e6xxx_reg_lock(chip);
2429
2430 switch (rxnfc->cmd) {
2431 case ETHTOOL_SRXCLSRLINS:
2432 err = mv88e6xxx_policy_insert(chip, port, fs);
2433 break;
2434 case ETHTOOL_SRXCLSRLDEL:
2435 err = -ENOENT;
2436 policy = idr_remove(&chip->policies, fs->location);
2437 if (policy) {
2438 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2439 err = mv88e6xxx_policy_apply(chip, port, policy);
2440 devm_kfree(chip->dev, policy);
2441 }
2442 break;
2443 default:
2444 err = -EOPNOTSUPP;
2445 break;
2446 }
2447
2448 mv88e6xxx_reg_unlock(chip);
2449
2450 return err;
2451}
2452
2453static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2454 u16 vid)
2455{
2456 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2457 u8 broadcast[ETH_ALEN];
2458
2459 eth_broadcast_addr(broadcast);
2460
2461 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2462}
2463
2464static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2465{
2466 int port;
2467 int err;
2468
2469 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2470 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2471 struct net_device *brport;
2472
2473 if (dsa_is_unused_port(chip->ds, port))
2474 continue;
2475
2476 brport = dsa_port_to_bridge_port(dp);
2477 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2478 /* Skip bridged user ports where broadcast
2479 * flooding is disabled.
2480 */
2481 continue;
2482
2483 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2484 if (err)
2485 return err;
2486 }
2487
2488 return 0;
2489}
2490
2491struct mv88e6xxx_port_broadcast_sync_ctx {
2492 int port;
2493 bool flood;
2494};
2495
2496static int
2497mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2498 const struct mv88e6xxx_vtu_entry *vlan,
2499 void *_ctx)
2500{
2501 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2502 u8 broadcast[ETH_ALEN];
2503 u8 state;
2504
2505 if (ctx->flood)
2506 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2507 else
2508 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2509
2510 eth_broadcast_addr(broadcast);
2511
2512 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2513 vlan->vid, state);
2514}
2515
2516static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2517 bool flood)
2518{
2519 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2520 .port = port,
2521 .flood = flood,
2522 };
2523 struct mv88e6xxx_vtu_entry vid0 = {
2524 .vid = 0,
2525 };
2526 int err;
2527
2528 /* Update the port's private database... */
2529 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2530 if (err)
2531 return err;
2532
2533 /* ...and the database for all VLANs. */
2534 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2535 &ctx);
2536}
2537
2538static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2539 u16 vid, u8 member, bool warn)
2540{
2541 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2542 struct mv88e6xxx_vtu_entry vlan;
2543 int i, err;
2544
2545 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2546 if (err)
2547 return err;
2548
2549 if (!vlan.valid) {
2550 memset(&vlan, 0, sizeof(vlan));
2551
2552 if (vid == MV88E6XXX_VID_STANDALONE)
2553 vlan.policy = true;
2554
2555 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2556 if (err)
2557 return err;
2558
2559 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2560 if (i == port)
2561 vlan.member[i] = member;
2562 else
2563 vlan.member[i] = non_member;
2564
2565 vlan.vid = vid;
2566 vlan.valid = true;
2567
2568 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2569 if (err)
2570 return err;
2571
2572 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2573 if (err)
2574 return err;
2575 } else if (vlan.member[port] != member) {
2576 vlan.member[port] = member;
2577
2578 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2579 if (err)
2580 return err;
2581 } else if (warn) {
2582 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2583 port, vid);
2584 }
2585
2586 return 0;
2587}
2588
2589static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2590 const struct switchdev_obj_port_vlan *vlan,
2591 struct netlink_ext_ack *extack)
2592{
2593 struct mv88e6xxx_chip *chip = ds->priv;
2594 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2595 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2596 struct mv88e6xxx_port *p = &chip->ports[port];
2597 bool warn;
2598 u8 member;
2599 int err;
2600
2601 if (!vlan->vid)
2602 return 0;
2603
2604 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2605 if (err)
2606 return err;
2607
2608 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2609 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2610 else if (untagged)
2611 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2612 else
2613 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2614
2615 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2616 * and then the CPU port. Do not warn for duplicates for the CPU port.
2617 */
2618 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2619
2620 mv88e6xxx_reg_lock(chip);
2621
2622 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2623 if (err) {
2624 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2625 vlan->vid, untagged ? 'u' : 't');
2626 goto out;
2627 }
2628
2629 if (pvid) {
2630 p->bridge_pvid.vid = vlan->vid;
2631 p->bridge_pvid.valid = true;
2632
2633 err = mv88e6xxx_port_commit_pvid(chip, port);
2634 if (err)
2635 goto out;
2636 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2637 /* The old pvid was reinstalled as a non-pvid VLAN */
2638 p->bridge_pvid.valid = false;
2639
2640 err = mv88e6xxx_port_commit_pvid(chip, port);
2641 if (err)
2642 goto out;
2643 }
2644
2645out:
2646 mv88e6xxx_reg_unlock(chip);
2647
2648 return err;
2649}
2650
2651static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2652 int port, u16 vid)
2653{
2654 struct mv88e6xxx_vtu_entry vlan;
2655 int i, err;
2656
2657 if (!vid)
2658 return 0;
2659
2660 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2661 if (err)
2662 return err;
2663
2664 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2665 * tell switchdev that this VLAN is likely handled in software.
2666 */
2667 if (!vlan.valid ||
2668 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2669 return -EOPNOTSUPP;
2670
2671 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2672
2673 /* keep the VLAN unless all ports are excluded */
2674 vlan.valid = false;
2675 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2676 if (vlan.member[i] !=
2677 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2678 vlan.valid = true;
2679 break;
2680 }
2681 }
2682
2683 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2684 if (err)
2685 return err;
2686
2687 if (!vlan.valid) {
2688 err = mv88e6xxx_mst_put(chip, vlan.sid);
2689 if (err)
2690 return err;
2691 }
2692
2693 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2694}
2695
2696static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2697 const struct switchdev_obj_port_vlan *vlan)
2698{
2699 struct mv88e6xxx_chip *chip = ds->priv;
2700 struct mv88e6xxx_port *p = &chip->ports[port];
2701 int err = 0;
2702 u16 pvid;
2703
2704 if (!mv88e6xxx_max_vid(chip))
2705 return -EOPNOTSUPP;
2706
2707 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2708 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2709 * switchdev workqueue to ensure that all FDB entries are deleted
2710 * before we remove the VLAN.
2711 */
2712 dsa_flush_workqueue();
2713
2714 mv88e6xxx_reg_lock(chip);
2715
2716 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2717 if (err)
2718 goto unlock;
2719
2720 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2721 if (err)
2722 goto unlock;
2723
2724 if (vlan->vid == pvid) {
2725 p->bridge_pvid.valid = false;
2726
2727 err = mv88e6xxx_port_commit_pvid(chip, port);
2728 if (err)
2729 goto unlock;
2730 }
2731
2732unlock:
2733 mv88e6xxx_reg_unlock(chip);
2734
2735 return err;
2736}
2737
2738static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2739{
2740 struct mv88e6xxx_chip *chip = ds->priv;
2741 struct mv88e6xxx_vtu_entry vlan;
2742 int err;
2743
2744 mv88e6xxx_reg_lock(chip);
2745
2746 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2747 if (err)
2748 goto unlock;
2749
2750 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2751
2752unlock:
2753 mv88e6xxx_reg_unlock(chip);
2754
2755 return err;
2756}
2757
2758static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2759 struct dsa_bridge bridge,
2760 const struct switchdev_vlan_msti *msti)
2761{
2762 struct mv88e6xxx_chip *chip = ds->priv;
2763 struct mv88e6xxx_vtu_entry vlan;
2764 u8 old_sid, new_sid;
2765 int err;
2766
2767 if (!mv88e6xxx_has_stu(chip))
2768 return -EOPNOTSUPP;
2769
2770 mv88e6xxx_reg_lock(chip);
2771
2772 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2773 if (err)
2774 goto unlock;
2775
2776 if (!vlan.valid) {
2777 err = -EINVAL;
2778 goto unlock;
2779 }
2780
2781 old_sid = vlan.sid;
2782
2783 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2784 if (err)
2785 goto unlock;
2786
2787 if (new_sid != old_sid) {
2788 vlan.sid = new_sid;
2789
2790 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2791 if (err) {
2792 mv88e6xxx_mst_put(chip, new_sid);
2793 goto unlock;
2794 }
2795 }
2796
2797 err = mv88e6xxx_mst_put(chip, old_sid);
2798
2799unlock:
2800 mv88e6xxx_reg_unlock(chip);
2801 return err;
2802}
2803
2804static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2805 const unsigned char *addr, u16 vid,
2806 struct dsa_db db)
2807{
2808 struct mv88e6xxx_chip *chip = ds->priv;
2809 int err;
2810
2811 mv88e6xxx_reg_lock(chip);
2812 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2813 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2814 mv88e6xxx_reg_unlock(chip);
2815
2816 return err;
2817}
2818
2819static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2820 const unsigned char *addr, u16 vid,
2821 struct dsa_db db)
2822{
2823 struct mv88e6xxx_chip *chip = ds->priv;
2824 int err;
2825
2826 mv88e6xxx_reg_lock(chip);
2827 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2828 mv88e6xxx_reg_unlock(chip);
2829
2830 return err;
2831}
2832
2833static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2834 u16 fid, u16 vid, int port,
2835 dsa_fdb_dump_cb_t *cb, void *data)
2836{
2837 struct mv88e6xxx_atu_entry addr;
2838 bool is_static;
2839 int err;
2840
2841 addr.state = 0;
2842 eth_broadcast_addr(addr.mac);
2843
2844 do {
2845 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2846 if (err)
2847 return err;
2848
2849 if (!addr.state)
2850 break;
2851
2852 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2853 continue;
2854
2855 if (!is_unicast_ether_addr(addr.mac))
2856 continue;
2857
2858 is_static = (addr.state ==
2859 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2860 err = cb(addr.mac, vid, is_static, data);
2861 if (err)
2862 return err;
2863 } while (!is_broadcast_ether_addr(addr.mac));
2864
2865 return err;
2866}
2867
2868struct mv88e6xxx_port_db_dump_vlan_ctx {
2869 int port;
2870 dsa_fdb_dump_cb_t *cb;
2871 void *data;
2872};
2873
2874static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2875 const struct mv88e6xxx_vtu_entry *entry,
2876 void *_data)
2877{
2878 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2879
2880 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2881 ctx->port, ctx->cb, ctx->data);
2882}
2883
2884static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2885 dsa_fdb_dump_cb_t *cb, void *data)
2886{
2887 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2888 .port = port,
2889 .cb = cb,
2890 .data = data,
2891 };
2892 u16 fid;
2893 int err;
2894
2895 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2896 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2897 if (err)
2898 return err;
2899
2900 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2901 if (err)
2902 return err;
2903
2904 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2905}
2906
2907static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2908 dsa_fdb_dump_cb_t *cb, void *data)
2909{
2910 struct mv88e6xxx_chip *chip = ds->priv;
2911 int err;
2912
2913 mv88e6xxx_reg_lock(chip);
2914 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2915 mv88e6xxx_reg_unlock(chip);
2916
2917 return err;
2918}
2919
2920static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2921 struct dsa_bridge bridge)
2922{
2923 struct dsa_switch *ds = chip->ds;
2924 struct dsa_switch_tree *dst = ds->dst;
2925 struct dsa_port *dp;
2926 int err;
2927
2928 list_for_each_entry(dp, &dst->ports, list) {
2929 if (dsa_port_offloads_bridge(dp, &bridge)) {
2930 if (dp->ds == ds) {
2931 /* This is a local bridge group member,
2932 * remap its Port VLAN Map.
2933 */
2934 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2935 if (err)
2936 return err;
2937 } else {
2938 /* This is an external bridge group member,
2939 * remap its cross-chip Port VLAN Table entry.
2940 */
2941 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2942 dp->index);
2943 if (err)
2944 return err;
2945 }
2946 }
2947 }
2948
2949 return 0;
2950}
2951
2952/* Treat the software bridge as a virtual single-port switch behind the
2953 * CPU and map in the PVT. First dst->last_switch elements are taken by
2954 * physical switches, so start from beyond that range.
2955 */
2956static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2957 unsigned int bridge_num)
2958{
2959 u8 dev = bridge_num + ds->dst->last_switch;
2960 struct mv88e6xxx_chip *chip = ds->priv;
2961
2962 return mv88e6xxx_pvt_map(chip, dev, 0);
2963}
2964
2965static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2966 struct dsa_bridge bridge,
2967 bool *tx_fwd_offload,
2968 struct netlink_ext_ack *extack)
2969{
2970 struct mv88e6xxx_chip *chip = ds->priv;
2971 int err;
2972
2973 mv88e6xxx_reg_lock(chip);
2974
2975 err = mv88e6xxx_bridge_map(chip, bridge);
2976 if (err)
2977 goto unlock;
2978
2979 err = mv88e6xxx_port_set_map_da(chip, port, true);
2980 if (err)
2981 goto unlock;
2982
2983 err = mv88e6xxx_port_commit_pvid(chip, port);
2984 if (err)
2985 goto unlock;
2986
2987 if (mv88e6xxx_has_pvt(chip)) {
2988 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2989 if (err)
2990 goto unlock;
2991
2992 *tx_fwd_offload = true;
2993 }
2994
2995unlock:
2996 mv88e6xxx_reg_unlock(chip);
2997
2998 return err;
2999}
3000
3001static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3002 struct dsa_bridge bridge)
3003{
3004 struct mv88e6xxx_chip *chip = ds->priv;
3005 int err;
3006
3007 mv88e6xxx_reg_lock(chip);
3008
3009 if (bridge.tx_fwd_offload &&
3010 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3011 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3012
3013 if (mv88e6xxx_bridge_map(chip, bridge) ||
3014 mv88e6xxx_port_vlan_map(chip, port))
3015 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3016
3017 err = mv88e6xxx_port_set_map_da(chip, port, false);
3018 if (err)
3019 dev_err(ds->dev,
3020 "port %d failed to restore map-DA: %pe\n",
3021 port, ERR_PTR(err));
3022
3023 err = mv88e6xxx_port_commit_pvid(chip, port);
3024 if (err)
3025 dev_err(ds->dev,
3026 "port %d failed to restore standalone pvid: %pe\n",
3027 port, ERR_PTR(err));
3028
3029 mv88e6xxx_reg_unlock(chip);
3030}
3031
3032static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3033 int tree_index, int sw_index,
3034 int port, struct dsa_bridge bridge,
3035 struct netlink_ext_ack *extack)
3036{
3037 struct mv88e6xxx_chip *chip = ds->priv;
3038 int err;
3039
3040 if (tree_index != ds->dst->index)
3041 return 0;
3042
3043 mv88e6xxx_reg_lock(chip);
3044 err = mv88e6xxx_pvt_map(chip, sw_index, port);
3045 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3046 mv88e6xxx_reg_unlock(chip);
3047
3048 return err;
3049}
3050
3051static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3052 int tree_index, int sw_index,
3053 int port, struct dsa_bridge bridge)
3054{
3055 struct mv88e6xxx_chip *chip = ds->priv;
3056
3057 if (tree_index != ds->dst->index)
3058 return;
3059
3060 mv88e6xxx_reg_lock(chip);
3061 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3062 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3063 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3064 mv88e6xxx_reg_unlock(chip);
3065}
3066
3067static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3068{
3069 if (chip->info->ops->reset)
3070 return chip->info->ops->reset(chip);
3071
3072 return 0;
3073}
3074
3075static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3076{
3077 struct gpio_desc *gpiod = chip->reset;
3078
3079 /* If there is a GPIO connected to the reset pin, toggle it */
3080 if (gpiod) {
3081 /* If the switch has just been reset and not yet completed
3082 * loading EEPROM, the reset may interrupt the I2C transaction
3083 * mid-byte, causing the first EEPROM read after the reset
3084 * from the wrong location resulting in the switch booting
3085 * to wrong mode and inoperable.
3086 */
3087 if (chip->info->ops->get_eeprom)
3088 mv88e6xxx_g2_eeprom_wait(chip);
3089
3090 gpiod_set_value_cansleep(gpiod, 1);
3091 usleep_range(10000, 20000);
3092 gpiod_set_value_cansleep(gpiod, 0);
3093 usleep_range(10000, 20000);
3094
3095 if (chip->info->ops->get_eeprom)
3096 mv88e6xxx_g2_eeprom_wait(chip);
3097 }
3098}
3099
3100static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3101{
3102 int i, err;
3103
3104 /* Set all ports to the Disabled state */
3105 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3106 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3107 if (err)
3108 return err;
3109 }
3110
3111 /* Wait for transmit queues to drain,
3112 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3113 */
3114 usleep_range(2000, 4000);
3115
3116 return 0;
3117}
3118
3119static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3120{
3121 int err;
3122
3123 err = mv88e6xxx_disable_ports(chip);
3124 if (err)
3125 return err;
3126
3127 mv88e6xxx_hardware_reset(chip);
3128
3129 return mv88e6xxx_software_reset(chip);
3130}
3131
3132static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3133 enum mv88e6xxx_frame_mode frame,
3134 enum mv88e6xxx_egress_mode egress, u16 etype)
3135{
3136 int err;
3137
3138 if (!chip->info->ops->port_set_frame_mode)
3139 return -EOPNOTSUPP;
3140
3141 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3142 if (err)
3143 return err;
3144
3145 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3146 if (err)
3147 return err;
3148
3149 if (chip->info->ops->port_set_ether_type)
3150 return chip->info->ops->port_set_ether_type(chip, port, etype);
3151
3152 return 0;
3153}
3154
3155static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3156{
3157 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3158 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3159 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3160}
3161
3162static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3163{
3164 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3165 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3166 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3167}
3168
3169static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3170{
3171 return mv88e6xxx_set_port_mode(chip, port,
3172 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3173 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3174 ETH_P_EDSA);
3175}
3176
3177static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3178{
3179 if (dsa_is_dsa_port(chip->ds, port))
3180 return mv88e6xxx_set_port_mode_dsa(chip, port);
3181
3182 if (dsa_is_user_port(chip->ds, port))
3183 return mv88e6xxx_set_port_mode_normal(chip, port);
3184
3185 /* Setup CPU port mode depending on its supported tag format */
3186 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3187 return mv88e6xxx_set_port_mode_dsa(chip, port);
3188
3189 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3190 return mv88e6xxx_set_port_mode_edsa(chip, port);
3191
3192 return -EINVAL;
3193}
3194
3195static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3196{
3197 bool message = dsa_is_dsa_port(chip->ds, port);
3198
3199 return mv88e6xxx_port_set_message_port(chip, port, message);
3200}
3201
3202static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3203{
3204 int err;
3205
3206 if (chip->info->ops->port_set_ucast_flood) {
3207 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3208 if (err)
3209 return err;
3210 }
3211 if (chip->info->ops->port_set_mcast_flood) {
3212 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3213 if (err)
3214 return err;
3215 }
3216
3217 return 0;
3218}
3219
3220static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3221 enum mv88e6xxx_egress_direction direction,
3222 int port)
3223{
3224 int err;
3225
3226 if (!chip->info->ops->set_egress_port)
3227 return -EOPNOTSUPP;
3228
3229 err = chip->info->ops->set_egress_port(chip, direction, port);
3230 if (err)
3231 return err;
3232
3233 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3234 chip->ingress_dest_port = port;
3235 else
3236 chip->egress_dest_port = port;
3237
3238 return 0;
3239}
3240
3241static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3242{
3243 struct dsa_switch *ds = chip->ds;
3244 int upstream_port;
3245 int err;
3246
3247 upstream_port = dsa_upstream_port(ds, port);
3248 if (chip->info->ops->port_set_upstream_port) {
3249 err = chip->info->ops->port_set_upstream_port(chip, port,
3250 upstream_port);
3251 if (err)
3252 return err;
3253 }
3254
3255 if (port == upstream_port) {
3256 if (chip->info->ops->set_cpu_port) {
3257 err = chip->info->ops->set_cpu_port(chip,
3258 upstream_port);
3259 if (err)
3260 return err;
3261 }
3262
3263 err = mv88e6xxx_set_egress_port(chip,
3264 MV88E6XXX_EGRESS_DIR_INGRESS,
3265 upstream_port);
3266 if (err && err != -EOPNOTSUPP)
3267 return err;
3268
3269 err = mv88e6xxx_set_egress_port(chip,
3270 MV88E6XXX_EGRESS_DIR_EGRESS,
3271 upstream_port);
3272 if (err && err != -EOPNOTSUPP)
3273 return err;
3274 }
3275
3276 return 0;
3277}
3278
3279static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3280{
3281 struct device_node *phy_handle = NULL;
3282 struct dsa_switch *ds = chip->ds;
3283 struct dsa_port *dp;
3284 int tx_amp;
3285 int err;
3286 u16 reg;
3287
3288 chip->ports[port].chip = chip;
3289 chip->ports[port].port = port;
3290
3291 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3292 SPEED_UNFORCED, DUPLEX_UNFORCED,
3293 PAUSE_ON, PHY_INTERFACE_MODE_NA);
3294 if (err)
3295 return err;
3296
3297 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3298 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3299 * tunneling, determine priority by looking at 802.1p and IP
3300 * priority fields (IP prio has precedence), and set STP state
3301 * to Forwarding.
3302 *
3303 * If this is the CPU link, use DSA or EDSA tagging depending
3304 * on which tagging mode was configured.
3305 *
3306 * If this is a link to another switch, use DSA tagging mode.
3307 *
3308 * If this is the upstream port for this switch, enable
3309 * forwarding of unknown unicasts and multicasts.
3310 */
3311 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3312 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3313 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3314 * by a USER port to the CPU port to allow snooping.
3315 */
3316 if (dsa_is_user_port(ds, port))
3317 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3318
3319 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3320 if (err)
3321 return err;
3322
3323 err = mv88e6xxx_setup_port_mode(chip, port);
3324 if (err)
3325 return err;
3326
3327 err = mv88e6xxx_setup_egress_floods(chip, port);
3328 if (err)
3329 return err;
3330
3331 /* Port Control 2: don't force a good FCS, set the MTU size to
3332 * 10222 bytes, disable 802.1q tags checking, don't discard
3333 * tagged or untagged frames on this port, skip destination
3334 * address lookup on user ports, disable ARP mirroring and don't
3335 * send a copy of all transmitted/received frames on this port
3336 * to the CPU.
3337 */
3338 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3339 if (err)
3340 return err;
3341
3342 err = mv88e6xxx_setup_upstream_port(chip, port);
3343 if (err)
3344 return err;
3345
3346 /* On chips that support it, set all downstream DSA ports'
3347 * VLAN policy to TRAP. In combination with loading
3348 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3349 * provides a better isolation barrier between standalone
3350 * ports, as the ATU is bypassed on any intermediate switches
3351 * between the incoming port and the CPU.
3352 */
3353 if (dsa_is_downstream_port(ds, port) &&
3354 chip->info->ops->port_set_policy) {
3355 err = chip->info->ops->port_set_policy(chip, port,
3356 MV88E6XXX_POLICY_MAPPING_VTU,
3357 MV88E6XXX_POLICY_ACTION_TRAP);
3358 if (err)
3359 return err;
3360 }
3361
3362 /* User ports start out in standalone mode and 802.1Q is
3363 * therefore disabled. On DSA ports, all valid VIDs are always
3364 * loaded in the VTU - therefore, enable 802.1Q in order to take
3365 * advantage of VLAN policy on chips that supports it.
3366 */
3367 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3368 dsa_is_user_port(ds, port) ?
3369 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3370 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3371 if (err)
3372 return err;
3373
3374 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3375 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3376 * the first free FID. This will be used as the private PVID for
3377 * unbridged ports. Shared (DSA and CPU) ports must also be
3378 * members of this VID, in order to trap all frames assigned to
3379 * it to the CPU.
3380 */
3381 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3382 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3383 false);
3384 if (err)
3385 return err;
3386
3387 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3388 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3389 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3390 * as the private PVID on ports under a VLAN-unaware bridge.
3391 * Shared (DSA and CPU) ports must also be members of it, to translate
3392 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3393 * relying on their port default FID.
3394 */
3395 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3396 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3397 false);
3398 if (err)
3399 return err;
3400
3401 if (chip->info->ops->port_set_jumbo_size) {
3402 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3403 if (err)
3404 return err;
3405 }
3406
3407 /* Port Association Vector: disable automatic address learning
3408 * on all user ports since they start out in standalone
3409 * mode. When joining a bridge, learning will be configured to
3410 * match the bridge port settings. Enable learning on all
3411 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3412 * learning process.
3413 *
3414 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3415 * and RefreshLocked. I.e. setup standard automatic learning.
3416 */
3417 if (dsa_is_user_port(ds, port))
3418 reg = 0;
3419 else
3420 reg = 1 << port;
3421
3422 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3423 reg);
3424 if (err)
3425 return err;
3426
3427 /* Egress rate control 2: disable egress rate control. */
3428 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3429 0x0000);
3430 if (err)
3431 return err;
3432
3433 if (chip->info->ops->port_pause_limit) {
3434 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3435 if (err)
3436 return err;
3437 }
3438
3439 if (chip->info->ops->port_disable_learn_limit) {
3440 err = chip->info->ops->port_disable_learn_limit(chip, port);
3441 if (err)
3442 return err;
3443 }
3444
3445 if (chip->info->ops->port_disable_pri_override) {
3446 err = chip->info->ops->port_disable_pri_override(chip, port);
3447 if (err)
3448 return err;
3449 }
3450
3451 if (chip->info->ops->port_tag_remap) {
3452 err = chip->info->ops->port_tag_remap(chip, port);
3453 if (err)
3454 return err;
3455 }
3456
3457 if (chip->info->ops->port_egress_rate_limiting) {
3458 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3459 if (err)
3460 return err;
3461 }
3462
3463 if (chip->info->ops->port_setup_message_port) {
3464 err = chip->info->ops->port_setup_message_port(chip, port);
3465 if (err)
3466 return err;
3467 }
3468
3469 if (chip->info->ops->serdes_set_tx_amplitude) {
3470 dp = dsa_to_port(ds, port);
3471 if (dp)
3472 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3473
3474 if (phy_handle && !of_property_read_u32(phy_handle,
3475 "tx-p2p-microvolt",
3476 &tx_amp))
3477 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3478 port, tx_amp);
3479 if (phy_handle) {
3480 of_node_put(phy_handle);
3481 if (err)
3482 return err;
3483 }
3484 }
3485
3486 /* Port based VLAN map: give each port the same default address
3487 * database, and allow bidirectional communication between the
3488 * CPU and DSA port(s), and the other ports.
3489 */
3490 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3491 if (err)
3492 return err;
3493
3494 err = mv88e6xxx_port_vlan_map(chip, port);
3495 if (err)
3496 return err;
3497
3498 /* Default VLAN ID and priority: don't set a default VLAN
3499 * ID, and set the default packet priority to zero.
3500 */
3501 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3502}
3503
3504static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3505{
3506 struct mv88e6xxx_chip *chip = ds->priv;
3507
3508 if (chip->info->ops->port_set_jumbo_size)
3509 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3510 else if (chip->info->ops->set_max_frame_size)
3511 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3512 return ETH_DATA_LEN;
3513}
3514
3515static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3516{
3517 struct mv88e6xxx_chip *chip = ds->priv;
3518 int ret = 0;
3519
3520 /* For families where we don't know how to alter the MTU,
3521 * just accept any value up to ETH_DATA_LEN
3522 */
3523 if (!chip->info->ops->port_set_jumbo_size &&
3524 !chip->info->ops->set_max_frame_size) {
3525 if (new_mtu > ETH_DATA_LEN)
3526 return -EINVAL;
3527
3528 return 0;
3529 }
3530
3531 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3532 new_mtu += EDSA_HLEN;
3533
3534 mv88e6xxx_reg_lock(chip);
3535 if (chip->info->ops->port_set_jumbo_size)
3536 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3537 else if (chip->info->ops->set_max_frame_size)
3538 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3539 mv88e6xxx_reg_unlock(chip);
3540
3541 return ret;
3542}
3543
3544static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3545 unsigned int ageing_time)
3546{
3547 struct mv88e6xxx_chip *chip = ds->priv;
3548 int err;
3549
3550 mv88e6xxx_reg_lock(chip);
3551 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3552 mv88e6xxx_reg_unlock(chip);
3553
3554 return err;
3555}
3556
3557static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3558{
3559 int err;
3560
3561 /* Initialize the statistics unit */
3562 if (chip->info->ops->stats_set_histogram) {
3563 err = chip->info->ops->stats_set_histogram(chip);
3564 if (err)
3565 return err;
3566 }
3567
3568 return mv88e6xxx_g1_stats_clear(chip);
3569}
3570
3571/* Check if the errata has already been applied. */
3572static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3573{
3574 int port;
3575 int err;
3576 u16 val;
3577
3578 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3579 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3580 if (err) {
3581 dev_err(chip->dev,
3582 "Error reading hidden register: %d\n", err);
3583 return false;
3584 }
3585 if (val != 0x01c0)
3586 return false;
3587 }
3588
3589 return true;
3590}
3591
3592/* The 6390 copper ports have an errata which require poking magic
3593 * values into undocumented hidden registers and then performing a
3594 * software reset.
3595 */
3596static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3597{
3598 int port;
3599 int err;
3600
3601 if (mv88e6390_setup_errata_applied(chip))
3602 return 0;
3603
3604 /* Set the ports into blocking mode */
3605 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3606 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3607 if (err)
3608 return err;
3609 }
3610
3611 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3612 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3613 if (err)
3614 return err;
3615 }
3616
3617 return mv88e6xxx_software_reset(chip);
3618}
3619
3620/* prod_id for switch families which do not have a PHY model number */
3621static const u16 family_prod_id_table[] = {
3622 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3623 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3624 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3625};
3626
3627static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3628{
3629 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3630 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3631 u16 prod_id;
3632 u16 val;
3633 int err;
3634
3635 if (!chip->info->ops->phy_read)
3636 return -EOPNOTSUPP;
3637
3638 mv88e6xxx_reg_lock(chip);
3639 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3640 mv88e6xxx_reg_unlock(chip);
3641
3642 /* Some internal PHYs don't have a model number. */
3643 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3644 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3645 prod_id = family_prod_id_table[chip->info->family];
3646 if (prod_id)
3647 val |= prod_id >> 4;
3648 }
3649
3650 return err ? err : val;
3651}
3652
3653static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3654 int reg)
3655{
3656 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3657 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3658 u16 val;
3659 int err;
3660
3661 if (!chip->info->ops->phy_read_c45)
3662 return 0xffff;
3663
3664 mv88e6xxx_reg_lock(chip);
3665 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3666 mv88e6xxx_reg_unlock(chip);
3667
3668 return err ? err : val;
3669}
3670
3671static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3672{
3673 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3674 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3675 int err;
3676
3677 if (!chip->info->ops->phy_write)
3678 return -EOPNOTSUPP;
3679
3680 mv88e6xxx_reg_lock(chip);
3681 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3682 mv88e6xxx_reg_unlock(chip);
3683
3684 return err;
3685}
3686
3687static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3688 int reg, u16 val)
3689{
3690 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3691 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3692 int err;
3693
3694 if (!chip->info->ops->phy_write_c45)
3695 return -EOPNOTSUPP;
3696
3697 mv88e6xxx_reg_lock(chip);
3698 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3699 mv88e6xxx_reg_unlock(chip);
3700
3701 return err;
3702}
3703
3704static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3705 struct device_node *np,
3706 bool external)
3707{
3708 static int index;
3709 struct mv88e6xxx_mdio_bus *mdio_bus;
3710 struct mii_bus *bus;
3711 int err;
3712
3713 if (external) {
3714 mv88e6xxx_reg_lock(chip);
3715 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3716 mv88e6xxx_reg_unlock(chip);
3717
3718 if (err)
3719 return err;
3720 }
3721
3722 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3723 if (!bus)
3724 return -ENOMEM;
3725
3726 mdio_bus = bus->priv;
3727 mdio_bus->bus = bus;
3728 mdio_bus->chip = chip;
3729 INIT_LIST_HEAD(&mdio_bus->list);
3730 mdio_bus->external = external;
3731
3732 if (np) {
3733 bus->name = np->full_name;
3734 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3735 } else {
3736 bus->name = "mv88e6xxx SMI";
3737 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3738 }
3739
3740 bus->read = mv88e6xxx_mdio_read;
3741 bus->write = mv88e6xxx_mdio_write;
3742 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3743 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3744 bus->parent = chip->dev;
3745 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3746 mv88e6xxx_num_ports(chip) - 1,
3747 chip->info->phy_base_addr);
3748
3749 if (!external) {
3750 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3751 if (err)
3752 goto out;
3753 }
3754
3755 err = of_mdiobus_register(bus, np);
3756 if (err) {
3757 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3758 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3759 goto out;
3760 }
3761
3762 if (external)
3763 list_add_tail(&mdio_bus->list, &chip->mdios);
3764 else
3765 list_add(&mdio_bus->list, &chip->mdios);
3766
3767 return 0;
3768
3769out:
3770 mdiobus_free(bus);
3771 return err;
3772}
3773
3774static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3775
3776{
3777 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3778 struct mii_bus *bus;
3779
3780 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3781 bus = mdio_bus->bus;
3782
3783 if (!mdio_bus->external)
3784 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3785
3786 mdiobus_unregister(bus);
3787 mdiobus_free(bus);
3788 }
3789}
3790
3791static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3792{
3793 struct device_node *np = chip->dev->of_node;
3794 struct device_node *child;
3795 int err;
3796
3797 /* Always register one mdio bus for the internal/default mdio
3798 * bus. This maybe represented in the device tree, but is
3799 * optional.
3800 */
3801 child = of_get_child_by_name(np, "mdio");
3802 err = mv88e6xxx_mdio_register(chip, child, false);
3803 of_node_put(child);
3804 if (err)
3805 return err;
3806
3807 /* Walk the device tree, and see if there are any other nodes
3808 * which say they are compatible with the external mdio
3809 * bus.
3810 */
3811 for_each_available_child_of_node(np, child) {
3812 if (of_device_is_compatible(
3813 child, "marvell,mv88e6xxx-mdio-external")) {
3814 err = mv88e6xxx_mdio_register(chip, child, true);
3815 if (err) {
3816 mv88e6xxx_mdios_unregister(chip);
3817 of_node_put(child);
3818 return err;
3819 }
3820 }
3821 }
3822
3823 return 0;
3824}
3825
3826static void mv88e6xxx_teardown(struct dsa_switch *ds)
3827{
3828 struct mv88e6xxx_chip *chip = ds->priv;
3829
3830 mv88e6xxx_teardown_devlink_params(ds);
3831 dsa_devlink_resources_unregister(ds);
3832 mv88e6xxx_teardown_devlink_regions_global(ds);
3833 mv88e6xxx_mdios_unregister(chip);
3834}
3835
3836static int mv88e6xxx_setup(struct dsa_switch *ds)
3837{
3838 struct mv88e6xxx_chip *chip = ds->priv;
3839 u8 cmode;
3840 int err;
3841 int i;
3842
3843 err = mv88e6xxx_mdios_register(chip);
3844 if (err)
3845 return err;
3846
3847 chip->ds = ds;
3848 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3849
3850 /* Since virtual bridges are mapped in the PVT, the number we support
3851 * depends on the physical switch topology. We need to let DSA figure
3852 * that out and therefore we cannot set this at dsa_register_switch()
3853 * time.
3854 */
3855 if (mv88e6xxx_has_pvt(chip))
3856 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3857 ds->dst->last_switch - 1;
3858
3859 mv88e6xxx_reg_lock(chip);
3860
3861 if (chip->info->ops->setup_errata) {
3862 err = chip->info->ops->setup_errata(chip);
3863 if (err)
3864 goto unlock;
3865 }
3866
3867 /* Cache the cmode of each port. */
3868 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3869 if (chip->info->ops->port_get_cmode) {
3870 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3871 if (err)
3872 goto unlock;
3873
3874 chip->ports[i].cmode = cmode;
3875 }
3876 }
3877
3878 err = mv88e6xxx_vtu_setup(chip);
3879 if (err)
3880 goto unlock;
3881
3882 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3883 * VTU, thereby also flushing the STU).
3884 */
3885 err = mv88e6xxx_stu_setup(chip);
3886 if (err)
3887 goto unlock;
3888
3889 /* Setup Switch Port Registers */
3890 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3891 if (dsa_is_unused_port(ds, i))
3892 continue;
3893
3894 /* Prevent the use of an invalid port. */
3895 if (mv88e6xxx_is_invalid_port(chip, i)) {
3896 dev_err(chip->dev, "port %d is invalid\n", i);
3897 err = -EINVAL;
3898 goto unlock;
3899 }
3900
3901 err = mv88e6xxx_setup_port(chip, i);
3902 if (err)
3903 goto unlock;
3904 }
3905
3906 err = mv88e6xxx_irl_setup(chip);
3907 if (err)
3908 goto unlock;
3909
3910 err = mv88e6xxx_mac_setup(chip);
3911 if (err)
3912 goto unlock;
3913
3914 err = mv88e6xxx_phy_setup(chip);
3915 if (err)
3916 goto unlock;
3917
3918 err = mv88e6xxx_pvt_setup(chip);
3919 if (err)
3920 goto unlock;
3921
3922 err = mv88e6xxx_atu_setup(chip);
3923 if (err)
3924 goto unlock;
3925
3926 err = mv88e6xxx_broadcast_setup(chip, 0);
3927 if (err)
3928 goto unlock;
3929
3930 err = mv88e6xxx_pot_setup(chip);
3931 if (err)
3932 goto unlock;
3933
3934 err = mv88e6xxx_rmu_setup(chip);
3935 if (err)
3936 goto unlock;
3937
3938 err = mv88e6xxx_rsvd2cpu_setup(chip);
3939 if (err)
3940 goto unlock;
3941
3942 err = mv88e6xxx_trunk_setup(chip);
3943 if (err)
3944 goto unlock;
3945
3946 err = mv88e6xxx_devmap_setup(chip);
3947 if (err)
3948 goto unlock;
3949
3950 err = mv88e6xxx_pri_setup(chip);
3951 if (err)
3952 goto unlock;
3953
3954 /* Setup PTP Hardware Clock and timestamping */
3955 if (chip->info->ptp_support) {
3956 err = mv88e6xxx_ptp_setup(chip);
3957 if (err)
3958 goto unlock;
3959
3960 err = mv88e6xxx_hwtstamp_setup(chip);
3961 if (err)
3962 goto unlock;
3963 }
3964
3965 err = mv88e6xxx_stats_setup(chip);
3966 if (err)
3967 goto unlock;
3968
3969unlock:
3970 mv88e6xxx_reg_unlock(chip);
3971
3972 if (err)
3973 goto out_mdios;
3974
3975 /* Have to be called without holding the register lock, since
3976 * they take the devlink lock, and we later take the locks in
3977 * the reverse order when getting/setting parameters or
3978 * resource occupancy.
3979 */
3980 err = mv88e6xxx_setup_devlink_resources(ds);
3981 if (err)
3982 goto out_mdios;
3983
3984 err = mv88e6xxx_setup_devlink_params(ds);
3985 if (err)
3986 goto out_resources;
3987
3988 err = mv88e6xxx_setup_devlink_regions_global(ds);
3989 if (err)
3990 goto out_params;
3991
3992 return 0;
3993
3994out_params:
3995 mv88e6xxx_teardown_devlink_params(ds);
3996out_resources:
3997 dsa_devlink_resources_unregister(ds);
3998out_mdios:
3999 mv88e6xxx_mdios_unregister(chip);
4000
4001 return err;
4002}
4003
4004static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4005{
4006 struct mv88e6xxx_chip *chip = ds->priv;
4007 int err;
4008
4009 if (chip->info->ops->pcs_ops &&
4010 chip->info->ops->pcs_ops->pcs_init) {
4011 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4012 if (err)
4013 return err;
4014 }
4015
4016 return mv88e6xxx_setup_devlink_regions_port(ds, port);
4017}
4018
4019static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4020{
4021 struct mv88e6xxx_chip *chip = ds->priv;
4022
4023 mv88e6xxx_teardown_devlink_regions_port(ds, port);
4024
4025 if (chip->info->ops->pcs_ops &&
4026 chip->info->ops->pcs_ops->pcs_teardown)
4027 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4028}
4029
4030static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4031{
4032 struct mv88e6xxx_chip *chip = ds->priv;
4033
4034 return chip->eeprom_len;
4035}
4036
4037static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4038 struct ethtool_eeprom *eeprom, u8 *data)
4039{
4040 struct mv88e6xxx_chip *chip = ds->priv;
4041 int err;
4042
4043 if (!chip->info->ops->get_eeprom)
4044 return -EOPNOTSUPP;
4045
4046 mv88e6xxx_reg_lock(chip);
4047 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4048 mv88e6xxx_reg_unlock(chip);
4049
4050 if (err)
4051 return err;
4052
4053 eeprom->magic = 0xc3ec4951;
4054
4055 return 0;
4056}
4057
4058static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4059 struct ethtool_eeprom *eeprom, u8 *data)
4060{
4061 struct mv88e6xxx_chip *chip = ds->priv;
4062 int err;
4063
4064 if (!chip->info->ops->set_eeprom)
4065 return -EOPNOTSUPP;
4066
4067 if (eeprom->magic != 0xc3ec4951)
4068 return -EINVAL;
4069
4070 mv88e6xxx_reg_lock(chip);
4071 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4072 mv88e6xxx_reg_unlock(chip);
4073
4074 return err;
4075}
4076
4077static const struct mv88e6xxx_ops mv88e6085_ops = {
4078 /* MV88E6XXX_FAMILY_6097 */
4079 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4080 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4081 .irl_init_all = mv88e6352_g2_irl_init_all,
4082 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4083 .phy_read = mv88e6185_phy_ppu_read,
4084 .phy_write = mv88e6185_phy_ppu_write,
4085 .port_set_link = mv88e6xxx_port_set_link,
4086 .port_sync_link = mv88e6xxx_port_sync_link,
4087 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4088 .port_tag_remap = mv88e6095_port_tag_remap,
4089 .port_set_policy = mv88e6352_port_set_policy,
4090 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4091 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4092 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4093 .port_set_ether_type = mv88e6351_port_set_ether_type,
4094 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4095 .port_pause_limit = mv88e6097_port_pause_limit,
4096 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4097 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4098 .port_get_cmode = mv88e6185_port_get_cmode,
4099 .port_setup_message_port = mv88e6xxx_setup_message_port,
4100 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4101 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4102 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4103 .stats_get_strings = mv88e6095_stats_get_strings,
4104 .stats_get_stat = mv88e6095_stats_get_stat,
4105 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4106 .set_egress_port = mv88e6095_g1_set_egress_port,
4107 .watchdog_ops = &mv88e6097_watchdog_ops,
4108 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4109 .pot_clear = mv88e6xxx_g2_pot_clear,
4110 .ppu_enable = mv88e6185_g1_ppu_enable,
4111 .ppu_disable = mv88e6185_g1_ppu_disable,
4112 .reset = mv88e6185_g1_reset,
4113 .rmu_disable = mv88e6085_g1_rmu_disable,
4114 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4115 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4116 .stu_getnext = mv88e6352_g1_stu_getnext,
4117 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4118 .phylink_get_caps = mv88e6185_phylink_get_caps,
4119 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4120};
4121
4122static const struct mv88e6xxx_ops mv88e6095_ops = {
4123 /* MV88E6XXX_FAMILY_6095 */
4124 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4125 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4126 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4127 .phy_read = mv88e6185_phy_ppu_read,
4128 .phy_write = mv88e6185_phy_ppu_write,
4129 .port_set_link = mv88e6xxx_port_set_link,
4130 .port_sync_link = mv88e6185_port_sync_link,
4131 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4132 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4133 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4134 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4135 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4136 .port_get_cmode = mv88e6185_port_get_cmode,
4137 .port_setup_message_port = mv88e6xxx_setup_message_port,
4138 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4139 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4140 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4141 .stats_get_strings = mv88e6095_stats_get_strings,
4142 .stats_get_stat = mv88e6095_stats_get_stat,
4143 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4144 .ppu_enable = mv88e6185_g1_ppu_enable,
4145 .ppu_disable = mv88e6185_g1_ppu_disable,
4146 .reset = mv88e6185_g1_reset,
4147 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4148 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4149 .phylink_get_caps = mv88e6095_phylink_get_caps,
4150 .pcs_ops = &mv88e6185_pcs_ops,
4151 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4152};
4153
4154static const struct mv88e6xxx_ops mv88e6097_ops = {
4155 /* MV88E6XXX_FAMILY_6097 */
4156 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4157 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4158 .irl_init_all = mv88e6352_g2_irl_init_all,
4159 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4160 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4161 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4162 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4163 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4164 .port_set_link = mv88e6xxx_port_set_link,
4165 .port_sync_link = mv88e6185_port_sync_link,
4166 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4167 .port_tag_remap = mv88e6095_port_tag_remap,
4168 .port_set_policy = mv88e6352_port_set_policy,
4169 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4170 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4171 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4172 .port_set_ether_type = mv88e6351_port_set_ether_type,
4173 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4174 .port_pause_limit = mv88e6097_port_pause_limit,
4175 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4176 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4177 .port_get_cmode = mv88e6185_port_get_cmode,
4178 .port_setup_message_port = mv88e6xxx_setup_message_port,
4179 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4180 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4181 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4182 .stats_get_strings = mv88e6095_stats_get_strings,
4183 .stats_get_stat = mv88e6095_stats_get_stat,
4184 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4185 .set_egress_port = mv88e6095_g1_set_egress_port,
4186 .watchdog_ops = &mv88e6097_watchdog_ops,
4187 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4188 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4189 .pot_clear = mv88e6xxx_g2_pot_clear,
4190 .reset = mv88e6352_g1_reset,
4191 .rmu_disable = mv88e6085_g1_rmu_disable,
4192 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4193 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4194 .phylink_get_caps = mv88e6095_phylink_get_caps,
4195 .pcs_ops = &mv88e6185_pcs_ops,
4196 .stu_getnext = mv88e6352_g1_stu_getnext,
4197 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4198 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4199};
4200
4201static const struct mv88e6xxx_ops mv88e6123_ops = {
4202 /* MV88E6XXX_FAMILY_6165 */
4203 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4204 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4205 .irl_init_all = mv88e6352_g2_irl_init_all,
4206 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4207 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4208 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4209 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4210 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4211 .port_set_link = mv88e6xxx_port_set_link,
4212 .port_sync_link = mv88e6xxx_port_sync_link,
4213 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4214 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4215 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4216 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4217 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4218 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4219 .port_get_cmode = mv88e6185_port_get_cmode,
4220 .port_setup_message_port = mv88e6xxx_setup_message_port,
4221 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4222 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4223 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4224 .stats_get_strings = mv88e6095_stats_get_strings,
4225 .stats_get_stat = mv88e6095_stats_get_stat,
4226 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4227 .set_egress_port = mv88e6095_g1_set_egress_port,
4228 .watchdog_ops = &mv88e6097_watchdog_ops,
4229 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4230 .pot_clear = mv88e6xxx_g2_pot_clear,
4231 .reset = mv88e6352_g1_reset,
4232 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4233 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4234 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4235 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4236 .stu_getnext = mv88e6352_g1_stu_getnext,
4237 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4238 .phylink_get_caps = mv88e6185_phylink_get_caps,
4239 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4240};
4241
4242static const struct mv88e6xxx_ops mv88e6131_ops = {
4243 /* MV88E6XXX_FAMILY_6185 */
4244 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4245 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4246 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4247 .phy_read = mv88e6185_phy_ppu_read,
4248 .phy_write = mv88e6185_phy_ppu_write,
4249 .port_set_link = mv88e6xxx_port_set_link,
4250 .port_sync_link = mv88e6xxx_port_sync_link,
4251 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4252 .port_tag_remap = mv88e6095_port_tag_remap,
4253 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4254 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4255 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4256 .port_set_ether_type = mv88e6351_port_set_ether_type,
4257 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4258 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4259 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4260 .port_pause_limit = mv88e6097_port_pause_limit,
4261 .port_set_pause = mv88e6185_port_set_pause,
4262 .port_get_cmode = mv88e6185_port_get_cmode,
4263 .port_setup_message_port = mv88e6xxx_setup_message_port,
4264 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4265 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4266 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4267 .stats_get_strings = mv88e6095_stats_get_strings,
4268 .stats_get_stat = mv88e6095_stats_get_stat,
4269 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4270 .set_egress_port = mv88e6095_g1_set_egress_port,
4271 .watchdog_ops = &mv88e6097_watchdog_ops,
4272 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4273 .ppu_enable = mv88e6185_g1_ppu_enable,
4274 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4275 .ppu_disable = mv88e6185_g1_ppu_disable,
4276 .reset = mv88e6185_g1_reset,
4277 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4278 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4279 .phylink_get_caps = mv88e6185_phylink_get_caps,
4280};
4281
4282static const struct mv88e6xxx_ops mv88e6141_ops = {
4283 /* MV88E6XXX_FAMILY_6341 */
4284 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4285 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4286 .irl_init_all = mv88e6352_g2_irl_init_all,
4287 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4288 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4289 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4290 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4291 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4292 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4293 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4294 .port_set_link = mv88e6xxx_port_set_link,
4295 .port_sync_link = mv88e6xxx_port_sync_link,
4296 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4297 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4298 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4299 .port_tag_remap = mv88e6095_port_tag_remap,
4300 .port_set_policy = mv88e6352_port_set_policy,
4301 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4302 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4303 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4304 .port_set_ether_type = mv88e6351_port_set_ether_type,
4305 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4306 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4307 .port_pause_limit = mv88e6097_port_pause_limit,
4308 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4309 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4310 .port_get_cmode = mv88e6352_port_get_cmode,
4311 .port_set_cmode = mv88e6341_port_set_cmode,
4312 .port_setup_message_port = mv88e6xxx_setup_message_port,
4313 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4314 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4315 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4316 .stats_get_strings = mv88e6320_stats_get_strings,
4317 .stats_get_stat = mv88e6390_stats_get_stat,
4318 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4319 .set_egress_port = mv88e6390_g1_set_egress_port,
4320 .watchdog_ops = &mv88e6390_watchdog_ops,
4321 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4322 .pot_clear = mv88e6xxx_g2_pot_clear,
4323 .reset = mv88e6352_g1_reset,
4324 .rmu_disable = mv88e6390_g1_rmu_disable,
4325 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4326 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4327 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4328 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4329 .stu_getnext = mv88e6352_g1_stu_getnext,
4330 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4331 .serdes_get_lane = mv88e6341_serdes_get_lane,
4332 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4333 .gpio_ops = &mv88e6352_gpio_ops,
4334 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4335 .serdes_get_strings = mv88e6390_serdes_get_strings,
4336 .serdes_get_stats = mv88e6390_serdes_get_stats,
4337 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4338 .serdes_get_regs = mv88e6390_serdes_get_regs,
4339 .phylink_get_caps = mv88e6341_phylink_get_caps,
4340 .pcs_ops = &mv88e6390_pcs_ops,
4341};
4342
4343static const struct mv88e6xxx_ops mv88e6161_ops = {
4344 /* MV88E6XXX_FAMILY_6165 */
4345 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4346 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4347 .irl_init_all = mv88e6352_g2_irl_init_all,
4348 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4349 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4350 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4351 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4352 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4353 .port_set_link = mv88e6xxx_port_set_link,
4354 .port_sync_link = mv88e6xxx_port_sync_link,
4355 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4356 .port_tag_remap = mv88e6095_port_tag_remap,
4357 .port_set_policy = mv88e6352_port_set_policy,
4358 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4359 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4360 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4361 .port_set_ether_type = mv88e6351_port_set_ether_type,
4362 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4363 .port_pause_limit = mv88e6097_port_pause_limit,
4364 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4365 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4366 .port_get_cmode = mv88e6185_port_get_cmode,
4367 .port_setup_message_port = mv88e6xxx_setup_message_port,
4368 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4369 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4370 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4371 .stats_get_strings = mv88e6095_stats_get_strings,
4372 .stats_get_stat = mv88e6095_stats_get_stat,
4373 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4374 .set_egress_port = mv88e6095_g1_set_egress_port,
4375 .watchdog_ops = &mv88e6097_watchdog_ops,
4376 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4377 .pot_clear = mv88e6xxx_g2_pot_clear,
4378 .reset = mv88e6352_g1_reset,
4379 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4380 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4381 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4382 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4383 .stu_getnext = mv88e6352_g1_stu_getnext,
4384 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4385 .avb_ops = &mv88e6165_avb_ops,
4386 .ptp_ops = &mv88e6165_ptp_ops,
4387 .phylink_get_caps = mv88e6185_phylink_get_caps,
4388 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4389};
4390
4391static const struct mv88e6xxx_ops mv88e6165_ops = {
4392 /* MV88E6XXX_FAMILY_6165 */
4393 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4394 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4395 .irl_init_all = mv88e6352_g2_irl_init_all,
4396 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4397 .phy_read = mv88e6165_phy_read,
4398 .phy_write = mv88e6165_phy_write,
4399 .port_set_link = mv88e6xxx_port_set_link,
4400 .port_sync_link = mv88e6xxx_port_sync_link,
4401 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4402 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4403 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4404 .port_get_cmode = mv88e6185_port_get_cmode,
4405 .port_setup_message_port = mv88e6xxx_setup_message_port,
4406 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4407 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4408 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4409 .stats_get_strings = mv88e6095_stats_get_strings,
4410 .stats_get_stat = mv88e6095_stats_get_stat,
4411 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4412 .set_egress_port = mv88e6095_g1_set_egress_port,
4413 .watchdog_ops = &mv88e6097_watchdog_ops,
4414 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4415 .pot_clear = mv88e6xxx_g2_pot_clear,
4416 .reset = mv88e6352_g1_reset,
4417 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4418 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4419 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4420 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4421 .stu_getnext = mv88e6352_g1_stu_getnext,
4422 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4423 .avb_ops = &mv88e6165_avb_ops,
4424 .ptp_ops = &mv88e6165_ptp_ops,
4425 .phylink_get_caps = mv88e6185_phylink_get_caps,
4426};
4427
4428static const struct mv88e6xxx_ops mv88e6171_ops = {
4429 /* MV88E6XXX_FAMILY_6351 */
4430 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4431 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4432 .irl_init_all = mv88e6352_g2_irl_init_all,
4433 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4434 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4435 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4436 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4437 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4438 .port_set_link = mv88e6xxx_port_set_link,
4439 .port_sync_link = mv88e6xxx_port_sync_link,
4440 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4441 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4442 .port_tag_remap = mv88e6095_port_tag_remap,
4443 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4444 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4445 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4446 .port_set_ether_type = mv88e6351_port_set_ether_type,
4447 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4448 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4449 .port_pause_limit = mv88e6097_port_pause_limit,
4450 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4451 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4452 .port_get_cmode = mv88e6352_port_get_cmode,
4453 .port_setup_message_port = mv88e6xxx_setup_message_port,
4454 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4455 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4456 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4457 .stats_get_strings = mv88e6095_stats_get_strings,
4458 .stats_get_stat = mv88e6095_stats_get_stat,
4459 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4460 .set_egress_port = mv88e6095_g1_set_egress_port,
4461 .watchdog_ops = &mv88e6097_watchdog_ops,
4462 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4463 .pot_clear = mv88e6xxx_g2_pot_clear,
4464 .reset = mv88e6352_g1_reset,
4465 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4466 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4467 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4468 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4469 .stu_getnext = mv88e6352_g1_stu_getnext,
4470 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4471 .phylink_get_caps = mv88e6351_phylink_get_caps,
4472};
4473
4474static const struct mv88e6xxx_ops mv88e6172_ops = {
4475 /* MV88E6XXX_FAMILY_6352 */
4476 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4477 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4478 .irl_init_all = mv88e6352_g2_irl_init_all,
4479 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4480 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4481 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4482 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4483 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4484 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4485 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4486 .port_set_link = mv88e6xxx_port_set_link,
4487 .port_sync_link = mv88e6xxx_port_sync_link,
4488 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4489 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4490 .port_tag_remap = mv88e6095_port_tag_remap,
4491 .port_set_policy = mv88e6352_port_set_policy,
4492 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4493 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4494 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4495 .port_set_ether_type = mv88e6351_port_set_ether_type,
4496 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4497 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4498 .port_pause_limit = mv88e6097_port_pause_limit,
4499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4501 .port_get_cmode = mv88e6352_port_get_cmode,
4502 .port_setup_message_port = mv88e6xxx_setup_message_port,
4503 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4504 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4505 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4506 .stats_get_strings = mv88e6095_stats_get_strings,
4507 .stats_get_stat = mv88e6095_stats_get_stat,
4508 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4509 .set_egress_port = mv88e6095_g1_set_egress_port,
4510 .watchdog_ops = &mv88e6097_watchdog_ops,
4511 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4512 .pot_clear = mv88e6xxx_g2_pot_clear,
4513 .reset = mv88e6352_g1_reset,
4514 .rmu_disable = mv88e6352_g1_rmu_disable,
4515 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4516 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4517 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4518 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4519 .stu_getnext = mv88e6352_g1_stu_getnext,
4520 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4521 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4522 .serdes_get_regs = mv88e6352_serdes_get_regs,
4523 .gpio_ops = &mv88e6352_gpio_ops,
4524 .phylink_get_caps = mv88e6352_phylink_get_caps,
4525 .pcs_ops = &mv88e6352_pcs_ops,
4526};
4527
4528static const struct mv88e6xxx_ops mv88e6175_ops = {
4529 /* MV88E6XXX_FAMILY_6351 */
4530 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4531 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4532 .irl_init_all = mv88e6352_g2_irl_init_all,
4533 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4534 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4535 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4536 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4537 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4538 .port_set_link = mv88e6xxx_port_set_link,
4539 .port_sync_link = mv88e6xxx_port_sync_link,
4540 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4541 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4542 .port_tag_remap = mv88e6095_port_tag_remap,
4543 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4544 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4545 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4546 .port_set_ether_type = mv88e6351_port_set_ether_type,
4547 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4548 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4549 .port_pause_limit = mv88e6097_port_pause_limit,
4550 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4551 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4552 .port_get_cmode = mv88e6352_port_get_cmode,
4553 .port_setup_message_port = mv88e6xxx_setup_message_port,
4554 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4555 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4556 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4557 .stats_get_strings = mv88e6095_stats_get_strings,
4558 .stats_get_stat = mv88e6095_stats_get_stat,
4559 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4560 .set_egress_port = mv88e6095_g1_set_egress_port,
4561 .watchdog_ops = &mv88e6097_watchdog_ops,
4562 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4563 .pot_clear = mv88e6xxx_g2_pot_clear,
4564 .reset = mv88e6352_g1_reset,
4565 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4566 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4567 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4568 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4569 .stu_getnext = mv88e6352_g1_stu_getnext,
4570 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4571 .phylink_get_caps = mv88e6351_phylink_get_caps,
4572};
4573
4574static const struct mv88e6xxx_ops mv88e6176_ops = {
4575 /* MV88E6XXX_FAMILY_6352 */
4576 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4577 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4578 .irl_init_all = mv88e6352_g2_irl_init_all,
4579 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4580 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4581 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4582 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4583 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4584 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4585 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4586 .port_set_link = mv88e6xxx_port_set_link,
4587 .port_sync_link = mv88e6xxx_port_sync_link,
4588 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4589 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4590 .port_tag_remap = mv88e6095_port_tag_remap,
4591 .port_set_policy = mv88e6352_port_set_policy,
4592 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4593 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4594 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4595 .port_set_ether_type = mv88e6351_port_set_ether_type,
4596 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4598 .port_pause_limit = mv88e6097_port_pause_limit,
4599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4601 .port_get_cmode = mv88e6352_port_get_cmode,
4602 .port_setup_message_port = mv88e6xxx_setup_message_port,
4603 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4604 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4605 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4606 .stats_get_strings = mv88e6095_stats_get_strings,
4607 .stats_get_stat = mv88e6095_stats_get_stat,
4608 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4609 .set_egress_port = mv88e6095_g1_set_egress_port,
4610 .watchdog_ops = &mv88e6097_watchdog_ops,
4611 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4612 .pot_clear = mv88e6xxx_g2_pot_clear,
4613 .reset = mv88e6352_g1_reset,
4614 .rmu_disable = mv88e6352_g1_rmu_disable,
4615 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4616 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4617 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4618 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4619 .stu_getnext = mv88e6352_g1_stu_getnext,
4620 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4621 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4622 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4623 .serdes_get_regs = mv88e6352_serdes_get_regs,
4624 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4625 .gpio_ops = &mv88e6352_gpio_ops,
4626 .phylink_get_caps = mv88e6352_phylink_get_caps,
4627 .pcs_ops = &mv88e6352_pcs_ops,
4628};
4629
4630static const struct mv88e6xxx_ops mv88e6185_ops = {
4631 /* MV88E6XXX_FAMILY_6185 */
4632 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4633 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4634 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4635 .phy_read = mv88e6185_phy_ppu_read,
4636 .phy_write = mv88e6185_phy_ppu_write,
4637 .port_set_link = mv88e6xxx_port_set_link,
4638 .port_sync_link = mv88e6185_port_sync_link,
4639 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4640 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4641 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4642 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4643 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4644 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4645 .port_set_pause = mv88e6185_port_set_pause,
4646 .port_get_cmode = mv88e6185_port_get_cmode,
4647 .port_setup_message_port = mv88e6xxx_setup_message_port,
4648 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4649 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4650 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4651 .stats_get_strings = mv88e6095_stats_get_strings,
4652 .stats_get_stat = mv88e6095_stats_get_stat,
4653 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4654 .set_egress_port = mv88e6095_g1_set_egress_port,
4655 .watchdog_ops = &mv88e6097_watchdog_ops,
4656 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4657 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4658 .ppu_enable = mv88e6185_g1_ppu_enable,
4659 .ppu_disable = mv88e6185_g1_ppu_disable,
4660 .reset = mv88e6185_g1_reset,
4661 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4662 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4663 .phylink_get_caps = mv88e6185_phylink_get_caps,
4664 .pcs_ops = &mv88e6185_pcs_ops,
4665 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4666};
4667
4668static const struct mv88e6xxx_ops mv88e6190_ops = {
4669 /* MV88E6XXX_FAMILY_6390 */
4670 .setup_errata = mv88e6390_setup_errata,
4671 .irl_init_all = mv88e6390_g2_irl_init_all,
4672 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4673 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4674 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4675 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4676 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4677 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4678 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4679 .port_set_link = mv88e6xxx_port_set_link,
4680 .port_sync_link = mv88e6xxx_port_sync_link,
4681 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4682 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4683 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4684 .port_tag_remap = mv88e6390_port_tag_remap,
4685 .port_set_policy = mv88e6352_port_set_policy,
4686 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4687 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4688 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4689 .port_set_ether_type = mv88e6351_port_set_ether_type,
4690 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4691 .port_pause_limit = mv88e6390_port_pause_limit,
4692 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4693 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4694 .port_get_cmode = mv88e6352_port_get_cmode,
4695 .port_set_cmode = mv88e6390_port_set_cmode,
4696 .port_setup_message_port = mv88e6xxx_setup_message_port,
4697 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4698 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4699 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4700 .stats_get_strings = mv88e6320_stats_get_strings,
4701 .stats_get_stat = mv88e6390_stats_get_stat,
4702 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4703 .set_egress_port = mv88e6390_g1_set_egress_port,
4704 .watchdog_ops = &mv88e6390_watchdog_ops,
4705 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4706 .pot_clear = mv88e6xxx_g2_pot_clear,
4707 .reset = mv88e6352_g1_reset,
4708 .rmu_disable = mv88e6390_g1_rmu_disable,
4709 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4710 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4711 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4712 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4713 .stu_getnext = mv88e6390_g1_stu_getnext,
4714 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4715 .serdes_get_lane = mv88e6390_serdes_get_lane,
4716 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4717 .serdes_get_strings = mv88e6390_serdes_get_strings,
4718 .serdes_get_stats = mv88e6390_serdes_get_stats,
4719 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4720 .serdes_get_regs = mv88e6390_serdes_get_regs,
4721 .gpio_ops = &mv88e6352_gpio_ops,
4722 .phylink_get_caps = mv88e6390_phylink_get_caps,
4723 .pcs_ops = &mv88e6390_pcs_ops,
4724};
4725
4726static const struct mv88e6xxx_ops mv88e6190x_ops = {
4727 /* MV88E6XXX_FAMILY_6390 */
4728 .setup_errata = mv88e6390_setup_errata,
4729 .irl_init_all = mv88e6390_g2_irl_init_all,
4730 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4731 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4732 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4733 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4734 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4735 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4736 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4737 .port_set_link = mv88e6xxx_port_set_link,
4738 .port_sync_link = mv88e6xxx_port_sync_link,
4739 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4740 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4741 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4742 .port_tag_remap = mv88e6390_port_tag_remap,
4743 .port_set_policy = mv88e6352_port_set_policy,
4744 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4745 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4746 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4747 .port_set_ether_type = mv88e6351_port_set_ether_type,
4748 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4749 .port_pause_limit = mv88e6390_port_pause_limit,
4750 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4751 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4752 .port_get_cmode = mv88e6352_port_get_cmode,
4753 .port_set_cmode = mv88e6390x_port_set_cmode,
4754 .port_setup_message_port = mv88e6xxx_setup_message_port,
4755 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4756 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4757 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4758 .stats_get_strings = mv88e6320_stats_get_strings,
4759 .stats_get_stat = mv88e6390_stats_get_stat,
4760 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4761 .set_egress_port = mv88e6390_g1_set_egress_port,
4762 .watchdog_ops = &mv88e6390_watchdog_ops,
4763 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4764 .pot_clear = mv88e6xxx_g2_pot_clear,
4765 .reset = mv88e6352_g1_reset,
4766 .rmu_disable = mv88e6390_g1_rmu_disable,
4767 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4768 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4769 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4770 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4771 .stu_getnext = mv88e6390_g1_stu_getnext,
4772 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4773 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4774 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4775 .serdes_get_strings = mv88e6390_serdes_get_strings,
4776 .serdes_get_stats = mv88e6390_serdes_get_stats,
4777 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4778 .serdes_get_regs = mv88e6390_serdes_get_regs,
4779 .gpio_ops = &mv88e6352_gpio_ops,
4780 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4781 .pcs_ops = &mv88e6390_pcs_ops,
4782};
4783
4784static const struct mv88e6xxx_ops mv88e6191_ops = {
4785 /* MV88E6XXX_FAMILY_6390 */
4786 .setup_errata = mv88e6390_setup_errata,
4787 .irl_init_all = mv88e6390_g2_irl_init_all,
4788 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4789 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4790 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4791 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4792 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4793 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4794 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4795 .port_set_link = mv88e6xxx_port_set_link,
4796 .port_sync_link = mv88e6xxx_port_sync_link,
4797 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4798 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4799 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4800 .port_tag_remap = mv88e6390_port_tag_remap,
4801 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4802 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4803 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4804 .port_set_ether_type = mv88e6351_port_set_ether_type,
4805 .port_pause_limit = mv88e6390_port_pause_limit,
4806 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4807 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4808 .port_get_cmode = mv88e6352_port_get_cmode,
4809 .port_set_cmode = mv88e6390_port_set_cmode,
4810 .port_setup_message_port = mv88e6xxx_setup_message_port,
4811 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4812 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4813 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4814 .stats_get_strings = mv88e6320_stats_get_strings,
4815 .stats_get_stat = mv88e6390_stats_get_stat,
4816 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4817 .set_egress_port = mv88e6390_g1_set_egress_port,
4818 .watchdog_ops = &mv88e6390_watchdog_ops,
4819 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4820 .pot_clear = mv88e6xxx_g2_pot_clear,
4821 .reset = mv88e6352_g1_reset,
4822 .rmu_disable = mv88e6390_g1_rmu_disable,
4823 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4824 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4825 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4826 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4827 .stu_getnext = mv88e6390_g1_stu_getnext,
4828 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4829 .serdes_get_lane = mv88e6390_serdes_get_lane,
4830 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4831 .serdes_get_strings = mv88e6390_serdes_get_strings,
4832 .serdes_get_stats = mv88e6390_serdes_get_stats,
4833 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4834 .serdes_get_regs = mv88e6390_serdes_get_regs,
4835 .avb_ops = &mv88e6390_avb_ops,
4836 .ptp_ops = &mv88e6352_ptp_ops,
4837 .phylink_get_caps = mv88e6390_phylink_get_caps,
4838 .pcs_ops = &mv88e6390_pcs_ops,
4839};
4840
4841static const struct mv88e6xxx_ops mv88e6240_ops = {
4842 /* MV88E6XXX_FAMILY_6352 */
4843 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4844 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4845 .irl_init_all = mv88e6352_g2_irl_init_all,
4846 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4847 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4848 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4849 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4850 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4851 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4852 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4853 .port_set_link = mv88e6xxx_port_set_link,
4854 .port_sync_link = mv88e6xxx_port_sync_link,
4855 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4856 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4857 .port_tag_remap = mv88e6095_port_tag_remap,
4858 .port_set_policy = mv88e6352_port_set_policy,
4859 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4860 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4861 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4862 .port_set_ether_type = mv88e6351_port_set_ether_type,
4863 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4864 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4865 .port_pause_limit = mv88e6097_port_pause_limit,
4866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4868 .port_get_cmode = mv88e6352_port_get_cmode,
4869 .port_setup_message_port = mv88e6xxx_setup_message_port,
4870 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4871 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4872 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4873 .stats_get_strings = mv88e6095_stats_get_strings,
4874 .stats_get_stat = mv88e6095_stats_get_stat,
4875 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4876 .set_egress_port = mv88e6095_g1_set_egress_port,
4877 .watchdog_ops = &mv88e6097_watchdog_ops,
4878 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4879 .pot_clear = mv88e6xxx_g2_pot_clear,
4880 .reset = mv88e6352_g1_reset,
4881 .rmu_disable = mv88e6352_g1_rmu_disable,
4882 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4883 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4884 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4885 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4886 .stu_getnext = mv88e6352_g1_stu_getnext,
4887 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4888 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4889 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4890 .serdes_get_regs = mv88e6352_serdes_get_regs,
4891 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4892 .gpio_ops = &mv88e6352_gpio_ops,
4893 .avb_ops = &mv88e6352_avb_ops,
4894 .ptp_ops = &mv88e6352_ptp_ops,
4895 .phylink_get_caps = mv88e6352_phylink_get_caps,
4896 .pcs_ops = &mv88e6352_pcs_ops,
4897};
4898
4899static const struct mv88e6xxx_ops mv88e6250_ops = {
4900 /* MV88E6XXX_FAMILY_6250 */
4901 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4902 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4903 .irl_init_all = mv88e6352_g2_irl_init_all,
4904 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4905 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4906 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4907 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4908 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4909 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4910 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4911 .port_set_link = mv88e6xxx_port_set_link,
4912 .port_sync_link = mv88e6xxx_port_sync_link,
4913 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4914 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4915 .port_tag_remap = mv88e6095_port_tag_remap,
4916 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4917 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4918 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4919 .port_set_ether_type = mv88e6351_port_set_ether_type,
4920 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4921 .port_pause_limit = mv88e6097_port_pause_limit,
4922 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4923 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4924 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4925 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4926 .stats_get_strings = mv88e6250_stats_get_strings,
4927 .stats_get_stat = mv88e6250_stats_get_stat,
4928 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4929 .set_egress_port = mv88e6095_g1_set_egress_port,
4930 .watchdog_ops = &mv88e6250_watchdog_ops,
4931 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4932 .pot_clear = mv88e6xxx_g2_pot_clear,
4933 .reset = mv88e6250_g1_reset,
4934 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4935 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4936 .avb_ops = &mv88e6352_avb_ops,
4937 .ptp_ops = &mv88e6250_ptp_ops,
4938 .phylink_get_caps = mv88e6250_phylink_get_caps,
4939 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4940};
4941
4942static const struct mv88e6xxx_ops mv88e6290_ops = {
4943 /* MV88E6XXX_FAMILY_6390 */
4944 .setup_errata = mv88e6390_setup_errata,
4945 .irl_init_all = mv88e6390_g2_irl_init_all,
4946 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4947 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4948 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4949 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4950 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4951 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4952 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4953 .port_set_link = mv88e6xxx_port_set_link,
4954 .port_sync_link = mv88e6xxx_port_sync_link,
4955 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4956 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4957 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4958 .port_tag_remap = mv88e6390_port_tag_remap,
4959 .port_set_policy = mv88e6352_port_set_policy,
4960 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4961 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4962 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4963 .port_set_ether_type = mv88e6351_port_set_ether_type,
4964 .port_pause_limit = mv88e6390_port_pause_limit,
4965 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4966 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4967 .port_get_cmode = mv88e6352_port_get_cmode,
4968 .port_set_cmode = mv88e6390_port_set_cmode,
4969 .port_setup_message_port = mv88e6xxx_setup_message_port,
4970 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4971 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4972 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4973 .stats_get_strings = mv88e6320_stats_get_strings,
4974 .stats_get_stat = mv88e6390_stats_get_stat,
4975 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4976 .set_egress_port = mv88e6390_g1_set_egress_port,
4977 .watchdog_ops = &mv88e6390_watchdog_ops,
4978 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4979 .pot_clear = mv88e6xxx_g2_pot_clear,
4980 .reset = mv88e6352_g1_reset,
4981 .rmu_disable = mv88e6390_g1_rmu_disable,
4982 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4983 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4984 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4985 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4986 .stu_getnext = mv88e6390_g1_stu_getnext,
4987 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4988 .serdes_get_lane = mv88e6390_serdes_get_lane,
4989 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4990 .serdes_get_strings = mv88e6390_serdes_get_strings,
4991 .serdes_get_stats = mv88e6390_serdes_get_stats,
4992 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4993 .serdes_get_regs = mv88e6390_serdes_get_regs,
4994 .gpio_ops = &mv88e6352_gpio_ops,
4995 .avb_ops = &mv88e6390_avb_ops,
4996 .ptp_ops = &mv88e6390_ptp_ops,
4997 .phylink_get_caps = mv88e6390_phylink_get_caps,
4998 .pcs_ops = &mv88e6390_pcs_ops,
4999};
5000
5001static const struct mv88e6xxx_ops mv88e6320_ops = {
5002 /* MV88E6XXX_FAMILY_6320 */
5003 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5004 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5005 .irl_init_all = mv88e6352_g2_irl_init_all,
5006 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5007 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5008 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5009 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5010 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5011 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5012 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5013 .port_set_link = mv88e6xxx_port_set_link,
5014 .port_sync_link = mv88e6xxx_port_sync_link,
5015 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5016 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5017 .port_tag_remap = mv88e6095_port_tag_remap,
5018 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5019 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5020 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5021 .port_set_ether_type = mv88e6351_port_set_ether_type,
5022 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5023 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5024 .port_pause_limit = mv88e6097_port_pause_limit,
5025 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5026 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5027 .port_get_cmode = mv88e6352_port_get_cmode,
5028 .port_setup_message_port = mv88e6xxx_setup_message_port,
5029 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5030 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5031 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5032 .stats_get_strings = mv88e6320_stats_get_strings,
5033 .stats_get_stat = mv88e6320_stats_get_stat,
5034 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5035 .set_egress_port = mv88e6095_g1_set_egress_port,
5036 .watchdog_ops = &mv88e6390_watchdog_ops,
5037 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5038 .pot_clear = mv88e6xxx_g2_pot_clear,
5039 .reset = mv88e6352_g1_reset,
5040 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5041 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5042 .gpio_ops = &mv88e6352_gpio_ops,
5043 .avb_ops = &mv88e6352_avb_ops,
5044 .ptp_ops = &mv88e6352_ptp_ops,
5045 .phylink_get_caps = mv88e6185_phylink_get_caps,
5046};
5047
5048static const struct mv88e6xxx_ops mv88e6321_ops = {
5049 /* MV88E6XXX_FAMILY_6320 */
5050 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5051 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5052 .irl_init_all = mv88e6352_g2_irl_init_all,
5053 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5054 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5055 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5056 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5057 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5058 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5059 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5060 .port_set_link = mv88e6xxx_port_set_link,
5061 .port_sync_link = mv88e6xxx_port_sync_link,
5062 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5063 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5064 .port_tag_remap = mv88e6095_port_tag_remap,
5065 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5066 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5067 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5068 .port_set_ether_type = mv88e6351_port_set_ether_type,
5069 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5070 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5071 .port_pause_limit = mv88e6097_port_pause_limit,
5072 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5073 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5074 .port_get_cmode = mv88e6352_port_get_cmode,
5075 .port_setup_message_port = mv88e6xxx_setup_message_port,
5076 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5077 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5078 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5079 .stats_get_strings = mv88e6320_stats_get_strings,
5080 .stats_get_stat = mv88e6320_stats_get_stat,
5081 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5082 .set_egress_port = mv88e6095_g1_set_egress_port,
5083 .watchdog_ops = &mv88e6390_watchdog_ops,
5084 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5085 .reset = mv88e6352_g1_reset,
5086 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5087 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5088 .gpio_ops = &mv88e6352_gpio_ops,
5089 .avb_ops = &mv88e6352_avb_ops,
5090 .ptp_ops = &mv88e6352_ptp_ops,
5091 .phylink_get_caps = mv88e6185_phylink_get_caps,
5092};
5093
5094static const struct mv88e6xxx_ops mv88e6341_ops = {
5095 /* MV88E6XXX_FAMILY_6341 */
5096 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5097 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5098 .irl_init_all = mv88e6352_g2_irl_init_all,
5099 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5100 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5101 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5102 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5103 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5104 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5105 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5106 .port_set_link = mv88e6xxx_port_set_link,
5107 .port_sync_link = mv88e6xxx_port_sync_link,
5108 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5109 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5110 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5111 .port_tag_remap = mv88e6095_port_tag_remap,
5112 .port_set_policy = mv88e6352_port_set_policy,
5113 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5114 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5115 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5116 .port_set_ether_type = mv88e6351_port_set_ether_type,
5117 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5118 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5119 .port_pause_limit = mv88e6097_port_pause_limit,
5120 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5121 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5122 .port_get_cmode = mv88e6352_port_get_cmode,
5123 .port_set_cmode = mv88e6341_port_set_cmode,
5124 .port_setup_message_port = mv88e6xxx_setup_message_port,
5125 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5126 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5127 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5128 .stats_get_strings = mv88e6320_stats_get_strings,
5129 .stats_get_stat = mv88e6390_stats_get_stat,
5130 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5131 .set_egress_port = mv88e6390_g1_set_egress_port,
5132 .watchdog_ops = &mv88e6390_watchdog_ops,
5133 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5134 .pot_clear = mv88e6xxx_g2_pot_clear,
5135 .reset = mv88e6352_g1_reset,
5136 .rmu_disable = mv88e6390_g1_rmu_disable,
5137 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5138 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5139 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5140 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5141 .stu_getnext = mv88e6352_g1_stu_getnext,
5142 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5143 .serdes_get_lane = mv88e6341_serdes_get_lane,
5144 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5145 .gpio_ops = &mv88e6352_gpio_ops,
5146 .avb_ops = &mv88e6390_avb_ops,
5147 .ptp_ops = &mv88e6352_ptp_ops,
5148 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5149 .serdes_get_strings = mv88e6390_serdes_get_strings,
5150 .serdes_get_stats = mv88e6390_serdes_get_stats,
5151 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5152 .serdes_get_regs = mv88e6390_serdes_get_regs,
5153 .phylink_get_caps = mv88e6341_phylink_get_caps,
5154 .pcs_ops = &mv88e6390_pcs_ops,
5155};
5156
5157static const struct mv88e6xxx_ops mv88e6350_ops = {
5158 /* MV88E6XXX_FAMILY_6351 */
5159 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5160 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5161 .irl_init_all = mv88e6352_g2_irl_init_all,
5162 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5163 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5164 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5165 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5166 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5167 .port_set_link = mv88e6xxx_port_set_link,
5168 .port_sync_link = mv88e6xxx_port_sync_link,
5169 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5170 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5171 .port_tag_remap = mv88e6095_port_tag_remap,
5172 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5173 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5174 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5175 .port_set_ether_type = mv88e6351_port_set_ether_type,
5176 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5177 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5178 .port_pause_limit = mv88e6097_port_pause_limit,
5179 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5180 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5181 .port_get_cmode = mv88e6352_port_get_cmode,
5182 .port_setup_message_port = mv88e6xxx_setup_message_port,
5183 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5184 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5185 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5186 .stats_get_strings = mv88e6095_stats_get_strings,
5187 .stats_get_stat = mv88e6095_stats_get_stat,
5188 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5189 .set_egress_port = mv88e6095_g1_set_egress_port,
5190 .watchdog_ops = &mv88e6097_watchdog_ops,
5191 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5192 .pot_clear = mv88e6xxx_g2_pot_clear,
5193 .reset = mv88e6352_g1_reset,
5194 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5195 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5196 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5197 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5198 .stu_getnext = mv88e6352_g1_stu_getnext,
5199 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5200 .phylink_get_caps = mv88e6351_phylink_get_caps,
5201};
5202
5203static const struct mv88e6xxx_ops mv88e6351_ops = {
5204 /* MV88E6XXX_FAMILY_6351 */
5205 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5206 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5207 .irl_init_all = mv88e6352_g2_irl_init_all,
5208 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5209 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5210 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5211 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5212 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5213 .port_set_link = mv88e6xxx_port_set_link,
5214 .port_sync_link = mv88e6xxx_port_sync_link,
5215 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5216 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5217 .port_tag_remap = mv88e6095_port_tag_remap,
5218 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5219 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5220 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5221 .port_set_ether_type = mv88e6351_port_set_ether_type,
5222 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5223 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5224 .port_pause_limit = mv88e6097_port_pause_limit,
5225 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5226 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5227 .port_get_cmode = mv88e6352_port_get_cmode,
5228 .port_setup_message_port = mv88e6xxx_setup_message_port,
5229 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5230 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5231 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5232 .stats_get_strings = mv88e6095_stats_get_strings,
5233 .stats_get_stat = mv88e6095_stats_get_stat,
5234 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5235 .set_egress_port = mv88e6095_g1_set_egress_port,
5236 .watchdog_ops = &mv88e6097_watchdog_ops,
5237 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5238 .pot_clear = mv88e6xxx_g2_pot_clear,
5239 .reset = mv88e6352_g1_reset,
5240 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5241 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5242 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5243 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5244 .stu_getnext = mv88e6352_g1_stu_getnext,
5245 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5246 .avb_ops = &mv88e6352_avb_ops,
5247 .ptp_ops = &mv88e6352_ptp_ops,
5248 .phylink_get_caps = mv88e6351_phylink_get_caps,
5249};
5250
5251static const struct mv88e6xxx_ops mv88e6352_ops = {
5252 /* MV88E6XXX_FAMILY_6352 */
5253 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5254 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5255 .irl_init_all = mv88e6352_g2_irl_init_all,
5256 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5257 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5258 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5259 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5260 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5261 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5262 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5263 .port_set_link = mv88e6xxx_port_set_link,
5264 .port_sync_link = mv88e6xxx_port_sync_link,
5265 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5266 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5267 .port_tag_remap = mv88e6095_port_tag_remap,
5268 .port_set_policy = mv88e6352_port_set_policy,
5269 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5270 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5271 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5272 .port_set_ether_type = mv88e6351_port_set_ether_type,
5273 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5274 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5275 .port_pause_limit = mv88e6097_port_pause_limit,
5276 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5277 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5278 .port_get_cmode = mv88e6352_port_get_cmode,
5279 .port_setup_message_port = mv88e6xxx_setup_message_port,
5280 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5281 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5282 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5283 .stats_get_strings = mv88e6095_stats_get_strings,
5284 .stats_get_stat = mv88e6095_stats_get_stat,
5285 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5286 .set_egress_port = mv88e6095_g1_set_egress_port,
5287 .watchdog_ops = &mv88e6097_watchdog_ops,
5288 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5289 .pot_clear = mv88e6xxx_g2_pot_clear,
5290 .reset = mv88e6352_g1_reset,
5291 .rmu_disable = mv88e6352_g1_rmu_disable,
5292 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5293 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5294 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5295 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5296 .stu_getnext = mv88e6352_g1_stu_getnext,
5297 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5298 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5299 .gpio_ops = &mv88e6352_gpio_ops,
5300 .avb_ops = &mv88e6352_avb_ops,
5301 .ptp_ops = &mv88e6352_ptp_ops,
5302 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5303 .serdes_get_strings = mv88e6352_serdes_get_strings,
5304 .serdes_get_stats = mv88e6352_serdes_get_stats,
5305 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5306 .serdes_get_regs = mv88e6352_serdes_get_regs,
5307 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5308 .phylink_get_caps = mv88e6352_phylink_get_caps,
5309 .pcs_ops = &mv88e6352_pcs_ops,
5310};
5311
5312static const struct mv88e6xxx_ops mv88e6390_ops = {
5313 /* MV88E6XXX_FAMILY_6390 */
5314 .setup_errata = mv88e6390_setup_errata,
5315 .irl_init_all = mv88e6390_g2_irl_init_all,
5316 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5317 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5318 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5319 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5320 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5321 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5322 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5323 .port_set_link = mv88e6xxx_port_set_link,
5324 .port_sync_link = mv88e6xxx_port_sync_link,
5325 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5326 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5327 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5328 .port_tag_remap = mv88e6390_port_tag_remap,
5329 .port_set_policy = mv88e6352_port_set_policy,
5330 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5331 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5332 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5333 .port_set_ether_type = mv88e6351_port_set_ether_type,
5334 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5335 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5336 .port_pause_limit = mv88e6390_port_pause_limit,
5337 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5338 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5339 .port_get_cmode = mv88e6352_port_get_cmode,
5340 .port_set_cmode = mv88e6390_port_set_cmode,
5341 .port_setup_message_port = mv88e6xxx_setup_message_port,
5342 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5343 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5344 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5345 .stats_get_strings = mv88e6320_stats_get_strings,
5346 .stats_get_stat = mv88e6390_stats_get_stat,
5347 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5348 .set_egress_port = mv88e6390_g1_set_egress_port,
5349 .watchdog_ops = &mv88e6390_watchdog_ops,
5350 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5351 .pot_clear = mv88e6xxx_g2_pot_clear,
5352 .reset = mv88e6352_g1_reset,
5353 .rmu_disable = mv88e6390_g1_rmu_disable,
5354 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5355 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5356 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5357 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5358 .stu_getnext = mv88e6390_g1_stu_getnext,
5359 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5360 .serdes_get_lane = mv88e6390_serdes_get_lane,
5361 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5362 .gpio_ops = &mv88e6352_gpio_ops,
5363 .avb_ops = &mv88e6390_avb_ops,
5364 .ptp_ops = &mv88e6390_ptp_ops,
5365 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5366 .serdes_get_strings = mv88e6390_serdes_get_strings,
5367 .serdes_get_stats = mv88e6390_serdes_get_stats,
5368 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5369 .serdes_get_regs = mv88e6390_serdes_get_regs,
5370 .phylink_get_caps = mv88e6390_phylink_get_caps,
5371 .pcs_ops = &mv88e6390_pcs_ops,
5372};
5373
5374static const struct mv88e6xxx_ops mv88e6390x_ops = {
5375 /* MV88E6XXX_FAMILY_6390 */
5376 .setup_errata = mv88e6390_setup_errata,
5377 .irl_init_all = mv88e6390_g2_irl_init_all,
5378 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5379 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5381 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5382 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5383 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5384 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5385 .port_set_link = mv88e6xxx_port_set_link,
5386 .port_sync_link = mv88e6xxx_port_sync_link,
5387 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5388 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5389 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5390 .port_tag_remap = mv88e6390_port_tag_remap,
5391 .port_set_policy = mv88e6352_port_set_policy,
5392 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5393 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5394 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5395 .port_set_ether_type = mv88e6351_port_set_ether_type,
5396 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5397 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5398 .port_pause_limit = mv88e6390_port_pause_limit,
5399 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5400 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5401 .port_get_cmode = mv88e6352_port_get_cmode,
5402 .port_set_cmode = mv88e6390x_port_set_cmode,
5403 .port_setup_message_port = mv88e6xxx_setup_message_port,
5404 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5405 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5406 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5407 .stats_get_strings = mv88e6320_stats_get_strings,
5408 .stats_get_stat = mv88e6390_stats_get_stat,
5409 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5410 .set_egress_port = mv88e6390_g1_set_egress_port,
5411 .watchdog_ops = &mv88e6390_watchdog_ops,
5412 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5413 .pot_clear = mv88e6xxx_g2_pot_clear,
5414 .reset = mv88e6352_g1_reset,
5415 .rmu_disable = mv88e6390_g1_rmu_disable,
5416 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5417 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5418 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5419 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5420 .stu_getnext = mv88e6390_g1_stu_getnext,
5421 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5422 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5423 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5424 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5425 .serdes_get_strings = mv88e6390_serdes_get_strings,
5426 .serdes_get_stats = mv88e6390_serdes_get_stats,
5427 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5428 .serdes_get_regs = mv88e6390_serdes_get_regs,
5429 .gpio_ops = &mv88e6352_gpio_ops,
5430 .avb_ops = &mv88e6390_avb_ops,
5431 .ptp_ops = &mv88e6390_ptp_ops,
5432 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5433 .pcs_ops = &mv88e6390_pcs_ops,
5434};
5435
5436static const struct mv88e6xxx_ops mv88e6393x_ops = {
5437 /* MV88E6XXX_FAMILY_6393 */
5438 .irl_init_all = mv88e6390_g2_irl_init_all,
5439 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5440 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5441 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5442 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5443 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5444 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5445 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5446 .port_set_link = mv88e6xxx_port_set_link,
5447 .port_sync_link = mv88e6xxx_port_sync_link,
5448 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5449 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5450 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5451 .port_tag_remap = mv88e6390_port_tag_remap,
5452 .port_set_policy = mv88e6393x_port_set_policy,
5453 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5454 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5455 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5456 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5457 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5458 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5459 .port_pause_limit = mv88e6390_port_pause_limit,
5460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5462 .port_get_cmode = mv88e6352_port_get_cmode,
5463 .port_set_cmode = mv88e6393x_port_set_cmode,
5464 .port_setup_message_port = mv88e6xxx_setup_message_port,
5465 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5466 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5467 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5468 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5469 .stats_get_strings = mv88e6320_stats_get_strings,
5470 .stats_get_stat = mv88e6390_stats_get_stat,
5471 /* .set_cpu_port is missing because this family does not support a global
5472 * CPU port, only per port CPU port which is set via
5473 * .port_set_upstream_port method.
5474 */
5475 .set_egress_port = mv88e6393x_set_egress_port,
5476 .watchdog_ops = &mv88e6393x_watchdog_ops,
5477 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5478 .pot_clear = mv88e6xxx_g2_pot_clear,
5479 .reset = mv88e6352_g1_reset,
5480 .rmu_disable = mv88e6390_g1_rmu_disable,
5481 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5482 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5483 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5484 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5485 .stu_getnext = mv88e6390_g1_stu_getnext,
5486 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5487 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5488 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5489 /* TODO: serdes stats */
5490 .gpio_ops = &mv88e6352_gpio_ops,
5491 .avb_ops = &mv88e6390_avb_ops,
5492 .ptp_ops = &mv88e6352_ptp_ops,
5493 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5494 .pcs_ops = &mv88e6393x_pcs_ops,
5495};
5496
5497static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5498 [MV88E6020] = {
5499 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5500 .family = MV88E6XXX_FAMILY_6250,
5501 .name = "Marvell 88E6020",
5502 .num_databases = 64,
5503 .num_ports = 4,
5504 .num_internal_phys = 2,
5505 .max_vid = 4095,
5506 .port_base_addr = 0x8,
5507 .phy_base_addr = 0x0,
5508 .global1_addr = 0xf,
5509 .global2_addr = 0x7,
5510 .age_time_coeff = 15000,
5511 .g1_irqs = 9,
5512 .g2_irqs = 5,
5513 .atu_move_port_mask = 0xf,
5514 .dual_chip = true,
5515 .ops = &mv88e6250_ops,
5516 },
5517
5518 [MV88E6071] = {
5519 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5520 .family = MV88E6XXX_FAMILY_6250,
5521 .name = "Marvell 88E6071",
5522 .num_databases = 64,
5523 .num_ports = 7,
5524 .num_internal_phys = 5,
5525 .max_vid = 4095,
5526 .port_base_addr = 0x08,
5527 .phy_base_addr = 0x00,
5528 .global1_addr = 0x0f,
5529 .global2_addr = 0x07,
5530 .age_time_coeff = 15000,
5531 .g1_irqs = 9,
5532 .g2_irqs = 5,
5533 .atu_move_port_mask = 0xf,
5534 .dual_chip = true,
5535 .ops = &mv88e6250_ops,
5536 },
5537
5538 [MV88E6085] = {
5539 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5540 .family = MV88E6XXX_FAMILY_6097,
5541 .name = "Marvell 88E6085",
5542 .num_databases = 4096,
5543 .num_macs = 8192,
5544 .num_ports = 10,
5545 .num_internal_phys = 5,
5546 .max_vid = 4095,
5547 .max_sid = 63,
5548 .port_base_addr = 0x10,
5549 .phy_base_addr = 0x0,
5550 .global1_addr = 0x1b,
5551 .global2_addr = 0x1c,
5552 .age_time_coeff = 15000,
5553 .g1_irqs = 8,
5554 .g2_irqs = 10,
5555 .atu_move_port_mask = 0xf,
5556 .pvt = true,
5557 .multi_chip = true,
5558 .ops = &mv88e6085_ops,
5559 },
5560
5561 [MV88E6095] = {
5562 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5563 .family = MV88E6XXX_FAMILY_6095,
5564 .name = "Marvell 88E6095/88E6095F",
5565 .num_databases = 256,
5566 .num_macs = 8192,
5567 .num_ports = 11,
5568 .num_internal_phys = 0,
5569 .max_vid = 4095,
5570 .port_base_addr = 0x10,
5571 .phy_base_addr = 0x0,
5572 .global1_addr = 0x1b,
5573 .global2_addr = 0x1c,
5574 .age_time_coeff = 15000,
5575 .g1_irqs = 8,
5576 .atu_move_port_mask = 0xf,
5577 .multi_chip = true,
5578 .ops = &mv88e6095_ops,
5579 },
5580
5581 [MV88E6097] = {
5582 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5583 .family = MV88E6XXX_FAMILY_6097,
5584 .name = "Marvell 88E6097/88E6097F",
5585 .num_databases = 4096,
5586 .num_macs = 8192,
5587 .num_ports = 11,
5588 .num_internal_phys = 8,
5589 .max_vid = 4095,
5590 .max_sid = 63,
5591 .port_base_addr = 0x10,
5592 .phy_base_addr = 0x0,
5593 .global1_addr = 0x1b,
5594 .global2_addr = 0x1c,
5595 .age_time_coeff = 15000,
5596 .g1_irqs = 8,
5597 .g2_irqs = 10,
5598 .atu_move_port_mask = 0xf,
5599 .pvt = true,
5600 .multi_chip = true,
5601 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5602 .ops = &mv88e6097_ops,
5603 },
5604
5605 [MV88E6123] = {
5606 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5607 .family = MV88E6XXX_FAMILY_6165,
5608 .name = "Marvell 88E6123",
5609 .num_databases = 4096,
5610 .num_macs = 1024,
5611 .num_ports = 3,
5612 .num_internal_phys = 5,
5613 .max_vid = 4095,
5614 .max_sid = 63,
5615 .port_base_addr = 0x10,
5616 .phy_base_addr = 0x0,
5617 .global1_addr = 0x1b,
5618 .global2_addr = 0x1c,
5619 .age_time_coeff = 15000,
5620 .g1_irqs = 9,
5621 .g2_irqs = 10,
5622 .atu_move_port_mask = 0xf,
5623 .pvt = true,
5624 .multi_chip = true,
5625 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5626 .ops = &mv88e6123_ops,
5627 },
5628
5629 [MV88E6131] = {
5630 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5631 .family = MV88E6XXX_FAMILY_6185,
5632 .name = "Marvell 88E6131",
5633 .num_databases = 256,
5634 .num_macs = 8192,
5635 .num_ports = 8,
5636 .num_internal_phys = 0,
5637 .max_vid = 4095,
5638 .port_base_addr = 0x10,
5639 .phy_base_addr = 0x0,
5640 .global1_addr = 0x1b,
5641 .global2_addr = 0x1c,
5642 .age_time_coeff = 15000,
5643 .g1_irqs = 9,
5644 .atu_move_port_mask = 0xf,
5645 .multi_chip = true,
5646 .ops = &mv88e6131_ops,
5647 },
5648
5649 [MV88E6141] = {
5650 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5651 .family = MV88E6XXX_FAMILY_6341,
5652 .name = "Marvell 88E6141",
5653 .num_databases = 4096,
5654 .num_macs = 2048,
5655 .num_ports = 6,
5656 .num_internal_phys = 5,
5657 .num_gpio = 11,
5658 .max_vid = 4095,
5659 .max_sid = 63,
5660 .port_base_addr = 0x10,
5661 .phy_base_addr = 0x10,
5662 .global1_addr = 0x1b,
5663 .global2_addr = 0x1c,
5664 .age_time_coeff = 3750,
5665 .atu_move_port_mask = 0x1f,
5666 .g1_irqs = 9,
5667 .g2_irqs = 10,
5668 .pvt = true,
5669 .multi_chip = true,
5670 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5671 .ops = &mv88e6141_ops,
5672 },
5673
5674 [MV88E6161] = {
5675 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5676 .family = MV88E6XXX_FAMILY_6165,
5677 .name = "Marvell 88E6161",
5678 .num_databases = 4096,
5679 .num_macs = 1024,
5680 .num_ports = 6,
5681 .num_internal_phys = 5,
5682 .max_vid = 4095,
5683 .max_sid = 63,
5684 .port_base_addr = 0x10,
5685 .phy_base_addr = 0x0,
5686 .global1_addr = 0x1b,
5687 .global2_addr = 0x1c,
5688 .age_time_coeff = 15000,
5689 .g1_irqs = 9,
5690 .g2_irqs = 10,
5691 .atu_move_port_mask = 0xf,
5692 .pvt = true,
5693 .multi_chip = true,
5694 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5695 .ptp_support = true,
5696 .ops = &mv88e6161_ops,
5697 },
5698
5699 [MV88E6165] = {
5700 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5701 .family = MV88E6XXX_FAMILY_6165,
5702 .name = "Marvell 88E6165",
5703 .num_databases = 4096,
5704 .num_macs = 8192,
5705 .num_ports = 6,
5706 .num_internal_phys = 0,
5707 .max_vid = 4095,
5708 .max_sid = 63,
5709 .port_base_addr = 0x10,
5710 .phy_base_addr = 0x0,
5711 .global1_addr = 0x1b,
5712 .global2_addr = 0x1c,
5713 .age_time_coeff = 15000,
5714 .g1_irqs = 9,
5715 .g2_irqs = 10,
5716 .atu_move_port_mask = 0xf,
5717 .pvt = true,
5718 .multi_chip = true,
5719 .ptp_support = true,
5720 .ops = &mv88e6165_ops,
5721 },
5722
5723 [MV88E6171] = {
5724 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5725 .family = MV88E6XXX_FAMILY_6351,
5726 .name = "Marvell 88E6171",
5727 .num_databases = 4096,
5728 .num_macs = 8192,
5729 .num_ports = 7,
5730 .num_internal_phys = 5,
5731 .max_vid = 4095,
5732 .max_sid = 63,
5733 .port_base_addr = 0x10,
5734 .phy_base_addr = 0x0,
5735 .global1_addr = 0x1b,
5736 .global2_addr = 0x1c,
5737 .age_time_coeff = 15000,
5738 .g1_irqs = 9,
5739 .g2_irqs = 10,
5740 .atu_move_port_mask = 0xf,
5741 .pvt = true,
5742 .multi_chip = true,
5743 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5744 .ops = &mv88e6171_ops,
5745 },
5746
5747 [MV88E6172] = {
5748 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5749 .family = MV88E6XXX_FAMILY_6352,
5750 .name = "Marvell 88E6172",
5751 .num_databases = 4096,
5752 .num_macs = 8192,
5753 .num_ports = 7,
5754 .num_internal_phys = 5,
5755 .num_gpio = 15,
5756 .max_vid = 4095,
5757 .max_sid = 63,
5758 .port_base_addr = 0x10,
5759 .phy_base_addr = 0x0,
5760 .global1_addr = 0x1b,
5761 .global2_addr = 0x1c,
5762 .age_time_coeff = 15000,
5763 .g1_irqs = 9,
5764 .g2_irqs = 10,
5765 .atu_move_port_mask = 0xf,
5766 .pvt = true,
5767 .multi_chip = true,
5768 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5769 .ops = &mv88e6172_ops,
5770 },
5771
5772 [MV88E6175] = {
5773 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5774 .family = MV88E6XXX_FAMILY_6351,
5775 .name = "Marvell 88E6175",
5776 .num_databases = 4096,
5777 .num_macs = 8192,
5778 .num_ports = 7,
5779 .num_internal_phys = 5,
5780 .max_vid = 4095,
5781 .max_sid = 63,
5782 .port_base_addr = 0x10,
5783 .phy_base_addr = 0x0,
5784 .global1_addr = 0x1b,
5785 .global2_addr = 0x1c,
5786 .age_time_coeff = 15000,
5787 .g1_irqs = 9,
5788 .g2_irqs = 10,
5789 .atu_move_port_mask = 0xf,
5790 .pvt = true,
5791 .multi_chip = true,
5792 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5793 .ops = &mv88e6175_ops,
5794 },
5795
5796 [MV88E6176] = {
5797 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5798 .family = MV88E6XXX_FAMILY_6352,
5799 .name = "Marvell 88E6176",
5800 .num_databases = 4096,
5801 .num_macs = 8192,
5802 .num_ports = 7,
5803 .num_internal_phys = 5,
5804 .num_gpio = 15,
5805 .max_vid = 4095,
5806 .max_sid = 63,
5807 .port_base_addr = 0x10,
5808 .phy_base_addr = 0x0,
5809 .global1_addr = 0x1b,
5810 .global2_addr = 0x1c,
5811 .age_time_coeff = 15000,
5812 .g1_irqs = 9,
5813 .g2_irqs = 10,
5814 .atu_move_port_mask = 0xf,
5815 .pvt = true,
5816 .multi_chip = true,
5817 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5818 .ops = &mv88e6176_ops,
5819 },
5820
5821 [MV88E6185] = {
5822 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5823 .family = MV88E6XXX_FAMILY_6185,
5824 .name = "Marvell 88E6185",
5825 .num_databases = 256,
5826 .num_macs = 8192,
5827 .num_ports = 10,
5828 .num_internal_phys = 0,
5829 .max_vid = 4095,
5830 .port_base_addr = 0x10,
5831 .phy_base_addr = 0x0,
5832 .global1_addr = 0x1b,
5833 .global2_addr = 0x1c,
5834 .age_time_coeff = 15000,
5835 .g1_irqs = 8,
5836 .atu_move_port_mask = 0xf,
5837 .multi_chip = true,
5838 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5839 .ops = &mv88e6185_ops,
5840 },
5841
5842 [MV88E6190] = {
5843 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5844 .family = MV88E6XXX_FAMILY_6390,
5845 .name = "Marvell 88E6190",
5846 .num_databases = 4096,
5847 .num_macs = 16384,
5848 .num_ports = 11, /* 10 + Z80 */
5849 .num_internal_phys = 9,
5850 .num_gpio = 16,
5851 .max_vid = 8191,
5852 .max_sid = 63,
5853 .port_base_addr = 0x0,
5854 .phy_base_addr = 0x0,
5855 .global1_addr = 0x1b,
5856 .global2_addr = 0x1c,
5857 .age_time_coeff = 3750,
5858 .g1_irqs = 9,
5859 .g2_irqs = 14,
5860 .pvt = true,
5861 .multi_chip = true,
5862 .atu_move_port_mask = 0x1f,
5863 .ops = &mv88e6190_ops,
5864 },
5865
5866 [MV88E6190X] = {
5867 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5868 .family = MV88E6XXX_FAMILY_6390,
5869 .name = "Marvell 88E6190X",
5870 .num_databases = 4096,
5871 .num_macs = 16384,
5872 .num_ports = 11, /* 10 + Z80 */
5873 .num_internal_phys = 9,
5874 .num_gpio = 16,
5875 .max_vid = 8191,
5876 .max_sid = 63,
5877 .port_base_addr = 0x0,
5878 .phy_base_addr = 0x0,
5879 .global1_addr = 0x1b,
5880 .global2_addr = 0x1c,
5881 .age_time_coeff = 3750,
5882 .g1_irqs = 9,
5883 .g2_irqs = 14,
5884 .atu_move_port_mask = 0x1f,
5885 .pvt = true,
5886 .multi_chip = true,
5887 .ops = &mv88e6190x_ops,
5888 },
5889
5890 [MV88E6191] = {
5891 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5892 .family = MV88E6XXX_FAMILY_6390,
5893 .name = "Marvell 88E6191",
5894 .num_databases = 4096,
5895 .num_macs = 16384,
5896 .num_ports = 11, /* 10 + Z80 */
5897 .num_internal_phys = 9,
5898 .max_vid = 8191,
5899 .max_sid = 63,
5900 .port_base_addr = 0x0,
5901 .phy_base_addr = 0x0,
5902 .global1_addr = 0x1b,
5903 .global2_addr = 0x1c,
5904 .age_time_coeff = 3750,
5905 .g1_irqs = 9,
5906 .g2_irqs = 14,
5907 .atu_move_port_mask = 0x1f,
5908 .pvt = true,
5909 .multi_chip = true,
5910 .ptp_support = true,
5911 .ops = &mv88e6191_ops,
5912 },
5913
5914 [MV88E6191X] = {
5915 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5916 .family = MV88E6XXX_FAMILY_6393,
5917 .name = "Marvell 88E6191X",
5918 .num_databases = 4096,
5919 .num_ports = 11, /* 10 + Z80 */
5920 .num_internal_phys = 8,
5921 .internal_phys_offset = 1,
5922 .max_vid = 8191,
5923 .max_sid = 63,
5924 .port_base_addr = 0x0,
5925 .phy_base_addr = 0x0,
5926 .global1_addr = 0x1b,
5927 .global2_addr = 0x1c,
5928 .age_time_coeff = 3750,
5929 .g1_irqs = 10,
5930 .g2_irqs = 14,
5931 .atu_move_port_mask = 0x1f,
5932 .pvt = true,
5933 .multi_chip = true,
5934 .ptp_support = true,
5935 .ops = &mv88e6393x_ops,
5936 },
5937
5938 [MV88E6193X] = {
5939 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5940 .family = MV88E6XXX_FAMILY_6393,
5941 .name = "Marvell 88E6193X",
5942 .num_databases = 4096,
5943 .num_ports = 11, /* 10 + Z80 */
5944 .num_internal_phys = 8,
5945 .internal_phys_offset = 1,
5946 .max_vid = 8191,
5947 .max_sid = 63,
5948 .port_base_addr = 0x0,
5949 .phy_base_addr = 0x0,
5950 .global1_addr = 0x1b,
5951 .global2_addr = 0x1c,
5952 .age_time_coeff = 3750,
5953 .g1_irqs = 10,
5954 .g2_irqs = 14,
5955 .atu_move_port_mask = 0x1f,
5956 .pvt = true,
5957 .multi_chip = true,
5958 .ptp_support = true,
5959 .ops = &mv88e6393x_ops,
5960 },
5961
5962 [MV88E6220] = {
5963 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5964 .family = MV88E6XXX_FAMILY_6250,
5965 .name = "Marvell 88E6220",
5966 .num_databases = 64,
5967
5968 /* Ports 2-4 are not routed to pins
5969 * => usable ports 0, 1, 5, 6
5970 */
5971 .num_ports = 7,
5972 .num_internal_phys = 2,
5973 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5974 .max_vid = 4095,
5975 .port_base_addr = 0x08,
5976 .phy_base_addr = 0x00,
5977 .global1_addr = 0x0f,
5978 .global2_addr = 0x07,
5979 .age_time_coeff = 15000,
5980 .g1_irqs = 9,
5981 .g2_irqs = 10,
5982 .atu_move_port_mask = 0xf,
5983 .dual_chip = true,
5984 .ptp_support = true,
5985 .ops = &mv88e6250_ops,
5986 },
5987
5988 [MV88E6240] = {
5989 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5990 .family = MV88E6XXX_FAMILY_6352,
5991 .name = "Marvell 88E6240",
5992 .num_databases = 4096,
5993 .num_macs = 8192,
5994 .num_ports = 7,
5995 .num_internal_phys = 5,
5996 .num_gpio = 15,
5997 .max_vid = 4095,
5998 .max_sid = 63,
5999 .port_base_addr = 0x10,
6000 .phy_base_addr = 0x0,
6001 .global1_addr = 0x1b,
6002 .global2_addr = 0x1c,
6003 .age_time_coeff = 15000,
6004 .g1_irqs = 9,
6005 .g2_irqs = 10,
6006 .atu_move_port_mask = 0xf,
6007 .pvt = true,
6008 .multi_chip = true,
6009 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6010 .ptp_support = true,
6011 .ops = &mv88e6240_ops,
6012 },
6013
6014 [MV88E6250] = {
6015 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6016 .family = MV88E6XXX_FAMILY_6250,
6017 .name = "Marvell 88E6250",
6018 .num_databases = 64,
6019 .num_ports = 7,
6020 .num_internal_phys = 5,
6021 .max_vid = 4095,
6022 .port_base_addr = 0x08,
6023 .phy_base_addr = 0x00,
6024 .global1_addr = 0x0f,
6025 .global2_addr = 0x07,
6026 .age_time_coeff = 15000,
6027 .g1_irqs = 9,
6028 .g2_irqs = 10,
6029 .atu_move_port_mask = 0xf,
6030 .dual_chip = true,
6031 .ptp_support = true,
6032 .ops = &mv88e6250_ops,
6033 },
6034
6035 [MV88E6290] = {
6036 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6037 .family = MV88E6XXX_FAMILY_6390,
6038 .name = "Marvell 88E6290",
6039 .num_databases = 4096,
6040 .num_ports = 11, /* 10 + Z80 */
6041 .num_internal_phys = 9,
6042 .num_gpio = 16,
6043 .max_vid = 8191,
6044 .max_sid = 63,
6045 .port_base_addr = 0x0,
6046 .phy_base_addr = 0x0,
6047 .global1_addr = 0x1b,
6048 .global2_addr = 0x1c,
6049 .age_time_coeff = 3750,
6050 .g1_irqs = 9,
6051 .g2_irqs = 14,
6052 .atu_move_port_mask = 0x1f,
6053 .pvt = true,
6054 .multi_chip = true,
6055 .ptp_support = true,
6056 .ops = &mv88e6290_ops,
6057 },
6058
6059 [MV88E6320] = {
6060 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6061 .family = MV88E6XXX_FAMILY_6320,
6062 .name = "Marvell 88E6320",
6063 .num_databases = 4096,
6064 .num_macs = 8192,
6065 .num_ports = 7,
6066 .num_internal_phys = 5,
6067 .num_gpio = 15,
6068 .max_vid = 4095,
6069 .port_base_addr = 0x10,
6070 .phy_base_addr = 0x0,
6071 .global1_addr = 0x1b,
6072 .global2_addr = 0x1c,
6073 .age_time_coeff = 15000,
6074 .g1_irqs = 8,
6075 .g2_irqs = 10,
6076 .atu_move_port_mask = 0xf,
6077 .pvt = true,
6078 .multi_chip = true,
6079 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6080 .ptp_support = true,
6081 .ops = &mv88e6320_ops,
6082 },
6083
6084 [MV88E6321] = {
6085 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6086 .family = MV88E6XXX_FAMILY_6320,
6087 .name = "Marvell 88E6321",
6088 .num_databases = 4096,
6089 .num_macs = 8192,
6090 .num_ports = 7,
6091 .num_internal_phys = 5,
6092 .num_gpio = 15,
6093 .max_vid = 4095,
6094 .port_base_addr = 0x10,
6095 .phy_base_addr = 0x0,
6096 .global1_addr = 0x1b,
6097 .global2_addr = 0x1c,
6098 .age_time_coeff = 15000,
6099 .g1_irqs = 8,
6100 .g2_irqs = 10,
6101 .atu_move_port_mask = 0xf,
6102 .multi_chip = true,
6103 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6104 .ptp_support = true,
6105 .ops = &mv88e6321_ops,
6106 },
6107
6108 [MV88E6341] = {
6109 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6110 .family = MV88E6XXX_FAMILY_6341,
6111 .name = "Marvell 88E6341",
6112 .num_databases = 4096,
6113 .num_macs = 2048,
6114 .num_internal_phys = 5,
6115 .num_ports = 6,
6116 .num_gpio = 11,
6117 .max_vid = 4095,
6118 .max_sid = 63,
6119 .port_base_addr = 0x10,
6120 .phy_base_addr = 0x10,
6121 .global1_addr = 0x1b,
6122 .global2_addr = 0x1c,
6123 .age_time_coeff = 3750,
6124 .atu_move_port_mask = 0x1f,
6125 .g1_irqs = 9,
6126 .g2_irqs = 10,
6127 .pvt = true,
6128 .multi_chip = true,
6129 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6130 .ptp_support = true,
6131 .ops = &mv88e6341_ops,
6132 },
6133
6134 [MV88E6350] = {
6135 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6136 .family = MV88E6XXX_FAMILY_6351,
6137 .name = "Marvell 88E6350",
6138 .num_databases = 4096,
6139 .num_macs = 8192,
6140 .num_ports = 7,
6141 .num_internal_phys = 5,
6142 .max_vid = 4095,
6143 .max_sid = 63,
6144 .port_base_addr = 0x10,
6145 .phy_base_addr = 0x0,
6146 .global1_addr = 0x1b,
6147 .global2_addr = 0x1c,
6148 .age_time_coeff = 15000,
6149 .g1_irqs = 9,
6150 .g2_irqs = 10,
6151 .atu_move_port_mask = 0xf,
6152 .pvt = true,
6153 .multi_chip = true,
6154 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6155 .ops = &mv88e6350_ops,
6156 },
6157
6158 [MV88E6351] = {
6159 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6160 .family = MV88E6XXX_FAMILY_6351,
6161 .name = "Marvell 88E6351",
6162 .num_databases = 4096,
6163 .num_macs = 8192,
6164 .num_ports = 7,
6165 .num_internal_phys = 5,
6166 .max_vid = 4095,
6167 .max_sid = 63,
6168 .port_base_addr = 0x10,
6169 .phy_base_addr = 0x0,
6170 .global1_addr = 0x1b,
6171 .global2_addr = 0x1c,
6172 .age_time_coeff = 15000,
6173 .g1_irqs = 9,
6174 .g2_irqs = 10,
6175 .atu_move_port_mask = 0xf,
6176 .pvt = true,
6177 .multi_chip = true,
6178 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6179 .ops = &mv88e6351_ops,
6180 },
6181
6182 [MV88E6352] = {
6183 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6184 .family = MV88E6XXX_FAMILY_6352,
6185 .name = "Marvell 88E6352",
6186 .num_databases = 4096,
6187 .num_macs = 8192,
6188 .num_ports = 7,
6189 .num_internal_phys = 5,
6190 .num_gpio = 15,
6191 .max_vid = 4095,
6192 .max_sid = 63,
6193 .port_base_addr = 0x10,
6194 .phy_base_addr = 0x0,
6195 .global1_addr = 0x1b,
6196 .global2_addr = 0x1c,
6197 .age_time_coeff = 15000,
6198 .g1_irqs = 9,
6199 .g2_irqs = 10,
6200 .atu_move_port_mask = 0xf,
6201 .pvt = true,
6202 .multi_chip = true,
6203 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6204 .ptp_support = true,
6205 .ops = &mv88e6352_ops,
6206 },
6207 [MV88E6361] = {
6208 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6209 .family = MV88E6XXX_FAMILY_6393,
6210 .name = "Marvell 88E6361",
6211 .num_databases = 4096,
6212 .num_macs = 16384,
6213 .num_ports = 11,
6214 /* Ports 1, 2 and 8 are not routed */
6215 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6216 .num_internal_phys = 5,
6217 .internal_phys_offset = 3,
6218 .max_vid = 4095,
6219 .max_sid = 63,
6220 .port_base_addr = 0x0,
6221 .phy_base_addr = 0x0,
6222 .global1_addr = 0x1b,
6223 .global2_addr = 0x1c,
6224 .age_time_coeff = 3750,
6225 .g1_irqs = 10,
6226 .g2_irqs = 14,
6227 .atu_move_port_mask = 0x1f,
6228 .pvt = true,
6229 .multi_chip = true,
6230 .ptp_support = true,
6231 .ops = &mv88e6393x_ops,
6232 },
6233 [MV88E6390] = {
6234 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6235 .family = MV88E6XXX_FAMILY_6390,
6236 .name = "Marvell 88E6390",
6237 .num_databases = 4096,
6238 .num_macs = 16384,
6239 .num_ports = 11, /* 10 + Z80 */
6240 .num_internal_phys = 9,
6241 .num_gpio = 16,
6242 .max_vid = 8191,
6243 .max_sid = 63,
6244 .port_base_addr = 0x0,
6245 .phy_base_addr = 0x0,
6246 .global1_addr = 0x1b,
6247 .global2_addr = 0x1c,
6248 .age_time_coeff = 3750,
6249 .g1_irqs = 9,
6250 .g2_irqs = 14,
6251 .atu_move_port_mask = 0x1f,
6252 .pvt = true,
6253 .multi_chip = true,
6254 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6255 .ptp_support = true,
6256 .ops = &mv88e6390_ops,
6257 },
6258 [MV88E6390X] = {
6259 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6260 .family = MV88E6XXX_FAMILY_6390,
6261 .name = "Marvell 88E6390X",
6262 .num_databases = 4096,
6263 .num_macs = 16384,
6264 .num_ports = 11, /* 10 + Z80 */
6265 .num_internal_phys = 9,
6266 .num_gpio = 16,
6267 .max_vid = 8191,
6268 .max_sid = 63,
6269 .port_base_addr = 0x0,
6270 .phy_base_addr = 0x0,
6271 .global1_addr = 0x1b,
6272 .global2_addr = 0x1c,
6273 .age_time_coeff = 3750,
6274 .g1_irqs = 9,
6275 .g2_irqs = 14,
6276 .atu_move_port_mask = 0x1f,
6277 .pvt = true,
6278 .multi_chip = true,
6279 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6280 .ptp_support = true,
6281 .ops = &mv88e6390x_ops,
6282 },
6283
6284 [MV88E6393X] = {
6285 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6286 .family = MV88E6XXX_FAMILY_6393,
6287 .name = "Marvell 88E6393X",
6288 .num_databases = 4096,
6289 .num_ports = 11, /* 10 + Z80 */
6290 .num_internal_phys = 8,
6291 .internal_phys_offset = 1,
6292 .max_vid = 8191,
6293 .max_sid = 63,
6294 .port_base_addr = 0x0,
6295 .phy_base_addr = 0x0,
6296 .global1_addr = 0x1b,
6297 .global2_addr = 0x1c,
6298 .age_time_coeff = 3750,
6299 .g1_irqs = 10,
6300 .g2_irqs = 14,
6301 .atu_move_port_mask = 0x1f,
6302 .pvt = true,
6303 .multi_chip = true,
6304 .ptp_support = true,
6305 .ops = &mv88e6393x_ops,
6306 },
6307};
6308
6309static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6310{
6311 int i;
6312
6313 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6314 if (mv88e6xxx_table[i].prod_num == prod_num)
6315 return &mv88e6xxx_table[i];
6316
6317 return NULL;
6318}
6319
6320static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6321{
6322 const struct mv88e6xxx_info *info;
6323 unsigned int prod_num, rev;
6324 u16 id;
6325 int err;
6326
6327 mv88e6xxx_reg_lock(chip);
6328 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6329 mv88e6xxx_reg_unlock(chip);
6330 if (err)
6331 return err;
6332
6333 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6334 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6335
6336 info = mv88e6xxx_lookup_info(prod_num);
6337 if (!info)
6338 return -ENODEV;
6339
6340 /* Update the compatible info with the probed one */
6341 chip->info = info;
6342
6343 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6344 chip->info->prod_num, chip->info->name, rev);
6345
6346 return 0;
6347}
6348
6349static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6350 struct mdio_device *mdiodev)
6351{
6352 int err;
6353
6354 /* dual_chip takes precedence over single/multi-chip modes */
6355 if (chip->info->dual_chip)
6356 return -EINVAL;
6357
6358 /* If the mdio addr is 16 indicating the first port address of a switch
6359 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6360 * configured in single chip addressing mode. Setup the smi access as
6361 * single chip addressing mode and attempt to detect the model of the
6362 * switch, if this fails the device is not configured in single chip
6363 * addressing mode.
6364 */
6365 if (mdiodev->addr != 16)
6366 return -EINVAL;
6367
6368 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6369 if (err)
6370 return err;
6371
6372 return mv88e6xxx_detect(chip);
6373}
6374
6375static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6376{
6377 struct mv88e6xxx_chip *chip;
6378
6379 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6380 if (!chip)
6381 return NULL;
6382
6383 chip->dev = dev;
6384
6385 mutex_init(&chip->reg_lock);
6386 INIT_LIST_HEAD(&chip->mdios);
6387 idr_init(&chip->policies);
6388 INIT_LIST_HEAD(&chip->msts);
6389
6390 return chip;
6391}
6392
6393static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6394 int port,
6395 enum dsa_tag_protocol m)
6396{
6397 struct mv88e6xxx_chip *chip = ds->priv;
6398
6399 return chip->tag_protocol;
6400}
6401
6402static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6403 enum dsa_tag_protocol proto)
6404{
6405 struct mv88e6xxx_chip *chip = ds->priv;
6406 enum dsa_tag_protocol old_protocol;
6407 struct dsa_port *cpu_dp;
6408 int err;
6409
6410 switch (proto) {
6411 case DSA_TAG_PROTO_EDSA:
6412 switch (chip->info->edsa_support) {
6413 case MV88E6XXX_EDSA_UNSUPPORTED:
6414 return -EPROTONOSUPPORT;
6415 case MV88E6XXX_EDSA_UNDOCUMENTED:
6416 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6417 fallthrough;
6418 case MV88E6XXX_EDSA_SUPPORTED:
6419 break;
6420 }
6421 break;
6422 case DSA_TAG_PROTO_DSA:
6423 break;
6424 default:
6425 return -EPROTONOSUPPORT;
6426 }
6427
6428 old_protocol = chip->tag_protocol;
6429 chip->tag_protocol = proto;
6430
6431 mv88e6xxx_reg_lock(chip);
6432 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6433 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6434 if (err) {
6435 mv88e6xxx_reg_unlock(chip);
6436 goto unwind;
6437 }
6438 }
6439 mv88e6xxx_reg_unlock(chip);
6440
6441 return 0;
6442
6443unwind:
6444 chip->tag_protocol = old_protocol;
6445
6446 mv88e6xxx_reg_lock(chip);
6447 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6448 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6449 mv88e6xxx_reg_unlock(chip);
6450
6451 return err;
6452}
6453
6454static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6455 const struct switchdev_obj_port_mdb *mdb,
6456 struct dsa_db db)
6457{
6458 struct mv88e6xxx_chip *chip = ds->priv;
6459 int err;
6460
6461 mv88e6xxx_reg_lock(chip);
6462 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6463 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6464 mv88e6xxx_reg_unlock(chip);
6465
6466 return err;
6467}
6468
6469static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6470 const struct switchdev_obj_port_mdb *mdb,
6471 struct dsa_db db)
6472{
6473 struct mv88e6xxx_chip *chip = ds->priv;
6474 int err;
6475
6476 mv88e6xxx_reg_lock(chip);
6477 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6478 mv88e6xxx_reg_unlock(chip);
6479
6480 return err;
6481}
6482
6483static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6484 struct dsa_mall_mirror_tc_entry *mirror,
6485 bool ingress,
6486 struct netlink_ext_ack *extack)
6487{
6488 enum mv88e6xxx_egress_direction direction = ingress ?
6489 MV88E6XXX_EGRESS_DIR_INGRESS :
6490 MV88E6XXX_EGRESS_DIR_EGRESS;
6491 struct mv88e6xxx_chip *chip = ds->priv;
6492 bool other_mirrors = false;
6493 int i;
6494 int err;
6495
6496 mutex_lock(&chip->reg_lock);
6497 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6498 mirror->to_local_port) {
6499 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6500 other_mirrors |= ingress ?
6501 chip->ports[i].mirror_ingress :
6502 chip->ports[i].mirror_egress;
6503
6504 /* Can't change egress port when other mirror is active */
6505 if (other_mirrors) {
6506 err = -EBUSY;
6507 goto out;
6508 }
6509
6510 err = mv88e6xxx_set_egress_port(chip, direction,
6511 mirror->to_local_port);
6512 if (err)
6513 goto out;
6514 }
6515
6516 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6517out:
6518 mutex_unlock(&chip->reg_lock);
6519
6520 return err;
6521}
6522
6523static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6524 struct dsa_mall_mirror_tc_entry *mirror)
6525{
6526 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6527 MV88E6XXX_EGRESS_DIR_INGRESS :
6528 MV88E6XXX_EGRESS_DIR_EGRESS;
6529 struct mv88e6xxx_chip *chip = ds->priv;
6530 bool other_mirrors = false;
6531 int i;
6532
6533 mutex_lock(&chip->reg_lock);
6534 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6535 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6536
6537 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6538 other_mirrors |= mirror->ingress ?
6539 chip->ports[i].mirror_ingress :
6540 chip->ports[i].mirror_egress;
6541
6542 /* Reset egress port when no other mirror is active */
6543 if (!other_mirrors) {
6544 if (mv88e6xxx_set_egress_port(chip, direction,
6545 dsa_upstream_port(ds, port)))
6546 dev_err(ds->dev, "failed to set egress port\n");
6547 }
6548
6549 mutex_unlock(&chip->reg_lock);
6550}
6551
6552static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6553 struct switchdev_brport_flags flags,
6554 struct netlink_ext_ack *extack)
6555{
6556 struct mv88e6xxx_chip *chip = ds->priv;
6557 const struct mv88e6xxx_ops *ops;
6558
6559 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6560 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6561 return -EINVAL;
6562
6563 ops = chip->info->ops;
6564
6565 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6566 return -EINVAL;
6567
6568 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6569 return -EINVAL;
6570
6571 return 0;
6572}
6573
6574static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6575 struct switchdev_brport_flags flags,
6576 struct netlink_ext_ack *extack)
6577{
6578 struct mv88e6xxx_chip *chip = ds->priv;
6579 int err = 0;
6580
6581 mv88e6xxx_reg_lock(chip);
6582
6583 if (flags.mask & BR_LEARNING) {
6584 bool learning = !!(flags.val & BR_LEARNING);
6585 u16 pav = learning ? (1 << port) : 0;
6586
6587 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6588 if (err)
6589 goto out;
6590 }
6591
6592 if (flags.mask & BR_FLOOD) {
6593 bool unicast = !!(flags.val & BR_FLOOD);
6594
6595 err = chip->info->ops->port_set_ucast_flood(chip, port,
6596 unicast);
6597 if (err)
6598 goto out;
6599 }
6600
6601 if (flags.mask & BR_MCAST_FLOOD) {
6602 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6603
6604 err = chip->info->ops->port_set_mcast_flood(chip, port,
6605 multicast);
6606 if (err)
6607 goto out;
6608 }
6609
6610 if (flags.mask & BR_BCAST_FLOOD) {
6611 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6612
6613 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6614 if (err)
6615 goto out;
6616 }
6617
6618 if (flags.mask & BR_PORT_MAB) {
6619 bool mab = !!(flags.val & BR_PORT_MAB);
6620
6621 mv88e6xxx_port_set_mab(chip, port, mab);
6622 }
6623
6624 if (flags.mask & BR_PORT_LOCKED) {
6625 bool locked = !!(flags.val & BR_PORT_LOCKED);
6626
6627 err = mv88e6xxx_port_set_lock(chip, port, locked);
6628 if (err)
6629 goto out;
6630 }
6631out:
6632 mv88e6xxx_reg_unlock(chip);
6633
6634 return err;
6635}
6636
6637static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6638 struct dsa_lag lag,
6639 struct netdev_lag_upper_info *info,
6640 struct netlink_ext_ack *extack)
6641{
6642 struct mv88e6xxx_chip *chip = ds->priv;
6643 struct dsa_port *dp;
6644 int members = 0;
6645
6646 if (!mv88e6xxx_has_lag(chip)) {
6647 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6648 return false;
6649 }
6650
6651 if (!lag.id)
6652 return false;
6653
6654 dsa_lag_foreach_port(dp, ds->dst, &lag)
6655 /* Includes the port joining the LAG */
6656 members++;
6657
6658 if (members > 8) {
6659 NL_SET_ERR_MSG_MOD(extack,
6660 "Cannot offload more than 8 LAG ports");
6661 return false;
6662 }
6663
6664 /* We could potentially relax this to include active
6665 * backup in the future.
6666 */
6667 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6668 NL_SET_ERR_MSG_MOD(extack,
6669 "Can only offload LAG using hash TX type");
6670 return false;
6671 }
6672
6673 /* Ideally we would also validate that the hash type matches
6674 * the hardware. Alas, this is always set to unknown on team
6675 * interfaces.
6676 */
6677 return true;
6678}
6679
6680static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6681{
6682 struct mv88e6xxx_chip *chip = ds->priv;
6683 struct dsa_port *dp;
6684 u16 map = 0;
6685 int id;
6686
6687 /* DSA LAG IDs are one-based, hardware is zero-based */
6688 id = lag.id - 1;
6689
6690 /* Build the map of all ports to distribute flows destined for
6691 * this LAG. This can be either a local user port, or a DSA
6692 * port if the LAG port is on a remote chip.
6693 */
6694 dsa_lag_foreach_port(dp, ds->dst, &lag)
6695 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6696
6697 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6698}
6699
6700static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6701 /* Row number corresponds to the number of active members in a
6702 * LAG. Each column states which of the eight hash buckets are
6703 * mapped to the column:th port in the LAG.
6704 *
6705 * Example: In a LAG with three active ports, the second port
6706 * ([2][1]) would be selected for traffic mapped to buckets
6707 * 3,4,5 (0x38).
6708 */
6709 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6710 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6711 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6712 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6713 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6714 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6715 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6716 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6717};
6718
6719static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6720 int num_tx, int nth)
6721{
6722 u8 active = 0;
6723 int i;
6724
6725 num_tx = num_tx <= 8 ? num_tx : 8;
6726 if (nth < num_tx)
6727 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6728
6729 for (i = 0; i < 8; i++) {
6730 if (BIT(i) & active)
6731 mask[i] |= BIT(port);
6732 }
6733}
6734
6735static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6736{
6737 struct mv88e6xxx_chip *chip = ds->priv;
6738 unsigned int id, num_tx;
6739 struct dsa_port *dp;
6740 struct dsa_lag *lag;
6741 int i, err, nth;
6742 u16 mask[8];
6743 u16 ivec;
6744
6745 /* Assume no port is a member of any LAG. */
6746 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6747
6748 /* Disable all masks for ports that _are_ members of a LAG. */
6749 dsa_switch_for_each_port(dp, ds) {
6750 if (!dp->lag)
6751 continue;
6752
6753 ivec &= ~BIT(dp->index);
6754 }
6755
6756 for (i = 0; i < 8; i++)
6757 mask[i] = ivec;
6758
6759 /* Enable the correct subset of masks for all LAG ports that
6760 * are in the Tx set.
6761 */
6762 dsa_lags_foreach_id(id, ds->dst) {
6763 lag = dsa_lag_by_id(ds->dst, id);
6764 if (!lag)
6765 continue;
6766
6767 num_tx = 0;
6768 dsa_lag_foreach_port(dp, ds->dst, lag) {
6769 if (dp->lag_tx_enabled)
6770 num_tx++;
6771 }
6772
6773 if (!num_tx)
6774 continue;
6775
6776 nth = 0;
6777 dsa_lag_foreach_port(dp, ds->dst, lag) {
6778 if (!dp->lag_tx_enabled)
6779 continue;
6780
6781 if (dp->ds == ds)
6782 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6783 num_tx, nth);
6784
6785 nth++;
6786 }
6787 }
6788
6789 for (i = 0; i < 8; i++) {
6790 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6791 if (err)
6792 return err;
6793 }
6794
6795 return 0;
6796}
6797
6798static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6799 struct dsa_lag lag)
6800{
6801 int err;
6802
6803 err = mv88e6xxx_lag_sync_masks(ds);
6804
6805 if (!err)
6806 err = mv88e6xxx_lag_sync_map(ds, lag);
6807
6808 return err;
6809}
6810
6811static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6812{
6813 struct mv88e6xxx_chip *chip = ds->priv;
6814 int err;
6815
6816 mv88e6xxx_reg_lock(chip);
6817 err = mv88e6xxx_lag_sync_masks(ds);
6818 mv88e6xxx_reg_unlock(chip);
6819 return err;
6820}
6821
6822static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6823 struct dsa_lag lag,
6824 struct netdev_lag_upper_info *info,
6825 struct netlink_ext_ack *extack)
6826{
6827 struct mv88e6xxx_chip *chip = ds->priv;
6828 int err, id;
6829
6830 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6831 return -EOPNOTSUPP;
6832
6833 /* DSA LAG IDs are one-based */
6834 id = lag.id - 1;
6835
6836 mv88e6xxx_reg_lock(chip);
6837
6838 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6839 if (err)
6840 goto err_unlock;
6841
6842 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6843 if (err)
6844 goto err_clear_trunk;
6845
6846 mv88e6xxx_reg_unlock(chip);
6847 return 0;
6848
6849err_clear_trunk:
6850 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6851err_unlock:
6852 mv88e6xxx_reg_unlock(chip);
6853 return err;
6854}
6855
6856static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6857 struct dsa_lag lag)
6858{
6859 struct mv88e6xxx_chip *chip = ds->priv;
6860 int err_sync, err_trunk;
6861
6862 mv88e6xxx_reg_lock(chip);
6863 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6864 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6865 mv88e6xxx_reg_unlock(chip);
6866 return err_sync ? : err_trunk;
6867}
6868
6869static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6870 int port)
6871{
6872 struct mv88e6xxx_chip *chip = ds->priv;
6873 int err;
6874
6875 mv88e6xxx_reg_lock(chip);
6876 err = mv88e6xxx_lag_sync_masks(ds);
6877 mv88e6xxx_reg_unlock(chip);
6878 return err;
6879}
6880
6881static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6882 int port, struct dsa_lag lag,
6883 struct netdev_lag_upper_info *info,
6884 struct netlink_ext_ack *extack)
6885{
6886 struct mv88e6xxx_chip *chip = ds->priv;
6887 int err;
6888
6889 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6890 return -EOPNOTSUPP;
6891
6892 mv88e6xxx_reg_lock(chip);
6893
6894 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6895 if (err)
6896 goto unlock;
6897
6898 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6899
6900unlock:
6901 mv88e6xxx_reg_unlock(chip);
6902 return err;
6903}
6904
6905static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6906 int port, struct dsa_lag lag)
6907{
6908 struct mv88e6xxx_chip *chip = ds->priv;
6909 int err_sync, err_pvt;
6910
6911 mv88e6xxx_reg_lock(chip);
6912 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6913 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6914 mv88e6xxx_reg_unlock(chip);
6915 return err_sync ? : err_pvt;
6916}
6917
6918static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6919 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6920 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6921 .setup = mv88e6xxx_setup,
6922 .teardown = mv88e6xxx_teardown,
6923 .port_setup = mv88e6xxx_port_setup,
6924 .port_teardown = mv88e6xxx_port_teardown,
6925 .phylink_get_caps = mv88e6xxx_get_caps,
6926 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs,
6927 .phylink_mac_prepare = mv88e6xxx_mac_prepare,
6928 .phylink_mac_config = mv88e6xxx_mac_config,
6929 .phylink_mac_finish = mv88e6xxx_mac_finish,
6930 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6931 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6932 .get_strings = mv88e6xxx_get_strings,
6933 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6934 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats,
6935 .get_rmon_stats = mv88e6xxx_get_rmon_stats,
6936 .get_sset_count = mv88e6xxx_get_sset_count,
6937 .port_max_mtu = mv88e6xxx_get_max_mtu,
6938 .port_change_mtu = mv88e6xxx_change_mtu,
6939 .get_mac_eee = mv88e6xxx_get_mac_eee,
6940 .set_mac_eee = mv88e6xxx_set_mac_eee,
6941 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6942 .get_eeprom = mv88e6xxx_get_eeprom,
6943 .set_eeprom = mv88e6xxx_set_eeprom,
6944 .get_regs_len = mv88e6xxx_get_regs_len,
6945 .get_regs = mv88e6xxx_get_regs,
6946 .get_rxnfc = mv88e6xxx_get_rxnfc,
6947 .set_rxnfc = mv88e6xxx_set_rxnfc,
6948 .set_ageing_time = mv88e6xxx_set_ageing_time,
6949 .port_bridge_join = mv88e6xxx_port_bridge_join,
6950 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6951 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6952 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6953 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6954 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
6955 .port_fast_age = mv88e6xxx_port_fast_age,
6956 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
6957 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6958 .port_vlan_add = mv88e6xxx_port_vlan_add,
6959 .port_vlan_del = mv88e6xxx_port_vlan_del,
6960 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
6961 .port_fdb_add = mv88e6xxx_port_fdb_add,
6962 .port_fdb_del = mv88e6xxx_port_fdb_del,
6963 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6964 .port_mdb_add = mv88e6xxx_port_mdb_add,
6965 .port_mdb_del = mv88e6xxx_port_mdb_del,
6966 .port_mirror_add = mv88e6xxx_port_mirror_add,
6967 .port_mirror_del = mv88e6xxx_port_mirror_del,
6968 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6969 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6970 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6971 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6972 .port_txtstamp = mv88e6xxx_port_txtstamp,
6973 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6974 .get_ts_info = mv88e6xxx_get_ts_info,
6975 .devlink_param_get = mv88e6xxx_devlink_param_get,
6976 .devlink_param_set = mv88e6xxx_devlink_param_set,
6977 .devlink_info_get = mv88e6xxx_devlink_info_get,
6978 .port_lag_change = mv88e6xxx_port_lag_change,
6979 .port_lag_join = mv88e6xxx_port_lag_join,
6980 .port_lag_leave = mv88e6xxx_port_lag_leave,
6981 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6982 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6983 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6984};
6985
6986static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6987{
6988 struct device *dev = chip->dev;
6989 struct dsa_switch *ds;
6990
6991 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6992 if (!ds)
6993 return -ENOMEM;
6994
6995 ds->dev = dev;
6996 ds->num_ports = mv88e6xxx_num_ports(chip);
6997 ds->priv = chip;
6998 ds->dev = dev;
6999 ds->ops = &mv88e6xxx_switch_ops;
7000 ds->ageing_time_min = chip->info->age_time_coeff;
7001 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7002
7003 /* Some chips support up to 32, but that requires enabling the
7004 * 5-bit port mode, which we do not support. 640k^W16 ought to
7005 * be enough for anyone.
7006 */
7007 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7008
7009 dev_set_drvdata(dev, ds);
7010
7011 return dsa_register_switch(ds);
7012}
7013
7014static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7015{
7016 dsa_unregister_switch(chip->ds);
7017}
7018
7019static const void *pdata_device_get_match_data(struct device *dev)
7020{
7021 const struct of_device_id *matches = dev->driver->of_match_table;
7022 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7023
7024 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7025 matches++) {
7026 if (!strcmp(pdata->compatible, matches->compatible))
7027 return matches->data;
7028 }
7029 return NULL;
7030}
7031
7032/* There is no suspend to RAM support at DSA level yet, the switch configuration
7033 * would be lost after a power cycle so prevent it to be suspended.
7034 */
7035static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7036{
7037 return -EOPNOTSUPP;
7038}
7039
7040static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7041{
7042 return 0;
7043}
7044
7045static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7046
7047static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7048{
7049 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7050 const struct mv88e6xxx_info *compat_info = NULL;
7051 struct device *dev = &mdiodev->dev;
7052 struct device_node *np = dev->of_node;
7053 struct mv88e6xxx_chip *chip;
7054 int port;
7055 int err;
7056
7057 if (!np && !pdata)
7058 return -EINVAL;
7059
7060 if (np)
7061 compat_info = of_device_get_match_data(dev);
7062
7063 if (pdata) {
7064 compat_info = pdata_device_get_match_data(dev);
7065
7066 if (!pdata->netdev)
7067 return -EINVAL;
7068
7069 for (port = 0; port < DSA_MAX_PORTS; port++) {
7070 if (!(pdata->enabled_ports & (1 << port)))
7071 continue;
7072 if (strcmp(pdata->cd.port_names[port], "cpu"))
7073 continue;
7074 pdata->cd.netdev[port] = &pdata->netdev->dev;
7075 break;
7076 }
7077 }
7078
7079 if (!compat_info)
7080 return -EINVAL;
7081
7082 chip = mv88e6xxx_alloc_chip(dev);
7083 if (!chip) {
7084 err = -ENOMEM;
7085 goto out;
7086 }
7087
7088 chip->info = compat_info;
7089
7090 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7091 if (IS_ERR(chip->reset)) {
7092 err = PTR_ERR(chip->reset);
7093 goto out;
7094 }
7095 if (chip->reset)
7096 usleep_range(10000, 20000);
7097
7098 /* Detect if the device is configured in single chip addressing mode,
7099 * otherwise continue with address specific smi init/detection.
7100 */
7101 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7102 if (err) {
7103 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7104 if (err)
7105 goto out;
7106
7107 err = mv88e6xxx_detect(chip);
7108 if (err)
7109 goto out;
7110 }
7111
7112 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7113 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7114 else
7115 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7116
7117 mv88e6xxx_phy_init(chip);
7118
7119 if (chip->info->ops->get_eeprom) {
7120 if (np)
7121 of_property_read_u32(np, "eeprom-length",
7122 &chip->eeprom_len);
7123 else
7124 chip->eeprom_len = pdata->eeprom_len;
7125 }
7126
7127 mv88e6xxx_reg_lock(chip);
7128 err = mv88e6xxx_switch_reset(chip);
7129 mv88e6xxx_reg_unlock(chip);
7130 if (err)
7131 goto out;
7132
7133 if (np) {
7134 chip->irq = of_irq_get(np, 0);
7135 if (chip->irq == -EPROBE_DEFER) {
7136 err = chip->irq;
7137 goto out;
7138 }
7139 }
7140
7141 if (pdata)
7142 chip->irq = pdata->irq;
7143
7144 /* Has to be performed before the MDIO bus is created, because
7145 * the PHYs will link their interrupts to these interrupt
7146 * controllers
7147 */
7148 mv88e6xxx_reg_lock(chip);
7149 if (chip->irq > 0)
7150 err = mv88e6xxx_g1_irq_setup(chip);
7151 else
7152 err = mv88e6xxx_irq_poll_setup(chip);
7153 mv88e6xxx_reg_unlock(chip);
7154
7155 if (err)
7156 goto out;
7157
7158 if (chip->info->g2_irqs > 0) {
7159 err = mv88e6xxx_g2_irq_setup(chip);
7160 if (err)
7161 goto out_g1_irq;
7162 }
7163
7164 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7165 if (err)
7166 goto out_g2_irq;
7167
7168 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7169 if (err)
7170 goto out_g1_atu_prob_irq;
7171
7172 err = mv88e6xxx_register_switch(chip);
7173 if (err)
7174 goto out_g1_vtu_prob_irq;
7175
7176 return 0;
7177
7178out_g1_vtu_prob_irq:
7179 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7180out_g1_atu_prob_irq:
7181 mv88e6xxx_g1_atu_prob_irq_free(chip);
7182out_g2_irq:
7183 if (chip->info->g2_irqs > 0)
7184 mv88e6xxx_g2_irq_free(chip);
7185out_g1_irq:
7186 if (chip->irq > 0)
7187 mv88e6xxx_g1_irq_free(chip);
7188 else
7189 mv88e6xxx_irq_poll_free(chip);
7190out:
7191 if (pdata)
7192 dev_put(pdata->netdev);
7193
7194 return err;
7195}
7196
7197static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7198{
7199 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7200 struct mv88e6xxx_chip *chip;
7201
7202 if (!ds)
7203 return;
7204
7205 chip = ds->priv;
7206
7207 if (chip->info->ptp_support) {
7208 mv88e6xxx_hwtstamp_free(chip);
7209 mv88e6xxx_ptp_free(chip);
7210 }
7211
7212 mv88e6xxx_phy_destroy(chip);
7213 mv88e6xxx_unregister_switch(chip);
7214
7215 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7216 mv88e6xxx_g1_atu_prob_irq_free(chip);
7217
7218 if (chip->info->g2_irqs > 0)
7219 mv88e6xxx_g2_irq_free(chip);
7220
7221 if (chip->irq > 0)
7222 mv88e6xxx_g1_irq_free(chip);
7223 else
7224 mv88e6xxx_irq_poll_free(chip);
7225}
7226
7227static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7228{
7229 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7230
7231 if (!ds)
7232 return;
7233
7234 dsa_switch_shutdown(ds);
7235
7236 dev_set_drvdata(&mdiodev->dev, NULL);
7237}
7238
7239static const struct of_device_id mv88e6xxx_of_match[] = {
7240 {
7241 .compatible = "marvell,mv88e6085",
7242 .data = &mv88e6xxx_table[MV88E6085],
7243 },
7244 {
7245 .compatible = "marvell,mv88e6190",
7246 .data = &mv88e6xxx_table[MV88E6190],
7247 },
7248 {
7249 .compatible = "marvell,mv88e6250",
7250 .data = &mv88e6xxx_table[MV88E6250],
7251 },
7252 { /* sentinel */ },
7253};
7254
7255MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7256
7257static struct mdio_driver mv88e6xxx_driver = {
7258 .probe = mv88e6xxx_probe,
7259 .remove = mv88e6xxx_remove,
7260 .shutdown = mv88e6xxx_shutdown,
7261 .mdiodrv.driver = {
7262 .name = "mv88e6085",
7263 .of_match_table = mv88e6xxx_of_match,
7264 .pm = &mv88e6xxx_pm_ops,
7265 },
7266};
7267
7268mdio_module_driver(mv88e6xxx_driver);
7269
7270MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7271MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7272MODULE_LICENSE("GPL");
1/*
2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include <linux/delay.h>
18#include <linux/etherdevice.h>
19#include <linux/ethtool.h>
20#include <linux/if_bridge.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
24#include <linux/jiffies.h>
25#include <linux/list.h>
26#include <linux/mdio.h>
27#include <linux/module.h>
28#include <linux/of_device.h>
29#include <linux/of_irq.h>
30#include <linux/of_mdio.h>
31#include <linux/netdevice.h>
32#include <linux/gpio/consumer.h>
33#include <linux/phy.h>
34#include <net/dsa.h>
35
36#include "chip.h"
37#include "global1.h"
38#include "global2.h"
39#include "hwtstamp.h"
40#include "phy.h"
41#include "port.h"
42#include "ptp.h"
43#include "serdes.h"
44
45static void assert_reg_lock(struct mv88e6xxx_chip *chip)
46{
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
49 dump_stack();
50 }
51}
52
53/* The switch ADDR[4:1] configuration pins define the chip SMI device address
54 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
55 *
56 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
57 * is the only device connected to the SMI master. In this mode it responds to
58 * all 32 possible SMI addresses, and thus maps directly the internal devices.
59 *
60 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
61 * multiple devices to share the SMI interface. In this mode it responds to only
62 * 2 registers, used to indirectly access the internal SMI devices.
63 */
64
65static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
66 int addr, int reg, u16 *val)
67{
68 if (!chip->smi_ops)
69 return -EOPNOTSUPP;
70
71 return chip->smi_ops->read(chip, addr, reg, val);
72}
73
74static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
75 int addr, int reg, u16 val)
76{
77 if (!chip->smi_ops)
78 return -EOPNOTSUPP;
79
80 return chip->smi_ops->write(chip, addr, reg, val);
81}
82
83static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
84 int addr, int reg, u16 *val)
85{
86 int ret;
87
88 ret = mdiobus_read_nested(chip->bus, addr, reg);
89 if (ret < 0)
90 return ret;
91
92 *val = ret & 0xffff;
93
94 return 0;
95}
96
97static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
98 int addr, int reg, u16 val)
99{
100 int ret;
101
102 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
103 if (ret < 0)
104 return ret;
105
106 return 0;
107}
108
109static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
110 .read = mv88e6xxx_smi_single_chip_read,
111 .write = mv88e6xxx_smi_single_chip_write,
112};
113
114static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
115{
116 int ret;
117 int i;
118
119 for (i = 0; i < 16; i++) {
120 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
121 if (ret < 0)
122 return ret;
123
124 if ((ret & SMI_CMD_BUSY) == 0)
125 return 0;
126 }
127
128 return -ETIMEDOUT;
129}
130
131static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
132 int addr, int reg, u16 *val)
133{
134 int ret;
135
136 /* Wait for the bus to become free. */
137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
138 if (ret < 0)
139 return ret;
140
141 /* Transmit the read command. */
142 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
143 SMI_CMD_OP_22_READ | (addr << 5) | reg);
144 if (ret < 0)
145 return ret;
146
147 /* Wait for the read command to complete. */
148 ret = mv88e6xxx_smi_multi_chip_wait(chip);
149 if (ret < 0)
150 return ret;
151
152 /* Read the data. */
153 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
154 if (ret < 0)
155 return ret;
156
157 *val = ret & 0xffff;
158
159 return 0;
160}
161
162static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
163 int addr, int reg, u16 val)
164{
165 int ret;
166
167 /* Wait for the bus to become free. */
168 ret = mv88e6xxx_smi_multi_chip_wait(chip);
169 if (ret < 0)
170 return ret;
171
172 /* Transmit the data to write. */
173 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
174 if (ret < 0)
175 return ret;
176
177 /* Transmit the write command. */
178 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
179 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
180 if (ret < 0)
181 return ret;
182
183 /* Wait for the write command to complete. */
184 ret = mv88e6xxx_smi_multi_chip_wait(chip);
185 if (ret < 0)
186 return ret;
187
188 return 0;
189}
190
191static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
192 .read = mv88e6xxx_smi_multi_chip_read,
193 .write = mv88e6xxx_smi_multi_chip_write,
194};
195
196int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
197{
198 int err;
199
200 assert_reg_lock(chip);
201
202 err = mv88e6xxx_smi_read(chip, addr, reg, val);
203 if (err)
204 return err;
205
206 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
207 addr, reg, *val);
208
209 return 0;
210}
211
212int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
213{
214 int err;
215
216 assert_reg_lock(chip);
217
218 err = mv88e6xxx_smi_write(chip, addr, reg, val);
219 if (err)
220 return err;
221
222 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
223 addr, reg, val);
224
225 return 0;
226}
227
228struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
229{
230 struct mv88e6xxx_mdio_bus *mdio_bus;
231
232 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
233 list);
234 if (!mdio_bus)
235 return NULL;
236
237 return mdio_bus->bus;
238}
239
240static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
241{
242 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
243 unsigned int n = d->hwirq;
244
245 chip->g1_irq.masked |= (1 << n);
246}
247
248static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
249{
250 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
251 unsigned int n = d->hwirq;
252
253 chip->g1_irq.masked &= ~(1 << n);
254}
255
256static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
257{
258 unsigned int nhandled = 0;
259 unsigned int sub_irq;
260 unsigned int n;
261 u16 reg;
262 int err;
263
264 mutex_lock(&chip->reg_lock);
265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
266 mutex_unlock(&chip->reg_lock);
267
268 if (err)
269 goto out;
270
271 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
272 if (reg & (1 << n)) {
273 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
274 handle_nested_irq(sub_irq);
275 ++nhandled;
276 }
277 }
278out:
279 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
280}
281
282static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
283{
284 struct mv88e6xxx_chip *chip = dev_id;
285
286 return mv88e6xxx_g1_irq_thread_work(chip);
287}
288
289static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
290{
291 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
292
293 mutex_lock(&chip->reg_lock);
294}
295
296static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
297{
298 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
299 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
300 u16 reg;
301 int err;
302
303 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
304 if (err)
305 goto out;
306
307 reg &= ~mask;
308 reg |= (~chip->g1_irq.masked & mask);
309
310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
311 if (err)
312 goto out;
313
314out:
315 mutex_unlock(&chip->reg_lock);
316}
317
318static const struct irq_chip mv88e6xxx_g1_irq_chip = {
319 .name = "mv88e6xxx-g1",
320 .irq_mask = mv88e6xxx_g1_irq_mask,
321 .irq_unmask = mv88e6xxx_g1_irq_unmask,
322 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
323 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
324};
325
326static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
327 unsigned int irq,
328 irq_hw_number_t hwirq)
329{
330 struct mv88e6xxx_chip *chip = d->host_data;
331
332 irq_set_chip_data(irq, d->host_data);
333 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
334 irq_set_noprobe(irq);
335
336 return 0;
337}
338
339static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
340 .map = mv88e6xxx_g1_irq_domain_map,
341 .xlate = irq_domain_xlate_twocell,
342};
343
344static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
345{
346 int irq, virq;
347 u16 mask;
348
349 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
350 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
351 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
352
353 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
354 virq = irq_find_mapping(chip->g1_irq.domain, irq);
355 irq_dispose_mapping(virq);
356 }
357
358 irq_domain_remove(chip->g1_irq.domain);
359}
360
361static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
362{
363 mv88e6xxx_g1_irq_free_common(chip);
364
365 free_irq(chip->irq, chip);
366}
367
368static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
369{
370 int err, irq, virq;
371 u16 reg, mask;
372
373 chip->g1_irq.nirqs = chip->info->g1_irqs;
374 chip->g1_irq.domain = irq_domain_add_simple(
375 NULL, chip->g1_irq.nirqs, 0,
376 &mv88e6xxx_g1_irq_domain_ops, chip);
377 if (!chip->g1_irq.domain)
378 return -ENOMEM;
379
380 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
381 irq_create_mapping(chip->g1_irq.domain, irq);
382
383 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
384 chip->g1_irq.masked = ~0;
385
386 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
387 if (err)
388 goto out_mapping;
389
390 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
391
392 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
393 if (err)
394 goto out_disable;
395
396 /* Reading the interrupt status clears (most of) them */
397 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
398 if (err)
399 goto out_disable;
400
401 return 0;
402
403out_disable:
404 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
405 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
406
407out_mapping:
408 for (irq = 0; irq < 16; irq++) {
409 virq = irq_find_mapping(chip->g1_irq.domain, irq);
410 irq_dispose_mapping(virq);
411 }
412
413 irq_domain_remove(chip->g1_irq.domain);
414
415 return err;
416}
417
418static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
419{
420 int err;
421
422 err = mv88e6xxx_g1_irq_setup_common(chip);
423 if (err)
424 return err;
425
426 err = request_threaded_irq(chip->irq, NULL,
427 mv88e6xxx_g1_irq_thread_fn,
428 IRQF_ONESHOT,
429 dev_name(chip->dev), chip);
430 if (err)
431 mv88e6xxx_g1_irq_free_common(chip);
432
433 return err;
434}
435
436static void mv88e6xxx_irq_poll(struct kthread_work *work)
437{
438 struct mv88e6xxx_chip *chip = container_of(work,
439 struct mv88e6xxx_chip,
440 irq_poll_work.work);
441 mv88e6xxx_g1_irq_thread_work(chip);
442
443 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
444 msecs_to_jiffies(100));
445}
446
447static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
448{
449 int err;
450
451 err = mv88e6xxx_g1_irq_setup_common(chip);
452 if (err)
453 return err;
454
455 kthread_init_delayed_work(&chip->irq_poll_work,
456 mv88e6xxx_irq_poll);
457
458 chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
459 if (IS_ERR(chip->kworker))
460 return PTR_ERR(chip->kworker);
461
462 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
463 msecs_to_jiffies(100));
464
465 return 0;
466}
467
468static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
469{
470 mv88e6xxx_g1_irq_free_common(chip);
471
472 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
473 kthread_destroy_worker(chip->kworker);
474}
475
476int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
477{
478 int i;
479
480 for (i = 0; i < 16; i++) {
481 u16 val;
482 int err;
483
484 err = mv88e6xxx_read(chip, addr, reg, &val);
485 if (err)
486 return err;
487
488 if (!(val & mask))
489 return 0;
490
491 usleep_range(1000, 2000);
492 }
493
494 dev_err(chip->dev, "Timeout while waiting for switch\n");
495 return -ETIMEDOUT;
496}
497
498/* Indirect write to single pointer-data register with an Update bit */
499int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
500{
501 u16 val;
502 int err;
503
504 /* Wait until the previous operation is completed */
505 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
506 if (err)
507 return err;
508
509 /* Set the Update bit to trigger a write operation */
510 val = BIT(15) | update;
511
512 return mv88e6xxx_write(chip, addr, reg, val);
513}
514
515static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
516 int link, int speed, int duplex,
517 phy_interface_t mode)
518{
519 int err;
520
521 if (!chip->info->ops->port_set_link)
522 return 0;
523
524 /* Port's MAC control must not be changed unless the link is down */
525 err = chip->info->ops->port_set_link(chip, port, 0);
526 if (err)
527 return err;
528
529 if (chip->info->ops->port_set_speed) {
530 err = chip->info->ops->port_set_speed(chip, port, speed);
531 if (err && err != -EOPNOTSUPP)
532 goto restore_link;
533 }
534
535 if (chip->info->ops->port_set_duplex) {
536 err = chip->info->ops->port_set_duplex(chip, port, duplex);
537 if (err && err != -EOPNOTSUPP)
538 goto restore_link;
539 }
540
541 if (chip->info->ops->port_set_rgmii_delay) {
542 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
543 if (err && err != -EOPNOTSUPP)
544 goto restore_link;
545 }
546
547 if (chip->info->ops->port_set_cmode) {
548 err = chip->info->ops->port_set_cmode(chip, port, mode);
549 if (err && err != -EOPNOTSUPP)
550 goto restore_link;
551 }
552
553 err = 0;
554restore_link:
555 if (chip->info->ops->port_set_link(chip, port, link))
556 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
557
558 return err;
559}
560
561/* We expect the switch to perform auto negotiation if there is a real
562 * phy. However, in the case of a fixed link phy, we force the port
563 * settings from the fixed link settings.
564 */
565static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
566 struct phy_device *phydev)
567{
568 struct mv88e6xxx_chip *chip = ds->priv;
569 int err;
570
571 if (!phy_is_pseudo_fixed_link(phydev))
572 return;
573
574 mutex_lock(&chip->reg_lock);
575 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
576 phydev->duplex, phydev->interface);
577 mutex_unlock(&chip->reg_lock);
578
579 if (err && err != -EOPNOTSUPP)
580 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
581}
582
583static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
584{
585 if (!chip->info->ops->stats_snapshot)
586 return -EOPNOTSUPP;
587
588 return chip->info->ops->stats_snapshot(chip, port);
589}
590
591static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
592 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
593 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
594 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
595 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
596 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
597 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
598 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
599 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
600 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
601 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
602 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
603 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
604 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
605 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
606 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
607 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
608 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
609 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
610 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
611 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
612 { "single", 4, 0x14, STATS_TYPE_BANK0, },
613 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
614 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
615 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
616 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
617 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
618 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
619 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
620 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
621 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
622 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
623 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
624 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
625 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
626 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
627 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
628 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
629 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
630 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
631 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
632 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
633 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
634 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
635 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
636 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
637 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
638 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
639 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
640 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
641 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
642 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
643 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
644 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
645 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
646 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
647 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
648 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
649 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
650 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
651};
652
653static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
654 struct mv88e6xxx_hw_stat *s,
655 int port, u16 bank1_select,
656 u16 histogram)
657{
658 u32 low;
659 u32 high = 0;
660 u16 reg = 0;
661 int err;
662 u64 value;
663
664 switch (s->type) {
665 case STATS_TYPE_PORT:
666 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
667 if (err)
668 return UINT64_MAX;
669
670 low = reg;
671 if (s->size == 4) {
672 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
673 if (err)
674 return UINT64_MAX;
675 high = reg;
676 }
677 break;
678 case STATS_TYPE_BANK1:
679 reg = bank1_select;
680 /* fall through */
681 case STATS_TYPE_BANK0:
682 reg |= s->reg | histogram;
683 mv88e6xxx_g1_stats_read(chip, reg, &low);
684 if (s->size == 8)
685 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
686 break;
687 default:
688 return UINT64_MAX;
689 }
690 value = (((u64)high) << 16) | low;
691 return value;
692}
693
694static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
695 uint8_t *data, int types)
696{
697 struct mv88e6xxx_hw_stat *stat;
698 int i, j;
699
700 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
701 stat = &mv88e6xxx_hw_stats[i];
702 if (stat->type & types) {
703 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
704 ETH_GSTRING_LEN);
705 j++;
706 }
707 }
708
709 return j;
710}
711
712static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
713 uint8_t *data)
714{
715 return mv88e6xxx_stats_get_strings(chip, data,
716 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
717}
718
719static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
720 uint8_t *data)
721{
722 return mv88e6xxx_stats_get_strings(chip, data,
723 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
724}
725
726static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
727 "atu_member_violation",
728 "atu_miss_violation",
729 "atu_full_violation",
730 "vtu_member_violation",
731 "vtu_miss_violation",
732};
733
734static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
735{
736 unsigned int i;
737
738 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
739 strlcpy(data + i * ETH_GSTRING_LEN,
740 mv88e6xxx_atu_vtu_stats_strings[i],
741 ETH_GSTRING_LEN);
742}
743
744static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
745 uint8_t *data)
746{
747 struct mv88e6xxx_chip *chip = ds->priv;
748 int count = 0;
749
750 mutex_lock(&chip->reg_lock);
751
752 if (chip->info->ops->stats_get_strings)
753 count = chip->info->ops->stats_get_strings(chip, data);
754
755 if (chip->info->ops->serdes_get_strings) {
756 data += count * ETH_GSTRING_LEN;
757 count = chip->info->ops->serdes_get_strings(chip, port, data);
758 }
759
760 data += count * ETH_GSTRING_LEN;
761 mv88e6xxx_atu_vtu_get_strings(data);
762
763 mutex_unlock(&chip->reg_lock);
764}
765
766static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
767 int types)
768{
769 struct mv88e6xxx_hw_stat *stat;
770 int i, j;
771
772 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
773 stat = &mv88e6xxx_hw_stats[i];
774 if (stat->type & types)
775 j++;
776 }
777 return j;
778}
779
780static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
781{
782 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
783 STATS_TYPE_PORT);
784}
785
786static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
787{
788 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
789 STATS_TYPE_BANK1);
790}
791
792static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port)
793{
794 struct mv88e6xxx_chip *chip = ds->priv;
795 int serdes_count = 0;
796 int count = 0;
797
798 mutex_lock(&chip->reg_lock);
799 if (chip->info->ops->stats_get_sset_count)
800 count = chip->info->ops->stats_get_sset_count(chip);
801 if (count < 0)
802 goto out;
803
804 if (chip->info->ops->serdes_get_sset_count)
805 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
806 port);
807 if (serdes_count < 0) {
808 count = serdes_count;
809 goto out;
810 }
811 count += serdes_count;
812 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
813
814out:
815 mutex_unlock(&chip->reg_lock);
816
817 return count;
818}
819
820static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
821 uint64_t *data, int types,
822 u16 bank1_select, u16 histogram)
823{
824 struct mv88e6xxx_hw_stat *stat;
825 int i, j;
826
827 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
828 stat = &mv88e6xxx_hw_stats[i];
829 if (stat->type & types) {
830 mutex_lock(&chip->reg_lock);
831 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
832 bank1_select,
833 histogram);
834 mutex_unlock(&chip->reg_lock);
835
836 j++;
837 }
838 }
839 return j;
840}
841
842static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
843 uint64_t *data)
844{
845 return mv88e6xxx_stats_get_stats(chip, port, data,
846 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
847 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
848}
849
850static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
851 uint64_t *data)
852{
853 return mv88e6xxx_stats_get_stats(chip, port, data,
854 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
855 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
856 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
857}
858
859static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
860 uint64_t *data)
861{
862 return mv88e6xxx_stats_get_stats(chip, port, data,
863 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
864 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
865 0);
866}
867
868static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
869 uint64_t *data)
870{
871 *data++ = chip->ports[port].atu_member_violation;
872 *data++ = chip->ports[port].atu_miss_violation;
873 *data++ = chip->ports[port].atu_full_violation;
874 *data++ = chip->ports[port].vtu_member_violation;
875 *data++ = chip->ports[port].vtu_miss_violation;
876}
877
878static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
879 uint64_t *data)
880{
881 int count = 0;
882
883 if (chip->info->ops->stats_get_stats)
884 count = chip->info->ops->stats_get_stats(chip, port, data);
885
886 mutex_lock(&chip->reg_lock);
887 if (chip->info->ops->serdes_get_stats) {
888 data += count;
889 count = chip->info->ops->serdes_get_stats(chip, port, data);
890 }
891 data += count;
892 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
893 mutex_unlock(&chip->reg_lock);
894}
895
896static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
897 uint64_t *data)
898{
899 struct mv88e6xxx_chip *chip = ds->priv;
900 int ret;
901
902 mutex_lock(&chip->reg_lock);
903
904 ret = mv88e6xxx_stats_snapshot(chip, port);
905 mutex_unlock(&chip->reg_lock);
906
907 if (ret < 0)
908 return;
909
910 mv88e6xxx_get_stats(chip, port, data);
911
912}
913
914static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
915{
916 if (chip->info->ops->stats_set_histogram)
917 return chip->info->ops->stats_set_histogram(chip);
918
919 return 0;
920}
921
922static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
923{
924 return 32 * sizeof(u16);
925}
926
927static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
928 struct ethtool_regs *regs, void *_p)
929{
930 struct mv88e6xxx_chip *chip = ds->priv;
931 int err;
932 u16 reg;
933 u16 *p = _p;
934 int i;
935
936 regs->version = 0;
937
938 memset(p, 0xff, 32 * sizeof(u16));
939
940 mutex_lock(&chip->reg_lock);
941
942 for (i = 0; i < 32; i++) {
943
944 err = mv88e6xxx_port_read(chip, port, i, ®);
945 if (!err)
946 p[i] = reg;
947 }
948
949 mutex_unlock(&chip->reg_lock);
950}
951
952static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
953 struct ethtool_eee *e)
954{
955 /* Nothing to do on the port's MAC */
956 return 0;
957}
958
959static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
960 struct ethtool_eee *e)
961{
962 /* Nothing to do on the port's MAC */
963 return 0;
964}
965
966static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
967{
968 struct dsa_switch *ds = NULL;
969 struct net_device *br;
970 u16 pvlan;
971 int i;
972
973 if (dev < DSA_MAX_SWITCHES)
974 ds = chip->ds->dst->ds[dev];
975
976 /* Prevent frames from unknown switch or port */
977 if (!ds || port >= ds->num_ports)
978 return 0;
979
980 /* Frames from DSA links and CPU ports can egress any local port */
981 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
982 return mv88e6xxx_port_mask(chip);
983
984 br = ds->ports[port].bridge_dev;
985 pvlan = 0;
986
987 /* Frames from user ports can egress any local DSA links and CPU ports,
988 * as well as any local member of their bridge group.
989 */
990 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
991 if (dsa_is_cpu_port(chip->ds, i) ||
992 dsa_is_dsa_port(chip->ds, i) ||
993 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
994 pvlan |= BIT(i);
995
996 return pvlan;
997}
998
999static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1000{
1001 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1002
1003 /* prevent frames from going back out of the port they came in on */
1004 output_ports &= ~BIT(port);
1005
1006 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1007}
1008
1009static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1010 u8 state)
1011{
1012 struct mv88e6xxx_chip *chip = ds->priv;
1013 int err;
1014
1015 mutex_lock(&chip->reg_lock);
1016 err = mv88e6xxx_port_set_state(chip, port, state);
1017 mutex_unlock(&chip->reg_lock);
1018
1019 if (err)
1020 dev_err(ds->dev, "p%d: failed to update state\n", port);
1021}
1022
1023static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1024{
1025 if (chip->info->ops->pot_clear)
1026 return chip->info->ops->pot_clear(chip);
1027
1028 return 0;
1029}
1030
1031static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1032{
1033 if (chip->info->ops->mgmt_rsvd2cpu)
1034 return chip->info->ops->mgmt_rsvd2cpu(chip);
1035
1036 return 0;
1037}
1038
1039static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1040{
1041 int err;
1042
1043 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1044 if (err)
1045 return err;
1046
1047 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1048 if (err)
1049 return err;
1050
1051 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1052}
1053
1054static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1055{
1056 int port;
1057 int err;
1058
1059 if (!chip->info->ops->irl_init_all)
1060 return 0;
1061
1062 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1063 /* Disable ingress rate limiting by resetting all per port
1064 * ingress rate limit resources to their initial state.
1065 */
1066 err = chip->info->ops->irl_init_all(chip, port);
1067 if (err)
1068 return err;
1069 }
1070
1071 return 0;
1072}
1073
1074static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1075{
1076 if (chip->info->ops->set_switch_mac) {
1077 u8 addr[ETH_ALEN];
1078
1079 eth_random_addr(addr);
1080
1081 return chip->info->ops->set_switch_mac(chip, addr);
1082 }
1083
1084 return 0;
1085}
1086
1087static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1088{
1089 u16 pvlan = 0;
1090
1091 if (!mv88e6xxx_has_pvt(chip))
1092 return -EOPNOTSUPP;
1093
1094 /* Skip the local source device, which uses in-chip port VLAN */
1095 if (dev != chip->ds->index)
1096 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1097
1098 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1099}
1100
1101static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1102{
1103 int dev, port;
1104 int err;
1105
1106 if (!mv88e6xxx_has_pvt(chip))
1107 return 0;
1108
1109 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1110 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1111 */
1112 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1113 if (err)
1114 return err;
1115
1116 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1117 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1118 err = mv88e6xxx_pvt_map(chip, dev, port);
1119 if (err)
1120 return err;
1121 }
1122 }
1123
1124 return 0;
1125}
1126
1127static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1128{
1129 struct mv88e6xxx_chip *chip = ds->priv;
1130 int err;
1131
1132 mutex_lock(&chip->reg_lock);
1133 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1134 mutex_unlock(&chip->reg_lock);
1135
1136 if (err)
1137 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1138}
1139
1140static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1141{
1142 if (!chip->info->max_vid)
1143 return 0;
1144
1145 return mv88e6xxx_g1_vtu_flush(chip);
1146}
1147
1148static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1149 struct mv88e6xxx_vtu_entry *entry)
1150{
1151 if (!chip->info->ops->vtu_getnext)
1152 return -EOPNOTSUPP;
1153
1154 return chip->info->ops->vtu_getnext(chip, entry);
1155}
1156
1157static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1158 struct mv88e6xxx_vtu_entry *entry)
1159{
1160 if (!chip->info->ops->vtu_loadpurge)
1161 return -EOPNOTSUPP;
1162
1163 return chip->info->ops->vtu_loadpurge(chip, entry);
1164}
1165
1166static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1167{
1168 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1169 struct mv88e6xxx_vtu_entry vlan = {
1170 .vid = chip->info->max_vid,
1171 };
1172 int i, err;
1173
1174 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1175
1176 /* Set every FID bit used by the (un)bridged ports */
1177 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1178 err = mv88e6xxx_port_get_fid(chip, i, fid);
1179 if (err)
1180 return err;
1181
1182 set_bit(*fid, fid_bitmap);
1183 }
1184
1185 /* Set every FID bit used by the VLAN entries */
1186 do {
1187 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1188 if (err)
1189 return err;
1190
1191 if (!vlan.valid)
1192 break;
1193
1194 set_bit(vlan.fid, fid_bitmap);
1195 } while (vlan.vid < chip->info->max_vid);
1196
1197 /* The reset value 0x000 is used to indicate that multiple address
1198 * databases are not needed. Return the next positive available.
1199 */
1200 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1201 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1202 return -ENOSPC;
1203
1204 /* Clear the database */
1205 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1206}
1207
1208static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1209 struct mv88e6xxx_vtu_entry *entry, bool new)
1210{
1211 int err;
1212
1213 if (!vid)
1214 return -EINVAL;
1215
1216 entry->vid = vid - 1;
1217 entry->valid = false;
1218
1219 err = mv88e6xxx_vtu_getnext(chip, entry);
1220 if (err)
1221 return err;
1222
1223 if (entry->vid == vid && entry->valid)
1224 return 0;
1225
1226 if (new) {
1227 int i;
1228
1229 /* Initialize a fresh VLAN entry */
1230 memset(entry, 0, sizeof(*entry));
1231 entry->valid = true;
1232 entry->vid = vid;
1233
1234 /* Exclude all ports */
1235 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1236 entry->member[i] =
1237 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1238
1239 return mv88e6xxx_atu_new(chip, &entry->fid);
1240 }
1241
1242 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1243 return -EOPNOTSUPP;
1244}
1245
1246static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1247 u16 vid_begin, u16 vid_end)
1248{
1249 struct mv88e6xxx_chip *chip = ds->priv;
1250 struct mv88e6xxx_vtu_entry vlan = {
1251 .vid = vid_begin - 1,
1252 };
1253 int i, err;
1254
1255 /* DSA and CPU ports have to be members of multiple vlans */
1256 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1257 return 0;
1258
1259 if (!vid_begin)
1260 return -EOPNOTSUPP;
1261
1262 mutex_lock(&chip->reg_lock);
1263
1264 do {
1265 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1266 if (err)
1267 goto unlock;
1268
1269 if (!vlan.valid)
1270 break;
1271
1272 if (vlan.vid > vid_end)
1273 break;
1274
1275 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1276 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1277 continue;
1278
1279 if (!ds->ports[i].slave)
1280 continue;
1281
1282 if (vlan.member[i] ==
1283 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1284 continue;
1285
1286 if (dsa_to_port(ds, i)->bridge_dev ==
1287 ds->ports[port].bridge_dev)
1288 break; /* same bridge, check next VLAN */
1289
1290 if (!dsa_to_port(ds, i)->bridge_dev)
1291 continue;
1292
1293 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1294 port, vlan.vid, i,
1295 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1296 err = -EOPNOTSUPP;
1297 goto unlock;
1298 }
1299 } while (vlan.vid < vid_end);
1300
1301unlock:
1302 mutex_unlock(&chip->reg_lock);
1303
1304 return err;
1305}
1306
1307static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1308 bool vlan_filtering)
1309{
1310 struct mv88e6xxx_chip *chip = ds->priv;
1311 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1312 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1313 int err;
1314
1315 if (!chip->info->max_vid)
1316 return -EOPNOTSUPP;
1317
1318 mutex_lock(&chip->reg_lock);
1319 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1320 mutex_unlock(&chip->reg_lock);
1321
1322 return err;
1323}
1324
1325static int
1326mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1327 const struct switchdev_obj_port_vlan *vlan)
1328{
1329 struct mv88e6xxx_chip *chip = ds->priv;
1330 int err;
1331
1332 if (!chip->info->max_vid)
1333 return -EOPNOTSUPP;
1334
1335 /* If the requested port doesn't belong to the same bridge as the VLAN
1336 * members, do not support it (yet) and fallback to software VLAN.
1337 */
1338 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1339 vlan->vid_end);
1340 if (err)
1341 return err;
1342
1343 /* We don't need any dynamic resource from the kernel (yet),
1344 * so skip the prepare phase.
1345 */
1346 return 0;
1347}
1348
1349static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1350 const unsigned char *addr, u16 vid,
1351 u8 state)
1352{
1353 struct mv88e6xxx_vtu_entry vlan;
1354 struct mv88e6xxx_atu_entry entry;
1355 int err;
1356
1357 /* Null VLAN ID corresponds to the port private database */
1358 if (vid == 0)
1359 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1360 else
1361 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1362 if (err)
1363 return err;
1364
1365 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1366 ether_addr_copy(entry.mac, addr);
1367 eth_addr_dec(entry.mac);
1368
1369 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1370 if (err)
1371 return err;
1372
1373 /* Initialize a fresh ATU entry if it isn't found */
1374 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1375 !ether_addr_equal(entry.mac, addr)) {
1376 memset(&entry, 0, sizeof(entry));
1377 ether_addr_copy(entry.mac, addr);
1378 }
1379
1380 /* Purge the ATU entry only if no port is using it anymore */
1381 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1382 entry.portvec &= ~BIT(port);
1383 if (!entry.portvec)
1384 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1385 } else {
1386 entry.portvec |= BIT(port);
1387 entry.state = state;
1388 }
1389
1390 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1391}
1392
1393static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1394 u16 vid)
1395{
1396 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1397 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1398
1399 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1400}
1401
1402static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1403{
1404 int port;
1405 int err;
1406
1407 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1408 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1409 if (err)
1410 return err;
1411 }
1412
1413 return 0;
1414}
1415
1416static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1417 u16 vid, u8 member)
1418{
1419 struct mv88e6xxx_vtu_entry vlan;
1420 int err;
1421
1422 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1423 if (err)
1424 return err;
1425
1426 vlan.member[port] = member;
1427
1428 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1429 if (err)
1430 return err;
1431
1432 return mv88e6xxx_broadcast_setup(chip, vid);
1433}
1434
1435static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1436 const struct switchdev_obj_port_vlan *vlan)
1437{
1438 struct mv88e6xxx_chip *chip = ds->priv;
1439 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1440 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1441 u8 member;
1442 u16 vid;
1443
1444 if (!chip->info->max_vid)
1445 return;
1446
1447 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1448 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1449 else if (untagged)
1450 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1451 else
1452 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1453
1454 mutex_lock(&chip->reg_lock);
1455
1456 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1457 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1458 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1459 vid, untagged ? 'u' : 't');
1460
1461 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1462 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1463 vlan->vid_end);
1464
1465 mutex_unlock(&chip->reg_lock);
1466}
1467
1468static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1469 int port, u16 vid)
1470{
1471 struct mv88e6xxx_vtu_entry vlan;
1472 int i, err;
1473
1474 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1475 if (err)
1476 return err;
1477
1478 /* Tell switchdev if this VLAN is handled in software */
1479 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1480 return -EOPNOTSUPP;
1481
1482 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1483
1484 /* keep the VLAN unless all ports are excluded */
1485 vlan.valid = false;
1486 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1487 if (vlan.member[i] !=
1488 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1489 vlan.valid = true;
1490 break;
1491 }
1492 }
1493
1494 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1495 if (err)
1496 return err;
1497
1498 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1499}
1500
1501static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1502 const struct switchdev_obj_port_vlan *vlan)
1503{
1504 struct mv88e6xxx_chip *chip = ds->priv;
1505 u16 pvid, vid;
1506 int err = 0;
1507
1508 if (!chip->info->max_vid)
1509 return -EOPNOTSUPP;
1510
1511 mutex_lock(&chip->reg_lock);
1512
1513 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1514 if (err)
1515 goto unlock;
1516
1517 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1518 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1519 if (err)
1520 goto unlock;
1521
1522 if (vid == pvid) {
1523 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1524 if (err)
1525 goto unlock;
1526 }
1527 }
1528
1529unlock:
1530 mutex_unlock(&chip->reg_lock);
1531
1532 return err;
1533}
1534
1535static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1536 const unsigned char *addr, u16 vid)
1537{
1538 struct mv88e6xxx_chip *chip = ds->priv;
1539 int err;
1540
1541 mutex_lock(&chip->reg_lock);
1542 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1543 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1544 mutex_unlock(&chip->reg_lock);
1545
1546 return err;
1547}
1548
1549static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1550 const unsigned char *addr, u16 vid)
1551{
1552 struct mv88e6xxx_chip *chip = ds->priv;
1553 int err;
1554
1555 mutex_lock(&chip->reg_lock);
1556 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1557 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1558 mutex_unlock(&chip->reg_lock);
1559
1560 return err;
1561}
1562
1563static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1564 u16 fid, u16 vid, int port,
1565 dsa_fdb_dump_cb_t *cb, void *data)
1566{
1567 struct mv88e6xxx_atu_entry addr;
1568 bool is_static;
1569 int err;
1570
1571 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1572 eth_broadcast_addr(addr.mac);
1573
1574 do {
1575 mutex_lock(&chip->reg_lock);
1576 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1577 mutex_unlock(&chip->reg_lock);
1578 if (err)
1579 return err;
1580
1581 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1582 break;
1583
1584 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1585 continue;
1586
1587 if (!is_unicast_ether_addr(addr.mac))
1588 continue;
1589
1590 is_static = (addr.state ==
1591 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1592 err = cb(addr.mac, vid, is_static, data);
1593 if (err)
1594 return err;
1595 } while (!is_broadcast_ether_addr(addr.mac));
1596
1597 return err;
1598}
1599
1600static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1601 dsa_fdb_dump_cb_t *cb, void *data)
1602{
1603 struct mv88e6xxx_vtu_entry vlan = {
1604 .vid = chip->info->max_vid,
1605 };
1606 u16 fid;
1607 int err;
1608
1609 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1610 mutex_lock(&chip->reg_lock);
1611 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1612 mutex_unlock(&chip->reg_lock);
1613
1614 if (err)
1615 return err;
1616
1617 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1618 if (err)
1619 return err;
1620
1621 /* Dump VLANs' Filtering Information Databases */
1622 do {
1623 mutex_lock(&chip->reg_lock);
1624 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1625 mutex_unlock(&chip->reg_lock);
1626 if (err)
1627 return err;
1628
1629 if (!vlan.valid)
1630 break;
1631
1632 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1633 cb, data);
1634 if (err)
1635 return err;
1636 } while (vlan.vid < chip->info->max_vid);
1637
1638 return err;
1639}
1640
1641static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1642 dsa_fdb_dump_cb_t *cb, void *data)
1643{
1644 struct mv88e6xxx_chip *chip = ds->priv;
1645
1646 return mv88e6xxx_port_db_dump(chip, port, cb, data);
1647}
1648
1649static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1650 struct net_device *br)
1651{
1652 struct dsa_switch *ds;
1653 int port;
1654 int dev;
1655 int err;
1656
1657 /* Remap the Port VLAN of each local bridge group member */
1658 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1659 if (chip->ds->ports[port].bridge_dev == br) {
1660 err = mv88e6xxx_port_vlan_map(chip, port);
1661 if (err)
1662 return err;
1663 }
1664 }
1665
1666 if (!mv88e6xxx_has_pvt(chip))
1667 return 0;
1668
1669 /* Remap the Port VLAN of each cross-chip bridge group member */
1670 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1671 ds = chip->ds->dst->ds[dev];
1672 if (!ds)
1673 break;
1674
1675 for (port = 0; port < ds->num_ports; ++port) {
1676 if (ds->ports[port].bridge_dev == br) {
1677 err = mv88e6xxx_pvt_map(chip, dev, port);
1678 if (err)
1679 return err;
1680 }
1681 }
1682 }
1683
1684 return 0;
1685}
1686
1687static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1688 struct net_device *br)
1689{
1690 struct mv88e6xxx_chip *chip = ds->priv;
1691 int err;
1692
1693 mutex_lock(&chip->reg_lock);
1694 err = mv88e6xxx_bridge_map(chip, br);
1695 mutex_unlock(&chip->reg_lock);
1696
1697 return err;
1698}
1699
1700static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1701 struct net_device *br)
1702{
1703 struct mv88e6xxx_chip *chip = ds->priv;
1704
1705 mutex_lock(&chip->reg_lock);
1706 if (mv88e6xxx_bridge_map(chip, br) ||
1707 mv88e6xxx_port_vlan_map(chip, port))
1708 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1709 mutex_unlock(&chip->reg_lock);
1710}
1711
1712static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1713 int port, struct net_device *br)
1714{
1715 struct mv88e6xxx_chip *chip = ds->priv;
1716 int err;
1717
1718 if (!mv88e6xxx_has_pvt(chip))
1719 return 0;
1720
1721 mutex_lock(&chip->reg_lock);
1722 err = mv88e6xxx_pvt_map(chip, dev, port);
1723 mutex_unlock(&chip->reg_lock);
1724
1725 return err;
1726}
1727
1728static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1729 int port, struct net_device *br)
1730{
1731 struct mv88e6xxx_chip *chip = ds->priv;
1732
1733 if (!mv88e6xxx_has_pvt(chip))
1734 return;
1735
1736 mutex_lock(&chip->reg_lock);
1737 if (mv88e6xxx_pvt_map(chip, dev, port))
1738 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1739 mutex_unlock(&chip->reg_lock);
1740}
1741
1742static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1743{
1744 if (chip->info->ops->reset)
1745 return chip->info->ops->reset(chip);
1746
1747 return 0;
1748}
1749
1750static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1751{
1752 struct gpio_desc *gpiod = chip->reset;
1753
1754 /* If there is a GPIO connected to the reset pin, toggle it */
1755 if (gpiod) {
1756 gpiod_set_value_cansleep(gpiod, 1);
1757 usleep_range(10000, 20000);
1758 gpiod_set_value_cansleep(gpiod, 0);
1759 usleep_range(10000, 20000);
1760 }
1761}
1762
1763static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1764{
1765 int i, err;
1766
1767 /* Set all ports to the Disabled state */
1768 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1769 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1770 if (err)
1771 return err;
1772 }
1773
1774 /* Wait for transmit queues to drain,
1775 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1776 */
1777 usleep_range(2000, 4000);
1778
1779 return 0;
1780}
1781
1782static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1783{
1784 int err;
1785
1786 err = mv88e6xxx_disable_ports(chip);
1787 if (err)
1788 return err;
1789
1790 mv88e6xxx_hardware_reset(chip);
1791
1792 return mv88e6xxx_software_reset(chip);
1793}
1794
1795static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1796 enum mv88e6xxx_frame_mode frame,
1797 enum mv88e6xxx_egress_mode egress, u16 etype)
1798{
1799 int err;
1800
1801 if (!chip->info->ops->port_set_frame_mode)
1802 return -EOPNOTSUPP;
1803
1804 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1805 if (err)
1806 return err;
1807
1808 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1809 if (err)
1810 return err;
1811
1812 if (chip->info->ops->port_set_ether_type)
1813 return chip->info->ops->port_set_ether_type(chip, port, etype);
1814
1815 return 0;
1816}
1817
1818static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1819{
1820 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1821 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1822 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1823}
1824
1825static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1826{
1827 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1828 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1829 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1830}
1831
1832static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1833{
1834 return mv88e6xxx_set_port_mode(chip, port,
1835 MV88E6XXX_FRAME_MODE_ETHERTYPE,
1836 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1837 ETH_P_EDSA);
1838}
1839
1840static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1841{
1842 if (dsa_is_dsa_port(chip->ds, port))
1843 return mv88e6xxx_set_port_mode_dsa(chip, port);
1844
1845 if (dsa_is_user_port(chip->ds, port))
1846 return mv88e6xxx_set_port_mode_normal(chip, port);
1847
1848 /* Setup CPU port mode depending on its supported tag format */
1849 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1850 return mv88e6xxx_set_port_mode_dsa(chip, port);
1851
1852 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1853 return mv88e6xxx_set_port_mode_edsa(chip, port);
1854
1855 return -EINVAL;
1856}
1857
1858static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1859{
1860 bool message = dsa_is_dsa_port(chip->ds, port);
1861
1862 return mv88e6xxx_port_set_message_port(chip, port, message);
1863}
1864
1865static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1866{
1867 struct dsa_switch *ds = chip->ds;
1868 bool flood;
1869
1870 /* Upstream ports flood frames with unknown unicast or multicast DA */
1871 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
1872 if (chip->info->ops->port_set_egress_floods)
1873 return chip->info->ops->port_set_egress_floods(chip, port,
1874 flood, flood);
1875
1876 return 0;
1877}
1878
1879static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1880 bool on)
1881{
1882 if (chip->info->ops->serdes_power)
1883 return chip->info->ops->serdes_power(chip, port, on);
1884
1885 return 0;
1886}
1887
1888static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
1889{
1890 struct dsa_switch *ds = chip->ds;
1891 int upstream_port;
1892 int err;
1893
1894 upstream_port = dsa_upstream_port(ds, port);
1895 if (chip->info->ops->port_set_upstream_port) {
1896 err = chip->info->ops->port_set_upstream_port(chip, port,
1897 upstream_port);
1898 if (err)
1899 return err;
1900 }
1901
1902 if (port == upstream_port) {
1903 if (chip->info->ops->set_cpu_port) {
1904 err = chip->info->ops->set_cpu_port(chip,
1905 upstream_port);
1906 if (err)
1907 return err;
1908 }
1909
1910 if (chip->info->ops->set_egress_port) {
1911 err = chip->info->ops->set_egress_port(chip,
1912 upstream_port);
1913 if (err)
1914 return err;
1915 }
1916 }
1917
1918 return 0;
1919}
1920
1921static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1922{
1923 struct dsa_switch *ds = chip->ds;
1924 int err;
1925 u16 reg;
1926
1927 /* MAC Forcing register: don't force link, speed, duplex or flow control
1928 * state to any particular values on physical ports, but force the CPU
1929 * port and all DSA ports to their maximum bandwidth and full duplex.
1930 */
1931 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1932 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1933 SPEED_MAX, DUPLEX_FULL,
1934 PHY_INTERFACE_MODE_NA);
1935 else
1936 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1937 SPEED_UNFORCED, DUPLEX_UNFORCED,
1938 PHY_INTERFACE_MODE_NA);
1939 if (err)
1940 return err;
1941
1942 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1943 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1944 * tunneling, determine priority by looking at 802.1p and IP
1945 * priority fields (IP prio has precedence), and set STP state
1946 * to Forwarding.
1947 *
1948 * If this is the CPU link, use DSA or EDSA tagging depending
1949 * on which tagging mode was configured.
1950 *
1951 * If this is a link to another switch, use DSA tagging mode.
1952 *
1953 * If this is the upstream port for this switch, enable
1954 * forwarding of unknown unicasts and multicasts.
1955 */
1956 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1957 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1958 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1959 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1960 if (err)
1961 return err;
1962
1963 err = mv88e6xxx_setup_port_mode(chip, port);
1964 if (err)
1965 return err;
1966
1967 err = mv88e6xxx_setup_egress_floods(chip, port);
1968 if (err)
1969 return err;
1970
1971 /* Enable the SERDES interface for DSA and CPU ports. Normal
1972 * ports SERDES are enabled when the port is enabled, thus
1973 * saving a bit of power.
1974 */
1975 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1976 err = mv88e6xxx_serdes_power(chip, port, true);
1977 if (err)
1978 return err;
1979 }
1980
1981 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1982 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1983 * untagged frames on this port, do a destination address lookup on all
1984 * received packets as usual, disable ARP mirroring and don't send a
1985 * copy of all transmitted/received frames on this port to the CPU.
1986 */
1987 err = mv88e6xxx_port_set_map_da(chip, port);
1988 if (err)
1989 return err;
1990
1991 err = mv88e6xxx_setup_upstream_port(chip, port);
1992 if (err)
1993 return err;
1994
1995 err = mv88e6xxx_port_set_8021q_mode(chip, port,
1996 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1997 if (err)
1998 return err;
1999
2000 if (chip->info->ops->port_set_jumbo_size) {
2001 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2002 if (err)
2003 return err;
2004 }
2005
2006 /* Port Association Vector: when learning source addresses
2007 * of packets, add the address to the address database using
2008 * a port bitmap that has only the bit for this port set and
2009 * the other bits clear.
2010 */
2011 reg = 1 << port;
2012 /* Disable learning for CPU port */
2013 if (dsa_is_cpu_port(ds, port))
2014 reg = 0;
2015
2016 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2017 reg);
2018 if (err)
2019 return err;
2020
2021 /* Egress rate control 2: disable egress rate control. */
2022 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2023 0x0000);
2024 if (err)
2025 return err;
2026
2027 if (chip->info->ops->port_pause_limit) {
2028 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2029 if (err)
2030 return err;
2031 }
2032
2033 if (chip->info->ops->port_disable_learn_limit) {
2034 err = chip->info->ops->port_disable_learn_limit(chip, port);
2035 if (err)
2036 return err;
2037 }
2038
2039 if (chip->info->ops->port_disable_pri_override) {
2040 err = chip->info->ops->port_disable_pri_override(chip, port);
2041 if (err)
2042 return err;
2043 }
2044
2045 if (chip->info->ops->port_tag_remap) {
2046 err = chip->info->ops->port_tag_remap(chip, port);
2047 if (err)
2048 return err;
2049 }
2050
2051 if (chip->info->ops->port_egress_rate_limiting) {
2052 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2053 if (err)
2054 return err;
2055 }
2056
2057 err = mv88e6xxx_setup_message_port(chip, port);
2058 if (err)
2059 return err;
2060
2061 /* Port based VLAN map: give each port the same default address
2062 * database, and allow bidirectional communication between the
2063 * CPU and DSA port(s), and the other ports.
2064 */
2065 err = mv88e6xxx_port_set_fid(chip, port, 0);
2066 if (err)
2067 return err;
2068
2069 err = mv88e6xxx_port_vlan_map(chip, port);
2070 if (err)
2071 return err;
2072
2073 /* Default VLAN ID and priority: don't set a default VLAN
2074 * ID, and set the default packet priority to zero.
2075 */
2076 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2077}
2078
2079static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2080 struct phy_device *phydev)
2081{
2082 struct mv88e6xxx_chip *chip = ds->priv;
2083 int err;
2084
2085 mutex_lock(&chip->reg_lock);
2086 err = mv88e6xxx_serdes_power(chip, port, true);
2087 mutex_unlock(&chip->reg_lock);
2088
2089 return err;
2090}
2091
2092static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2093 struct phy_device *phydev)
2094{
2095 struct mv88e6xxx_chip *chip = ds->priv;
2096
2097 mutex_lock(&chip->reg_lock);
2098 if (mv88e6xxx_serdes_power(chip, port, false))
2099 dev_err(chip->dev, "failed to power off SERDES\n");
2100 mutex_unlock(&chip->reg_lock);
2101}
2102
2103static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2104 unsigned int ageing_time)
2105{
2106 struct mv88e6xxx_chip *chip = ds->priv;
2107 int err;
2108
2109 mutex_lock(&chip->reg_lock);
2110 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2111 mutex_unlock(&chip->reg_lock);
2112
2113 return err;
2114}
2115
2116static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2117{
2118 struct dsa_switch *ds = chip->ds;
2119 int err;
2120
2121 /* Disable remote management, and set the switch's DSA device number. */
2122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
2123 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
2124 (ds->index & 0x1f));
2125 if (err)
2126 return err;
2127
2128 /* Configure the IP ToS mapping registers. */
2129 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
2130 if (err)
2131 return err;
2132 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
2133 if (err)
2134 return err;
2135 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
2136 if (err)
2137 return err;
2138 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
2139 if (err)
2140 return err;
2141 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2142 if (err)
2143 return err;
2144 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2145 if (err)
2146 return err;
2147 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2148 if (err)
2149 return err;
2150 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2151 if (err)
2152 return err;
2153
2154 /* Configure the IEEE 802.1p priority mapping register. */
2155 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2156 if (err)
2157 return err;
2158
2159 /* Initialize the statistics unit */
2160 err = mv88e6xxx_stats_set_histogram(chip);
2161 if (err)
2162 return err;
2163
2164 return mv88e6xxx_g1_stats_clear(chip);
2165}
2166
2167static int mv88e6xxx_setup(struct dsa_switch *ds)
2168{
2169 struct mv88e6xxx_chip *chip = ds->priv;
2170 int err;
2171 int i;
2172
2173 chip->ds = ds;
2174 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2175
2176 mutex_lock(&chip->reg_lock);
2177
2178 /* Setup Switch Port Registers */
2179 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2180 if (dsa_is_unused_port(ds, i))
2181 continue;
2182
2183 err = mv88e6xxx_setup_port(chip, i);
2184 if (err)
2185 goto unlock;
2186 }
2187
2188 /* Setup Switch Global 1 Registers */
2189 err = mv88e6xxx_g1_setup(chip);
2190 if (err)
2191 goto unlock;
2192
2193 /* Setup Switch Global 2 Registers */
2194 if (chip->info->global2_addr) {
2195 err = mv88e6xxx_g2_setup(chip);
2196 if (err)
2197 goto unlock;
2198 }
2199
2200 err = mv88e6xxx_irl_setup(chip);
2201 if (err)
2202 goto unlock;
2203
2204 err = mv88e6xxx_mac_setup(chip);
2205 if (err)
2206 goto unlock;
2207
2208 err = mv88e6xxx_phy_setup(chip);
2209 if (err)
2210 goto unlock;
2211
2212 err = mv88e6xxx_vtu_setup(chip);
2213 if (err)
2214 goto unlock;
2215
2216 err = mv88e6xxx_pvt_setup(chip);
2217 if (err)
2218 goto unlock;
2219
2220 err = mv88e6xxx_atu_setup(chip);
2221 if (err)
2222 goto unlock;
2223
2224 err = mv88e6xxx_broadcast_setup(chip, 0);
2225 if (err)
2226 goto unlock;
2227
2228 err = mv88e6xxx_pot_setup(chip);
2229 if (err)
2230 goto unlock;
2231
2232 err = mv88e6xxx_rsvd2cpu_setup(chip);
2233 if (err)
2234 goto unlock;
2235
2236 /* Setup PTP Hardware Clock and timestamping */
2237 if (chip->info->ptp_support) {
2238 err = mv88e6xxx_ptp_setup(chip);
2239 if (err)
2240 goto unlock;
2241
2242 err = mv88e6xxx_hwtstamp_setup(chip);
2243 if (err)
2244 goto unlock;
2245 }
2246
2247unlock:
2248 mutex_unlock(&chip->reg_lock);
2249
2250 return err;
2251}
2252
2253static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2254{
2255 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2256 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2257 u16 val;
2258 int err;
2259
2260 if (!chip->info->ops->phy_read)
2261 return -EOPNOTSUPP;
2262
2263 mutex_lock(&chip->reg_lock);
2264 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2265 mutex_unlock(&chip->reg_lock);
2266
2267 if (reg == MII_PHYSID2) {
2268 /* Some internal PHYS don't have a model number. Use
2269 * the mv88e6390 family model number instead.
2270 */
2271 if (!(val & 0x3f0))
2272 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2273 }
2274
2275 return err ? err : val;
2276}
2277
2278static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2279{
2280 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2281 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2282 int err;
2283
2284 if (!chip->info->ops->phy_write)
2285 return -EOPNOTSUPP;
2286
2287 mutex_lock(&chip->reg_lock);
2288 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2289 mutex_unlock(&chip->reg_lock);
2290
2291 return err;
2292}
2293
2294static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2295 struct device_node *np,
2296 bool external)
2297{
2298 static int index;
2299 struct mv88e6xxx_mdio_bus *mdio_bus;
2300 struct mii_bus *bus;
2301 int err;
2302
2303 if (external) {
2304 mutex_lock(&chip->reg_lock);
2305 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2306 mutex_unlock(&chip->reg_lock);
2307
2308 if (err)
2309 return err;
2310 }
2311
2312 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2313 if (!bus)
2314 return -ENOMEM;
2315
2316 mdio_bus = bus->priv;
2317 mdio_bus->bus = bus;
2318 mdio_bus->chip = chip;
2319 INIT_LIST_HEAD(&mdio_bus->list);
2320 mdio_bus->external = external;
2321
2322 if (np) {
2323 bus->name = np->full_name;
2324 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2325 } else {
2326 bus->name = "mv88e6xxx SMI";
2327 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2328 }
2329
2330 bus->read = mv88e6xxx_mdio_read;
2331 bus->write = mv88e6xxx_mdio_write;
2332 bus->parent = chip->dev;
2333
2334 if (!external) {
2335 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2336 if (err)
2337 return err;
2338 }
2339
2340 if (np)
2341 err = of_mdiobus_register(bus, np);
2342 else
2343 err = mdiobus_register(bus);
2344 if (err) {
2345 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2346 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2347 return err;
2348 }
2349
2350 if (external)
2351 list_add_tail(&mdio_bus->list, &chip->mdios);
2352 else
2353 list_add(&mdio_bus->list, &chip->mdios);
2354
2355 return 0;
2356}
2357
2358static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2359 { .compatible = "marvell,mv88e6xxx-mdio-external",
2360 .data = (void *)true },
2361 { },
2362};
2363
2364static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2365
2366{
2367 struct mv88e6xxx_mdio_bus *mdio_bus;
2368 struct mii_bus *bus;
2369
2370 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2371 bus = mdio_bus->bus;
2372
2373 if (!mdio_bus->external)
2374 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2375
2376 mdiobus_unregister(bus);
2377 }
2378}
2379
2380static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2381 struct device_node *np)
2382{
2383 const struct of_device_id *match;
2384 struct device_node *child;
2385 int err;
2386
2387 /* Always register one mdio bus for the internal/default mdio
2388 * bus. This maybe represented in the device tree, but is
2389 * optional.
2390 */
2391 child = of_get_child_by_name(np, "mdio");
2392 err = mv88e6xxx_mdio_register(chip, child, false);
2393 if (err)
2394 return err;
2395
2396 /* Walk the device tree, and see if there are any other nodes
2397 * which say they are compatible with the external mdio
2398 * bus.
2399 */
2400 for_each_available_child_of_node(np, child) {
2401 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2402 if (match) {
2403 err = mv88e6xxx_mdio_register(chip, child, true);
2404 if (err) {
2405 mv88e6xxx_mdios_unregister(chip);
2406 return err;
2407 }
2408 }
2409 }
2410
2411 return 0;
2412}
2413
2414static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2415{
2416 struct mv88e6xxx_chip *chip = ds->priv;
2417
2418 return chip->eeprom_len;
2419}
2420
2421static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2422 struct ethtool_eeprom *eeprom, u8 *data)
2423{
2424 struct mv88e6xxx_chip *chip = ds->priv;
2425 int err;
2426
2427 if (!chip->info->ops->get_eeprom)
2428 return -EOPNOTSUPP;
2429
2430 mutex_lock(&chip->reg_lock);
2431 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2432 mutex_unlock(&chip->reg_lock);
2433
2434 if (err)
2435 return err;
2436
2437 eeprom->magic = 0xc3ec4951;
2438
2439 return 0;
2440}
2441
2442static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2443 struct ethtool_eeprom *eeprom, u8 *data)
2444{
2445 struct mv88e6xxx_chip *chip = ds->priv;
2446 int err;
2447
2448 if (!chip->info->ops->set_eeprom)
2449 return -EOPNOTSUPP;
2450
2451 if (eeprom->magic != 0xc3ec4951)
2452 return -EINVAL;
2453
2454 mutex_lock(&chip->reg_lock);
2455 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2456 mutex_unlock(&chip->reg_lock);
2457
2458 return err;
2459}
2460
2461static const struct mv88e6xxx_ops mv88e6085_ops = {
2462 /* MV88E6XXX_FAMILY_6097 */
2463 .irl_init_all = mv88e6352_g2_irl_init_all,
2464 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2465 .phy_read = mv88e6185_phy_ppu_read,
2466 .phy_write = mv88e6185_phy_ppu_write,
2467 .port_set_link = mv88e6xxx_port_set_link,
2468 .port_set_duplex = mv88e6xxx_port_set_duplex,
2469 .port_set_speed = mv88e6185_port_set_speed,
2470 .port_tag_remap = mv88e6095_port_tag_remap,
2471 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2472 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2473 .port_set_ether_type = mv88e6351_port_set_ether_type,
2474 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2475 .port_pause_limit = mv88e6097_port_pause_limit,
2476 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2477 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2478 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2479 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2480 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2481 .stats_get_strings = mv88e6095_stats_get_strings,
2482 .stats_get_stats = mv88e6095_stats_get_stats,
2483 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2484 .set_egress_port = mv88e6095_g1_set_egress_port,
2485 .watchdog_ops = &mv88e6097_watchdog_ops,
2486 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2487 .pot_clear = mv88e6xxx_g2_pot_clear,
2488 .ppu_enable = mv88e6185_g1_ppu_enable,
2489 .ppu_disable = mv88e6185_g1_ppu_disable,
2490 .reset = mv88e6185_g1_reset,
2491 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2492 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2493};
2494
2495static const struct mv88e6xxx_ops mv88e6095_ops = {
2496 /* MV88E6XXX_FAMILY_6095 */
2497 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2498 .phy_read = mv88e6185_phy_ppu_read,
2499 .phy_write = mv88e6185_phy_ppu_write,
2500 .port_set_link = mv88e6xxx_port_set_link,
2501 .port_set_duplex = mv88e6xxx_port_set_duplex,
2502 .port_set_speed = mv88e6185_port_set_speed,
2503 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2504 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2505 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2506 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2507 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2508 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2509 .stats_get_strings = mv88e6095_stats_get_strings,
2510 .stats_get_stats = mv88e6095_stats_get_stats,
2511 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2512 .ppu_enable = mv88e6185_g1_ppu_enable,
2513 .ppu_disable = mv88e6185_g1_ppu_disable,
2514 .reset = mv88e6185_g1_reset,
2515 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2516 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2517};
2518
2519static const struct mv88e6xxx_ops mv88e6097_ops = {
2520 /* MV88E6XXX_FAMILY_6097 */
2521 .irl_init_all = mv88e6352_g2_irl_init_all,
2522 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2523 .phy_read = mv88e6xxx_g2_smi_phy_read,
2524 .phy_write = mv88e6xxx_g2_smi_phy_write,
2525 .port_set_link = mv88e6xxx_port_set_link,
2526 .port_set_duplex = mv88e6xxx_port_set_duplex,
2527 .port_set_speed = mv88e6185_port_set_speed,
2528 .port_tag_remap = mv88e6095_port_tag_remap,
2529 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2530 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2531 .port_set_ether_type = mv88e6351_port_set_ether_type,
2532 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2533 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2534 .port_pause_limit = mv88e6097_port_pause_limit,
2535 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2536 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2537 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2538 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2539 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2540 .stats_get_strings = mv88e6095_stats_get_strings,
2541 .stats_get_stats = mv88e6095_stats_get_stats,
2542 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2543 .set_egress_port = mv88e6095_g1_set_egress_port,
2544 .watchdog_ops = &mv88e6097_watchdog_ops,
2545 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2546 .pot_clear = mv88e6xxx_g2_pot_clear,
2547 .reset = mv88e6352_g1_reset,
2548 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2549 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2550};
2551
2552static const struct mv88e6xxx_ops mv88e6123_ops = {
2553 /* MV88E6XXX_FAMILY_6165 */
2554 .irl_init_all = mv88e6352_g2_irl_init_all,
2555 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2556 .phy_read = mv88e6xxx_g2_smi_phy_read,
2557 .phy_write = mv88e6xxx_g2_smi_phy_write,
2558 .port_set_link = mv88e6xxx_port_set_link,
2559 .port_set_duplex = mv88e6xxx_port_set_duplex,
2560 .port_set_speed = mv88e6185_port_set_speed,
2561 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2562 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2563 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2564 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2565 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2566 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2567 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2568 .stats_get_strings = mv88e6095_stats_get_strings,
2569 .stats_get_stats = mv88e6095_stats_get_stats,
2570 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2571 .set_egress_port = mv88e6095_g1_set_egress_port,
2572 .watchdog_ops = &mv88e6097_watchdog_ops,
2573 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2574 .pot_clear = mv88e6xxx_g2_pot_clear,
2575 .reset = mv88e6352_g1_reset,
2576 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2577 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2578};
2579
2580static const struct mv88e6xxx_ops mv88e6131_ops = {
2581 /* MV88E6XXX_FAMILY_6185 */
2582 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2583 .phy_read = mv88e6185_phy_ppu_read,
2584 .phy_write = mv88e6185_phy_ppu_write,
2585 .port_set_link = mv88e6xxx_port_set_link,
2586 .port_set_duplex = mv88e6xxx_port_set_duplex,
2587 .port_set_speed = mv88e6185_port_set_speed,
2588 .port_tag_remap = mv88e6095_port_tag_remap,
2589 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2590 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2591 .port_set_ether_type = mv88e6351_port_set_ether_type,
2592 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2593 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2594 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2595 .port_pause_limit = mv88e6097_port_pause_limit,
2596 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2597 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2598 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2599 .stats_get_strings = mv88e6095_stats_get_strings,
2600 .stats_get_stats = mv88e6095_stats_get_stats,
2601 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2602 .set_egress_port = mv88e6095_g1_set_egress_port,
2603 .watchdog_ops = &mv88e6097_watchdog_ops,
2604 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2605 .ppu_enable = mv88e6185_g1_ppu_enable,
2606 .ppu_disable = mv88e6185_g1_ppu_disable,
2607 .reset = mv88e6185_g1_reset,
2608 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2609 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2610};
2611
2612static const struct mv88e6xxx_ops mv88e6141_ops = {
2613 /* MV88E6XXX_FAMILY_6341 */
2614 .irl_init_all = mv88e6352_g2_irl_init_all,
2615 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2616 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2617 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2618 .phy_read = mv88e6xxx_g2_smi_phy_read,
2619 .phy_write = mv88e6xxx_g2_smi_phy_write,
2620 .port_set_link = mv88e6xxx_port_set_link,
2621 .port_set_duplex = mv88e6xxx_port_set_duplex,
2622 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2623 .port_set_speed = mv88e6390_port_set_speed,
2624 .port_tag_remap = mv88e6095_port_tag_remap,
2625 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2626 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2627 .port_set_ether_type = mv88e6351_port_set_ether_type,
2628 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2629 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2630 .port_pause_limit = mv88e6097_port_pause_limit,
2631 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2632 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2633 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2634 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2635 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2636 .stats_get_strings = mv88e6320_stats_get_strings,
2637 .stats_get_stats = mv88e6390_stats_get_stats,
2638 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2639 .set_egress_port = mv88e6390_g1_set_egress_port,
2640 .watchdog_ops = &mv88e6390_watchdog_ops,
2641 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2642 .pot_clear = mv88e6xxx_g2_pot_clear,
2643 .reset = mv88e6352_g1_reset,
2644 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2645 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2646 .gpio_ops = &mv88e6352_gpio_ops,
2647};
2648
2649static const struct mv88e6xxx_ops mv88e6161_ops = {
2650 /* MV88E6XXX_FAMILY_6165 */
2651 .irl_init_all = mv88e6352_g2_irl_init_all,
2652 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2653 .phy_read = mv88e6xxx_g2_smi_phy_read,
2654 .phy_write = mv88e6xxx_g2_smi_phy_write,
2655 .port_set_link = mv88e6xxx_port_set_link,
2656 .port_set_duplex = mv88e6xxx_port_set_duplex,
2657 .port_set_speed = mv88e6185_port_set_speed,
2658 .port_tag_remap = mv88e6095_port_tag_remap,
2659 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2660 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2661 .port_set_ether_type = mv88e6351_port_set_ether_type,
2662 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2663 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2664 .port_pause_limit = mv88e6097_port_pause_limit,
2665 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2666 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2667 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2668 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2669 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2670 .stats_get_strings = mv88e6095_stats_get_strings,
2671 .stats_get_stats = mv88e6095_stats_get_stats,
2672 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2673 .set_egress_port = mv88e6095_g1_set_egress_port,
2674 .watchdog_ops = &mv88e6097_watchdog_ops,
2675 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2676 .pot_clear = mv88e6xxx_g2_pot_clear,
2677 .reset = mv88e6352_g1_reset,
2678 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2679 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2680};
2681
2682static const struct mv88e6xxx_ops mv88e6165_ops = {
2683 /* MV88E6XXX_FAMILY_6165 */
2684 .irl_init_all = mv88e6352_g2_irl_init_all,
2685 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2686 .phy_read = mv88e6165_phy_read,
2687 .phy_write = mv88e6165_phy_write,
2688 .port_set_link = mv88e6xxx_port_set_link,
2689 .port_set_duplex = mv88e6xxx_port_set_duplex,
2690 .port_set_speed = mv88e6185_port_set_speed,
2691 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2692 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2693 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2694 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2695 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2696 .stats_get_strings = mv88e6095_stats_get_strings,
2697 .stats_get_stats = mv88e6095_stats_get_stats,
2698 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2699 .set_egress_port = mv88e6095_g1_set_egress_port,
2700 .watchdog_ops = &mv88e6097_watchdog_ops,
2701 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2702 .pot_clear = mv88e6xxx_g2_pot_clear,
2703 .reset = mv88e6352_g1_reset,
2704 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2705 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2706};
2707
2708static const struct mv88e6xxx_ops mv88e6171_ops = {
2709 /* MV88E6XXX_FAMILY_6351 */
2710 .irl_init_all = mv88e6352_g2_irl_init_all,
2711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2712 .phy_read = mv88e6xxx_g2_smi_phy_read,
2713 .phy_write = mv88e6xxx_g2_smi_phy_write,
2714 .port_set_link = mv88e6xxx_port_set_link,
2715 .port_set_duplex = mv88e6xxx_port_set_duplex,
2716 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2717 .port_set_speed = mv88e6185_port_set_speed,
2718 .port_tag_remap = mv88e6095_port_tag_remap,
2719 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2720 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2721 .port_set_ether_type = mv88e6351_port_set_ether_type,
2722 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2723 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2724 .port_pause_limit = mv88e6097_port_pause_limit,
2725 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2726 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2727 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2728 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2729 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2730 .stats_get_strings = mv88e6095_stats_get_strings,
2731 .stats_get_stats = mv88e6095_stats_get_stats,
2732 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2733 .set_egress_port = mv88e6095_g1_set_egress_port,
2734 .watchdog_ops = &mv88e6097_watchdog_ops,
2735 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2736 .pot_clear = mv88e6xxx_g2_pot_clear,
2737 .reset = mv88e6352_g1_reset,
2738 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2739 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2740};
2741
2742static const struct mv88e6xxx_ops mv88e6172_ops = {
2743 /* MV88E6XXX_FAMILY_6352 */
2744 .irl_init_all = mv88e6352_g2_irl_init_all,
2745 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2746 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2747 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2748 .phy_read = mv88e6xxx_g2_smi_phy_read,
2749 .phy_write = mv88e6xxx_g2_smi_phy_write,
2750 .port_set_link = mv88e6xxx_port_set_link,
2751 .port_set_duplex = mv88e6xxx_port_set_duplex,
2752 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2753 .port_set_speed = mv88e6352_port_set_speed,
2754 .port_tag_remap = mv88e6095_port_tag_remap,
2755 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2756 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2757 .port_set_ether_type = mv88e6351_port_set_ether_type,
2758 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2759 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2760 .port_pause_limit = mv88e6097_port_pause_limit,
2761 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2762 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2763 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2764 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2765 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2766 .stats_get_strings = mv88e6095_stats_get_strings,
2767 .stats_get_stats = mv88e6095_stats_get_stats,
2768 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2769 .set_egress_port = mv88e6095_g1_set_egress_port,
2770 .watchdog_ops = &mv88e6097_watchdog_ops,
2771 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2772 .pot_clear = mv88e6xxx_g2_pot_clear,
2773 .reset = mv88e6352_g1_reset,
2774 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2775 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2776 .serdes_power = mv88e6352_serdes_power,
2777 .gpio_ops = &mv88e6352_gpio_ops,
2778};
2779
2780static const struct mv88e6xxx_ops mv88e6175_ops = {
2781 /* MV88E6XXX_FAMILY_6351 */
2782 .irl_init_all = mv88e6352_g2_irl_init_all,
2783 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2784 .phy_read = mv88e6xxx_g2_smi_phy_read,
2785 .phy_write = mv88e6xxx_g2_smi_phy_write,
2786 .port_set_link = mv88e6xxx_port_set_link,
2787 .port_set_duplex = mv88e6xxx_port_set_duplex,
2788 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2789 .port_set_speed = mv88e6185_port_set_speed,
2790 .port_tag_remap = mv88e6095_port_tag_remap,
2791 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2792 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2793 .port_set_ether_type = mv88e6351_port_set_ether_type,
2794 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2795 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2796 .port_pause_limit = mv88e6097_port_pause_limit,
2797 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2798 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2799 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2800 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2801 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2802 .stats_get_strings = mv88e6095_stats_get_strings,
2803 .stats_get_stats = mv88e6095_stats_get_stats,
2804 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2805 .set_egress_port = mv88e6095_g1_set_egress_port,
2806 .watchdog_ops = &mv88e6097_watchdog_ops,
2807 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2808 .pot_clear = mv88e6xxx_g2_pot_clear,
2809 .reset = mv88e6352_g1_reset,
2810 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2811 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2812};
2813
2814static const struct mv88e6xxx_ops mv88e6176_ops = {
2815 /* MV88E6XXX_FAMILY_6352 */
2816 .irl_init_all = mv88e6352_g2_irl_init_all,
2817 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2818 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2819 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2820 .phy_read = mv88e6xxx_g2_smi_phy_read,
2821 .phy_write = mv88e6xxx_g2_smi_phy_write,
2822 .port_set_link = mv88e6xxx_port_set_link,
2823 .port_set_duplex = mv88e6xxx_port_set_duplex,
2824 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2825 .port_set_speed = mv88e6352_port_set_speed,
2826 .port_tag_remap = mv88e6095_port_tag_remap,
2827 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2828 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2829 .port_set_ether_type = mv88e6351_port_set_ether_type,
2830 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2831 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2832 .port_pause_limit = mv88e6097_port_pause_limit,
2833 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2834 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2835 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2836 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2837 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2838 .stats_get_strings = mv88e6095_stats_get_strings,
2839 .stats_get_stats = mv88e6095_stats_get_stats,
2840 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2841 .set_egress_port = mv88e6095_g1_set_egress_port,
2842 .watchdog_ops = &mv88e6097_watchdog_ops,
2843 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2844 .pot_clear = mv88e6xxx_g2_pot_clear,
2845 .reset = mv88e6352_g1_reset,
2846 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2847 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2848 .serdes_power = mv88e6352_serdes_power,
2849 .gpio_ops = &mv88e6352_gpio_ops,
2850};
2851
2852static const struct mv88e6xxx_ops mv88e6185_ops = {
2853 /* MV88E6XXX_FAMILY_6185 */
2854 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2855 .phy_read = mv88e6185_phy_ppu_read,
2856 .phy_write = mv88e6185_phy_ppu_write,
2857 .port_set_link = mv88e6xxx_port_set_link,
2858 .port_set_duplex = mv88e6xxx_port_set_duplex,
2859 .port_set_speed = mv88e6185_port_set_speed,
2860 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2861 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2862 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2863 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2864 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2865 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2866 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2867 .stats_get_strings = mv88e6095_stats_get_strings,
2868 .stats_get_stats = mv88e6095_stats_get_stats,
2869 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2870 .set_egress_port = mv88e6095_g1_set_egress_port,
2871 .watchdog_ops = &mv88e6097_watchdog_ops,
2872 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2873 .ppu_enable = mv88e6185_g1_ppu_enable,
2874 .ppu_disable = mv88e6185_g1_ppu_disable,
2875 .reset = mv88e6185_g1_reset,
2876 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2877 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2878};
2879
2880static const struct mv88e6xxx_ops mv88e6190_ops = {
2881 /* MV88E6XXX_FAMILY_6390 */
2882 .irl_init_all = mv88e6390_g2_irl_init_all,
2883 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2884 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2885 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2886 .phy_read = mv88e6xxx_g2_smi_phy_read,
2887 .phy_write = mv88e6xxx_g2_smi_phy_write,
2888 .port_set_link = mv88e6xxx_port_set_link,
2889 .port_set_duplex = mv88e6xxx_port_set_duplex,
2890 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2891 .port_set_speed = mv88e6390_port_set_speed,
2892 .port_tag_remap = mv88e6390_port_tag_remap,
2893 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2894 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2895 .port_set_ether_type = mv88e6351_port_set_ether_type,
2896 .port_pause_limit = mv88e6390_port_pause_limit,
2897 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2898 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2899 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2900 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2901 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2902 .stats_get_strings = mv88e6320_stats_get_strings,
2903 .stats_get_stats = mv88e6390_stats_get_stats,
2904 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2905 .set_egress_port = mv88e6390_g1_set_egress_port,
2906 .watchdog_ops = &mv88e6390_watchdog_ops,
2907 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2908 .pot_clear = mv88e6xxx_g2_pot_clear,
2909 .reset = mv88e6352_g1_reset,
2910 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2911 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2912 .serdes_power = mv88e6390_serdes_power,
2913 .gpio_ops = &mv88e6352_gpio_ops,
2914};
2915
2916static const struct mv88e6xxx_ops mv88e6190x_ops = {
2917 /* MV88E6XXX_FAMILY_6390 */
2918 .irl_init_all = mv88e6390_g2_irl_init_all,
2919 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2920 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2921 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2922 .phy_read = mv88e6xxx_g2_smi_phy_read,
2923 .phy_write = mv88e6xxx_g2_smi_phy_write,
2924 .port_set_link = mv88e6xxx_port_set_link,
2925 .port_set_duplex = mv88e6xxx_port_set_duplex,
2926 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2927 .port_set_speed = mv88e6390x_port_set_speed,
2928 .port_tag_remap = mv88e6390_port_tag_remap,
2929 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2930 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2931 .port_set_ether_type = mv88e6351_port_set_ether_type,
2932 .port_pause_limit = mv88e6390_port_pause_limit,
2933 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2934 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2935 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2936 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2937 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2938 .stats_get_strings = mv88e6320_stats_get_strings,
2939 .stats_get_stats = mv88e6390_stats_get_stats,
2940 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2941 .set_egress_port = mv88e6390_g1_set_egress_port,
2942 .watchdog_ops = &mv88e6390_watchdog_ops,
2943 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2944 .pot_clear = mv88e6xxx_g2_pot_clear,
2945 .reset = mv88e6352_g1_reset,
2946 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2947 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2948 .serdes_power = mv88e6390_serdes_power,
2949 .gpio_ops = &mv88e6352_gpio_ops,
2950};
2951
2952static const struct mv88e6xxx_ops mv88e6191_ops = {
2953 /* MV88E6XXX_FAMILY_6390 */
2954 .irl_init_all = mv88e6390_g2_irl_init_all,
2955 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2956 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2957 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2958 .phy_read = mv88e6xxx_g2_smi_phy_read,
2959 .phy_write = mv88e6xxx_g2_smi_phy_write,
2960 .port_set_link = mv88e6xxx_port_set_link,
2961 .port_set_duplex = mv88e6xxx_port_set_duplex,
2962 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2963 .port_set_speed = mv88e6390_port_set_speed,
2964 .port_tag_remap = mv88e6390_port_tag_remap,
2965 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2966 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2967 .port_set_ether_type = mv88e6351_port_set_ether_type,
2968 .port_pause_limit = mv88e6390_port_pause_limit,
2969 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2970 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2971 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2972 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2973 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2974 .stats_get_strings = mv88e6320_stats_get_strings,
2975 .stats_get_stats = mv88e6390_stats_get_stats,
2976 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2977 .set_egress_port = mv88e6390_g1_set_egress_port,
2978 .watchdog_ops = &mv88e6390_watchdog_ops,
2979 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2980 .pot_clear = mv88e6xxx_g2_pot_clear,
2981 .reset = mv88e6352_g1_reset,
2982 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2983 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2984 .serdes_power = mv88e6390_serdes_power,
2985};
2986
2987static const struct mv88e6xxx_ops mv88e6240_ops = {
2988 /* MV88E6XXX_FAMILY_6352 */
2989 .irl_init_all = mv88e6352_g2_irl_init_all,
2990 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2991 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2992 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2993 .phy_read = mv88e6xxx_g2_smi_phy_read,
2994 .phy_write = mv88e6xxx_g2_smi_phy_write,
2995 .port_set_link = mv88e6xxx_port_set_link,
2996 .port_set_duplex = mv88e6xxx_port_set_duplex,
2997 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2998 .port_set_speed = mv88e6352_port_set_speed,
2999 .port_tag_remap = mv88e6095_port_tag_remap,
3000 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3001 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3002 .port_set_ether_type = mv88e6351_port_set_ether_type,
3003 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3004 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3005 .port_pause_limit = mv88e6097_port_pause_limit,
3006 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3007 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3008 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3009 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3010 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3011 .stats_get_strings = mv88e6095_stats_get_strings,
3012 .stats_get_stats = mv88e6095_stats_get_stats,
3013 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3014 .set_egress_port = mv88e6095_g1_set_egress_port,
3015 .watchdog_ops = &mv88e6097_watchdog_ops,
3016 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3017 .pot_clear = mv88e6xxx_g2_pot_clear,
3018 .reset = mv88e6352_g1_reset,
3019 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3020 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3021 .serdes_power = mv88e6352_serdes_power,
3022 .gpio_ops = &mv88e6352_gpio_ops,
3023 .avb_ops = &mv88e6352_avb_ops,
3024};
3025
3026static const struct mv88e6xxx_ops mv88e6290_ops = {
3027 /* MV88E6XXX_FAMILY_6390 */
3028 .irl_init_all = mv88e6390_g2_irl_init_all,
3029 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3030 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3031 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3032 .phy_read = mv88e6xxx_g2_smi_phy_read,
3033 .phy_write = mv88e6xxx_g2_smi_phy_write,
3034 .port_set_link = mv88e6xxx_port_set_link,
3035 .port_set_duplex = mv88e6xxx_port_set_duplex,
3036 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3037 .port_set_speed = mv88e6390_port_set_speed,
3038 .port_tag_remap = mv88e6390_port_tag_remap,
3039 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3040 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3041 .port_set_ether_type = mv88e6351_port_set_ether_type,
3042 .port_pause_limit = mv88e6390_port_pause_limit,
3043 .port_set_cmode = mv88e6390x_port_set_cmode,
3044 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3045 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3046 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3047 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3048 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3049 .stats_get_strings = mv88e6320_stats_get_strings,
3050 .stats_get_stats = mv88e6390_stats_get_stats,
3051 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3052 .set_egress_port = mv88e6390_g1_set_egress_port,
3053 .watchdog_ops = &mv88e6390_watchdog_ops,
3054 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3055 .pot_clear = mv88e6xxx_g2_pot_clear,
3056 .reset = mv88e6352_g1_reset,
3057 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3058 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3059 .serdes_power = mv88e6390_serdes_power,
3060 .gpio_ops = &mv88e6352_gpio_ops,
3061 .avb_ops = &mv88e6390_avb_ops,
3062};
3063
3064static const struct mv88e6xxx_ops mv88e6320_ops = {
3065 /* MV88E6XXX_FAMILY_6320 */
3066 .irl_init_all = mv88e6352_g2_irl_init_all,
3067 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3068 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3069 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3070 .phy_read = mv88e6xxx_g2_smi_phy_read,
3071 .phy_write = mv88e6xxx_g2_smi_phy_write,
3072 .port_set_link = mv88e6xxx_port_set_link,
3073 .port_set_duplex = mv88e6xxx_port_set_duplex,
3074 .port_set_speed = mv88e6185_port_set_speed,
3075 .port_tag_remap = mv88e6095_port_tag_remap,
3076 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3077 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3078 .port_set_ether_type = mv88e6351_port_set_ether_type,
3079 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3080 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3081 .port_pause_limit = mv88e6097_port_pause_limit,
3082 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3083 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3084 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3085 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3086 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3087 .stats_get_strings = mv88e6320_stats_get_strings,
3088 .stats_get_stats = mv88e6320_stats_get_stats,
3089 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3090 .set_egress_port = mv88e6095_g1_set_egress_port,
3091 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3092 .pot_clear = mv88e6xxx_g2_pot_clear,
3093 .reset = mv88e6352_g1_reset,
3094 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3095 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3096 .gpio_ops = &mv88e6352_gpio_ops,
3097 .avb_ops = &mv88e6352_avb_ops,
3098};
3099
3100static const struct mv88e6xxx_ops mv88e6321_ops = {
3101 /* MV88E6XXX_FAMILY_6320 */
3102 .irl_init_all = mv88e6352_g2_irl_init_all,
3103 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3104 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3105 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3106 .phy_read = mv88e6xxx_g2_smi_phy_read,
3107 .phy_write = mv88e6xxx_g2_smi_phy_write,
3108 .port_set_link = mv88e6xxx_port_set_link,
3109 .port_set_duplex = mv88e6xxx_port_set_duplex,
3110 .port_set_speed = mv88e6185_port_set_speed,
3111 .port_tag_remap = mv88e6095_port_tag_remap,
3112 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3113 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3114 .port_set_ether_type = mv88e6351_port_set_ether_type,
3115 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3116 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3117 .port_pause_limit = mv88e6097_port_pause_limit,
3118 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3119 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3120 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3121 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3122 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3123 .stats_get_strings = mv88e6320_stats_get_strings,
3124 .stats_get_stats = mv88e6320_stats_get_stats,
3125 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3126 .set_egress_port = mv88e6095_g1_set_egress_port,
3127 .reset = mv88e6352_g1_reset,
3128 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3129 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3130 .gpio_ops = &mv88e6352_gpio_ops,
3131 .avb_ops = &mv88e6352_avb_ops,
3132};
3133
3134static const struct mv88e6xxx_ops mv88e6341_ops = {
3135 /* MV88E6XXX_FAMILY_6341 */
3136 .irl_init_all = mv88e6352_g2_irl_init_all,
3137 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3138 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3139 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3140 .phy_read = mv88e6xxx_g2_smi_phy_read,
3141 .phy_write = mv88e6xxx_g2_smi_phy_write,
3142 .port_set_link = mv88e6xxx_port_set_link,
3143 .port_set_duplex = mv88e6xxx_port_set_duplex,
3144 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3145 .port_set_speed = mv88e6390_port_set_speed,
3146 .port_tag_remap = mv88e6095_port_tag_remap,
3147 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3148 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3149 .port_set_ether_type = mv88e6351_port_set_ether_type,
3150 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3151 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3152 .port_pause_limit = mv88e6097_port_pause_limit,
3153 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3154 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3155 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3156 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3157 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3158 .stats_get_strings = mv88e6320_stats_get_strings,
3159 .stats_get_stats = mv88e6390_stats_get_stats,
3160 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3161 .set_egress_port = mv88e6390_g1_set_egress_port,
3162 .watchdog_ops = &mv88e6390_watchdog_ops,
3163 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3164 .pot_clear = mv88e6xxx_g2_pot_clear,
3165 .reset = mv88e6352_g1_reset,
3166 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3167 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3168 .gpio_ops = &mv88e6352_gpio_ops,
3169 .avb_ops = &mv88e6390_avb_ops,
3170};
3171
3172static const struct mv88e6xxx_ops mv88e6350_ops = {
3173 /* MV88E6XXX_FAMILY_6351 */
3174 .irl_init_all = mv88e6352_g2_irl_init_all,
3175 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3176 .phy_read = mv88e6xxx_g2_smi_phy_read,
3177 .phy_write = mv88e6xxx_g2_smi_phy_write,
3178 .port_set_link = mv88e6xxx_port_set_link,
3179 .port_set_duplex = mv88e6xxx_port_set_duplex,
3180 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3181 .port_set_speed = mv88e6185_port_set_speed,
3182 .port_tag_remap = mv88e6095_port_tag_remap,
3183 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3184 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3185 .port_set_ether_type = mv88e6351_port_set_ether_type,
3186 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3187 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3188 .port_pause_limit = mv88e6097_port_pause_limit,
3189 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3190 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3191 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3192 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3193 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3194 .stats_get_strings = mv88e6095_stats_get_strings,
3195 .stats_get_stats = mv88e6095_stats_get_stats,
3196 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3197 .set_egress_port = mv88e6095_g1_set_egress_port,
3198 .watchdog_ops = &mv88e6097_watchdog_ops,
3199 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3200 .pot_clear = mv88e6xxx_g2_pot_clear,
3201 .reset = mv88e6352_g1_reset,
3202 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3203 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3204};
3205
3206static const struct mv88e6xxx_ops mv88e6351_ops = {
3207 /* MV88E6XXX_FAMILY_6351 */
3208 .irl_init_all = mv88e6352_g2_irl_init_all,
3209 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3210 .phy_read = mv88e6xxx_g2_smi_phy_read,
3211 .phy_write = mv88e6xxx_g2_smi_phy_write,
3212 .port_set_link = mv88e6xxx_port_set_link,
3213 .port_set_duplex = mv88e6xxx_port_set_duplex,
3214 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3215 .port_set_speed = mv88e6185_port_set_speed,
3216 .port_tag_remap = mv88e6095_port_tag_remap,
3217 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3218 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3219 .port_set_ether_type = mv88e6351_port_set_ether_type,
3220 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3221 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3222 .port_pause_limit = mv88e6097_port_pause_limit,
3223 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3224 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3225 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3226 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3227 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3228 .stats_get_strings = mv88e6095_stats_get_strings,
3229 .stats_get_stats = mv88e6095_stats_get_stats,
3230 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3231 .set_egress_port = mv88e6095_g1_set_egress_port,
3232 .watchdog_ops = &mv88e6097_watchdog_ops,
3233 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3234 .pot_clear = mv88e6xxx_g2_pot_clear,
3235 .reset = mv88e6352_g1_reset,
3236 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3237 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3238 .avb_ops = &mv88e6352_avb_ops,
3239};
3240
3241static const struct mv88e6xxx_ops mv88e6352_ops = {
3242 /* MV88E6XXX_FAMILY_6352 */
3243 .irl_init_all = mv88e6352_g2_irl_init_all,
3244 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3245 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3246 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3247 .phy_read = mv88e6xxx_g2_smi_phy_read,
3248 .phy_write = mv88e6xxx_g2_smi_phy_write,
3249 .port_set_link = mv88e6xxx_port_set_link,
3250 .port_set_duplex = mv88e6xxx_port_set_duplex,
3251 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3252 .port_set_speed = mv88e6352_port_set_speed,
3253 .port_tag_remap = mv88e6095_port_tag_remap,
3254 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3255 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3256 .port_set_ether_type = mv88e6351_port_set_ether_type,
3257 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3258 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3259 .port_pause_limit = mv88e6097_port_pause_limit,
3260 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3261 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3262 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3263 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3264 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3265 .stats_get_strings = mv88e6095_stats_get_strings,
3266 .stats_get_stats = mv88e6095_stats_get_stats,
3267 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3268 .set_egress_port = mv88e6095_g1_set_egress_port,
3269 .watchdog_ops = &mv88e6097_watchdog_ops,
3270 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3271 .pot_clear = mv88e6xxx_g2_pot_clear,
3272 .reset = mv88e6352_g1_reset,
3273 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3274 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3275 .serdes_power = mv88e6352_serdes_power,
3276 .gpio_ops = &mv88e6352_gpio_ops,
3277 .avb_ops = &mv88e6352_avb_ops,
3278 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3279 .serdes_get_strings = mv88e6352_serdes_get_strings,
3280 .serdes_get_stats = mv88e6352_serdes_get_stats,
3281};
3282
3283static const struct mv88e6xxx_ops mv88e6390_ops = {
3284 /* MV88E6XXX_FAMILY_6390 */
3285 .irl_init_all = mv88e6390_g2_irl_init_all,
3286 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3287 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3288 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3289 .phy_read = mv88e6xxx_g2_smi_phy_read,
3290 .phy_write = mv88e6xxx_g2_smi_phy_write,
3291 .port_set_link = mv88e6xxx_port_set_link,
3292 .port_set_duplex = mv88e6xxx_port_set_duplex,
3293 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3294 .port_set_speed = mv88e6390_port_set_speed,
3295 .port_tag_remap = mv88e6390_port_tag_remap,
3296 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3297 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3298 .port_set_ether_type = mv88e6351_port_set_ether_type,
3299 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3300 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3301 .port_pause_limit = mv88e6390_port_pause_limit,
3302 .port_set_cmode = mv88e6390x_port_set_cmode,
3303 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3304 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3305 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3306 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3307 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3308 .stats_get_strings = mv88e6320_stats_get_strings,
3309 .stats_get_stats = mv88e6390_stats_get_stats,
3310 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3311 .set_egress_port = mv88e6390_g1_set_egress_port,
3312 .watchdog_ops = &mv88e6390_watchdog_ops,
3313 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3314 .pot_clear = mv88e6xxx_g2_pot_clear,
3315 .reset = mv88e6352_g1_reset,
3316 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3317 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3318 .serdes_power = mv88e6390_serdes_power,
3319 .gpio_ops = &mv88e6352_gpio_ops,
3320 .avb_ops = &mv88e6390_avb_ops,
3321};
3322
3323static const struct mv88e6xxx_ops mv88e6390x_ops = {
3324 /* MV88E6XXX_FAMILY_6390 */
3325 .irl_init_all = mv88e6390_g2_irl_init_all,
3326 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3327 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3328 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3329 .phy_read = mv88e6xxx_g2_smi_phy_read,
3330 .phy_write = mv88e6xxx_g2_smi_phy_write,
3331 .port_set_link = mv88e6xxx_port_set_link,
3332 .port_set_duplex = mv88e6xxx_port_set_duplex,
3333 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3334 .port_set_speed = mv88e6390x_port_set_speed,
3335 .port_tag_remap = mv88e6390_port_tag_remap,
3336 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3337 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3338 .port_set_ether_type = mv88e6351_port_set_ether_type,
3339 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3340 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3341 .port_pause_limit = mv88e6390_port_pause_limit,
3342 .port_set_cmode = mv88e6390x_port_set_cmode,
3343 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3344 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3345 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3346 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3347 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3348 .stats_get_strings = mv88e6320_stats_get_strings,
3349 .stats_get_stats = mv88e6390_stats_get_stats,
3350 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3351 .set_egress_port = mv88e6390_g1_set_egress_port,
3352 .watchdog_ops = &mv88e6390_watchdog_ops,
3353 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3354 .pot_clear = mv88e6xxx_g2_pot_clear,
3355 .reset = mv88e6352_g1_reset,
3356 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3357 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3358 .serdes_power = mv88e6390_serdes_power,
3359 .gpio_ops = &mv88e6352_gpio_ops,
3360 .avb_ops = &mv88e6390_avb_ops,
3361};
3362
3363static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3364 [MV88E6085] = {
3365 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3366 .family = MV88E6XXX_FAMILY_6097,
3367 .name = "Marvell 88E6085",
3368 .num_databases = 4096,
3369 .num_ports = 10,
3370 .num_internal_phys = 5,
3371 .max_vid = 4095,
3372 .port_base_addr = 0x10,
3373 .phy_base_addr = 0x0,
3374 .global1_addr = 0x1b,
3375 .global2_addr = 0x1c,
3376 .age_time_coeff = 15000,
3377 .g1_irqs = 8,
3378 .g2_irqs = 10,
3379 .atu_move_port_mask = 0xf,
3380 .pvt = true,
3381 .multi_chip = true,
3382 .tag_protocol = DSA_TAG_PROTO_DSA,
3383 .ops = &mv88e6085_ops,
3384 },
3385
3386 [MV88E6095] = {
3387 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3388 .family = MV88E6XXX_FAMILY_6095,
3389 .name = "Marvell 88E6095/88E6095F",
3390 .num_databases = 256,
3391 .num_ports = 11,
3392 .num_internal_phys = 0,
3393 .max_vid = 4095,
3394 .port_base_addr = 0x10,
3395 .phy_base_addr = 0x0,
3396 .global1_addr = 0x1b,
3397 .global2_addr = 0x1c,
3398 .age_time_coeff = 15000,
3399 .g1_irqs = 8,
3400 .atu_move_port_mask = 0xf,
3401 .multi_chip = true,
3402 .tag_protocol = DSA_TAG_PROTO_DSA,
3403 .ops = &mv88e6095_ops,
3404 },
3405
3406 [MV88E6097] = {
3407 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3408 .family = MV88E6XXX_FAMILY_6097,
3409 .name = "Marvell 88E6097/88E6097F",
3410 .num_databases = 4096,
3411 .num_ports = 11,
3412 .num_internal_phys = 8,
3413 .max_vid = 4095,
3414 .port_base_addr = 0x10,
3415 .phy_base_addr = 0x0,
3416 .global1_addr = 0x1b,
3417 .global2_addr = 0x1c,
3418 .age_time_coeff = 15000,
3419 .g1_irqs = 8,
3420 .g2_irqs = 10,
3421 .atu_move_port_mask = 0xf,
3422 .pvt = true,
3423 .multi_chip = true,
3424 .tag_protocol = DSA_TAG_PROTO_EDSA,
3425 .ops = &mv88e6097_ops,
3426 },
3427
3428 [MV88E6123] = {
3429 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3430 .family = MV88E6XXX_FAMILY_6165,
3431 .name = "Marvell 88E6123",
3432 .num_databases = 4096,
3433 .num_ports = 3,
3434 .num_internal_phys = 5,
3435 .max_vid = 4095,
3436 .port_base_addr = 0x10,
3437 .phy_base_addr = 0x0,
3438 .global1_addr = 0x1b,
3439 .global2_addr = 0x1c,
3440 .age_time_coeff = 15000,
3441 .g1_irqs = 9,
3442 .g2_irqs = 10,
3443 .atu_move_port_mask = 0xf,
3444 .pvt = true,
3445 .multi_chip = true,
3446 .tag_protocol = DSA_TAG_PROTO_EDSA,
3447 .ops = &mv88e6123_ops,
3448 },
3449
3450 [MV88E6131] = {
3451 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3452 .family = MV88E6XXX_FAMILY_6185,
3453 .name = "Marvell 88E6131",
3454 .num_databases = 256,
3455 .num_ports = 8,
3456 .num_internal_phys = 0,
3457 .max_vid = 4095,
3458 .port_base_addr = 0x10,
3459 .phy_base_addr = 0x0,
3460 .global1_addr = 0x1b,
3461 .global2_addr = 0x1c,
3462 .age_time_coeff = 15000,
3463 .g1_irqs = 9,
3464 .atu_move_port_mask = 0xf,
3465 .multi_chip = true,
3466 .tag_protocol = DSA_TAG_PROTO_DSA,
3467 .ops = &mv88e6131_ops,
3468 },
3469
3470 [MV88E6141] = {
3471 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3472 .family = MV88E6XXX_FAMILY_6341,
3473 .name = "Marvell 88E6141",
3474 .num_databases = 4096,
3475 .num_ports = 6,
3476 .num_internal_phys = 5,
3477 .num_gpio = 11,
3478 .max_vid = 4095,
3479 .port_base_addr = 0x10,
3480 .phy_base_addr = 0x10,
3481 .global1_addr = 0x1b,
3482 .global2_addr = 0x1c,
3483 .age_time_coeff = 3750,
3484 .atu_move_port_mask = 0x1f,
3485 .g1_irqs = 9,
3486 .g2_irqs = 10,
3487 .pvt = true,
3488 .multi_chip = true,
3489 .tag_protocol = DSA_TAG_PROTO_EDSA,
3490 .ops = &mv88e6141_ops,
3491 },
3492
3493 [MV88E6161] = {
3494 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3495 .family = MV88E6XXX_FAMILY_6165,
3496 .name = "Marvell 88E6161",
3497 .num_databases = 4096,
3498 .num_ports = 6,
3499 .num_internal_phys = 5,
3500 .max_vid = 4095,
3501 .port_base_addr = 0x10,
3502 .phy_base_addr = 0x0,
3503 .global1_addr = 0x1b,
3504 .global2_addr = 0x1c,
3505 .age_time_coeff = 15000,
3506 .g1_irqs = 9,
3507 .g2_irqs = 10,
3508 .atu_move_port_mask = 0xf,
3509 .pvt = true,
3510 .multi_chip = true,
3511 .tag_protocol = DSA_TAG_PROTO_EDSA,
3512 .ops = &mv88e6161_ops,
3513 },
3514
3515 [MV88E6165] = {
3516 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3517 .family = MV88E6XXX_FAMILY_6165,
3518 .name = "Marvell 88E6165",
3519 .num_databases = 4096,
3520 .num_ports = 6,
3521 .num_internal_phys = 0,
3522 .max_vid = 4095,
3523 .port_base_addr = 0x10,
3524 .phy_base_addr = 0x0,
3525 .global1_addr = 0x1b,
3526 .global2_addr = 0x1c,
3527 .age_time_coeff = 15000,
3528 .g1_irqs = 9,
3529 .g2_irqs = 10,
3530 .atu_move_port_mask = 0xf,
3531 .pvt = true,
3532 .multi_chip = true,
3533 .tag_protocol = DSA_TAG_PROTO_DSA,
3534 .ops = &mv88e6165_ops,
3535 },
3536
3537 [MV88E6171] = {
3538 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3539 .family = MV88E6XXX_FAMILY_6351,
3540 .name = "Marvell 88E6171",
3541 .num_databases = 4096,
3542 .num_ports = 7,
3543 .num_internal_phys = 5,
3544 .max_vid = 4095,
3545 .port_base_addr = 0x10,
3546 .phy_base_addr = 0x0,
3547 .global1_addr = 0x1b,
3548 .global2_addr = 0x1c,
3549 .age_time_coeff = 15000,
3550 .g1_irqs = 9,
3551 .g2_irqs = 10,
3552 .atu_move_port_mask = 0xf,
3553 .pvt = true,
3554 .multi_chip = true,
3555 .tag_protocol = DSA_TAG_PROTO_EDSA,
3556 .ops = &mv88e6171_ops,
3557 },
3558
3559 [MV88E6172] = {
3560 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3561 .family = MV88E6XXX_FAMILY_6352,
3562 .name = "Marvell 88E6172",
3563 .num_databases = 4096,
3564 .num_ports = 7,
3565 .num_internal_phys = 5,
3566 .num_gpio = 15,
3567 .max_vid = 4095,
3568 .port_base_addr = 0x10,
3569 .phy_base_addr = 0x0,
3570 .global1_addr = 0x1b,
3571 .global2_addr = 0x1c,
3572 .age_time_coeff = 15000,
3573 .g1_irqs = 9,
3574 .g2_irqs = 10,
3575 .atu_move_port_mask = 0xf,
3576 .pvt = true,
3577 .multi_chip = true,
3578 .tag_protocol = DSA_TAG_PROTO_EDSA,
3579 .ops = &mv88e6172_ops,
3580 },
3581
3582 [MV88E6175] = {
3583 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3584 .family = MV88E6XXX_FAMILY_6351,
3585 .name = "Marvell 88E6175",
3586 .num_databases = 4096,
3587 .num_ports = 7,
3588 .num_internal_phys = 5,
3589 .max_vid = 4095,
3590 .port_base_addr = 0x10,
3591 .phy_base_addr = 0x0,
3592 .global1_addr = 0x1b,
3593 .global2_addr = 0x1c,
3594 .age_time_coeff = 15000,
3595 .g1_irqs = 9,
3596 .g2_irqs = 10,
3597 .atu_move_port_mask = 0xf,
3598 .pvt = true,
3599 .multi_chip = true,
3600 .tag_protocol = DSA_TAG_PROTO_EDSA,
3601 .ops = &mv88e6175_ops,
3602 },
3603
3604 [MV88E6176] = {
3605 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3606 .family = MV88E6XXX_FAMILY_6352,
3607 .name = "Marvell 88E6176",
3608 .num_databases = 4096,
3609 .num_ports = 7,
3610 .num_internal_phys = 5,
3611 .num_gpio = 15,
3612 .max_vid = 4095,
3613 .port_base_addr = 0x10,
3614 .phy_base_addr = 0x0,
3615 .global1_addr = 0x1b,
3616 .global2_addr = 0x1c,
3617 .age_time_coeff = 15000,
3618 .g1_irqs = 9,
3619 .g2_irqs = 10,
3620 .atu_move_port_mask = 0xf,
3621 .pvt = true,
3622 .multi_chip = true,
3623 .tag_protocol = DSA_TAG_PROTO_EDSA,
3624 .ops = &mv88e6176_ops,
3625 },
3626
3627 [MV88E6185] = {
3628 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3629 .family = MV88E6XXX_FAMILY_6185,
3630 .name = "Marvell 88E6185",
3631 .num_databases = 256,
3632 .num_ports = 10,
3633 .num_internal_phys = 0,
3634 .max_vid = 4095,
3635 .port_base_addr = 0x10,
3636 .phy_base_addr = 0x0,
3637 .global1_addr = 0x1b,
3638 .global2_addr = 0x1c,
3639 .age_time_coeff = 15000,
3640 .g1_irqs = 8,
3641 .atu_move_port_mask = 0xf,
3642 .multi_chip = true,
3643 .tag_protocol = DSA_TAG_PROTO_EDSA,
3644 .ops = &mv88e6185_ops,
3645 },
3646
3647 [MV88E6190] = {
3648 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3649 .family = MV88E6XXX_FAMILY_6390,
3650 .name = "Marvell 88E6190",
3651 .num_databases = 4096,
3652 .num_ports = 11, /* 10 + Z80 */
3653 .num_internal_phys = 11,
3654 .num_gpio = 16,
3655 .max_vid = 8191,
3656 .port_base_addr = 0x0,
3657 .phy_base_addr = 0x0,
3658 .global1_addr = 0x1b,
3659 .global2_addr = 0x1c,
3660 .tag_protocol = DSA_TAG_PROTO_DSA,
3661 .age_time_coeff = 3750,
3662 .g1_irqs = 9,
3663 .g2_irqs = 14,
3664 .pvt = true,
3665 .multi_chip = true,
3666 .atu_move_port_mask = 0x1f,
3667 .ops = &mv88e6190_ops,
3668 },
3669
3670 [MV88E6190X] = {
3671 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3672 .family = MV88E6XXX_FAMILY_6390,
3673 .name = "Marvell 88E6190X",
3674 .num_databases = 4096,
3675 .num_ports = 11, /* 10 + Z80 */
3676 .num_internal_phys = 11,
3677 .num_gpio = 16,
3678 .max_vid = 8191,
3679 .port_base_addr = 0x0,
3680 .phy_base_addr = 0x0,
3681 .global1_addr = 0x1b,
3682 .global2_addr = 0x1c,
3683 .age_time_coeff = 3750,
3684 .g1_irqs = 9,
3685 .g2_irqs = 14,
3686 .atu_move_port_mask = 0x1f,
3687 .pvt = true,
3688 .multi_chip = true,
3689 .tag_protocol = DSA_TAG_PROTO_DSA,
3690 .ops = &mv88e6190x_ops,
3691 },
3692
3693 [MV88E6191] = {
3694 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3695 .family = MV88E6XXX_FAMILY_6390,
3696 .name = "Marvell 88E6191",
3697 .num_databases = 4096,
3698 .num_ports = 11, /* 10 + Z80 */
3699 .num_internal_phys = 11,
3700 .max_vid = 8191,
3701 .port_base_addr = 0x0,
3702 .phy_base_addr = 0x0,
3703 .global1_addr = 0x1b,
3704 .global2_addr = 0x1c,
3705 .age_time_coeff = 3750,
3706 .g1_irqs = 9,
3707 .g2_irqs = 14,
3708 .atu_move_port_mask = 0x1f,
3709 .pvt = true,
3710 .multi_chip = true,
3711 .tag_protocol = DSA_TAG_PROTO_DSA,
3712 .ptp_support = true,
3713 .ops = &mv88e6191_ops,
3714 },
3715
3716 [MV88E6240] = {
3717 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3718 .family = MV88E6XXX_FAMILY_6352,
3719 .name = "Marvell 88E6240",
3720 .num_databases = 4096,
3721 .num_ports = 7,
3722 .num_internal_phys = 5,
3723 .num_gpio = 15,
3724 .max_vid = 4095,
3725 .port_base_addr = 0x10,
3726 .phy_base_addr = 0x0,
3727 .global1_addr = 0x1b,
3728 .global2_addr = 0x1c,
3729 .age_time_coeff = 15000,
3730 .g1_irqs = 9,
3731 .g2_irqs = 10,
3732 .atu_move_port_mask = 0xf,
3733 .pvt = true,
3734 .multi_chip = true,
3735 .tag_protocol = DSA_TAG_PROTO_EDSA,
3736 .ptp_support = true,
3737 .ops = &mv88e6240_ops,
3738 },
3739
3740 [MV88E6290] = {
3741 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3742 .family = MV88E6XXX_FAMILY_6390,
3743 .name = "Marvell 88E6290",
3744 .num_databases = 4096,
3745 .num_ports = 11, /* 10 + Z80 */
3746 .num_internal_phys = 11,
3747 .num_gpio = 16,
3748 .max_vid = 8191,
3749 .port_base_addr = 0x0,
3750 .phy_base_addr = 0x0,
3751 .global1_addr = 0x1b,
3752 .global2_addr = 0x1c,
3753 .age_time_coeff = 3750,
3754 .g1_irqs = 9,
3755 .g2_irqs = 14,
3756 .atu_move_port_mask = 0x1f,
3757 .pvt = true,
3758 .multi_chip = true,
3759 .tag_protocol = DSA_TAG_PROTO_DSA,
3760 .ptp_support = true,
3761 .ops = &mv88e6290_ops,
3762 },
3763
3764 [MV88E6320] = {
3765 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3766 .family = MV88E6XXX_FAMILY_6320,
3767 .name = "Marvell 88E6320",
3768 .num_databases = 4096,
3769 .num_ports = 7,
3770 .num_internal_phys = 5,
3771 .num_gpio = 15,
3772 .max_vid = 4095,
3773 .port_base_addr = 0x10,
3774 .phy_base_addr = 0x0,
3775 .global1_addr = 0x1b,
3776 .global2_addr = 0x1c,
3777 .age_time_coeff = 15000,
3778 .g1_irqs = 8,
3779 .g2_irqs = 10,
3780 .atu_move_port_mask = 0xf,
3781 .pvt = true,
3782 .multi_chip = true,
3783 .tag_protocol = DSA_TAG_PROTO_EDSA,
3784 .ptp_support = true,
3785 .ops = &mv88e6320_ops,
3786 },
3787
3788 [MV88E6321] = {
3789 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3790 .family = MV88E6XXX_FAMILY_6320,
3791 .name = "Marvell 88E6321",
3792 .num_databases = 4096,
3793 .num_ports = 7,
3794 .num_internal_phys = 5,
3795 .num_gpio = 15,
3796 .max_vid = 4095,
3797 .port_base_addr = 0x10,
3798 .phy_base_addr = 0x0,
3799 .global1_addr = 0x1b,
3800 .global2_addr = 0x1c,
3801 .age_time_coeff = 15000,
3802 .g1_irqs = 8,
3803 .g2_irqs = 10,
3804 .atu_move_port_mask = 0xf,
3805 .multi_chip = true,
3806 .tag_protocol = DSA_TAG_PROTO_EDSA,
3807 .ptp_support = true,
3808 .ops = &mv88e6321_ops,
3809 },
3810
3811 [MV88E6341] = {
3812 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3813 .family = MV88E6XXX_FAMILY_6341,
3814 .name = "Marvell 88E6341",
3815 .num_databases = 4096,
3816 .num_internal_phys = 5,
3817 .num_ports = 6,
3818 .num_gpio = 11,
3819 .max_vid = 4095,
3820 .port_base_addr = 0x10,
3821 .phy_base_addr = 0x10,
3822 .global1_addr = 0x1b,
3823 .global2_addr = 0x1c,
3824 .age_time_coeff = 3750,
3825 .atu_move_port_mask = 0x1f,
3826 .g1_irqs = 9,
3827 .g2_irqs = 10,
3828 .pvt = true,
3829 .multi_chip = true,
3830 .tag_protocol = DSA_TAG_PROTO_EDSA,
3831 .ptp_support = true,
3832 .ops = &mv88e6341_ops,
3833 },
3834
3835 [MV88E6350] = {
3836 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3837 .family = MV88E6XXX_FAMILY_6351,
3838 .name = "Marvell 88E6350",
3839 .num_databases = 4096,
3840 .num_ports = 7,
3841 .num_internal_phys = 5,
3842 .max_vid = 4095,
3843 .port_base_addr = 0x10,
3844 .phy_base_addr = 0x0,
3845 .global1_addr = 0x1b,
3846 .global2_addr = 0x1c,
3847 .age_time_coeff = 15000,
3848 .g1_irqs = 9,
3849 .g2_irqs = 10,
3850 .atu_move_port_mask = 0xf,
3851 .pvt = true,
3852 .multi_chip = true,
3853 .tag_protocol = DSA_TAG_PROTO_EDSA,
3854 .ops = &mv88e6350_ops,
3855 },
3856
3857 [MV88E6351] = {
3858 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3859 .family = MV88E6XXX_FAMILY_6351,
3860 .name = "Marvell 88E6351",
3861 .num_databases = 4096,
3862 .num_ports = 7,
3863 .num_internal_phys = 5,
3864 .max_vid = 4095,
3865 .port_base_addr = 0x10,
3866 .phy_base_addr = 0x0,
3867 .global1_addr = 0x1b,
3868 .global2_addr = 0x1c,
3869 .age_time_coeff = 15000,
3870 .g1_irqs = 9,
3871 .g2_irqs = 10,
3872 .atu_move_port_mask = 0xf,
3873 .pvt = true,
3874 .multi_chip = true,
3875 .tag_protocol = DSA_TAG_PROTO_EDSA,
3876 .ops = &mv88e6351_ops,
3877 },
3878
3879 [MV88E6352] = {
3880 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3881 .family = MV88E6XXX_FAMILY_6352,
3882 .name = "Marvell 88E6352",
3883 .num_databases = 4096,
3884 .num_ports = 7,
3885 .num_internal_phys = 5,
3886 .num_gpio = 15,
3887 .max_vid = 4095,
3888 .port_base_addr = 0x10,
3889 .phy_base_addr = 0x0,
3890 .global1_addr = 0x1b,
3891 .global2_addr = 0x1c,
3892 .age_time_coeff = 15000,
3893 .g1_irqs = 9,
3894 .g2_irqs = 10,
3895 .atu_move_port_mask = 0xf,
3896 .pvt = true,
3897 .multi_chip = true,
3898 .tag_protocol = DSA_TAG_PROTO_EDSA,
3899 .ptp_support = true,
3900 .ops = &mv88e6352_ops,
3901 },
3902 [MV88E6390] = {
3903 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3904 .family = MV88E6XXX_FAMILY_6390,
3905 .name = "Marvell 88E6390",
3906 .num_databases = 4096,
3907 .num_ports = 11, /* 10 + Z80 */
3908 .num_internal_phys = 11,
3909 .num_gpio = 16,
3910 .max_vid = 8191,
3911 .port_base_addr = 0x0,
3912 .phy_base_addr = 0x0,
3913 .global1_addr = 0x1b,
3914 .global2_addr = 0x1c,
3915 .age_time_coeff = 3750,
3916 .g1_irqs = 9,
3917 .g2_irqs = 14,
3918 .atu_move_port_mask = 0x1f,
3919 .pvt = true,
3920 .multi_chip = true,
3921 .tag_protocol = DSA_TAG_PROTO_DSA,
3922 .ptp_support = true,
3923 .ops = &mv88e6390_ops,
3924 },
3925 [MV88E6390X] = {
3926 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3927 .family = MV88E6XXX_FAMILY_6390,
3928 .name = "Marvell 88E6390X",
3929 .num_databases = 4096,
3930 .num_ports = 11, /* 10 + Z80 */
3931 .num_internal_phys = 11,
3932 .num_gpio = 16,
3933 .max_vid = 8191,
3934 .port_base_addr = 0x0,
3935 .phy_base_addr = 0x0,
3936 .global1_addr = 0x1b,
3937 .global2_addr = 0x1c,
3938 .age_time_coeff = 3750,
3939 .g1_irqs = 9,
3940 .g2_irqs = 14,
3941 .atu_move_port_mask = 0x1f,
3942 .pvt = true,
3943 .multi_chip = true,
3944 .tag_protocol = DSA_TAG_PROTO_DSA,
3945 .ptp_support = true,
3946 .ops = &mv88e6390x_ops,
3947 },
3948};
3949
3950static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3951{
3952 int i;
3953
3954 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3955 if (mv88e6xxx_table[i].prod_num == prod_num)
3956 return &mv88e6xxx_table[i];
3957
3958 return NULL;
3959}
3960
3961static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3962{
3963 const struct mv88e6xxx_info *info;
3964 unsigned int prod_num, rev;
3965 u16 id;
3966 int err;
3967
3968 mutex_lock(&chip->reg_lock);
3969 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3970 mutex_unlock(&chip->reg_lock);
3971 if (err)
3972 return err;
3973
3974 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3975 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3976
3977 info = mv88e6xxx_lookup_info(prod_num);
3978 if (!info)
3979 return -ENODEV;
3980
3981 /* Update the compatible info with the probed one */
3982 chip->info = info;
3983
3984 err = mv88e6xxx_g2_require(chip);
3985 if (err)
3986 return err;
3987
3988 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3989 chip->info->prod_num, chip->info->name, rev);
3990
3991 return 0;
3992}
3993
3994static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3995{
3996 struct mv88e6xxx_chip *chip;
3997
3998 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3999 if (!chip)
4000 return NULL;
4001
4002 chip->dev = dev;
4003
4004 mutex_init(&chip->reg_lock);
4005 INIT_LIST_HEAD(&chip->mdios);
4006
4007 return chip;
4008}
4009
4010static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4011 struct mii_bus *bus, int sw_addr)
4012{
4013 if (sw_addr == 0)
4014 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4015 else if (chip->info->multi_chip)
4016 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4017 else
4018 return -EINVAL;
4019
4020 chip->bus = bus;
4021 chip->sw_addr = sw_addr;
4022
4023 return 0;
4024}
4025
4026static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4027 int port)
4028{
4029 struct mv88e6xxx_chip *chip = ds->priv;
4030
4031 return chip->info->tag_protocol;
4032}
4033
4034#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4035static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4036 struct device *host_dev, int sw_addr,
4037 void **priv)
4038{
4039 struct mv88e6xxx_chip *chip;
4040 struct mii_bus *bus;
4041 int err;
4042
4043 bus = dsa_host_dev_to_mii_bus(host_dev);
4044 if (!bus)
4045 return NULL;
4046
4047 chip = mv88e6xxx_alloc_chip(dsa_dev);
4048 if (!chip)
4049 return NULL;
4050
4051 /* Legacy SMI probing will only support chips similar to 88E6085 */
4052 chip->info = &mv88e6xxx_table[MV88E6085];
4053
4054 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4055 if (err)
4056 goto free;
4057
4058 err = mv88e6xxx_detect(chip);
4059 if (err)
4060 goto free;
4061
4062 mutex_lock(&chip->reg_lock);
4063 err = mv88e6xxx_switch_reset(chip);
4064 mutex_unlock(&chip->reg_lock);
4065 if (err)
4066 goto free;
4067
4068 mv88e6xxx_phy_init(chip);
4069
4070 err = mv88e6xxx_mdios_register(chip, NULL);
4071 if (err)
4072 goto free;
4073
4074 *priv = chip;
4075
4076 return chip->info->name;
4077free:
4078 devm_kfree(dsa_dev, chip);
4079
4080 return NULL;
4081}
4082#endif
4083
4084static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4085 const struct switchdev_obj_port_mdb *mdb)
4086{
4087 /* We don't need any dynamic resource from the kernel (yet),
4088 * so skip the prepare phase.
4089 */
4090
4091 return 0;
4092}
4093
4094static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4095 const struct switchdev_obj_port_mdb *mdb)
4096{
4097 struct mv88e6xxx_chip *chip = ds->priv;
4098
4099 mutex_lock(&chip->reg_lock);
4100 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4101 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4102 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4103 port);
4104 mutex_unlock(&chip->reg_lock);
4105}
4106
4107static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4108 const struct switchdev_obj_port_mdb *mdb)
4109{
4110 struct mv88e6xxx_chip *chip = ds->priv;
4111 int err;
4112
4113 mutex_lock(&chip->reg_lock);
4114 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4115 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4116 mutex_unlock(&chip->reg_lock);
4117
4118 return err;
4119}
4120
4121static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4122#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4123 .probe = mv88e6xxx_drv_probe,
4124#endif
4125 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4126 .setup = mv88e6xxx_setup,
4127 .adjust_link = mv88e6xxx_adjust_link,
4128 .get_strings = mv88e6xxx_get_strings,
4129 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4130 .get_sset_count = mv88e6xxx_get_sset_count,
4131 .port_enable = mv88e6xxx_port_enable,
4132 .port_disable = mv88e6xxx_port_disable,
4133 .get_mac_eee = mv88e6xxx_get_mac_eee,
4134 .set_mac_eee = mv88e6xxx_set_mac_eee,
4135 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4136 .get_eeprom = mv88e6xxx_get_eeprom,
4137 .set_eeprom = mv88e6xxx_set_eeprom,
4138 .get_regs_len = mv88e6xxx_get_regs_len,
4139 .get_regs = mv88e6xxx_get_regs,
4140 .set_ageing_time = mv88e6xxx_set_ageing_time,
4141 .port_bridge_join = mv88e6xxx_port_bridge_join,
4142 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4143 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4144 .port_fast_age = mv88e6xxx_port_fast_age,
4145 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4146 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4147 .port_vlan_add = mv88e6xxx_port_vlan_add,
4148 .port_vlan_del = mv88e6xxx_port_vlan_del,
4149 .port_fdb_add = mv88e6xxx_port_fdb_add,
4150 .port_fdb_del = mv88e6xxx_port_fdb_del,
4151 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4152 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4153 .port_mdb_add = mv88e6xxx_port_mdb_add,
4154 .port_mdb_del = mv88e6xxx_port_mdb_del,
4155 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4156 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4157 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
4158 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
4159 .port_txtstamp = mv88e6xxx_port_txtstamp,
4160 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
4161 .get_ts_info = mv88e6xxx_get_ts_info,
4162};
4163
4164static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4165 .ops = &mv88e6xxx_switch_ops,
4166};
4167
4168static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4169{
4170 struct device *dev = chip->dev;
4171 struct dsa_switch *ds;
4172
4173 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4174 if (!ds)
4175 return -ENOMEM;
4176
4177 ds->priv = chip;
4178 ds->ops = &mv88e6xxx_switch_ops;
4179 ds->ageing_time_min = chip->info->age_time_coeff;
4180 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4181
4182 dev_set_drvdata(dev, ds);
4183
4184 return dsa_register_switch(ds);
4185}
4186
4187static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4188{
4189 dsa_unregister_switch(chip->ds);
4190}
4191
4192static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4193{
4194 struct device *dev = &mdiodev->dev;
4195 struct device_node *np = dev->of_node;
4196 const struct mv88e6xxx_info *compat_info;
4197 struct mv88e6xxx_chip *chip;
4198 u32 eeprom_len;
4199 int err;
4200
4201 compat_info = of_device_get_match_data(dev);
4202 if (!compat_info)
4203 return -EINVAL;
4204
4205 chip = mv88e6xxx_alloc_chip(dev);
4206 if (!chip)
4207 return -ENOMEM;
4208
4209 chip->info = compat_info;
4210
4211 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4212 if (err)
4213 return err;
4214
4215 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4216 if (IS_ERR(chip->reset))
4217 return PTR_ERR(chip->reset);
4218
4219 err = mv88e6xxx_detect(chip);
4220 if (err)
4221 return err;
4222
4223 mv88e6xxx_phy_init(chip);
4224
4225 if (chip->info->ops->get_eeprom &&
4226 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4227 chip->eeprom_len = eeprom_len;
4228
4229 mutex_lock(&chip->reg_lock);
4230 err = mv88e6xxx_switch_reset(chip);
4231 mutex_unlock(&chip->reg_lock);
4232 if (err)
4233 goto out;
4234
4235 chip->irq = of_irq_get(np, 0);
4236 if (chip->irq == -EPROBE_DEFER) {
4237 err = chip->irq;
4238 goto out;
4239 }
4240
4241 /* Has to be performed before the MDIO bus is created, because
4242 * the PHYs will link their interrupts to these interrupt
4243 * controllers
4244 */
4245 mutex_lock(&chip->reg_lock);
4246 if (chip->irq > 0)
4247 err = mv88e6xxx_g1_irq_setup(chip);
4248 else
4249 err = mv88e6xxx_irq_poll_setup(chip);
4250 mutex_unlock(&chip->reg_lock);
4251
4252 if (err)
4253 goto out;
4254
4255 if (chip->info->g2_irqs > 0) {
4256 err = mv88e6xxx_g2_irq_setup(chip);
4257 if (err)
4258 goto out_g1_irq;
4259 }
4260
4261 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4262 if (err)
4263 goto out_g2_irq;
4264
4265 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4266 if (err)
4267 goto out_g1_atu_prob_irq;
4268
4269 err = mv88e6xxx_mdios_register(chip, np);
4270 if (err)
4271 goto out_g1_vtu_prob_irq;
4272
4273 err = mv88e6xxx_register_switch(chip);
4274 if (err)
4275 goto out_mdio;
4276
4277 return 0;
4278
4279out_mdio:
4280 mv88e6xxx_mdios_unregister(chip);
4281out_g1_vtu_prob_irq:
4282 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4283out_g1_atu_prob_irq:
4284 mv88e6xxx_g1_atu_prob_irq_free(chip);
4285out_g2_irq:
4286 if (chip->info->g2_irqs > 0)
4287 mv88e6xxx_g2_irq_free(chip);
4288out_g1_irq:
4289 mutex_lock(&chip->reg_lock);
4290 if (chip->irq > 0)
4291 mv88e6xxx_g1_irq_free(chip);
4292 else
4293 mv88e6xxx_irq_poll_free(chip);
4294 mutex_unlock(&chip->reg_lock);
4295out:
4296 return err;
4297}
4298
4299static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4300{
4301 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4302 struct mv88e6xxx_chip *chip = ds->priv;
4303
4304 if (chip->info->ptp_support) {
4305 mv88e6xxx_hwtstamp_free(chip);
4306 mv88e6xxx_ptp_free(chip);
4307 }
4308
4309 mv88e6xxx_phy_destroy(chip);
4310 mv88e6xxx_unregister_switch(chip);
4311 mv88e6xxx_mdios_unregister(chip);
4312
4313 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4314 mv88e6xxx_g1_atu_prob_irq_free(chip);
4315
4316 if (chip->info->g2_irqs > 0)
4317 mv88e6xxx_g2_irq_free(chip);
4318
4319 mutex_lock(&chip->reg_lock);
4320 if (chip->irq > 0)
4321 mv88e6xxx_g1_irq_free(chip);
4322 else
4323 mv88e6xxx_irq_poll_free(chip);
4324 mutex_unlock(&chip->reg_lock);
4325}
4326
4327static const struct of_device_id mv88e6xxx_of_match[] = {
4328 {
4329 .compatible = "marvell,mv88e6085",
4330 .data = &mv88e6xxx_table[MV88E6085],
4331 },
4332 {
4333 .compatible = "marvell,mv88e6190",
4334 .data = &mv88e6xxx_table[MV88E6190],
4335 },
4336 { /* sentinel */ },
4337};
4338
4339MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4340
4341static struct mdio_driver mv88e6xxx_driver = {
4342 .probe = mv88e6xxx_probe,
4343 .remove = mv88e6xxx_remove,
4344 .mdiodrv.driver = {
4345 .name = "mv88e6085",
4346 .of_match_table = mv88e6xxx_of_match,
4347 },
4348};
4349
4350static int __init mv88e6xxx_init(void)
4351{
4352 register_switch_driver(&mv88e6xxx_switch_drv);
4353 return mdio_driver_register(&mv88e6xxx_driver);
4354}
4355module_init(mv88e6xxx_init);
4356
4357static void __exit mv88e6xxx_cleanup(void)
4358{
4359 mdio_driver_unregister(&mv88e6xxx_driver);
4360 unregister_switch_driver(&mv88e6xxx_switch_drv);
4361}
4362module_exit(mv88e6xxx_cleanup);
4363
4364MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4365MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4366MODULE_LICENSE("GPL");