Loading...
Note: File does not exist in v6.8.
1/*
2 * Microchip KSZ9477 register definitions
3 *
4 * Copyright (C) 2017
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#ifndef __KSZ9477_REGS_H
20#define __KSZ9477_REGS_H
21
22#define KS_PRIO_M 0x7
23#define KS_PRIO_S 4
24
25/* 0 - Operation */
26#define REG_CHIP_ID0__1 0x0000
27
28#define REG_CHIP_ID1__1 0x0001
29
30#define FAMILY_ID 0x95
31#define FAMILY_ID_94 0x94
32#define FAMILY_ID_95 0x95
33#define FAMILY_ID_85 0x85
34#define FAMILY_ID_98 0x98
35#define FAMILY_ID_88 0x88
36
37#define REG_CHIP_ID2__1 0x0002
38
39#define CHIP_ID_63 0x63
40#define CHIP_ID_66 0x66
41#define CHIP_ID_67 0x67
42#define CHIP_ID_77 0x77
43#define CHIP_ID_93 0x93
44#define CHIP_ID_96 0x96
45#define CHIP_ID_97 0x97
46
47#define REG_CHIP_ID3__1 0x0003
48
49#define SWITCH_REVISION_M 0x0F
50#define SWITCH_REVISION_S 4
51#define SWITCH_RESET 0x01
52
53#define REG_SW_PME_CTRL 0x0006
54
55#define PME_ENABLE BIT(1)
56#define PME_POLARITY BIT(0)
57
58#define REG_GLOBAL_OPTIONS 0x000F
59
60#define SW_GIGABIT_ABLE BIT(6)
61#define SW_REDUNDANCY_ABLE BIT(5)
62#define SW_AVB_ABLE BIT(4)
63#define SW_9567_RL_5_2 0xC
64#define SW_9477_SL_5_2 0xD
65
66#define SW_9896_GL_5_1 0xB
67#define SW_9896_RL_5_1 0x8
68#define SW_9896_SL_5_1 0x9
69
70#define SW_9895_GL_4_1 0x7
71#define SW_9895_RL_4_1 0x4
72#define SW_9895_SL_4_1 0x5
73
74#define SW_9896_RL_4_2 0x6
75
76#define SW_9893_RL_2_1 0x0
77#define SW_9893_SL_2_1 0x1
78#define SW_9893_GL_2_1 0x3
79
80#define SW_QW_ABLE BIT(5)
81#define SW_9893_RN_2_1 0xC
82
83#define REG_SW_INT_STATUS__4 0x0010
84#define REG_SW_INT_MASK__4 0x0014
85
86#define LUE_INT BIT(31)
87#define TRIG_TS_INT BIT(30)
88#define APB_TIMEOUT_INT BIT(29)
89
90#define SWITCH_INT_MASK (TRIG_TS_INT | APB_TIMEOUT_INT)
91
92#define REG_SW_PORT_INT_STATUS__4 0x0018
93#define REG_SW_PORT_INT_MASK__4 0x001C
94#define REG_SW_PHY_INT_STATUS 0x0020
95#define REG_SW_PHY_INT_ENABLE 0x0024
96
97/* 1 - Global */
98#define REG_SW_GLOBAL_SERIAL_CTRL_0 0x0100
99#define SW_SPARE_REG_2 BIT(7)
100#define SW_SPARE_REG_1 BIT(6)
101#define SW_SPARE_REG_0 BIT(5)
102#define SW_BIG_ENDIAN BIT(4)
103#define SPI_AUTO_EDGE_DETECTION BIT(1)
104#define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
105
106#define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
107#define SW_ENABLE_REFCLKO BIT(1)
108#define SW_REFCLKO_IS_125MHZ BIT(0)
109
110#define REG_SW_IBA__4 0x0104
111
112#define SW_IBA_ENABLE BIT(31)
113#define SW_IBA_DA_MATCH BIT(30)
114#define SW_IBA_INIT BIT(29)
115#define SW_IBA_QID_M 0xF
116#define SW_IBA_QID_S 22
117#define SW_IBA_PORT_M 0x2F
118#define SW_IBA_PORT_S 16
119#define SW_IBA_FRAME_TPID_M 0xFFFF
120
121#define REG_SW_APB_TIMEOUT_ADDR__4 0x0108
122
123#define APB_TIMEOUT_ACKNOWLEDGE BIT(31)
124
125#define REG_SW_IBA_SYNC__1 0x010C
126
127#define REG_SW_IO_STRENGTH__1 0x010D
128#define SW_DRIVE_STRENGTH_M 0x7
129#define SW_DRIVE_STRENGTH_2MA 0
130#define SW_DRIVE_STRENGTH_4MA 1
131#define SW_DRIVE_STRENGTH_8MA 2
132#define SW_DRIVE_STRENGTH_12MA 3
133#define SW_DRIVE_STRENGTH_16MA 4
134#define SW_DRIVE_STRENGTH_20MA 5
135#define SW_DRIVE_STRENGTH_24MA 6
136#define SW_DRIVE_STRENGTH_28MA 7
137#define SW_HI_SPEED_DRIVE_STRENGTH_S 4
138#define SW_LO_SPEED_DRIVE_STRENGTH_S 0
139
140#define REG_SW_IBA_STATUS__4 0x0110
141
142#define SW_IBA_REQ BIT(31)
143#define SW_IBA_RESP BIT(30)
144#define SW_IBA_DA_MISMATCH BIT(14)
145#define SW_IBA_FMT_MISMATCH BIT(13)
146#define SW_IBA_CODE_ERROR BIT(12)
147#define SW_IBA_CMD_ERROR BIT(11)
148#define SW_IBA_CMD_LOC_M (BIT(6) - 1)
149
150#define REG_SW_IBA_STATES__4 0x0114
151
152#define SW_IBA_BUF_STATE_S 30
153#define SW_IBA_CMD_STATE_S 28
154#define SW_IBA_RESP_STATE_S 26
155#define SW_IBA_STATE_M 0x3
156#define SW_IBA_PACKET_SIZE_M 0x7F
157#define SW_IBA_PACKET_SIZE_S 16
158#define SW_IBA_FMT_ID_M 0xFFFF
159
160#define REG_SW_IBA_RESULT__4 0x0118
161
162#define SW_IBA_SIZE_S 24
163
164#define SW_IBA_RETRY_CNT_M (BIT(5) - 1)
165
166/* 2 - PHY */
167#define REG_SW_POWER_MANAGEMENT_CTRL 0x0201
168
169#define SW_PLL_POWER_DOWN BIT(5)
170#define SW_POWER_DOWN_MODE 0x3
171#define SW_ENERGY_DETECTION 1
172#define SW_SOFT_POWER_DOWN 2
173#define SW_POWER_SAVING 3
174
175/* 3 - Operation Control */
176#define REG_SW_OPERATION 0x0300
177
178#define SW_DOUBLE_TAG BIT(7)
179#define SW_RESET BIT(1)
180#define SW_START BIT(0)
181
182#define REG_SW_MAC_ADDR_0 0x0302
183#define REG_SW_MAC_ADDR_1 0x0303
184#define REG_SW_MAC_ADDR_2 0x0304
185#define REG_SW_MAC_ADDR_3 0x0305
186#define REG_SW_MAC_ADDR_4 0x0306
187#define REG_SW_MAC_ADDR_5 0x0307
188
189#define REG_SW_MTU__2 0x0308
190
191#define REG_SW_ISP_TPID__2 0x030A
192
193#define REG_SW_HSR_TPID__2 0x030C
194
195#define REG_AVB_STRATEGY__2 0x030E
196
197#define SW_SHAPING_CREDIT_ACCT BIT(1)
198#define SW_POLICING_CREDIT_ACCT BIT(0)
199
200#define REG_SW_LUE_CTRL_0 0x0310
201
202#define SW_VLAN_ENABLE BIT(7)
203#define SW_DROP_INVALID_VID BIT(6)
204#define SW_AGE_CNT_M 0x7
205#define SW_AGE_CNT_S 3
206#define SW_RESV_MCAST_ENABLE BIT(2)
207#define SW_HASH_OPTION_M 0x03
208#define SW_HASH_OPTION_CRC 1
209#define SW_HASH_OPTION_XOR 2
210#define SW_HASH_OPTION_DIRECT 3
211
212#define REG_SW_LUE_CTRL_1 0x0311
213
214#define UNICAST_LEARN_DISABLE BIT(7)
215#define SW_SRC_ADDR_FILTER BIT(6)
216#define SW_FLUSH_STP_TABLE BIT(5)
217#define SW_FLUSH_MSTP_TABLE BIT(4)
218#define SW_FWD_MCAST_SRC_ADDR BIT(3)
219#define SW_AGING_ENABLE BIT(2)
220#define SW_FAST_AGING BIT(1)
221#define SW_LINK_AUTO_AGING BIT(0)
222
223#define REG_SW_LUE_CTRL_2 0x0312
224
225#define SW_TRAP_DOUBLE_TAG BIT(6)
226#define SW_EGRESS_VLAN_FILTER_DYN BIT(5)
227#define SW_EGRESS_VLAN_FILTER_STA BIT(4)
228#define SW_FLUSH_OPTION_M 0x3
229#define SW_FLUSH_OPTION_S 2
230#define SW_FLUSH_OPTION_DYN_MAC 1
231#define SW_FLUSH_OPTION_STA_MAC 2
232#define SW_FLUSH_OPTION_BOTH 3
233#define SW_PRIO_M 0x3
234#define SW_PRIO_DA 0
235#define SW_PRIO_SA 1
236#define SW_PRIO_HIGHEST_DA_SA 2
237#define SW_PRIO_LOWEST_DA_SA 3
238
239#define REG_SW_LUE_CTRL_3 0x0313
240
241#define REG_SW_LUE_INT_STATUS 0x0314
242#define REG_SW_LUE_INT_ENABLE 0x0315
243
244#define LEARN_FAIL_INT BIT(2)
245#define ALMOST_FULL_INT BIT(1)
246#define WRITE_FAIL_INT BIT(0)
247
248#define REG_SW_LUE_INDEX_0__2 0x0316
249
250#define ENTRY_INDEX_M 0x0FFF
251
252#define REG_SW_LUE_INDEX_1__2 0x0318
253
254#define FAIL_INDEX_M 0x03FF
255
256#define REG_SW_LUE_INDEX_2__2 0x031A
257
258#define REG_SW_LUE_UNK_UCAST_CTRL__4 0x0320
259
260#define SW_UNK_UCAST_ENABLE BIT(31)
261
262#define REG_SW_LUE_UNK_MCAST_CTRL__4 0x0324
263
264#define SW_UNK_MCAST_ENABLE BIT(31)
265
266#define REG_SW_LUE_UNK_VID_CTRL__4 0x0328
267
268#define SW_UNK_VID_ENABLE BIT(31)
269
270#define REG_SW_MAC_CTRL_0 0x0330
271
272#define SW_NEW_BACKOFF BIT(7)
273#define SW_CHECK_LENGTH BIT(3)
274#define SW_PAUSE_UNH_MODE BIT(1)
275#define SW_AGGR_BACKOFF BIT(0)
276
277#define REG_SW_MAC_CTRL_1 0x0331
278
279#define MULTICAST_STORM_DISABLE BIT(6)
280#define SW_BACK_PRESSURE BIT(5)
281#define FAIR_FLOW_CTRL BIT(4)
282#define NO_EXC_COLLISION_DROP BIT(3)
283#define SW_JUMBO_PACKET BIT(2)
284#define SW_LEGAL_PACKET_DISABLE BIT(1)
285#define SW_PASS_SHORT_FRAME BIT(0)
286
287#define REG_SW_MAC_CTRL_2 0x0332
288
289#define SW_REPLACE_VID BIT(3)
290#define BROADCAST_STORM_RATE_HI 0x07
291
292#define REG_SW_MAC_CTRL_3 0x0333
293
294#define BROADCAST_STORM_RATE_LO 0xFF
295#define BROADCAST_STORM_RATE 0x07FF
296
297#define REG_SW_MAC_CTRL_4 0x0334
298
299#define SW_PASS_PAUSE BIT(3)
300
301#define REG_SW_MAC_CTRL_5 0x0335
302
303#define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
304
305#define REG_SW_MAC_CTRL_6 0x0336
306
307#define SW_MIB_COUNTER_FLUSH BIT(7)
308#define SW_MIB_COUNTER_FREEZE BIT(6)
309
310#define REG_SW_MAC_802_1P_MAP_0 0x0338
311#define REG_SW_MAC_802_1P_MAP_1 0x0339
312#define REG_SW_MAC_802_1P_MAP_2 0x033A
313#define REG_SW_MAC_802_1P_MAP_3 0x033B
314
315#define SW_802_1P_MAP_M KS_PRIO_M
316#define SW_802_1P_MAP_S KS_PRIO_S
317
318#define REG_SW_MAC_ISP_CTRL 0x033C
319
320#define REG_SW_MAC_TOS_CTRL 0x033E
321
322#define SW_TOS_DSCP_REMARK BIT(1)
323#define SW_TOS_DSCP_REMAP BIT(0)
324
325#define REG_SW_MAC_TOS_PRIO_0 0x0340
326#define REG_SW_MAC_TOS_PRIO_1 0x0341
327#define REG_SW_MAC_TOS_PRIO_2 0x0342
328#define REG_SW_MAC_TOS_PRIO_3 0x0343
329#define REG_SW_MAC_TOS_PRIO_4 0x0344
330#define REG_SW_MAC_TOS_PRIO_5 0x0345
331#define REG_SW_MAC_TOS_PRIO_6 0x0346
332#define REG_SW_MAC_TOS_PRIO_7 0x0347
333#define REG_SW_MAC_TOS_PRIO_8 0x0348
334#define REG_SW_MAC_TOS_PRIO_9 0x0349
335#define REG_SW_MAC_TOS_PRIO_10 0x034A
336#define REG_SW_MAC_TOS_PRIO_11 0x034B
337#define REG_SW_MAC_TOS_PRIO_12 0x034C
338#define REG_SW_MAC_TOS_PRIO_13 0x034D
339#define REG_SW_MAC_TOS_PRIO_14 0x034E
340#define REG_SW_MAC_TOS_PRIO_15 0x034F
341#define REG_SW_MAC_TOS_PRIO_16 0x0350
342#define REG_SW_MAC_TOS_PRIO_17 0x0351
343#define REG_SW_MAC_TOS_PRIO_18 0x0352
344#define REG_SW_MAC_TOS_PRIO_19 0x0353
345#define REG_SW_MAC_TOS_PRIO_20 0x0354
346#define REG_SW_MAC_TOS_PRIO_21 0x0355
347#define REG_SW_MAC_TOS_PRIO_22 0x0356
348#define REG_SW_MAC_TOS_PRIO_23 0x0357
349#define REG_SW_MAC_TOS_PRIO_24 0x0358
350#define REG_SW_MAC_TOS_PRIO_25 0x0359
351#define REG_SW_MAC_TOS_PRIO_26 0x035A
352#define REG_SW_MAC_TOS_PRIO_27 0x035B
353#define REG_SW_MAC_TOS_PRIO_28 0x035C
354#define REG_SW_MAC_TOS_PRIO_29 0x035D
355#define REG_SW_MAC_TOS_PRIO_30 0x035E
356#define REG_SW_MAC_TOS_PRIO_31 0x035F
357
358#define REG_SW_MRI_CTRL_0 0x0370
359
360#define SW_IGMP_SNOOP BIT(6)
361#define SW_IPV6_MLD_OPTION BIT(3)
362#define SW_IPV6_MLD_SNOOP BIT(2)
363#define SW_MIRROR_RX_TX BIT(0)
364
365#define REG_SW_CLASS_D_IP_CTRL__4 0x0374
366
367#define SW_CLASS_D_IP_ENABLE BIT(31)
368
369#define REG_SW_MRI_CTRL_8 0x0378
370
371#define SW_NO_COLOR_S 6
372#define SW_RED_COLOR_S 4
373#define SW_YELLOW_COLOR_S 2
374#define SW_GREEN_COLOR_S 0
375#define SW_COLOR_M 0x3
376
377#define REG_SW_QM_CTRL__4 0x0390
378
379#define PRIO_SCHEME_SELECT_M KS_PRIO_M
380#define PRIO_SCHEME_SELECT_S 6
381#define PRIO_MAP_3_HI 0
382#define PRIO_MAP_2_HI 2
383#define PRIO_MAP_0_LO 3
384#define UNICAST_VLAN_BOUNDARY BIT(1)
385
386#define REG_SW_EEE_QM_CTRL__2 0x03C0
387
388#define REG_SW_EEE_TXQ_WAIT_TIME__2 0x03C2
389
390/* 4 - */
391#define REG_SW_VLAN_ENTRY__4 0x0400
392
393#define VLAN_VALID BIT(31)
394#define VLAN_FORWARD_OPTION BIT(27)
395#define VLAN_PRIO_M KS_PRIO_M
396#define VLAN_PRIO_S 24
397#define VLAN_MSTP_M 0x7
398#define VLAN_MSTP_S 12
399#define VLAN_FID_M 0x7F
400
401#define REG_SW_VLAN_ENTRY_UNTAG__4 0x0404
402#define REG_SW_VLAN_ENTRY_PORTS__4 0x0408
403
404#define REG_SW_VLAN_ENTRY_INDEX__2 0x040C
405
406#define VLAN_INDEX_M 0x0FFF
407
408#define REG_SW_VLAN_CTRL 0x040E
409
410#define VLAN_START BIT(7)
411#define VLAN_ACTION 0x3
412#define VLAN_WRITE 1
413#define VLAN_READ 2
414#define VLAN_CLEAR 3
415
416#define REG_SW_ALU_INDEX_0 0x0410
417
418#define ALU_FID_INDEX_S 16
419#define ALU_MAC_ADDR_HI 0xFFFF
420
421#define REG_SW_ALU_INDEX_1 0x0414
422
423#define ALU_DIRECT_INDEX_M (BIT(12) - 1)
424
425#define REG_SW_ALU_CTRL__4 0x0418
426
427#define ALU_VALID_CNT_M (BIT(14) - 1)
428#define ALU_VALID_CNT_S 16
429#define ALU_START BIT(7)
430#define ALU_VALID BIT(6)
431#define ALU_DIRECT BIT(2)
432#define ALU_ACTION 0x3
433#define ALU_WRITE 1
434#define ALU_READ 2
435#define ALU_SEARCH 3
436
437#define REG_SW_ALU_STAT_CTRL__4 0x041C
438
439#define ALU_STAT_INDEX_M (BIT(4) - 1)
440#define ALU_STAT_INDEX_S 16
441#define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)
442#define ALU_STAT_START BIT(7)
443#define ALU_RESV_MCAST_ADDR BIT(1)
444#define ALU_STAT_READ BIT(0)
445
446#define REG_SW_ALU_VAL_A 0x0420
447
448#define ALU_V_STATIC_VALID BIT(31)
449#define ALU_V_SRC_FILTER BIT(30)
450#define ALU_V_DST_FILTER BIT(29)
451#define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1)
452#define ALU_V_PRIO_AGE_CNT_S 26
453#define ALU_V_MSTP_M 0x7
454
455#define REG_SW_ALU_VAL_B 0x0424
456
457#define ALU_V_OVERRIDE BIT(31)
458#define ALU_V_USE_FID BIT(30)
459#define ALU_V_PORT_MAP (BIT(24) - 1)
460
461#define REG_SW_ALU_VAL_C 0x0428
462
463#define ALU_V_FID_M (BIT(16) - 1)
464#define ALU_V_FID_S 16
465#define ALU_V_MAC_ADDR_HI 0xFFFF
466
467#define REG_SW_ALU_VAL_D 0x042C
468
469#define REG_HSR_ALU_INDEX_0 0x0440
470
471#define REG_HSR_ALU_INDEX_1 0x0444
472
473#define HSR_DST_MAC_INDEX_LO_S 16
474#define HSR_SRC_MAC_INDEX_HI 0xFFFF
475
476#define REG_HSR_ALU_INDEX_2 0x0448
477
478#define HSR_INDEX_MAX BIT(9)
479#define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1)
480
481#define REG_HSR_ALU_INDEX_3 0x044C
482
483#define HSR_PATH_INDEX_M (BIT(4) - 1)
484
485#define REG_HSR_ALU_CTRL__4 0x0450
486
487#define HSR_VALID_CNT_M (BIT(14) - 1)
488#define HSR_VALID_CNT_S 16
489#define HSR_START BIT(7)
490#define HSR_VALID BIT(6)
491#define HSR_SEARCH_END BIT(5)
492#define HSR_DIRECT BIT(2)
493#define HSR_ACTION 0x3
494#define HSR_WRITE 1
495#define HSR_READ 2
496#define HSR_SEARCH 3
497
498#define REG_HSR_ALU_VAL_A 0x0454
499
500#define HSR_V_STATIC_VALID BIT(31)
501#define HSR_V_AGE_CNT_M (BIT(3) - 1)
502#define HSR_V_AGE_CNT_S 26
503#define HSR_V_PATH_ID_M (BIT(4) - 1)
504
505#define REG_HSR_ALU_VAL_B 0x0458
506
507#define REG_HSR_ALU_VAL_C 0x045C
508
509#define HSR_V_DST_MAC_ADDR_LO_S 16
510#define HSR_V_SRC_MAC_ADDR_HI 0xFFFF
511
512#define REG_HSR_ALU_VAL_D 0x0460
513
514#define REG_HSR_ALU_VAL_E 0x0464
515
516#define HSR_V_START_SEQ_1_S 16
517#define HSR_V_START_SEQ_2_S 0
518
519#define REG_HSR_ALU_VAL_F 0x0468
520
521#define HSR_V_EXP_SEQ_1_S 16
522#define HSR_V_EXP_SEQ_2_S 0
523
524#define REG_HSR_ALU_VAL_G 0x046C
525
526#define HSR_V_SEQ_CNT_1_S 16
527#define HSR_V_SEQ_CNT_2_S 0
528
529#define HSR_V_SEQ_M (BIT(16) - 1)
530
531/* 5 - PTP Clock */
532#define REG_PTP_CLK_CTRL 0x0500
533
534#define PTP_STEP_ADJ BIT(6)
535#define PTP_STEP_DIR BIT(5)
536#define PTP_READ_TIME BIT(4)
537#define PTP_LOAD_TIME BIT(3)
538#define PTP_CLK_ADJ_ENABLE BIT(2)
539#define PTP_CLK_ENABLE BIT(1)
540#define PTP_CLK_RESET BIT(0)
541
542#define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
543
544#define PTP_RTC_SUB_NANOSEC_M 0x0007
545
546#define REG_PTP_RTC_NANOSEC 0x0504
547#define REG_PTP_RTC_NANOSEC_H 0x0504
548#define REG_PTP_RTC_NANOSEC_L 0x0506
549
550#define REG_PTP_RTC_SEC 0x0508
551#define REG_PTP_RTC_SEC_H 0x0508
552#define REG_PTP_RTC_SEC_L 0x050A
553
554#define REG_PTP_SUBNANOSEC_RATE 0x050C
555#define REG_PTP_SUBNANOSEC_RATE_H 0x050C
556
557#define PTP_RATE_DIR BIT(31)
558#define PTP_TMP_RATE_ENABLE BIT(30)
559
560#define REG_PTP_SUBNANOSEC_RATE_L 0x050E
561
562#define REG_PTP_RATE_DURATION 0x0510
563#define REG_PTP_RATE_DURATION_H 0x0510
564#define REG_PTP_RATE_DURATION_L 0x0512
565
566#define REG_PTP_MSG_CONF1 0x0514
567
568#define PTP_802_1AS BIT(7)
569#define PTP_ENABLE BIT(6)
570#define PTP_ETH_ENABLE BIT(5)
571#define PTP_IPV4_UDP_ENABLE BIT(4)
572#define PTP_IPV6_UDP_ENABLE BIT(3)
573#define PTP_TC_P2P BIT(2)
574#define PTP_MASTER BIT(1)
575#define PTP_1STEP BIT(0)
576
577#define REG_PTP_MSG_CONF2 0x0516
578
579#define PTP_UNICAST_ENABLE BIT(12)
580#define PTP_ALTERNATE_MASTER BIT(11)
581#define PTP_ALL_HIGH_PRIO BIT(10)
582#define PTP_SYNC_CHECK BIT(9)
583#define PTP_DELAY_CHECK BIT(8)
584#define PTP_PDELAY_CHECK BIT(7)
585#define PTP_DROP_SYNC_DELAY_REQ BIT(5)
586#define PTP_DOMAIN_CHECK BIT(4)
587#define PTP_UDP_CHECKSUM BIT(2)
588
589#define REG_PTP_DOMAIN_VERSION 0x0518
590#define PTP_VERSION_M 0xFF00
591#define PTP_DOMAIN_M 0x00FF
592
593#define REG_PTP_UNIT_INDEX__4 0x0520
594
595#define PTP_UNIT_M 0xF
596
597#define PTP_GPIO_INDEX_S 16
598#define PTP_TSI_INDEX_S 8
599#define PTP_TOU_INDEX_S 0
600
601#define REG_PTP_TRIG_STATUS__4 0x0524
602
603#define TRIG_ERROR_S 16
604#define TRIG_DONE_S 0
605
606#define REG_PTP_INT_STATUS__4 0x0528
607
608#define TRIG_INT_S 16
609#define TS_INT_S 0
610
611#define TRIG_UNIT_M 0x7
612#define TS_UNIT_M 0x3
613
614#define REG_PTP_CTRL_STAT__4 0x052C
615
616#define GPIO_IN BIT(7)
617#define GPIO_OUT BIT(6)
618#define TS_INT_ENABLE BIT(5)
619#define TRIG_ACTIVE BIT(4)
620#define TRIG_ENABLE BIT(3)
621#define TRIG_RESET BIT(2)
622#define TS_ENABLE BIT(1)
623#define TS_RESET BIT(0)
624
625#define GPIO_CTRL_M (GPIO_IN | GPIO_OUT)
626
627#define TRIG_CTRL_M \
628 (TRIG_ACTIVE | TRIG_ENABLE | TRIG_RESET)
629
630#define TS_CTRL_M \
631 (TS_INT_ENABLE | TS_ENABLE | TS_RESET)
632
633#define REG_TRIG_TARGET_NANOSEC 0x0530
634#define REG_TRIG_TARGET_SEC 0x0534
635
636#define REG_TRIG_CTRL__4 0x0538
637
638#define TRIG_CASCADE_ENABLE BIT(31)
639#define TRIG_CASCADE_TAIL BIT(30)
640#define TRIG_CASCADE_UPS_M 0xF
641#define TRIG_CASCADE_UPS_S 26
642#define TRIG_NOW BIT(25)
643#define TRIG_NOTIFY BIT(24)
644#define TRIG_EDGE BIT(23)
645#define TRIG_PATTERN_S 20
646#define TRIG_PATTERN_M 0x7
647#define TRIG_NEG_EDGE 0
648#define TRIG_POS_EDGE 1
649#define TRIG_NEG_PULSE 2
650#define TRIG_POS_PULSE 3
651#define TRIG_NEG_PERIOD 4
652#define TRIG_POS_PERIOD 5
653#define TRIG_REG_OUTPUT 6
654#define TRIG_GPO_S 16
655#define TRIG_GPO_M 0xF
656#define TRIG_CASCADE_ITERATE_CNT_M 0xFFFF
657
658#define REG_TRIG_CYCLE_WIDTH 0x053C
659
660#define REG_TRIG_CYCLE_CNT 0x0540
661
662#define TRIG_CYCLE_CNT_M 0xFFFF
663#define TRIG_CYCLE_CNT_S 16
664#define TRIG_BIT_PATTERN_M 0xFFFF
665
666#define REG_TRIG_ITERATE_TIME 0x0544
667
668#define REG_TRIG_PULSE_WIDTH__4 0x0548
669
670#define TRIG_PULSE_WIDTH_M 0x00FFFFFF
671
672#define REG_TS_CTRL_STAT__4 0x0550
673
674#define TS_EVENT_DETECT_M 0xF
675#define TS_EVENT_DETECT_S 17
676#define TS_EVENT_OVERFLOW BIT(16)
677#define TS_GPI_M 0xF
678#define TS_GPI_S 8
679#define TS_DETECT_RISE BIT(7)
680#define TS_DETECT_FALL BIT(6)
681#define TS_DETECT_S 6
682#define TS_CASCADE_TAIL BIT(5)
683#define TS_CASCADE_UPS_M 0xF
684#define TS_CASCADE_UPS_S 1
685#define TS_CASCADE_ENABLE BIT(0)
686
687#define DETECT_RISE (TS_DETECT_RISE >> TS_DETECT_S)
688#define DETECT_FALL (TS_DETECT_FALL >> TS_DETECT_S)
689
690#define REG_TS_EVENT_0_NANOSEC 0x0554
691#define REG_TS_EVENT_0_SEC 0x0558
692#define REG_TS_EVENT_0_SUB_NANOSEC 0x055C
693
694#define REG_TS_EVENT_1_NANOSEC 0x0560
695#define REG_TS_EVENT_1_SEC 0x0564
696#define REG_TS_EVENT_1_SUB_NANOSEC 0x0568
697
698#define REG_TS_EVENT_2_NANOSEC 0x056C
699#define REG_TS_EVENT_2_SEC 0x0570
700#define REG_TS_EVENT_2_SUB_NANOSEC 0x0574
701
702#define REG_TS_EVENT_3_NANOSEC 0x0578
703#define REG_TS_EVENT_3_SEC 0x057C
704#define REG_TS_EVENT_3_SUB_NANOSEC 0x0580
705
706#define REG_TS_EVENT_4_NANOSEC 0x0584
707#define REG_TS_EVENT_4_SEC 0x0588
708#define REG_TS_EVENT_4_SUB_NANOSEC 0x058C
709
710#define REG_TS_EVENT_5_NANOSEC 0x0590
711#define REG_TS_EVENT_5_SEC 0x0594
712#define REG_TS_EVENT_5_SUB_NANOSEC 0x0598
713
714#define REG_TS_EVENT_6_NANOSEC 0x059C
715#define REG_TS_EVENT_6_SEC 0x05A0
716#define REG_TS_EVENT_6_SUB_NANOSEC 0x05A4
717
718#define REG_TS_EVENT_7_NANOSEC 0x05A8
719#define REG_TS_EVENT_7_SEC 0x05AC
720#define REG_TS_EVENT_7_SUB_NANOSEC 0x05B0
721
722#define TS_EVENT_EDGE_M 0x1
723#define TS_EVENT_EDGE_S 30
724#define TS_EVENT_NANOSEC_M (BIT(30) - 1)
725
726#define TS_EVENT_SUB_NANOSEC_M 0x7
727
728#define TS_EVENT_SAMPLE \
729 (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC)
730
731#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
732
733#define REG_GLOBAL_RR_INDEX__1 0x0600
734
735/* DLR */
736#define REG_DLR_SRC_PORT__4 0x0604
737
738#define DLR_SRC_PORT_UNICAST BIT(31)
739#define DLR_SRC_PORT_M 0x3
740#define DLR_SRC_PORT_BOTH 0
741#define DLR_SRC_PORT_EACH 1
742
743#define REG_DLR_IP_ADDR__4 0x0608
744
745#define REG_DLR_CTRL__1 0x0610
746
747#define DLR_RESET_SEQ_ID BIT(3)
748#define DLR_BACKUP_AUTO_ON BIT(2)
749#define DLR_BEACON_TX_ENABLE BIT(1)
750#define DLR_ASSIST_ENABLE BIT(0)
751
752#define REG_DLR_STATE__1 0x0611
753
754#define DLR_NODE_STATE_M 0x3
755#define DLR_NODE_STATE_S 1
756#define DLR_NODE_STATE_IDLE 0
757#define DLR_NODE_STATE_FAULT 1
758#define DLR_NODE_STATE_NORMAL 2
759#define DLR_RING_STATE_FAULT 0
760#define DLR_RING_STATE_NORMAL 1
761
762#define REG_DLR_PRECEDENCE__1 0x0612
763
764#define REG_DLR_BEACON_INTERVAL__4 0x0614
765
766#define REG_DLR_BEACON_TIMEOUT__4 0x0618
767
768#define REG_DLR_TIMEOUT_WINDOW__4 0x061C
769
770#define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1)
771
772#define REG_DLR_VLAN_ID__2 0x0620
773
774#define DLR_VLAN_ID_M (BIT(12) - 1)
775
776#define REG_DLR_DEST_ADDR_0 0x0622
777#define REG_DLR_DEST_ADDR_1 0x0623
778#define REG_DLR_DEST_ADDR_2 0x0624
779#define REG_DLR_DEST_ADDR_3 0x0625
780#define REG_DLR_DEST_ADDR_4 0x0626
781#define REG_DLR_DEST_ADDR_5 0x0627
782
783#define REG_DLR_PORT_MAP__4 0x0628
784
785#define REG_DLR_CLASS__1 0x062C
786
787#define DLR_FRAME_QID_M 0x3
788
789/* HSR */
790#define REG_HSR_PORT_MAP__4 0x0640
791
792#define REG_HSR_ALU_CTRL_0__1 0x0644
793
794#define HSR_DUPLICATE_DISCARD BIT(7)
795#define HSR_NODE_UNICAST BIT(6)
796#define HSR_AGE_CNT_DEFAULT_M 0x7
797#define HSR_AGE_CNT_DEFAULT_S 3
798#define HSR_LEARN_MCAST_DISABLE BIT(2)
799#define HSR_HASH_OPTION_M 0x3
800#define HSR_HASH_DISABLE 0
801#define HSR_HASH_UPPER_BITS 1
802#define HSR_HASH_LOWER_BITS 2
803#define HSR_HASH_XOR_BOTH_BITS 3
804
805#define REG_HSR_ALU_CTRL_1__1 0x0645
806
807#define HSR_LEARN_UCAST_DISABLE BIT(7)
808#define HSR_FLUSH_TABLE BIT(5)
809#define HSR_PROC_MCAST_SRC BIT(3)
810#define HSR_AGING_ENABLE BIT(2)
811
812#define REG_HSR_ALU_CTRL_2__2 0x0646
813
814#define REG_HSR_ALU_AGE_PERIOD__4 0x0648
815
816#define REG_HSR_ALU_INT_STATUS__1 0x064C
817#define REG_HSR_ALU_INT_MASK__1 0x064D
818
819#define HSR_WINDOW_OVERFLOW_INT BIT(3)
820#define HSR_LEARN_FAIL_INT BIT(2)
821#define HSR_ALMOST_FULL_INT BIT(1)
822#define HSR_WRITE_FAIL_INT BIT(0)
823
824#define REG_HSR_ALU_ENTRY_0__2 0x0650
825
826#define HSR_ENTRY_INDEX_M (BIT(10) - 1)
827#define HSR_FAIL_INDEX_M (BIT(8) - 1)
828
829#define REG_HSR_ALU_ENTRY_1__2 0x0652
830
831#define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1)
832
833#define REG_HSR_ALU_ENTRY_3__2 0x0654
834
835#define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1)
836
837/* 0 - Operation */
838#define REG_PORT_DEFAULT_VID 0x0000
839
840#define REG_PORT_CUSTOM_VID 0x0002
841#define REG_PORT_AVB_SR_1_VID 0x0004
842#define REG_PORT_AVB_SR_2_VID 0x0006
843
844#define REG_PORT_AVB_SR_1_TYPE 0x0008
845#define REG_PORT_AVB_SR_2_TYPE 0x000A
846
847#define REG_PORT_PME_STATUS 0x0013
848#define REG_PORT_PME_CTRL 0x0017
849
850#define PME_WOL_MAGICPKT BIT(2)
851#define PME_WOL_LINKUP BIT(1)
852#define PME_WOL_ENERGY BIT(0)
853
854#define REG_PORT_INT_STATUS 0x001B
855#define REG_PORT_INT_MASK 0x001F
856
857#define PORT_SGMII_INT BIT(3)
858#define PORT_PTP_INT BIT(2)
859#define PORT_PHY_INT BIT(1)
860#define PORT_ACL_INT BIT(0)
861
862#define PORT_INT_MASK \
863 (PORT_SGMII_INT | PORT_PTP_INT | PORT_PHY_INT | PORT_ACL_INT)
864
865#define REG_PORT_CTRL_0 0x0020
866
867#define PORT_MAC_LOOPBACK BIT(7)
868#define PORT_FORCE_TX_FLOW_CTRL BIT(4)
869#define PORT_FORCE_RX_FLOW_CTRL BIT(3)
870#define PORT_TAIL_TAG_ENABLE BIT(2)
871#define PORT_QUEUE_SPLIT_ENABLE 0x3
872
873#define REG_PORT_CTRL_1 0x0021
874
875#define PORT_SRP_ENABLE 0x3
876
877#define REG_PORT_STATUS_0 0x0030
878
879#define PORT_INTF_SPEED_M 0x3
880#define PORT_INTF_SPEED_S 3
881#define PORT_INTF_FULL_DUPLEX BIT(2)
882#define PORT_TX_FLOW_CTRL BIT(1)
883#define PORT_RX_FLOW_CTRL BIT(0)
884
885#define REG_PORT_STATUS_1 0x0034
886
887/* 1 - PHY */
888#define REG_PORT_PHY_CTRL 0x0100
889
890#define PORT_PHY_RESET BIT(15)
891#define PORT_PHY_LOOPBACK BIT(14)
892#define PORT_SPEED_100MBIT BIT(13)
893#define PORT_AUTO_NEG_ENABLE BIT(12)
894#define PORT_POWER_DOWN BIT(11)
895#define PORT_ISOLATE BIT(10)
896#define PORT_AUTO_NEG_RESTART BIT(9)
897#define PORT_FULL_DUPLEX BIT(8)
898#define PORT_COLLISION_TEST BIT(7)
899#define PORT_SPEED_1000MBIT BIT(6)
900
901#define REG_PORT_PHY_STATUS 0x0102
902
903#define PORT_100BT4_CAPABLE BIT(15)
904#define PORT_100BTX_FD_CAPABLE BIT(14)
905#define PORT_100BTX_CAPABLE BIT(13)
906#define PORT_10BT_FD_CAPABLE BIT(12)
907#define PORT_10BT_CAPABLE BIT(11)
908#define PORT_EXTENDED_STATUS BIT(8)
909#define PORT_MII_SUPPRESS_CAPABLE BIT(6)
910#define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5)
911#define PORT_REMOTE_FAULT BIT(4)
912#define PORT_AUTO_NEG_CAPABLE BIT(3)
913#define PORT_LINK_STATUS BIT(2)
914#define PORT_JABBER_DETECT BIT(1)
915#define PORT_EXTENDED_CAPABILITY BIT(0)
916
917#define REG_PORT_PHY_ID_HI 0x0104
918#define REG_PORT_PHY_ID_LO 0x0106
919
920#define KSZ9477_ID_HI 0x0022
921#define KSZ9477_ID_LO 0x1622
922
923#define REG_PORT_PHY_AUTO_NEGOTIATION 0x0108
924
925#define PORT_AUTO_NEG_NEXT_PAGE BIT(15)
926#define PORT_AUTO_NEG_REMOTE_FAULT BIT(13)
927#define PORT_AUTO_NEG_ASYM_PAUSE BIT(11)
928#define PORT_AUTO_NEG_SYM_PAUSE BIT(10)
929#define PORT_AUTO_NEG_100BT4 BIT(9)
930#define PORT_AUTO_NEG_100BTX_FD BIT(8)
931#define PORT_AUTO_NEG_100BTX BIT(7)
932#define PORT_AUTO_NEG_10BT_FD BIT(6)
933#define PORT_AUTO_NEG_10BT BIT(5)
934#define PORT_AUTO_NEG_SELECTOR 0x001F
935#define PORT_AUTO_NEG_802_3 0x0001
936
937#define PORT_AUTO_NEG_PAUSE \
938 (PORT_AUTO_NEG_ASYM_PAUSE | PORT_AUTO_NEG_SYM_PAUSE)
939
940#define REG_PORT_PHY_REMOTE_CAPABILITY 0x010A
941
942#define PORT_REMOTE_NEXT_PAGE BIT(15)
943#define PORT_REMOTE_ACKNOWLEDGE BIT(14)
944#define PORT_REMOTE_REMOTE_FAULT BIT(13)
945#define PORT_REMOTE_ASYM_PAUSE BIT(11)
946#define PORT_REMOTE_SYM_PAUSE BIT(10)
947#define PORT_REMOTE_100BTX_FD BIT(8)
948#define PORT_REMOTE_100BTX BIT(7)
949#define PORT_REMOTE_10BT_FD BIT(6)
950#define PORT_REMOTE_10BT BIT(5)
951
952#define REG_PORT_PHY_1000_CTRL 0x0112
953
954#define PORT_AUTO_NEG_MANUAL BIT(12)
955#define PORT_AUTO_NEG_MASTER BIT(11)
956#define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10)
957#define PORT_AUTO_NEG_1000BT_FD BIT(9)
958#define PORT_AUTO_NEG_1000BT BIT(8)
959
960#define REG_PORT_PHY_1000_STATUS 0x0114
961
962#define PORT_MASTER_FAULT BIT(15)
963#define PORT_LOCAL_MASTER BIT(14)
964#define PORT_LOCAL_RX_OK BIT(13)
965#define PORT_REMOTE_RX_OK BIT(12)
966#define PORT_REMOTE_1000BT_FD BIT(11)
967#define PORT_REMOTE_1000BT BIT(10)
968#define PORT_REMOTE_IDLE_CNT_M 0x0F
969
970#define PORT_PHY_1000_STATIC_STATUS \
971 (PORT_LOCAL_RX_OK | \
972 PORT_REMOTE_RX_OK | \
973 PORT_REMOTE_1000BT_FD | \
974 PORT_REMOTE_1000BT)
975
976#define REG_PORT_PHY_MMD_SETUP 0x011A
977
978#define PORT_MMD_OP_MODE_M 0x3
979#define PORT_MMD_OP_MODE_S 14
980#define PORT_MMD_OP_INDEX 0
981#define PORT_MMD_OP_DATA_NO_INCR 1
982#define PORT_MMD_OP_DATA_INCR_RW 2
983#define PORT_MMD_OP_DATA_INCR_W 3
984#define PORT_MMD_DEVICE_ID_M 0x1F
985
986#define MMD_SETUP(mode, dev) \
987 (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
988
989#define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
990
991#define MMD_DEVICE_ID_DSP 1
992
993#define MMD_DSP_SQI_CHAN_A 0xAC
994#define MMD_DSP_SQI_CHAN_B 0xAD
995#define MMD_DSP_SQI_CHAN_C 0xAE
996#define MMD_DSP_SQI_CHAN_D 0xAF
997
998#define DSP_SQI_ERR_DETECTED BIT(15)
999#define DSP_SQI_AVG_ERR 0x7FFF
1000
1001#define MMD_DEVICE_ID_COMMON 2
1002
1003#define MMD_DEVICE_ID_EEE_ADV 7
1004
1005#define MMD_EEE_ADV 0x3C
1006#define EEE_ADV_100MBIT BIT(1)
1007#define EEE_ADV_1GBIT BIT(2)
1008
1009#define MMD_EEE_LP_ADV 0x3D
1010#define MMD_EEE_MSG_CODE 0x3F
1011
1012#define MMD_DEVICE_ID_AFED 0x1C
1013
1014#define REG_PORT_PHY_EXTENDED_STATUS 0x011E
1015
1016#define PORT_100BTX_FD_ABLE BIT(15)
1017#define PORT_100BTX_ABLE BIT(14)
1018#define PORT_10BT_FD_ABLE BIT(13)
1019#define PORT_10BT_ABLE BIT(12)
1020
1021#define REG_PORT_SGMII_ADDR__4 0x0200
1022#define PORT_SGMII_AUTO_INCR BIT(23)
1023#define PORT_SGMII_DEVICE_ID_M 0x1F
1024#define PORT_SGMII_DEVICE_ID_S 16
1025#define PORT_SGMII_ADDR_M (BIT(21) - 1)
1026
1027#define REG_PORT_SGMII_DATA__4 0x0204
1028#define PORT_SGMII_DATA_M (BIT(16) - 1)
1029
1030#define MMD_DEVICE_ID_PMA 0x01
1031#define MMD_DEVICE_ID_PCS 0x03
1032#define MMD_DEVICE_ID_PHY_XS 0x04
1033#define MMD_DEVICE_ID_DTE_XS 0x05
1034#define MMD_DEVICE_ID_AN 0x07
1035#define MMD_DEVICE_ID_VENDOR_CTRL 0x1E
1036#define MMD_DEVICE_ID_VENDOR_MII 0x1F
1037
1038#define SR_MII MMD_DEVICE_ID_VENDOR_MII
1039
1040#define MMD_SR_MII_CTRL 0x0000
1041
1042#define SR_MII_RESET BIT(15)
1043#define SR_MII_LOOPBACK BIT(14)
1044#define SR_MII_SPEED_100MBIT BIT(13)
1045#define SR_MII_AUTO_NEG_ENABLE BIT(12)
1046#define SR_MII_POWER_DOWN BIT(11)
1047#define SR_MII_AUTO_NEG_RESTART BIT(9)
1048#define SR_MII_FULL_DUPLEX BIT(8)
1049#define SR_MII_SPEED_1000MBIT BIT(6)
1050
1051#define MMD_SR_MII_STATUS 0x0001
1052#define MMD_SR_MII_ID_1 0x0002
1053#define MMD_SR_MII_ID_2 0x0003
1054#define MMD_SR_MII_AUTO_NEGOTIATION 0x0004
1055
1056#define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15)
1057#define SR_MII_AUTO_NEG_REMOTE_FAULT_M 0x3
1058#define SR_MII_AUTO_NEG_REMOTE_FAULT_S 12
1059#define SR_MII_AUTO_NEG_NO_ERROR 0
1060#define SR_MII_AUTO_NEG_OFFLINE 1
1061#define SR_MII_AUTO_NEG_LINK_FAILURE 2
1062#define SR_MII_AUTO_NEG_ERROR 3
1063#define SR_MII_AUTO_NEG_PAUSE_M 0x3
1064#define SR_MII_AUTO_NEG_PAUSE_S 7
1065#define SR_MII_AUTO_NEG_NO_PAUSE 0
1066#define SR_MII_AUTO_NEG_ASYM_PAUSE_TX 1
1067#define SR_MII_AUTO_NEG_SYM_PAUSE 2
1068#define SR_MII_AUTO_NEG_ASYM_PAUSE_RX 3
1069#define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6)
1070#define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5)
1071
1072#define MMD_SR_MII_REMOTE_CAPABILITY 0x0005
1073#define MMD_SR_MII_AUTO_NEG_EXP 0x0006
1074#define MMD_SR_MII_AUTO_NEG_EXT 0x000F
1075
1076#define MMD_SR_MII_DIGITAL_CTRL_1 0x8000
1077
1078#define MMD_SR_MII_AUTO_NEG_CTRL 0x8001
1079
1080#define SR_MII_8_BIT BIT(8)
1081#define SR_MII_SGMII_LINK_UP BIT(4)
1082#define SR_MII_TX_CFG_PHY_MASTER BIT(3)
1083#define SR_MII_PCS_MODE_M 0x3
1084#define SR_MII_PCS_MODE_S 1
1085#define SR_MII_PCS_SGMII 2
1086#define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
1087
1088#define MMD_SR_MII_AUTO_NEG_STATUS 0x8002
1089
1090#define SR_MII_STAT_LINK_UP BIT(4)
1091#define SR_MII_STAT_M 0x3
1092#define SR_MII_STAT_S 2
1093#define SR_MII_STAT_10_MBPS 0
1094#define SR_MII_STAT_100_MBPS 1
1095#define SR_MII_STAT_1000_MBPS 2
1096#define SR_MII_STAT_FULL_DUPLEX BIT(1)
1097
1098#define MMD_SR_MII_PHY_CTRL 0x80A0
1099
1100#define SR_MII_PHY_LANE_SEL_M 0xF
1101#define SR_MII_PHY_LANE_SEL_S 8
1102#define SR_MII_PHY_WRITE BIT(1)
1103#define SR_MII_PHY_START_BUSY BIT(0)
1104
1105#define MMD_SR_MII_PHY_ADDR 0x80A1
1106
1107#define SR_MII_PHY_ADDR_M (BIT(16) - 1)
1108
1109#define MMD_SR_MII_PHY_DATA 0x80A2
1110
1111#define SR_MII_PHY_DATA_M (BIT(16) - 1)
1112
1113#define SR_MII_PHY_JTAG_CHIP_ID_HI 0x000C
1114#define SR_MII_PHY_JTAG_CHIP_ID_LO 0x000D
1115
1116#define REG_PORT_PHY_REMOTE_LB_LED 0x0122
1117
1118#define PORT_REMOTE_LOOPBACK BIT(8)
1119#define PORT_LED_SELECT (3 << 6)
1120#define PORT_LED_CTRL (3 << 4)
1121#define PORT_LED_CTRL_TEST BIT(3)
1122#define PORT_10BT_PREAMBLE BIT(2)
1123#define PORT_LINK_MD_10BT_ENABLE BIT(1)
1124#define PORT_LINK_MD_PASS BIT(0)
1125
1126#define REG_PORT_PHY_LINK_MD 0x0124
1127
1128#define PORT_START_CABLE_DIAG BIT(15)
1129#define PORT_TX_DISABLE BIT(14)
1130#define PORT_CABLE_DIAG_PAIR_M 0x3
1131#define PORT_CABLE_DIAG_PAIR_S 12
1132#define PORT_CABLE_DIAG_SELECT_M 0x3
1133#define PORT_CABLE_DIAG_SELECT_S 10
1134#define PORT_CABLE_DIAG_RESULT_M 0x3
1135#define PORT_CABLE_DIAG_RESULT_S 8
1136#define PORT_CABLE_STAT_NORMAL 0
1137#define PORT_CABLE_STAT_OPEN 1
1138#define PORT_CABLE_STAT_SHORT 2
1139#define PORT_CABLE_STAT_FAILED 3
1140#define PORT_CABLE_FAULT_COUNTER 0x00FF
1141
1142#define REG_PORT_PHY_PMA_STATUS 0x0126
1143
1144#define PORT_1000_LINK_GOOD BIT(1)
1145#define PORT_100_LINK_GOOD BIT(0)
1146
1147#define REG_PORT_PHY_DIGITAL_STATUS 0x0128
1148
1149#define PORT_LINK_DETECT BIT(14)
1150#define PORT_SIGNAL_DETECT BIT(13)
1151#define PORT_PHY_STAT_MDI BIT(12)
1152#define PORT_PHY_STAT_MASTER BIT(11)
1153
1154#define REG_PORT_PHY_RXER_COUNTER 0x012A
1155
1156#define REG_PORT_PHY_INT_ENABLE 0x0136
1157#define REG_PORT_PHY_INT_STATUS 0x0137
1158
1159#define JABBER_INT BIT(7)
1160#define RX_ERR_INT BIT(6)
1161#define PAGE_RX_INT BIT(5)
1162#define PARALLEL_DETECT_FAULT_INT BIT(4)
1163#define LINK_PARTNER_ACK_INT BIT(3)
1164#define LINK_DOWN_INT BIT(2)
1165#define REMOTE_FAULT_INT BIT(1)
1166#define LINK_UP_INT BIT(0)
1167
1168#define REG_PORT_PHY_DIGITAL_DEBUG_1 0x0138
1169
1170#define PORT_REG_CLK_SPEED_25_MHZ BIT(14)
1171#define PORT_PHY_FORCE_MDI BIT(7)
1172#define PORT_PHY_AUTO_MDIX_DISABLE BIT(6)
1173
1174/* Same as PORT_PHY_LOOPBACK */
1175#define PORT_PHY_PCS_LOOPBACK BIT(0)
1176
1177#define REG_PORT_PHY_DIGITAL_DEBUG_2 0x013A
1178
1179#define REG_PORT_PHY_DIGITAL_DEBUG_3 0x013C
1180
1181#define PORT_100BT_FIXED_LATENCY BIT(15)
1182
1183#define REG_PORT_PHY_PHY_CTRL 0x013E
1184
1185#define PORT_INT_PIN_HIGH BIT(14)
1186#define PORT_ENABLE_JABBER BIT(9)
1187#define PORT_STAT_SPEED_1000MBIT BIT(6)
1188#define PORT_STAT_SPEED_100MBIT BIT(5)
1189#define PORT_STAT_SPEED_10MBIT BIT(4)
1190#define PORT_STAT_FULL_DUPLEX BIT(3)
1191
1192/* Same as PORT_PHY_STAT_MASTER */
1193#define PORT_STAT_MASTER BIT(2)
1194#define PORT_RESET BIT(1)
1195#define PORT_LINK_STATUS_FAIL BIT(0)
1196
1197/* 3 - xMII */
1198#define REG_PORT_XMII_CTRL_0 0x0300
1199
1200#define PORT_SGMII_SEL BIT(7)
1201#define PORT_MII_FULL_DUPLEX BIT(6)
1202#define PORT_MII_100MBIT BIT(4)
1203#define PORT_GRXC_ENABLE BIT(0)
1204
1205#define REG_PORT_XMII_CTRL_1 0x0301
1206
1207#define PORT_RMII_CLK_SEL BIT(7)
1208/* S1 */
1209#define PORT_MII_1000MBIT_S1 BIT(6)
1210/* S2 */
1211#define PORT_MII_NOT_1GBIT BIT(6)
1212#define PORT_MII_SEL_EDGE BIT(5)
1213#define PORT_RGMII_ID_IG_ENABLE BIT(4)
1214#define PORT_RGMII_ID_EG_ENABLE BIT(3)
1215#define PORT_MII_MAC_MODE BIT(2)
1216#define PORT_MII_SEL_M 0x3
1217/* S1 */
1218#define PORT_MII_SEL_S1 0x0
1219#define PORT_RMII_SEL_S1 0x1
1220#define PORT_GMII_SEL_S1 0x2
1221#define PORT_RGMII_SEL_S1 0x3
1222/* S2 */
1223#define PORT_RGMII_SEL 0x0
1224#define PORT_RMII_SEL 0x1
1225#define PORT_GMII_SEL 0x2
1226#define PORT_MII_SEL 0x3
1227
1228/* 4 - MAC */
1229#define REG_PORT_MAC_CTRL_0 0x0400
1230
1231#define PORT_BROADCAST_STORM BIT(1)
1232#define PORT_JUMBO_FRAME BIT(0)
1233
1234#define REG_PORT_MAC_CTRL_1 0x0401
1235
1236#define PORT_BACK_PRESSURE BIT(3)
1237#define PORT_PASS_ALL BIT(0)
1238
1239#define REG_PORT_MAC_CTRL_2 0x0402
1240
1241#define PORT_100BT_EEE_DISABLE BIT(7)
1242#define PORT_1000BT_EEE_DISABLE BIT(6)
1243
1244#define REG_PORT_MAC_IN_RATE_LIMIT 0x0403
1245
1246#define PORT_IN_PORT_BASED_S 6
1247#define PORT_RATE_PACKET_BASED_S 5
1248#define PORT_IN_FLOW_CTRL_S 4
1249#define PORT_COUNT_IFG_S 1
1250#define PORT_COUNT_PREAMBLE_S 0
1251#define PORT_IN_PORT_BASED BIT(6)
1252#define PORT_IN_PACKET_BASED BIT(5)
1253#define PORT_IN_FLOW_CTRL BIT(4)
1254#define PORT_IN_LIMIT_MODE_M 0x3
1255#define PORT_IN_LIMIT_MODE_S 2
1256#define PORT_IN_ALL 0
1257#define PORT_IN_UNICAST 1
1258#define PORT_IN_MULTICAST 2
1259#define PORT_IN_BROADCAST 3
1260#define PORT_COUNT_IFG BIT(1)
1261#define PORT_COUNT_PREAMBLE BIT(0)
1262
1263#define REG_PORT_IN_RATE_0 0x0410
1264#define REG_PORT_IN_RATE_1 0x0411
1265#define REG_PORT_IN_RATE_2 0x0412
1266#define REG_PORT_IN_RATE_3 0x0413
1267#define REG_PORT_IN_RATE_4 0x0414
1268#define REG_PORT_IN_RATE_5 0x0415
1269#define REG_PORT_IN_RATE_6 0x0416
1270#define REG_PORT_IN_RATE_7 0x0417
1271
1272#define REG_PORT_OUT_RATE_0 0x0420
1273#define REG_PORT_OUT_RATE_1 0x0421
1274#define REG_PORT_OUT_RATE_2 0x0422
1275#define REG_PORT_OUT_RATE_3 0x0423
1276
1277#define PORT_RATE_LIMIT_M (BIT(7) - 1)
1278
1279/* 5 - MIB Counters */
1280#define REG_PORT_MIB_CTRL_STAT__4 0x0500
1281
1282#define MIB_COUNTER_OVERFLOW BIT(31)
1283#define MIB_COUNTER_VALID BIT(30)
1284#define MIB_COUNTER_READ BIT(25)
1285#define MIB_COUNTER_FLUSH_FREEZE BIT(24)
1286#define MIB_COUNTER_INDEX_M (BIT(8) - 1)
1287#define MIB_COUNTER_INDEX_S 16
1288#define MIB_COUNTER_DATA_HI_M 0xF
1289
1290#define REG_PORT_MIB_DATA 0x0504
1291
1292/* 6 - ACL */
1293#define REG_PORT_ACL_0 0x0600
1294
1295#define ACL_FIRST_RULE_M 0xF
1296
1297#define REG_PORT_ACL_1 0x0601
1298
1299#define ACL_MODE_M 0x3
1300#define ACL_MODE_S 4
1301#define ACL_MODE_DISABLE 0
1302#define ACL_MODE_LAYER_2 1
1303#define ACL_MODE_LAYER_3 2
1304#define ACL_MODE_LAYER_4 3
1305#define ACL_ENABLE_M 0x3
1306#define ACL_ENABLE_S 2
1307#define ACL_ENABLE_2_COUNT 0
1308#define ACL_ENABLE_2_TYPE 1
1309#define ACL_ENABLE_2_MAC 2
1310#define ACL_ENABLE_2_BOTH 3
1311#define ACL_ENABLE_3_IP 1
1312#define ACL_ENABLE_3_SRC_DST_COMP 2
1313#define ACL_ENABLE_4_PROTOCOL 0
1314#define ACL_ENABLE_4_TCP_PORT_COMP 1
1315#define ACL_ENABLE_4_UDP_PORT_COMP 2
1316#define ACL_ENABLE_4_TCP_SEQN_COMP 3
1317#define ACL_SRC BIT(1)
1318#define ACL_EQUAL BIT(0)
1319
1320#define REG_PORT_ACL_2 0x0602
1321#define REG_PORT_ACL_3 0x0603
1322
1323#define ACL_MAX_PORT 0xFFFF
1324
1325#define REG_PORT_ACL_4 0x0604
1326#define REG_PORT_ACL_5 0x0605
1327
1328#define ACL_MIN_PORT 0xFFFF
1329#define ACL_IP_ADDR 0xFFFFFFFF
1330#define ACL_TCP_SEQNUM 0xFFFFFFFF
1331
1332#define REG_PORT_ACL_6 0x0606
1333
1334#define ACL_RESERVED 0xF8
1335#define ACL_PORT_MODE_M 0x3
1336#define ACL_PORT_MODE_S 1
1337#define ACL_PORT_MODE_DISABLE 0
1338#define ACL_PORT_MODE_EITHER 1
1339#define ACL_PORT_MODE_IN_RANGE 2
1340#define ACL_PORT_MODE_OUT_OF_RANGE 3
1341
1342#define REG_PORT_ACL_7 0x0607
1343
1344#define ACL_TCP_FLAG_ENABLE BIT(0)
1345
1346#define REG_PORT_ACL_8 0x0608
1347
1348#define ACL_TCP_FLAG_M 0xFF
1349
1350#define REG_PORT_ACL_9 0x0609
1351
1352#define ACL_TCP_FLAG 0xFF
1353#define ACL_ETH_TYPE 0xFFFF
1354#define ACL_IP_M 0xFFFFFFFF
1355
1356#define REG_PORT_ACL_A 0x060A
1357
1358#define ACL_PRIO_MODE_M 0x3
1359#define ACL_PRIO_MODE_S 6
1360#define ACL_PRIO_MODE_DISABLE 0
1361#define ACL_PRIO_MODE_HIGHER 1
1362#define ACL_PRIO_MODE_LOWER 2
1363#define ACL_PRIO_MODE_REPLACE 3
1364#define ACL_PRIO_M KS_PRIO_M
1365#define ACL_PRIO_S 3
1366#define ACL_VLAN_PRIO_REPLACE BIT(2)
1367#define ACL_VLAN_PRIO_M KS_PRIO_M
1368#define ACL_VLAN_PRIO_HI_M 0x3
1369
1370#define REG_PORT_ACL_B 0x060B
1371
1372#define ACL_VLAN_PRIO_LO_M 0x8
1373#define ACL_VLAN_PRIO_S 7
1374#define ACL_MAP_MODE_M 0x3
1375#define ACL_MAP_MODE_S 5
1376#define ACL_MAP_MODE_DISABLE 0
1377#define ACL_MAP_MODE_OR 1
1378#define ACL_MAP_MODE_AND 2
1379#define ACL_MAP_MODE_REPLACE 3
1380
1381#define ACL_CNT_M (BIT(11) - 1)
1382#define ACL_CNT_S 5
1383
1384#define REG_PORT_ACL_C 0x060C
1385
1386#define REG_PORT_ACL_D 0x060D
1387#define ACL_MSEC_UNIT BIT(6)
1388#define ACL_INTR_MODE BIT(5)
1389#define ACL_PORT_MAP 0x7F
1390
1391#define REG_PORT_ACL_E 0x060E
1392#define REG_PORT_ACL_F 0x060F
1393
1394#define REG_PORT_ACL_BYTE_EN_MSB 0x0610
1395#define REG_PORT_ACL_BYTE_EN_LSB 0x0611
1396
1397#define ACL_ACTION_START 0xA
1398#define ACL_ACTION_LEN 4
1399#define ACL_INTR_CNT_START 0xD
1400#define ACL_RULESET_START 0xE
1401#define ACL_RULESET_LEN 2
1402#define ACL_TABLE_LEN 16
1403
1404#define ACL_ACTION_ENABLE 0x003C
1405#define ACL_MATCH_ENABLE 0x7FC3
1406#define ACL_RULESET_ENABLE 0x8003
1407#define ACL_BYTE_ENABLE 0xFFFF
1408
1409#define REG_PORT_ACL_CTRL_0 0x0612
1410
1411#define PORT_ACL_WRITE_DONE BIT(6)
1412#define PORT_ACL_READ_DONE BIT(5)
1413#define PORT_ACL_WRITE BIT(4)
1414#define PORT_ACL_INDEX_M 0xF
1415
1416#define REG_PORT_ACL_CTRL_1 0x0613
1417
1418/* 8 - Classification and Policing */
1419#define REG_PORT_MRI_MIRROR_CTRL 0x0800
1420
1421#define PORT_MIRROR_RX BIT(6)
1422#define PORT_MIRROR_TX BIT(5)
1423#define PORT_MIRROR_SNIFFER BIT(1)
1424
1425#define REG_PORT_MRI_PRIO_CTRL 0x0801
1426
1427#define PORT_HIGHEST_PRIO BIT(7)
1428#define PORT_OR_PRIO BIT(6)
1429#define PORT_MAC_PRIO_ENABLE BIT(4)
1430#define PORT_VLAN_PRIO_ENABLE BIT(3)
1431#define PORT_802_1P_PRIO_ENABLE BIT(2)
1432#define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
1433#define PORT_ACL_PRIO_ENABLE BIT(0)
1434
1435#define REG_PORT_MRI_MAC_CTRL 0x0802
1436
1437#define PORT_USER_PRIO_CEILING BIT(7)
1438#define PORT_DROP_NON_VLAN BIT(4)
1439#define PORT_DROP_TAG BIT(3)
1440#define PORT_BASED_PRIO_M KS_PRIO_M
1441#define PORT_BASED_PRIO_S 0
1442
1443#define REG_PORT_MRI_AUTHEN_CTRL 0x0803
1444
1445#define PORT_ACL_ENABLE BIT(2)
1446#define PORT_AUTHEN_MODE 0x3
1447#define PORT_AUTHEN_PASS 0
1448#define PORT_AUTHEN_BLOCK 1
1449#define PORT_AUTHEN_TRAP 2
1450
1451#define REG_PORT_MRI_INDEX__4 0x0804
1452
1453#define MRI_INDEX_P_M 0x7
1454#define MRI_INDEX_P_S 16
1455#define MRI_INDEX_Q_M 0x3
1456#define MRI_INDEX_Q_S 0
1457
1458#define REG_PORT_MRI_TC_MAP__4 0x0808
1459
1460#define PORT_TC_MAP_M 0xf
1461#define PORT_TC_MAP_S 4
1462
1463#define REG_PORT_MRI_POLICE_CTRL__4 0x080C
1464
1465#define POLICE_DROP_ALL BIT(10)
1466#define POLICE_PACKET_TYPE_M 0x3
1467#define POLICE_PACKET_TYPE_S 8
1468#define POLICE_PACKET_DROPPED 0
1469#define POLICE_PACKET_GREEN 1
1470#define POLICE_PACKET_YELLOW 2
1471#define POLICE_PACKET_RED 3
1472#define PORT_BASED_POLICING BIT(7)
1473#define NON_DSCP_COLOR_M 0x3
1474#define NON_DSCP_COLOR_S 5
1475#define COLOR_MARK_ENABLE BIT(4)
1476#define COLOR_REMAP_ENABLE BIT(3)
1477#define POLICE_DROP_SRP BIT(2)
1478#define POLICE_COLOR_NOT_AWARE BIT(1)
1479#define POLICE_ENABLE BIT(0)
1480
1481#define REG_PORT_POLICE_COLOR_0__4 0x0810
1482#define REG_PORT_POLICE_COLOR_1__4 0x0814
1483#define REG_PORT_POLICE_COLOR_2__4 0x0818
1484#define REG_PORT_POLICE_COLOR_3__4 0x081C
1485
1486#define POLICE_COLOR_MAP_S 2
1487#define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1)
1488
1489#define REG_PORT_POLICE_RATE__4 0x0820
1490
1491#define POLICE_CIR_S 16
1492#define POLICE_PIR_S 0
1493
1494#define REG_PORT_POLICE_BURST_SIZE__4 0x0824
1495
1496#define POLICE_BURST_SIZE_M 0x3FFF
1497#define POLICE_CBS_S 16
1498#define POLICE_PBS_S 0
1499
1500#define REG_PORT_WRED_PM_CTRL_0__4 0x0830
1501
1502#define WRED_PM_CTRL_M (BIT(11) - 1)
1503
1504#define WRED_PM_MAX_THRESHOLD_S 16
1505#define WRED_PM_MIN_THRESHOLD_S 0
1506
1507#define REG_PORT_WRED_PM_CTRL_1__4 0x0834
1508
1509#define WRED_PM_MULTIPLIER_S 16
1510#define WRED_PM_AVG_QUEUE_SIZE_S 0
1511
1512#define REG_PORT_WRED_QUEUE_CTRL_0__4 0x0840
1513#define REG_PORT_WRED_QUEUE_CTRL_1__4 0x0844
1514
1515#define REG_PORT_WRED_QUEUE_PMON__4 0x0848
1516
1517#define WRED_RANDOM_DROP_ENABLE BIT(31)
1518#define WRED_PMON_FLUSH BIT(30)
1519#define WRED_DROP_GYR_DISABLE BIT(29)
1520#define WRED_DROP_YR_DISABLE BIT(28)
1521#define WRED_DROP_R_DISABLE BIT(27)
1522#define WRED_DROP_ALL BIT(26)
1523#define WRED_PMON_M (BIT(24) - 1)
1524
1525/* 9 - Shaping */
1526
1527#define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
1528
1529#define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904
1530
1531#define MTI_PVID_REPLACE BIT(0)
1532
1533#define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
1534
1535#define MTI_SCHEDULE_MODE_M 0x3
1536#define MTI_SCHEDULE_MODE_S 6
1537#define MTI_SCHEDULE_STRICT_PRIO 0
1538#define MTI_SCHEDULE_WRR 2
1539#define MTI_SHAPING_M 0x3
1540#define MTI_SHAPING_S 4
1541#define MTI_SHAPING_OFF 0
1542#define MTI_SHAPING_SRP 1
1543#define MTI_SHAPING_TIME_AWARE 2
1544
1545#define REG_PORT_MTI_QUEUE_CTRL_1 0x0915
1546
1547#define MTI_TX_RATIO_M (BIT(7) - 1)
1548
1549#define REG_PORT_MTI_QUEUE_CTRL_2__2 0x0916
1550#define REG_PORT_MTI_HI_WATER_MARK 0x0916
1551#define REG_PORT_MTI_QUEUE_CTRL_3__2 0x0918
1552#define REG_PORT_MTI_LO_WATER_MARK 0x0918
1553#define REG_PORT_MTI_QUEUE_CTRL_4__2 0x091A
1554#define REG_PORT_MTI_CREDIT_INCREMENT 0x091A
1555
1556/* A - QM */
1557
1558#define REG_PORT_QM_CTRL__4 0x0A00
1559
1560#define PORT_QM_DROP_PRIO_M 0x3
1561
1562#define REG_PORT_VLAN_MEMBERSHIP__4 0x0A04
1563
1564#define REG_PORT_QM_QUEUE_INDEX__4 0x0A08
1565
1566#define PORT_QM_QUEUE_INDEX_S 24
1567#define PORT_QM_BURST_SIZE_S 16
1568#define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1)
1569
1570#define REG_PORT_QM_WATER_MARK__4 0x0A0C
1571
1572#define PORT_QM_HI_WATER_MARK_S 16
1573#define PORT_QM_LO_WATER_MARK_S 0
1574#define PORT_QM_WATER_MARK_M (BIT(11) - 1)
1575
1576#define REG_PORT_QM_TX_CNT_0__4 0x0A10
1577
1578#define PORT_QM_TX_CNT_USED_S 0
1579#define PORT_QM_TX_CNT_M (BIT(11) - 1)
1580
1581#define REG_PORT_QM_TX_CNT_1__4 0x0A14
1582
1583#define PORT_QM_TX_CNT_CALCULATED_S 16
1584#define PORT_QM_TX_CNT_AVAIL_S 0
1585
1586/* B - LUE */
1587#define REG_PORT_LUE_CTRL 0x0B00
1588
1589#define PORT_VLAN_LOOKUP_VID_0 BIT(7)
1590#define PORT_INGRESS_FILTER BIT(6)
1591#define PORT_DISCARD_NON_VID BIT(5)
1592#define PORT_MAC_BASED_802_1X BIT(4)
1593#define PORT_SRC_ADDR_FILTER BIT(3)
1594
1595#define REG_PORT_LUE_MSTP_INDEX 0x0B01
1596
1597#define REG_PORT_LUE_MSTP_STATE 0x0B04
1598
1599#define PORT_TX_ENABLE BIT(2)
1600#define PORT_RX_ENABLE BIT(1)
1601#define PORT_LEARN_DISABLE BIT(0)
1602
1603/* C - PTP */
1604
1605#define REG_PTP_PORT_RX_DELAY__2 0x0C00
1606#define REG_PTP_PORT_TX_DELAY__2 0x0C02
1607#define REG_PTP_PORT_ASYM_DELAY__2 0x0C04
1608
1609#define REG_PTP_PORT_XDELAY_TS 0x0C08
1610#define REG_PTP_PORT_XDELAY_TS_H 0x0C08
1611#define REG_PTP_PORT_XDELAY_TS_L 0x0C0A
1612
1613#define REG_PTP_PORT_SYNC_TS 0x0C0C
1614#define REG_PTP_PORT_SYNC_TS_H 0x0C0C
1615#define REG_PTP_PORT_SYNC_TS_L 0x0C0E
1616
1617#define REG_PTP_PORT_PDRESP_TS 0x0C10
1618#define REG_PTP_PORT_PDRESP_TS_H 0x0C10
1619#define REG_PTP_PORT_PDRESP_TS_L 0x0C12
1620
1621#define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14
1622#define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16
1623
1624#define PTP_PORT_SYNC_INT BIT(15)
1625#define PTP_PORT_XDELAY_REQ_INT BIT(14)
1626#define PTP_PORT_PDELAY_RESP_INT BIT(13)
1627
1628#define REG_PTP_PORT_LINK_DELAY__4 0x0C18
1629
1630#define PRIO_QUEUES 4
1631#define RX_PRIO_QUEUES 8
1632
1633#define KS_PRIO_IN_REG 2
1634
1635#define TOTAL_PORT_NUM 7
1636
1637#define KSZ9477_COUNTER_NUM 0x20
1638#define TOTAL_KSZ9477_COUNTER_NUM (KSZ9477_COUNTER_NUM + 2 + 2)
1639
1640#define SWITCH_COUNTER_NUM KSZ9477_COUNTER_NUM
1641#define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ9477_COUNTER_NUM
1642
1643#define P_BCAST_STORM_CTRL REG_PORT_MAC_CTRL_0
1644#define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL
1645#define P_MIRROR_CTRL REG_PORT_MRI_MIRROR_CTRL
1646#define P_STP_CTRL REG_PORT_LUE_MSTP_STATE
1647#define P_PHY_CTRL REG_PORT_PHY_CTRL
1648#define P_NEG_RESTART_CTRL REG_PORT_PHY_CTRL
1649#define P_LINK_STATUS REG_PORT_PHY_STATUS
1650#define P_SPEED_STATUS REG_PORT_PHY_PHY_CTRL
1651#define P_RATE_LIMIT_CTRL REG_PORT_MAC_IN_RATE_LIMIT
1652
1653#define S_LINK_AGING_CTRL REG_SW_LUE_CTRL_1
1654#define S_MIRROR_CTRL REG_SW_MRI_CTRL_0
1655#define S_REPLACE_VID_CTRL REG_SW_MAC_CTRL_2
1656#define S_802_1P_PRIO_CTRL REG_SW_MAC_802_1P_MAP_0
1657#define S_TOS_PRIO_CTRL REG_SW_MAC_TOS_PRIO_0
1658#define S_FLUSH_TABLE_CTRL REG_SW_LUE_CTRL_1
1659
1660#define SW_FLUSH_DYN_MAC_TABLE SW_FLUSH_MSTP_TABLE
1661
1662#define MAX_TIMESTAMP_UNIT 2
1663#define MAX_TRIG_UNIT 3
1664#define MAX_TIMESTAMP_EVENT_UNIT 8
1665#define MAX_GPIO 4
1666
1667#define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1)
1668#define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1)
1669
1670/* Driver set switch broadcast storm protection at 10% rate. */
1671#define BROADCAST_STORM_PROT_RATE 10
1672
1673/* 148,800 frames * 67 ms / 100 */
1674#define BROADCAST_STORM_VALUE 9969
1675
1676#endif /* KSZ9477_REGS_H */