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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/of.h>
7#include <linux/mm.h>
8
9#include <dt-bindings/memory/tegra114-mc.h>
10
11#include "mc.h"
12
13static const struct tegra_mc_client tegra114_mc_clients[] = {
14 {
15 .id = 0x00,
16 .name = "ptcr",
17 .swgroup = TEGRA_SWGROUP_PTC,
18 .regs = {
19 .la = {
20 .reg = 0x34c,
21 .shift = 0,
22 .mask = 0xff,
23 .def = 0x0,
24 },
25 },
26 }, {
27 .id = 0x01,
28 .name = "display0a",
29 .swgroup = TEGRA_SWGROUP_DC,
30 .regs = {
31 .smmu = {
32 .reg = 0x228,
33 .bit = 1,
34 },
35 .la = {
36 .reg = 0x2e8,
37 .shift = 0,
38 .mask = 0xff,
39 .def = 0x4e,
40 },
41 },
42 }, {
43 .id = 0x02,
44 .name = "display0ab",
45 .swgroup = TEGRA_SWGROUP_DCB,
46 .regs = {
47 .smmu = {
48 .reg = 0x228,
49 .bit = 2,
50 },
51 .la = {
52 .reg = 0x2f4,
53 .shift = 0,
54 .mask = 0xff,
55 .def = 0x4e,
56 },
57 },
58 }, {
59 .id = 0x03,
60 .name = "display0b",
61 .swgroup = TEGRA_SWGROUP_DC,
62 .regs = {
63 .smmu = {
64 .reg = 0x228,
65 .bit = 3,
66 },
67 .la = {
68 .reg = 0x2e8,
69 .shift = 16,
70 .mask = 0xff,
71 .def = 0x4e,
72 },
73 },
74 }, {
75 .id = 0x04,
76 .name = "display0bb",
77 .swgroup = TEGRA_SWGROUP_DCB,
78 .regs = {
79 .smmu = {
80 .reg = 0x228,
81 .bit = 4,
82 },
83 .la = {
84 .reg = 0x2f4,
85 .shift = 16,
86 .mask = 0xff,
87 .def = 0x4e,
88 },
89 },
90 }, {
91 .id = 0x05,
92 .name = "display0c",
93 .swgroup = TEGRA_SWGROUP_DC,
94 .regs = {
95 .smmu = {
96 .reg = 0x228,
97 .bit = 5,
98 },
99 .la = {
100 .reg = 0x2ec,
101 .shift = 0,
102 .mask = 0xff,
103 .def = 0x4e,
104 },
105 },
106 }, {
107 .id = 0x06,
108 .name = "display0cb",
109 .swgroup = TEGRA_SWGROUP_DCB,
110 .regs = {
111 .smmu = {
112 .reg = 0x228,
113 .bit = 6,
114 },
115 .la = {
116 .reg = 0x2f8,
117 .shift = 0,
118 .mask = 0xff,
119 .def = 0x4e,
120 },
121 },
122 }, {
123 .id = 0x09,
124 .name = "eppup",
125 .swgroup = TEGRA_SWGROUP_EPP,
126 .regs = {
127 .smmu = {
128 .reg = 0x228,
129 .bit = 9,
130 },
131 .la = {
132 .reg = 0x300,
133 .shift = 0,
134 .mask = 0xff,
135 .def = 0x33,
136 },
137 },
138 }, {
139 .id = 0x0a,
140 .name = "g2pr",
141 .swgroup = TEGRA_SWGROUP_G2,
142 .regs = {
143 .smmu = {
144 .reg = 0x228,
145 .bit = 10,
146 },
147 .la = {
148 .reg = 0x308,
149 .shift = 0,
150 .mask = 0xff,
151 .def = 0x09,
152 },
153 },
154 }, {
155 .id = 0x0b,
156 .name = "g2sr",
157 .swgroup = TEGRA_SWGROUP_G2,
158 .regs = {
159 .smmu = {
160 .reg = 0x228,
161 .bit = 11,
162 },
163 .la = {
164 .reg = 0x308,
165 .shift = 16,
166 .mask = 0xff,
167 .def = 0x09,
168 },
169 },
170 }, {
171 .id = 0x0f,
172 .name = "avpcarm7r",
173 .swgroup = TEGRA_SWGROUP_AVPC,
174 .regs = {
175 .smmu = {
176 .reg = 0x228,
177 .bit = 15,
178 },
179 .la = {
180 .reg = 0x2e4,
181 .shift = 0,
182 .mask = 0xff,
183 .def = 0x04,
184 },
185 },
186 }, {
187 .id = 0x10,
188 .name = "displayhc",
189 .swgroup = TEGRA_SWGROUP_DC,
190 .regs = {
191 .smmu = {
192 .reg = 0x228,
193 .bit = 16,
194 },
195 .la = {
196 .reg = 0x2f0,
197 .shift = 0,
198 .mask = 0xff,
199 .def = 0x68,
200 },
201 },
202 }, {
203 .id = 0x11,
204 .name = "displayhcb",
205 .swgroup = TEGRA_SWGROUP_DCB,
206 .regs = {
207 .smmu = {
208 .reg = 0x228,
209 .bit = 17,
210 },
211 .la = {
212 .reg = 0x2fc,
213 .shift = 0,
214 .mask = 0xff,
215 .def = 0x68,
216 },
217 },
218 }, {
219 .id = 0x12,
220 .name = "fdcdrd",
221 .swgroup = TEGRA_SWGROUP_NV,
222 .regs = {
223 .smmu = {
224 .reg = 0x228,
225 .bit = 18,
226 },
227 .la = {
228 .reg = 0x334,
229 .shift = 0,
230 .mask = 0xff,
231 .def = 0x0c,
232 },
233 },
234 }, {
235 .id = 0x13,
236 .name = "fdcdrd2",
237 .swgroup = TEGRA_SWGROUP_NV,
238 .regs = {
239 .smmu = {
240 .reg = 0x228,
241 .bit = 19,
242 },
243 .la = {
244 .reg = 0x33c,
245 .shift = 0,
246 .mask = 0xff,
247 .def = 0x0c,
248 },
249 },
250 }, {
251 .id = 0x14,
252 .name = "g2dr",
253 .swgroup = TEGRA_SWGROUP_G2,
254 .regs = {
255 .smmu = {
256 .reg = 0x228,
257 .bit = 20,
258 },
259 .la = {
260 .reg = 0x30c,
261 .shift = 0,
262 .mask = 0xff,
263 .def = 0x0a,
264 },
265 },
266 }, {
267 .id = 0x15,
268 .name = "hdar",
269 .swgroup = TEGRA_SWGROUP_HDA,
270 .regs = {
271 .smmu = {
272 .reg = 0x228,
273 .bit = 21,
274 },
275 .la = {
276 .reg = 0x318,
277 .shift = 0,
278 .mask = 0xff,
279 .def = 0xff,
280 },
281 },
282 }, {
283 .id = 0x16,
284 .name = "host1xdmar",
285 .swgroup = TEGRA_SWGROUP_HC,
286 .regs = {
287 .smmu = {
288 .reg = 0x228,
289 .bit = 22,
290 },
291 .la = {
292 .reg = 0x310,
293 .shift = 0,
294 .mask = 0xff,
295 .def = 0x10,
296 },
297 },
298 }, {
299 .id = 0x17,
300 .name = "host1xr",
301 .swgroup = TEGRA_SWGROUP_HC,
302 .regs = {
303 .smmu = {
304 .reg = 0x228,
305 .bit = 23,
306 },
307 .la = {
308 .reg = 0x310,
309 .shift = 16,
310 .mask = 0xff,
311 .def = 0xa5,
312 },
313 },
314 }, {
315 .id = 0x18,
316 .name = "idxsrd",
317 .swgroup = TEGRA_SWGROUP_NV,
318 .regs = {
319 .smmu = {
320 .reg = 0x228,
321 .bit = 24,
322 },
323 .la = {
324 .reg = 0x334,
325 .shift = 16,
326 .mask = 0xff,
327 .def = 0x0b,
328 },
329 },
330 }, {
331 .id = 0x1c,
332 .name = "msencsrd",
333 .swgroup = TEGRA_SWGROUP_MSENC,
334 .regs = {
335 .smmu = {
336 .reg = 0x228,
337 .bit = 28,
338 },
339 .la = {
340 .reg = 0x328,
341 .shift = 0,
342 .mask = 0xff,
343 .def = 0x80,
344 },
345 },
346 }, {
347 .id = 0x1d,
348 .name = "ppcsahbdmar",
349 .swgroup = TEGRA_SWGROUP_PPCS,
350 .regs = {
351 .smmu = {
352 .reg = 0x228,
353 .bit = 29,
354 },
355 .la = {
356 .reg = 0x344,
357 .shift = 0,
358 .mask = 0xff,
359 .def = 0x50,
360 },
361 },
362 }, {
363 .id = 0x1e,
364 .name = "ppcsahbslvr",
365 .swgroup = TEGRA_SWGROUP_PPCS,
366 .regs = {
367 .smmu = {
368 .reg = 0x228,
369 .bit = 30,
370 },
371 .la = {
372 .reg = 0x344,
373 .shift = 16,
374 .mask = 0xff,
375 .def = 0xe8,
376 },
377 },
378 }, {
379 .id = 0x20,
380 .name = "texl2srd",
381 .swgroup = TEGRA_SWGROUP_NV,
382 .regs = {
383 .smmu = {
384 .reg = 0x22c,
385 .bit = 0,
386 },
387 .la = {
388 .reg = 0x338,
389 .shift = 0,
390 .mask = 0xff,
391 .def = 0x0c,
392 },
393 },
394 }, {
395 .id = 0x22,
396 .name = "vdebsevr",
397 .swgroup = TEGRA_SWGROUP_VDE,
398 .regs = {
399 .smmu = {
400 .reg = 0x22c,
401 .bit = 2,
402 },
403 .la = {
404 .reg = 0x354,
405 .shift = 0,
406 .mask = 0xff,
407 .def = 0xff,
408 },
409 },
410 }, {
411 .id = 0x23,
412 .name = "vdember",
413 .swgroup = TEGRA_SWGROUP_VDE,
414 .regs = {
415 .smmu = {
416 .reg = 0x22c,
417 .bit = 3,
418 },
419 .la = {
420 .reg = 0x354,
421 .shift = 16,
422 .mask = 0xff,
423 .def = 0xff,
424 },
425 },
426 }, {
427 .id = 0x24,
428 .name = "vdemcer",
429 .swgroup = TEGRA_SWGROUP_VDE,
430 .regs = {
431 .smmu = {
432 .reg = 0x22c,
433 .bit = 4,
434 },
435 .la = {
436 .reg = 0x358,
437 .shift = 0,
438 .mask = 0xff,
439 .def = 0xb8,
440 },
441 },
442 }, {
443 .id = 0x25,
444 .name = "vdetper",
445 .swgroup = TEGRA_SWGROUP_VDE,
446 .regs = {
447 .smmu = {
448 .reg = 0x22c,
449 .bit = 5,
450 },
451 .la = {
452 .reg = 0x358,
453 .shift = 16,
454 .mask = 0xff,
455 .def = 0xee,
456 },
457 },
458 }, {
459 .id = 0x26,
460 .name = "mpcorelpr",
461 .swgroup = TEGRA_SWGROUP_MPCORELP,
462 .regs = {
463 .la = {
464 .reg = 0x324,
465 .shift = 0,
466 .mask = 0xff,
467 .def = 0x04,
468 },
469 },
470 }, {
471 .id = 0x27,
472 .name = "mpcorer",
473 .swgroup = TEGRA_SWGROUP_MPCORE,
474 .regs = {
475 .la = {
476 .reg = 0x320,
477 .shift = 0,
478 .mask = 0xff,
479 .def = 0x04,
480 },
481 },
482 }, {
483 .id = 0x28,
484 .name = "eppu",
485 .swgroup = TEGRA_SWGROUP_EPP,
486 .regs = {
487 .smmu = {
488 .reg = 0x22c,
489 .bit = 8,
490 },
491 .la = {
492 .reg = 0x300,
493 .shift = 16,
494 .mask = 0xff,
495 .def = 0x33,
496 },
497 },
498 }, {
499 .id = 0x29,
500 .name = "eppv",
501 .swgroup = TEGRA_SWGROUP_EPP,
502 .regs = {
503 .smmu = {
504 .reg = 0x22c,
505 .bit = 9,
506 },
507 .la = {
508 .reg = 0x304,
509 .shift = 0,
510 .mask = 0xff,
511 .def = 0x6c,
512 },
513 },
514 }, {
515 .id = 0x2a,
516 .name = "eppy",
517 .swgroup = TEGRA_SWGROUP_EPP,
518 .regs = {
519 .smmu = {
520 .reg = 0x22c,
521 .bit = 10,
522 },
523 .la = {
524 .reg = 0x304,
525 .shift = 16,
526 .mask = 0xff,
527 .def = 0x6c,
528 },
529 },
530 }, {
531 .id = 0x2b,
532 .name = "msencswr",
533 .swgroup = TEGRA_SWGROUP_MSENC,
534 .regs = {
535 .smmu = {
536 .reg = 0x22c,
537 .bit = 11,
538 },
539 .la = {
540 .reg = 0x328,
541 .shift = 16,
542 .mask = 0xff,
543 .def = 0x80,
544 },
545 },
546 }, {
547 .id = 0x2c,
548 .name = "viwsb",
549 .swgroup = TEGRA_SWGROUP_VI,
550 .regs = {
551 .smmu = {
552 .reg = 0x22c,
553 .bit = 12,
554 },
555 .la = {
556 .reg = 0x364,
557 .shift = 0,
558 .mask = 0xff,
559 .def = 0x47,
560 },
561 },
562 }, {
563 .id = 0x2d,
564 .name = "viwu",
565 .swgroup = TEGRA_SWGROUP_VI,
566 .regs = {
567 .smmu = {
568 .reg = 0x22c,
569 .bit = 13,
570 },
571 .la = {
572 .reg = 0x368,
573 .shift = 0,
574 .mask = 0xff,
575 .def = 0xff,
576 },
577 },
578 }, {
579 .id = 0x2e,
580 .name = "viwv",
581 .swgroup = TEGRA_SWGROUP_VI,
582 .regs = {
583 .smmu = {
584 .reg = 0x22c,
585 .bit = 14,
586 },
587 .la = {
588 .reg = 0x368,
589 .shift = 16,
590 .mask = 0xff,
591 .def = 0xff,
592 },
593 },
594 }, {
595 .id = 0x2f,
596 .name = "viwy",
597 .swgroup = TEGRA_SWGROUP_VI,
598 .regs = {
599 .smmu = {
600 .reg = 0x22c,
601 .bit = 15,
602 },
603 .la = {
604 .reg = 0x36c,
605 .shift = 0,
606 .mask = 0xff,
607 .def = 0x47,
608 },
609 },
610 }, {
611 .id = 0x30,
612 .name = "g2dw",
613 .swgroup = TEGRA_SWGROUP_G2,
614 .regs = {
615 .smmu = {
616 .reg = 0x22c,
617 .bit = 16,
618 },
619 .la = {
620 .reg = 0x30c,
621 .shift = 16,
622 .mask = 0xff,
623 .def = 0x9,
624 },
625 },
626 }, {
627 .id = 0x32,
628 .name = "avpcarm7w",
629 .swgroup = TEGRA_SWGROUP_AVPC,
630 .regs = {
631 .smmu = {
632 .reg = 0x22c,
633 .bit = 18,
634 },
635 .la = {
636 .reg = 0x2e4,
637 .shift = 16,
638 .mask = 0xff,
639 .def = 0x0e,
640 },
641 },
642 }, {
643 .id = 0x33,
644 .name = "fdcdwr",
645 .swgroup = TEGRA_SWGROUP_NV,
646 .regs = {
647 .smmu = {
648 .reg = 0x22c,
649 .bit = 19,
650 },
651 .la = {
652 .reg = 0x338,
653 .shift = 16,
654 .mask = 0xff,
655 .def = 0x10,
656 },
657 },
658 }, {
659 .id = 0x34,
660 .name = "fdcdwr2",
661 .swgroup = TEGRA_SWGROUP_NV,
662 .regs = {
663 .smmu = {
664 .reg = 0x22c,
665 .bit = 20,
666 },
667 .la = {
668 .reg = 0x340,
669 .shift = 0,
670 .mask = 0xff,
671 .def = 0x10,
672 },
673 },
674 }, {
675 .id = 0x35,
676 .name = "hdaw",
677 .swgroup = TEGRA_SWGROUP_HDA,
678 .regs = {
679 .smmu = {
680 .reg = 0x22c,
681 .bit = 21,
682 },
683 .la = {
684 .reg = 0x318,
685 .shift = 16,
686 .mask = 0xff,
687 .def = 0xff,
688 },
689 },
690 }, {
691 .id = 0x36,
692 .name = "host1xw",
693 .swgroup = TEGRA_SWGROUP_HC,
694 .regs = {
695 .smmu = {
696 .reg = 0x22c,
697 .bit = 22,
698 },
699 .la = {
700 .reg = 0x314,
701 .shift = 0,
702 .mask = 0xff,
703 .def = 0x25,
704 },
705 },
706 }, {
707 .id = 0x37,
708 .name = "ispw",
709 .swgroup = TEGRA_SWGROUP_ISP,
710 .regs = {
711 .smmu = {
712 .reg = 0x22c,
713 .bit = 23,
714 },
715 .la = {
716 .reg = 0x31c,
717 .shift = 0,
718 .mask = 0xff,
719 .def = 0xff,
720 },
721 },
722 }, {
723 .id = 0x38,
724 .name = "mpcorelpw",
725 .swgroup = TEGRA_SWGROUP_MPCORELP,
726 .regs = {
727 .la = {
728 .reg = 0x324,
729 .shift = 16,
730 .mask = 0xff,
731 .def = 0x80,
732 },
733 },
734 }, {
735 .id = 0x39,
736 .name = "mpcorew",
737 .swgroup = TEGRA_SWGROUP_MPCORE,
738 .regs = {
739 .la = {
740 .reg = 0x320,
741 .shift = 16,
742 .mask = 0xff,
743 .def = 0x0e,
744 },
745 },
746 }, {
747 .id = 0x3b,
748 .name = "ppcsahbdmaw",
749 .swgroup = TEGRA_SWGROUP_PPCS,
750 .regs = {
751 .smmu = {
752 .reg = 0x22c,
753 .bit = 27,
754 },
755 .la = {
756 .reg = 0x348,
757 .shift = 0,
758 .mask = 0xff,
759 .def = 0xa5,
760 },
761 },
762 }, {
763 .id = 0x3c,
764 .name = "ppcsahbslvw",
765 .swgroup = TEGRA_SWGROUP_PPCS,
766 .regs = {
767 .smmu = {
768 .reg = 0x22c,
769 .bit = 28,
770 },
771 .la = {
772 .reg = 0x348,
773 .shift = 16,
774 .mask = 0xff,
775 .def = 0xe8,
776 },
777 },
778 }, {
779 .id = 0x3e,
780 .name = "vdebsevw",
781 .swgroup = TEGRA_SWGROUP_VDE,
782 .regs = {
783 .smmu = {
784 .reg = 0x22c,
785 .bit = 30,
786 },
787 .la = {
788 .reg = 0x35c,
789 .shift = 0,
790 .mask = 0xff,
791 .def = 0xff,
792 },
793 },
794 }, {
795 .id = 0x3f,
796 .name = "vdedbgw",
797 .swgroup = TEGRA_SWGROUP_VDE,
798 .regs = {
799 .smmu = {
800 .reg = 0x22c,
801 .bit = 31,
802 },
803 .la = {
804 .reg = 0x35c,
805 .shift = 16,
806 .mask = 0xff,
807 .def = 0xff,
808 },
809 },
810 }, {
811 .id = 0x40,
812 .name = "vdembew",
813 .swgroup = TEGRA_SWGROUP_VDE,
814 .regs = {
815 .smmu = {
816 .reg = 0x230,
817 .bit = 0,
818 },
819 .la = {
820 .reg = 0x360,
821 .shift = 0,
822 .mask = 0xff,
823 .def = 0x89,
824 },
825 },
826 }, {
827 .id = 0x41,
828 .name = "vdetpmw",
829 .swgroup = TEGRA_SWGROUP_VDE,
830 .regs = {
831 .smmu = {
832 .reg = 0x230,
833 .bit = 1,
834 },
835 .la = {
836 .reg = 0x360,
837 .shift = 16,
838 .mask = 0xff,
839 .def = 0x59,
840 },
841 },
842 }, {
843 .id = 0x4a,
844 .name = "xusb_hostr",
845 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
846 .regs = {
847 .smmu = {
848 .reg = 0x230,
849 .bit = 10,
850 },
851 .la = {
852 .reg = 0x37c,
853 .shift = 0,
854 .mask = 0xff,
855 .def = 0xa5,
856 },
857 },
858 }, {
859 .id = 0x4b,
860 .name = "xusb_hostw",
861 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
862 .regs = {
863 .smmu = {
864 .reg = 0x230,
865 .bit = 11,
866 },
867 .la = {
868 .reg = 0x37c,
869 .shift = 16,
870 .mask = 0xff,
871 .def = 0xa5,
872 },
873 },
874 }, {
875 .id = 0x4c,
876 .name = "xusb_devr",
877 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
878 .regs = {
879 .smmu = {
880 .reg = 0x230,
881 .bit = 12,
882 },
883 .la = {
884 .reg = 0x380,
885 .shift = 0,
886 .mask = 0xff,
887 .def = 0xa5,
888 },
889 },
890 }, {
891 .id = 0x4d,
892 .name = "xusb_devw",
893 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
894 .regs = {
895 .smmu = {
896 .reg = 0x230,
897 .bit = 13,
898 },
899 .la = {
900 .reg = 0x380,
901 .shift = 16,
902 .mask = 0xff,
903 .def = 0xa5,
904 },
905 },
906 }, {
907 .id = 0x4e,
908 .name = "fdcdwr3",
909 .swgroup = TEGRA_SWGROUP_NV,
910 .regs = {
911 .smmu = {
912 .reg = 0x230,
913 .bit = 14,
914 },
915 .la = {
916 .reg = 0x388,
917 .shift = 0,
918 .mask = 0xff,
919 .def = 0x10,
920 },
921 },
922 }, {
923 .id = 0x4f,
924 .name = "fdcdrd3",
925 .swgroup = TEGRA_SWGROUP_NV,
926 .regs = {
927 .smmu = {
928 .reg = 0x230,
929 .bit = 15,
930 },
931 .la = {
932 .reg = 0x384,
933 .shift = 0,
934 .mask = 0xff,
935 .def = 0x0c,
936 },
937 },
938 }, {
939 .id = 0x50,
940 .name = "fdcwr4",
941 .swgroup = TEGRA_SWGROUP_NV,
942 .regs = {
943 .smmu = {
944 .reg = 0x230,
945 .bit = 16,
946 },
947 .la = {
948 .reg = 0x388,
949 .shift = 16,
950 .mask = 0xff,
951 .def = 0x10,
952 },
953 },
954 }, {
955 .id = 0x51,
956 .name = "fdcrd4",
957 .swgroup = TEGRA_SWGROUP_NV,
958 .regs = {
959 .smmu = {
960 .reg = 0x230,
961 .bit = 17,
962 },
963 .la = {
964 .reg = 0x384,
965 .shift = 16,
966 .mask = 0xff,
967 .def = 0x0c,
968 },
969 },
970 }, {
971 .id = 0x52,
972 .name = "emucifr",
973 .swgroup = TEGRA_SWGROUP_EMUCIF,
974 .regs = {
975 .la = {
976 .reg = 0x38c,
977 .shift = 0,
978 .mask = 0xff,
979 .def = 0x04,
980 },
981 },
982 }, {
983 .id = 0x53,
984 .name = "emucifw",
985 .swgroup = TEGRA_SWGROUP_EMUCIF,
986 .regs = {
987 .la = {
988 .reg = 0x38c,
989 .shift = 16,
990 .mask = 0xff,
991 .def = 0x0e,
992 },
993 },
994 }, {
995 .id = 0x54,
996 .name = "tsecsrd",
997 .swgroup = TEGRA_SWGROUP_TSEC,
998 .regs = {
999 .smmu = {
1000 .reg = 0x230,
1001 .bit = 20,
1002 },
1003 .la = {
1004 .reg = 0x390,
1005 .shift = 0,
1006 .mask = 0xff,
1007 .def = 0x50,
1008 },
1009 },
1010 }, {
1011 .id = 0x55,
1012 .name = "tsecswr",
1013 .swgroup = TEGRA_SWGROUP_TSEC,
1014 .regs = {
1015 .smmu = {
1016 .reg = 0x230,
1017 .bit = 21,
1018 },
1019 .la = {
1020 .reg = 0x390,
1021 .shift = 16,
1022 .mask = 0xff,
1023 .def = 0x50,
1024 },
1025 },
1026 },
1027};
1028
1029static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
1030 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1031 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1032 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
1033 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
1034 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1035 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1036 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1037 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1038 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
1039 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1040 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
1041 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1042 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
1043 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1044 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1045 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1046};
1047
1048static const unsigned int tegra114_group_drm[] = {
1049 TEGRA_SWGROUP_DC,
1050 TEGRA_SWGROUP_DCB,
1051 TEGRA_SWGROUP_G2,
1052 TEGRA_SWGROUP_NV,
1053};
1054
1055static const struct tegra_smmu_group_soc tegra114_groups[] = {
1056 {
1057 .name = "drm",
1058 .swgroups = tegra114_group_drm,
1059 .num_swgroups = ARRAY_SIZE(tegra114_group_drm),
1060 },
1061};
1062
1063static const struct tegra_smmu_soc tegra114_smmu_soc = {
1064 .clients = tegra114_mc_clients,
1065 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
1066 .swgroups = tegra114_swgroups,
1067 .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
1068 .groups = tegra114_groups,
1069 .num_groups = ARRAY_SIZE(tegra114_groups),
1070 .supports_round_robin_arbitration = false,
1071 .supports_request_limit = false,
1072 .num_tlb_lines = 32,
1073 .num_asids = 4,
1074};
1075
1076#define TEGRA114_MC_RESET(_name, _control, _status, _bit) \
1077 { \
1078 .name = #_name, \
1079 .id = TEGRA114_MC_RESET_##_name, \
1080 .control = _control, \
1081 .status = _status, \
1082 .bit = _bit, \
1083 }
1084
1085static const struct tegra_mc_reset tegra114_mc_resets[] = {
1086 TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
1087 TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
1088 TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
1089 TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
1090 TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
1091 TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
1092 TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
1093 TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
1094 TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
1095 TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1096 TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
1097 TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
1098 TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
1099 TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
1100 TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
1101 TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
1102};
1103
1104const struct tegra_mc_soc tegra114_mc_soc = {
1105 .clients = tegra114_mc_clients,
1106 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
1107 .num_address_bits = 32,
1108 .atom_size = 32,
1109 .client_id_mask = 0x7f,
1110 .smmu = &tegra114_smmu_soc,
1111 .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1112 MC_INT_DECERR_EMEM,
1113 .reset_ops = &tegra_mc_reset_ops_common,
1114 .resets = tegra114_mc_resets,
1115 .num_resets = ARRAY_SIZE(tegra114_mc_resets),
1116 .ops = &tegra30_mc_ops,
1117};
1/*
2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/of.h>
10#include <linux/mm.h>
11
12#include <dt-bindings/memory/tegra114-mc.h>
13
14#include "mc.h"
15
16static const struct tegra_mc_client tegra114_mc_clients[] = {
17 {
18 .id = 0x00,
19 .name = "ptcr",
20 .swgroup = TEGRA_SWGROUP_PTC,
21 }, {
22 .id = 0x01,
23 .name = "display0a",
24 .swgroup = TEGRA_SWGROUP_DC,
25 .smmu = {
26 .reg = 0x228,
27 .bit = 1,
28 },
29 .la = {
30 .reg = 0x2e8,
31 .shift = 0,
32 .mask = 0xff,
33 .def = 0x4e,
34 },
35 }, {
36 .id = 0x02,
37 .name = "display0ab",
38 .swgroup = TEGRA_SWGROUP_DCB,
39 .smmu = {
40 .reg = 0x228,
41 .bit = 2,
42 },
43 .la = {
44 .reg = 0x2f4,
45 .shift = 0,
46 .mask = 0xff,
47 .def = 0x4e,
48 },
49 }, {
50 .id = 0x03,
51 .name = "display0b",
52 .swgroup = TEGRA_SWGROUP_DC,
53 .smmu = {
54 .reg = 0x228,
55 .bit = 3,
56 },
57 .la = {
58 .reg = 0x2e8,
59 .shift = 16,
60 .mask = 0xff,
61 .def = 0x4e,
62 },
63 }, {
64 .id = 0x04,
65 .name = "display0bb",
66 .swgroup = TEGRA_SWGROUP_DCB,
67 .smmu = {
68 .reg = 0x228,
69 .bit = 4,
70 },
71 .la = {
72 .reg = 0x2f4,
73 .shift = 16,
74 .mask = 0xff,
75 .def = 0x4e,
76 },
77 }, {
78 .id = 0x05,
79 .name = "display0c",
80 .swgroup = TEGRA_SWGROUP_DC,
81 .smmu = {
82 .reg = 0x228,
83 .bit = 5,
84 },
85 .la = {
86 .reg = 0x2ec,
87 .shift = 0,
88 .mask = 0xff,
89 .def = 0x4e,
90 },
91 }, {
92 .id = 0x06,
93 .name = "display0cb",
94 .swgroup = TEGRA_SWGROUP_DCB,
95 .smmu = {
96 .reg = 0x228,
97 .bit = 6,
98 },
99 .la = {
100 .reg = 0x2f8,
101 .shift = 0,
102 .mask = 0xff,
103 .def = 0x4e,
104 },
105 }, {
106 .id = 0x09,
107 .name = "eppup",
108 .swgroup = TEGRA_SWGROUP_EPP,
109 .smmu = {
110 .reg = 0x228,
111 .bit = 9,
112 },
113 .la = {
114 .reg = 0x300,
115 .shift = 0,
116 .mask = 0xff,
117 .def = 0x33,
118 },
119 }, {
120 .id = 0x0a,
121 .name = "g2pr",
122 .swgroup = TEGRA_SWGROUP_G2,
123 .smmu = {
124 .reg = 0x228,
125 .bit = 10,
126 },
127 .la = {
128 .reg = 0x308,
129 .shift = 0,
130 .mask = 0xff,
131 .def = 0x09,
132 },
133 }, {
134 .id = 0x0b,
135 .name = "g2sr",
136 .swgroup = TEGRA_SWGROUP_G2,
137 .smmu = {
138 .reg = 0x228,
139 .bit = 11,
140 },
141 .la = {
142 .reg = 0x308,
143 .shift = 16,
144 .mask = 0xff,
145 .def = 0x09,
146 },
147 }, {
148 .id = 0x0f,
149 .name = "avpcarm7r",
150 .swgroup = TEGRA_SWGROUP_AVPC,
151 .smmu = {
152 .reg = 0x228,
153 .bit = 15,
154 },
155 .la = {
156 .reg = 0x2e4,
157 .shift = 0,
158 .mask = 0xff,
159 .def = 0x04,
160 },
161 }, {
162 .id = 0x10,
163 .name = "displayhc",
164 .swgroup = TEGRA_SWGROUP_DC,
165 .smmu = {
166 .reg = 0x228,
167 .bit = 16,
168 },
169 .la = {
170 .reg = 0x2f0,
171 .shift = 0,
172 .mask = 0xff,
173 .def = 0x68,
174 },
175 }, {
176 .id = 0x11,
177 .name = "displayhcb",
178 .swgroup = TEGRA_SWGROUP_DCB,
179 .smmu = {
180 .reg = 0x228,
181 .bit = 17,
182 },
183 .la = {
184 .reg = 0x2fc,
185 .shift = 0,
186 .mask = 0xff,
187 .def = 0x68,
188 },
189 }, {
190 .id = 0x12,
191 .name = "fdcdrd",
192 .swgroup = TEGRA_SWGROUP_NV,
193 .smmu = {
194 .reg = 0x228,
195 .bit = 18,
196 },
197 .la = {
198 .reg = 0x334,
199 .shift = 0,
200 .mask = 0xff,
201 .def = 0x0c,
202 },
203 }, {
204 .id = 0x13,
205 .name = "fdcdrd2",
206 .swgroup = TEGRA_SWGROUP_NV,
207 .smmu = {
208 .reg = 0x228,
209 .bit = 19,
210 },
211 .la = {
212 .reg = 0x33c,
213 .shift = 0,
214 .mask = 0xff,
215 .def = 0x0c,
216 },
217 }, {
218 .id = 0x14,
219 .name = "g2dr",
220 .swgroup = TEGRA_SWGROUP_G2,
221 .smmu = {
222 .reg = 0x228,
223 .bit = 20,
224 },
225 .la = {
226 .reg = 0x30c,
227 .shift = 0,
228 .mask = 0xff,
229 .def = 0x0a,
230 },
231 }, {
232 .id = 0x15,
233 .name = "hdar",
234 .swgroup = TEGRA_SWGROUP_HDA,
235 .smmu = {
236 .reg = 0x228,
237 .bit = 21,
238 },
239 .la = {
240 .reg = 0x318,
241 .shift = 0,
242 .mask = 0xff,
243 .def = 0xff,
244 },
245 }, {
246 .id = 0x16,
247 .name = "host1xdmar",
248 .swgroup = TEGRA_SWGROUP_HC,
249 .smmu = {
250 .reg = 0x228,
251 .bit = 22,
252 },
253 .la = {
254 .reg = 0x310,
255 .shift = 0,
256 .mask = 0xff,
257 .def = 0x10,
258 },
259 }, {
260 .id = 0x17,
261 .name = "host1xr",
262 .swgroup = TEGRA_SWGROUP_HC,
263 .smmu = {
264 .reg = 0x228,
265 .bit = 23,
266 },
267 .la = {
268 .reg = 0x310,
269 .shift = 16,
270 .mask = 0xff,
271 .def = 0xa5,
272 },
273 }, {
274 .id = 0x18,
275 .name = "idxsrd",
276 .swgroup = TEGRA_SWGROUP_NV,
277 .smmu = {
278 .reg = 0x228,
279 .bit = 24,
280 },
281 .la = {
282 .reg = 0x334,
283 .shift = 16,
284 .mask = 0xff,
285 .def = 0x0b,
286 },
287 }, {
288 .id = 0x1c,
289 .name = "msencsrd",
290 .swgroup = TEGRA_SWGROUP_MSENC,
291 .smmu = {
292 .reg = 0x228,
293 .bit = 28,
294 },
295 .la = {
296 .reg = 0x328,
297 .shift = 0,
298 .mask = 0xff,
299 .def = 0x80,
300 },
301 }, {
302 .id = 0x1d,
303 .name = "ppcsahbdmar",
304 .swgroup = TEGRA_SWGROUP_PPCS,
305 .smmu = {
306 .reg = 0x228,
307 .bit = 29,
308 },
309 .la = {
310 .reg = 0x344,
311 .shift = 0,
312 .mask = 0xff,
313 .def = 0x50,
314 },
315 }, {
316 .id = 0x1e,
317 .name = "ppcsahbslvr",
318 .swgroup = TEGRA_SWGROUP_PPCS,
319 .smmu = {
320 .reg = 0x228,
321 .bit = 30,
322 },
323 .la = {
324 .reg = 0x344,
325 .shift = 16,
326 .mask = 0xff,
327 .def = 0xe8,
328 },
329 }, {
330 .id = 0x20,
331 .name = "texl2srd",
332 .swgroup = TEGRA_SWGROUP_NV,
333 .smmu = {
334 .reg = 0x22c,
335 .bit = 0,
336 },
337 .la = {
338 .reg = 0x338,
339 .shift = 0,
340 .mask = 0xff,
341 .def = 0x0c,
342 },
343 }, {
344 .id = 0x22,
345 .name = "vdebsevr",
346 .swgroup = TEGRA_SWGROUP_VDE,
347 .smmu = {
348 .reg = 0x22c,
349 .bit = 2,
350 },
351 .la = {
352 .reg = 0x354,
353 .shift = 0,
354 .mask = 0xff,
355 .def = 0xff,
356 },
357 }, {
358 .id = 0x23,
359 .name = "vdember",
360 .swgroup = TEGRA_SWGROUP_VDE,
361 .smmu = {
362 .reg = 0x22c,
363 .bit = 3,
364 },
365 .la = {
366 .reg = 0x354,
367 .shift = 16,
368 .mask = 0xff,
369 .def = 0xff,
370 },
371 }, {
372 .id = 0x24,
373 .name = "vdemcer",
374 .swgroup = TEGRA_SWGROUP_VDE,
375 .smmu = {
376 .reg = 0x22c,
377 .bit = 4,
378 },
379 .la = {
380 .reg = 0x358,
381 .shift = 0,
382 .mask = 0xff,
383 .def = 0xb8,
384 },
385 }, {
386 .id = 0x25,
387 .name = "vdetper",
388 .swgroup = TEGRA_SWGROUP_VDE,
389 .smmu = {
390 .reg = 0x22c,
391 .bit = 5,
392 },
393 .la = {
394 .reg = 0x358,
395 .shift = 16,
396 .mask = 0xff,
397 .def = 0xee,
398 },
399 }, {
400 .id = 0x26,
401 .name = "mpcorelpr",
402 .swgroup = TEGRA_SWGROUP_MPCORELP,
403 .la = {
404 .reg = 0x324,
405 .shift = 0,
406 .mask = 0xff,
407 .def = 0x04,
408 },
409 }, {
410 .id = 0x27,
411 .name = "mpcorer",
412 .swgroup = TEGRA_SWGROUP_MPCORE,
413 .la = {
414 .reg = 0x320,
415 .shift = 0,
416 .mask = 0xff,
417 .def = 0x04,
418 },
419 }, {
420 .id = 0x28,
421 .name = "eppu",
422 .swgroup = TEGRA_SWGROUP_EPP,
423 .smmu = {
424 .reg = 0x22c,
425 .bit = 8,
426 },
427 .la = {
428 .reg = 0x300,
429 .shift = 16,
430 .mask = 0xff,
431 .def = 0x33,
432 },
433 }, {
434 .id = 0x29,
435 .name = "eppv",
436 .swgroup = TEGRA_SWGROUP_EPP,
437 .smmu = {
438 .reg = 0x22c,
439 .bit = 9,
440 },
441 .la = {
442 .reg = 0x304,
443 .shift = 0,
444 .mask = 0xff,
445 .def = 0x6c,
446 },
447 }, {
448 .id = 0x2a,
449 .name = "eppy",
450 .swgroup = TEGRA_SWGROUP_EPP,
451 .smmu = {
452 .reg = 0x22c,
453 .bit = 10,
454 },
455 .la = {
456 .reg = 0x304,
457 .shift = 16,
458 .mask = 0xff,
459 .def = 0x6c,
460 },
461 }, {
462 .id = 0x2b,
463 .name = "msencswr",
464 .swgroup = TEGRA_SWGROUP_MSENC,
465 .smmu = {
466 .reg = 0x22c,
467 .bit = 11,
468 },
469 .la = {
470 .reg = 0x328,
471 .shift = 16,
472 .mask = 0xff,
473 .def = 0x80,
474 },
475 }, {
476 .id = 0x2c,
477 .name = "viwsb",
478 .swgroup = TEGRA_SWGROUP_VI,
479 .smmu = {
480 .reg = 0x22c,
481 .bit = 12,
482 },
483 .la = {
484 .reg = 0x364,
485 .shift = 0,
486 .mask = 0xff,
487 .def = 0x47,
488 },
489 }, {
490 .id = 0x2d,
491 .name = "viwu",
492 .swgroup = TEGRA_SWGROUP_VI,
493 .smmu = {
494 .reg = 0x22c,
495 .bit = 13,
496 },
497 .la = {
498 .reg = 0x368,
499 .shift = 0,
500 .mask = 0xff,
501 .def = 0xff,
502 },
503 }, {
504 .id = 0x2e,
505 .name = "viwv",
506 .swgroup = TEGRA_SWGROUP_VI,
507 .smmu = {
508 .reg = 0x22c,
509 .bit = 14,
510 },
511 .la = {
512 .reg = 0x368,
513 .shift = 16,
514 .mask = 0xff,
515 .def = 0xff,
516 },
517 }, {
518 .id = 0x2f,
519 .name = "viwy",
520 .swgroup = TEGRA_SWGROUP_VI,
521 .smmu = {
522 .reg = 0x22c,
523 .bit = 15,
524 },
525 .la = {
526 .reg = 0x36c,
527 .shift = 0,
528 .mask = 0xff,
529 .def = 0x47,
530 },
531 }, {
532 .id = 0x30,
533 .name = "g2dw",
534 .swgroup = TEGRA_SWGROUP_G2,
535 .smmu = {
536 .reg = 0x22c,
537 .bit = 16,
538 },
539 .la = {
540 .reg = 0x30c,
541 .shift = 16,
542 .mask = 0xff,
543 .def = 0x9,
544 },
545 }, {
546 .id = 0x32,
547 .name = "avpcarm7w",
548 .swgroup = TEGRA_SWGROUP_AVPC,
549 .smmu = {
550 .reg = 0x22c,
551 .bit = 18,
552 },
553 .la = {
554 .reg = 0x2e4,
555 .shift = 16,
556 .mask = 0xff,
557 .def = 0x0e,
558 },
559 }, {
560 .id = 0x33,
561 .name = "fdcdwr",
562 .swgroup = TEGRA_SWGROUP_NV,
563 .smmu = {
564 .reg = 0x22c,
565 .bit = 19,
566 },
567 .la = {
568 .reg = 0x338,
569 .shift = 16,
570 .mask = 0xff,
571 .def = 0x10,
572 },
573 }, {
574 .id = 0x34,
575 .name = "fdcwr2",
576 .swgroup = TEGRA_SWGROUP_NV,
577 .smmu = {
578 .reg = 0x22c,
579 .bit = 20,
580 },
581 .la = {
582 .reg = 0x340,
583 .shift = 0,
584 .mask = 0xff,
585 .def = 0x10,
586 },
587 }, {
588 .id = 0x35,
589 .name = "hdaw",
590 .swgroup = TEGRA_SWGROUP_HDA,
591 .smmu = {
592 .reg = 0x22c,
593 .bit = 21,
594 },
595 .la = {
596 .reg = 0x318,
597 .shift = 16,
598 .mask = 0xff,
599 .def = 0xff,
600 },
601 }, {
602 .id = 0x36,
603 .name = "host1xw",
604 .swgroup = TEGRA_SWGROUP_HC,
605 .smmu = {
606 .reg = 0x22c,
607 .bit = 22,
608 },
609 .la = {
610 .reg = 0x314,
611 .shift = 0,
612 .mask = 0xff,
613 .def = 0x25,
614 },
615 }, {
616 .id = 0x37,
617 .name = "ispw",
618 .swgroup = TEGRA_SWGROUP_ISP,
619 .smmu = {
620 .reg = 0x22c,
621 .bit = 23,
622 },
623 .la = {
624 .reg = 0x31c,
625 .shift = 0,
626 .mask = 0xff,
627 .def = 0xff,
628 },
629 }, {
630 .id = 0x38,
631 .name = "mpcorelpw",
632 .swgroup = TEGRA_SWGROUP_MPCORELP,
633 .la = {
634 .reg = 0x324,
635 .shift = 16,
636 .mask = 0xff,
637 .def = 0x80,
638 },
639 }, {
640 .id = 0x39,
641 .name = "mpcorew",
642 .swgroup = TEGRA_SWGROUP_MPCORE,
643 .la = {
644 .reg = 0x320,
645 .shift = 16,
646 .mask = 0xff,
647 .def = 0x0e,
648 },
649 }, {
650 .id = 0x3b,
651 .name = "ppcsahbdmaw",
652 .swgroup = TEGRA_SWGROUP_PPCS,
653 .smmu = {
654 .reg = 0x22c,
655 .bit = 27,
656 },
657 .la = {
658 .reg = 0x348,
659 .shift = 0,
660 .mask = 0xff,
661 .def = 0xa5,
662 },
663 }, {
664 .id = 0x3c,
665 .name = "ppcsahbslvw",
666 .swgroup = TEGRA_SWGROUP_PPCS,
667 .smmu = {
668 .reg = 0x22c,
669 .bit = 28,
670 },
671 .la = {
672 .reg = 0x348,
673 .shift = 16,
674 .mask = 0xff,
675 .def = 0xe8,
676 },
677 }, {
678 .id = 0x3e,
679 .name = "vdebsevw",
680 .swgroup = TEGRA_SWGROUP_VDE,
681 .smmu = {
682 .reg = 0x22c,
683 .bit = 30,
684 },
685 .la = {
686 .reg = 0x35c,
687 .shift = 0,
688 .mask = 0xff,
689 .def = 0xff,
690 },
691 }, {
692 .id = 0x3f,
693 .name = "vdedbgw",
694 .swgroup = TEGRA_SWGROUP_VDE,
695 .smmu = {
696 .reg = 0x22c,
697 .bit = 31,
698 },
699 .la = {
700 .reg = 0x35c,
701 .shift = 16,
702 .mask = 0xff,
703 .def = 0xff,
704 },
705 }, {
706 .id = 0x40,
707 .name = "vdembew",
708 .swgroup = TEGRA_SWGROUP_VDE,
709 .smmu = {
710 .reg = 0x230,
711 .bit = 0,
712 },
713 .la = {
714 .reg = 0x360,
715 .shift = 0,
716 .mask = 0xff,
717 .def = 0x89,
718 },
719 }, {
720 .id = 0x41,
721 .name = "vdetpmw",
722 .swgroup = TEGRA_SWGROUP_VDE,
723 .smmu = {
724 .reg = 0x230,
725 .bit = 1,
726 },
727 .la = {
728 .reg = 0x360,
729 .shift = 16,
730 .mask = 0xff,
731 .def = 0x59,
732 },
733 }, {
734 .id = 0x4a,
735 .name = "xusb_hostr",
736 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
737 .smmu = {
738 .reg = 0x230,
739 .bit = 10,
740 },
741 .la = {
742 .reg = 0x37c,
743 .shift = 0,
744 .mask = 0xff,
745 .def = 0xa5,
746 },
747 }, {
748 .id = 0x4b,
749 .name = "xusb_hostw",
750 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
751 .smmu = {
752 .reg = 0x230,
753 .bit = 11,
754 },
755 .la = {
756 .reg = 0x37c,
757 .shift = 16,
758 .mask = 0xff,
759 .def = 0xa5,
760 },
761 }, {
762 .id = 0x4c,
763 .name = "xusb_devr",
764 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
765 .smmu = {
766 .reg = 0x230,
767 .bit = 12,
768 },
769 .la = {
770 .reg = 0x380,
771 .shift = 0,
772 .mask = 0xff,
773 .def = 0xa5,
774 },
775 }, {
776 .id = 0x4d,
777 .name = "xusb_devw",
778 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
779 .smmu = {
780 .reg = 0x230,
781 .bit = 13,
782 },
783 .la = {
784 .reg = 0x380,
785 .shift = 16,
786 .mask = 0xff,
787 .def = 0xa5,
788 },
789 }, {
790 .id = 0x4e,
791 .name = "fdcdwr3",
792 .swgroup = TEGRA_SWGROUP_NV,
793 .smmu = {
794 .reg = 0x230,
795 .bit = 14,
796 },
797 .la = {
798 .reg = 0x388,
799 .shift = 0,
800 .mask = 0xff,
801 .def = 0x10,
802 },
803 }, {
804 .id = 0x4f,
805 .name = "fdcdrd3",
806 .swgroup = TEGRA_SWGROUP_NV,
807 .smmu = {
808 .reg = 0x230,
809 .bit = 15,
810 },
811 .la = {
812 .reg = 0x384,
813 .shift = 0,
814 .mask = 0xff,
815 .def = 0x0c,
816 },
817 }, {
818 .id = 0x50,
819 .name = "fdcwr4",
820 .swgroup = TEGRA_SWGROUP_NV,
821 .smmu = {
822 .reg = 0x230,
823 .bit = 16,
824 },
825 .la = {
826 .reg = 0x388,
827 .shift = 16,
828 .mask = 0xff,
829 .def = 0x10,
830 },
831 }, {
832 .id = 0x51,
833 .name = "fdcrd4",
834 .swgroup = TEGRA_SWGROUP_NV,
835 .smmu = {
836 .reg = 0x230,
837 .bit = 17,
838 },
839 .la = {
840 .reg = 0x384,
841 .shift = 16,
842 .mask = 0xff,
843 .def = 0x0c,
844 },
845 }, {
846 .id = 0x52,
847 .name = "emucifr",
848 .swgroup = TEGRA_SWGROUP_EMUCIF,
849 .la = {
850 .reg = 0x38c,
851 .shift = 0,
852 .mask = 0xff,
853 .def = 0x04,
854 },
855 }, {
856 .id = 0x53,
857 .name = "emucifw",
858 .swgroup = TEGRA_SWGROUP_EMUCIF,
859 .la = {
860 .reg = 0x38c,
861 .shift = 16,
862 .mask = 0xff,
863 .def = 0x0e,
864 },
865 }, {
866 .id = 0x54,
867 .name = "tsecsrd",
868 .swgroup = TEGRA_SWGROUP_TSEC,
869 .smmu = {
870 .reg = 0x230,
871 .bit = 20,
872 },
873 .la = {
874 .reg = 0x390,
875 .shift = 0,
876 .mask = 0xff,
877 .def = 0x50,
878 },
879 }, {
880 .id = 0x55,
881 .name = "tsecswr",
882 .swgroup = TEGRA_SWGROUP_TSEC,
883 .smmu = {
884 .reg = 0x230,
885 .bit = 21,
886 },
887 .la = {
888 .reg = 0x390,
889 .shift = 16,
890 .mask = 0xff,
891 .def = 0x50,
892 },
893 },
894};
895
896static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
897 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
898 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
899 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
900 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
901 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
902 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
903 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
904 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
905 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
906 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
907 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
908 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
909 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
910 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
911 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
912 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
913};
914
915static const unsigned int tegra114_group_display[] = {
916 TEGRA_SWGROUP_DC,
917 TEGRA_SWGROUP_DCB,
918};
919
920static const struct tegra_smmu_group_soc tegra114_groups[] = {
921 {
922 .name = "display",
923 .swgroups = tegra114_group_display,
924 .num_swgroups = ARRAY_SIZE(tegra114_group_display),
925 },
926};
927
928static const struct tegra_smmu_soc tegra114_smmu_soc = {
929 .clients = tegra114_mc_clients,
930 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
931 .swgroups = tegra114_swgroups,
932 .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
933 .groups = tegra114_groups,
934 .num_groups = ARRAY_SIZE(tegra114_groups),
935 .supports_round_robin_arbitration = false,
936 .supports_request_limit = false,
937 .num_tlb_lines = 32,
938 .num_asids = 4,
939};
940
941const struct tegra_mc_soc tegra114_mc_soc = {
942 .clients = tegra114_mc_clients,
943 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
944 .num_address_bits = 32,
945 .atom_size = 32,
946 .client_id_mask = 0x7f,
947 .smmu = &tegra114_smmu_soc,
948};