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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6#include <linux/arm-smccc.h>
7#include <linux/clk.h>
8#include <linux/component.h>
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_platform.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/soc/mediatek/mtk_sip_svc.h>
19#include <soc/mediatek/smi.h>
20#include <dt-bindings/memory/mt2701-larb-port.h>
21#include <dt-bindings/memory/mtk-memory-port.h>
22
23/* SMI COMMON */
24#define SMI_L1LEN 0x100
25
26#define SMI_L1_ARB 0x200
27#define SMI_BUS_SEL 0x220
28#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
29/* All are MMU0 defaultly. Only specialize mmu1 here. */
30#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
31
32#define SMI_READ_FIFO_TH 0x230
33#define SMI_M4U_TH 0x234
34#define SMI_FIFO_TH1 0x238
35#define SMI_FIFO_TH2 0x23c
36#define SMI_DCM 0x300
37#define SMI_DUMMY 0x444
38
39/* SMI LARB */
40#define SMI_LARB_SLP_CON 0xc
41#define SLP_PROT_EN BIT(0)
42#define SLP_PROT_RDY BIT(16)
43
44#define SMI_LARB_CMD_THRT_CON 0x24
45#define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4)
46#define SMI_LARB_THRT_RD_NU_LMT (5 << 4)
47
48#define SMI_LARB_SW_FLAG 0x40
49#define SMI_LARB_SW_FLAG_1 0x1
50
51#define SMI_LARB_OSTDL_PORT 0x200
52#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
53
54/* Below are about mmu enable registers, they are different in SoCs */
55/* gen1: mt2701 */
56#define REG_SMI_SECUR_CON_BASE 0x5c0
57
58/* every register control 8 port, register offset 0x4 */
59#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
60#define REG_SMI_SECUR_CON_ADDR(id) \
61 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
62
63/*
64 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
65 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
66 * or non-security.
67 */
68#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
69#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
70/* mt2701 domain should be set to 3 */
71#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
72
73/* gen2: */
74/* mt8167 */
75#define MT8167_SMI_LARB_MMU_EN 0xfc0
76
77/* mt8173 */
78#define MT8173_SMI_LARB_MMU_EN 0xf00
79
80/* general */
81#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
82#define F_MMU_EN BIT(0)
83#define BANK_SEL(id) ({ \
84 u32 _id = (id) & 0x3; \
85 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
86})
87
88#define SMI_COMMON_INIT_REGS_NR 6
89#define SMI_LARB_PORT_NR_MAX 32
90
91#define MTK_SMI_FLAG_THRT_UPDATE BIT(0)
92#define MTK_SMI_FLAG_SW_FLAG BIT(1)
93#define MTK_SMI_FLAG_SLEEP_CTL BIT(2)
94#define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3)
95#define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x)))
96
97struct mtk_smi_reg_pair {
98 unsigned int offset;
99 u32 value;
100};
101
102enum mtk_smi_type {
103 MTK_SMI_GEN1,
104 MTK_SMI_GEN2, /* gen2 smi common */
105 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */
106};
107
108/* larbs: Require apb/smi clocks while gals is optional. */
109static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
110#define MTK_SMI_LARB_REQ_CLK_NR 2
111#define MTK_SMI_LARB_OPT_CLK_NR 1
112
113/*
114 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required.
115 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
116 */
117static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
118#define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks)
119#define MTK_SMI_COM_REQ_CLK_NR 2
120#define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX
121#define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3
122
123struct mtk_smi_common_plat {
124 enum mtk_smi_type type;
125 bool has_gals;
126 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
127
128 const struct mtk_smi_reg_pair *init;
129};
130
131struct mtk_smi_larb_gen {
132 int port_in_larb[MTK_LARB_NR_MAX + 1];
133 int (*config_port)(struct device *dev);
134 unsigned int larb_direct_to_common_mask;
135 unsigned int flags_general;
136 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX];
137};
138
139struct mtk_smi {
140 struct device *dev;
141 unsigned int clk_num;
142 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX];
143 struct clk *clk_async; /*only needed by mt2701*/
144 union {
145 void __iomem *smi_ao_base; /* only for gen1 */
146 void __iomem *base; /* only for gen2 */
147 };
148 struct device *smi_common_dev; /* for sub common */
149 const struct mtk_smi_common_plat *plat;
150};
151
152struct mtk_smi_larb { /* larb: local arbiter */
153 struct mtk_smi smi;
154 void __iomem *base;
155 struct device *smi_common_dev; /* common or sub-common dev */
156 const struct mtk_smi_larb_gen *larb_gen;
157 int larbid;
158 u32 *mmu;
159 unsigned char *bank;
160};
161
162static int
163mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
164{
165 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
166 struct mtk_smi_larb_iommu *larb_mmu = data;
167 unsigned int i;
168
169 for (i = 0; i < MTK_LARB_NR_MAX; i++) {
170 if (dev == larb_mmu[i].dev) {
171 larb->larbid = i;
172 larb->mmu = &larb_mmu[i].mmu;
173 larb->bank = larb_mmu[i].bank;
174 return 0;
175 }
176 }
177 return -ENODEV;
178}
179
180static void
181mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
182{
183 /* Do nothing as the iommu is always enabled. */
184}
185
186static const struct component_ops mtk_smi_larb_component_ops = {
187 .bind = mtk_smi_larb_bind,
188 .unbind = mtk_smi_larb_unbind,
189};
190
191static int mtk_smi_larb_config_port_gen1(struct device *dev)
192{
193 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
194 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
195 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
196 int i, m4u_port_id, larb_port_num;
197 u32 sec_con_val, reg_val;
198
199 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
200 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
201 - larb_gen->port_in_larb[larb->larbid];
202
203 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
204 if (*larb->mmu & BIT(i)) {
205 /* bit[port + 3] controls the virtual or physical */
206 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
207 } else {
208 /* do not need to enable m4u for this port */
209 continue;
210 }
211 reg_val = readl(common->smi_ao_base
212 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
213 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
214 reg_val |= sec_con_val;
215 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
216 writel(reg_val,
217 common->smi_ao_base
218 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
219 }
220 return 0;
221}
222
223static int mtk_smi_larb_config_port_mt8167(struct device *dev)
224{
225 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
226
227 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
228 return 0;
229}
230
231static int mtk_smi_larb_config_port_mt8173(struct device *dev)
232{
233 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
234
235 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
236 return 0;
237}
238
239static int mtk_smi_larb_config_port_gen2_general(struct device *dev)
240{
241 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
242 u32 reg, flags_general = larb->larb_gen->flags_general;
243 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;
244 struct arm_smccc_res res;
245 int i;
246
247 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
248 return 0;
249
250 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {
251 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
252 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;
253 reg |= SMI_LARB_THRT_RD_NU_LMT;
254 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
255 }
256
257 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))
258 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
259
260 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
261 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
262
263 /*
264 * When mmu_en bits are in security world, the bank_sel still is in the
265 * LARB_NONSEC_CON below. And the mmu_en bits of LARB_NONSEC_CON have no
266 * effect in this case.
267 */
268 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) {
269 arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB,
270 larb->larbid, *larb->mmu, 0, 0, 0, 0, &res);
271 if (res.a0 != 0) {
272 dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0);
273 return -EINVAL;
274 }
275 }
276
277 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
278 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
279 reg |= F_MMU_EN;
280 reg |= BANK_SEL(larb->bank[i]);
281 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
282 }
283 return 0;
284}
285
286static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
287 [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
288 [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
289 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
290 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
291 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
292 [5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,},
293 [6] = {0x06, 0x01, 0x06, 0x0a,},
294 [7] = {0x0c, 0x0c, 0x12,},
295 [8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14,
296 0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05,
297 0x03, 0x01, 0x1e, 0x01, 0x05,},
298 [9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10,
299 0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,},
300 [10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
301 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
302 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
303 [11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
304 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
305 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
306 [12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
307 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
308 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
309 [13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
310 0x07, 0x02, 0x04, 0x02, 0x05, 0x05,},
311 [14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02,
312 0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
313 0x02, 0x02, 0x01, 0x01,},
314 [15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c,
315 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02,
316 0x0c, 0x01, 0x01,},
317 [16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d,
318 0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,},
319 [17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
320 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
321 [18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
322 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
323 [19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
324 [20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
325 [21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
326 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
327 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
328 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,
329 0x01,},
330 [23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,},
331 [24] = {0x12, 0x06, 0x12, 0x06,},
332 [25] = {0x01},
333};
334
335static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
336 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
337 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
338 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */
339 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
340 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
341 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},
342 [6] = {0x06, 0x01, 0x06, 0x0a,},
343 [7] = {0x0c, 0x0c, 0x12,},
344 [8] = {0x0c, 0x0c, 0x12,},
345 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,
346 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},
347 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
348 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,
349 0x0d, 0x06, 0x10, 0x10,},
350 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},
351 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},
352 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
353 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
354 0x01, 0x02, 0x02, 0x08, 0x02,},
355 [15] = {},
356 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
357 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
358 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
359 [18] = {0x12, 0x06, 0x12, 0x06,},
360 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
361 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
362 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
363 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
364 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
365 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
366 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
367 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
368 [23] = {0x18, 0x01,},
369 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,
370 0x01, 0x01,},
371 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
372 0x02, 0x01,},
373 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
374 0x02, 0x01,},
375 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
376 0x02, 0x01,},
377 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
378};
379
380static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
381 .port_in_larb = {
382 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
383 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
384 },
385 .config_port = mtk_smi_larb_config_port_gen1,
386};
387
388static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
389 .config_port = mtk_smi_larb_config_port_gen2_general,
390 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
391};
392
393static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
394 .config_port = mtk_smi_larb_config_port_gen2_general,
395 .larb_direct_to_common_mask =
396 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
397 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
398};
399
400static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
401 /* mt8167 do not need the port in larb */
402 .config_port = mtk_smi_larb_config_port_mt8167,
403};
404
405static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
406 /* mt8173 do not need the port in larb */
407 .config_port = mtk_smi_larb_config_port_mt8173,
408};
409
410static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
411 .config_port = mtk_smi_larb_config_port_gen2_general,
412 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
413 /* IPU0 | IPU1 | CCU */
414};
415
416static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
417 .config_port = mtk_smi_larb_config_port_gen2_general,
418 .flags_general = MTK_SMI_FLAG_SLEEP_CTL,
419};
420
421static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
422 .config_port = mtk_smi_larb_config_port_gen2_general,
423 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
424 MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
425 .ostd = mtk_smi_larb_mt8188_ostd,
426};
427
428static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
429 .config_port = mtk_smi_larb_config_port_gen2_general,
430};
431
432static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {
433 .config_port = mtk_smi_larb_config_port_gen2_general,
434 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
435 MTK_SMI_FLAG_SLEEP_CTL,
436 .ostd = mtk_smi_larb_mt8195_ostd,
437};
438
439static const struct of_device_id mtk_smi_larb_of_ids[] = {
440 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
441 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
442 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
443 {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173},
444 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
445 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
446 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
447 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
448 {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
449 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
450 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
451 {}
452};
453
454static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb)
455{
456 int ret;
457 u32 tmp;
458
459 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
460 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON,
461 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000);
462 if (ret) {
463 /* TODO: Reset this larb if it fails here. */
464 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);
465 }
466 return ret;
467}
468
469static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb)
470{
471 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
472}
473
474static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev)
475{
476 struct platform_device *smi_com_pdev;
477 struct device_node *smi_com_node;
478 struct device *smi_com_dev;
479 struct device_link *link;
480
481 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
482 if (!smi_com_node)
483 return -EINVAL;
484
485 smi_com_pdev = of_find_device_by_node(smi_com_node);
486 of_node_put(smi_com_node);
487 if (smi_com_pdev) {
488 /* smi common is the supplier, Make sure it is ready before */
489 if (!platform_get_drvdata(smi_com_pdev)) {
490 put_device(&smi_com_pdev->dev);
491 return -EPROBE_DEFER;
492 }
493 smi_com_dev = &smi_com_pdev->dev;
494 link = device_link_add(dev, smi_com_dev,
495 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
496 if (!link) {
497 dev_err(dev, "Unable to link smi-common dev\n");
498 put_device(&smi_com_pdev->dev);
499 return -ENODEV;
500 }
501 *com_dev = smi_com_dev;
502 } else {
503 dev_err(dev, "Failed to get the smi_common device\n");
504 return -EINVAL;
505 }
506 return 0;
507}
508
509static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
510 const char * const clks[],
511 unsigned int clk_nr_required,
512 unsigned int clk_nr_optional)
513{
514 int i, ret;
515
516 for (i = 0; i < clk_nr_required; i++)
517 smi->clks[i].id = clks[i];
518 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
519 if (ret)
520 return ret;
521
522 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++)
523 smi->clks[i].id = clks[i];
524 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional,
525 smi->clks + clk_nr_required);
526 smi->clk_num = clk_nr_required + clk_nr_optional;
527 return ret;
528}
529
530static int mtk_smi_larb_probe(struct platform_device *pdev)
531{
532 struct mtk_smi_larb *larb;
533 struct device *dev = &pdev->dev;
534 int ret;
535
536 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
537 if (!larb)
538 return -ENOMEM;
539
540 larb->larb_gen = of_device_get_match_data(dev);
541 larb->base = devm_platform_ioremap_resource(pdev, 0);
542 if (IS_ERR(larb->base))
543 return PTR_ERR(larb->base);
544
545 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
546 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR);
547 if (ret)
548 return ret;
549
550 larb->smi.dev = dev;
551
552 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev);
553 if (ret < 0)
554 return ret;
555
556 pm_runtime_enable(dev);
557 platform_set_drvdata(pdev, larb);
558 ret = component_add(dev, &mtk_smi_larb_component_ops);
559 if (ret)
560 goto err_pm_disable;
561 return 0;
562
563err_pm_disable:
564 pm_runtime_disable(dev);
565 device_link_remove(dev, larb->smi_common_dev);
566 return ret;
567}
568
569static void mtk_smi_larb_remove(struct platform_device *pdev)
570{
571 struct mtk_smi_larb *larb = platform_get_drvdata(pdev);
572
573 device_link_remove(&pdev->dev, larb->smi_common_dev);
574 pm_runtime_disable(&pdev->dev);
575 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
576}
577
578static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
579{
580 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
581 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
582 int ret;
583
584 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks);
585 if (ret)
586 return ret;
587
588 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL))
589 mtk_smi_larb_sleep_ctrl_disable(larb);
590
591 /* Configure the basic setting for this larb */
592 return larb_gen->config_port(dev);
593}
594
595static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
596{
597 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
598 int ret;
599
600 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) {
601 ret = mtk_smi_larb_sleep_ctrl_enable(larb);
602 if (ret)
603 return ret;
604 }
605
606 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks);
607 return 0;
608}
609
610static const struct dev_pm_ops smi_larb_pm_ops = {
611 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
612 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
613 pm_runtime_force_resume)
614};
615
616static struct platform_driver mtk_smi_larb_driver = {
617 .probe = mtk_smi_larb_probe,
618 .remove_new = mtk_smi_larb_remove,
619 .driver = {
620 .name = "mtk-smi-larb",
621 .of_match_table = mtk_smi_larb_of_ids,
622 .pm = &smi_larb_pm_ops,
623 }
624};
625
626static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = {
627 {SMI_L1_ARB, 0x1b},
628 {SMI_M4U_TH, 0xce810c85},
629 {SMI_FIFO_TH1, 0x43214c8},
630 {SMI_READ_FIFO_TH, 0x191f},
631};
632
633static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
634 {SMI_L1LEN, 0xb},
635 {SMI_M4U_TH, 0xe100e10},
636 {SMI_FIFO_TH1, 0x506090a},
637 {SMI_FIFO_TH2, 0x506090a},
638 {SMI_DCM, 0x4f1},
639 {SMI_DUMMY, 0x1},
640};
641
642static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
643 .type = MTK_SMI_GEN1,
644};
645
646static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
647 .type = MTK_SMI_GEN2,
648};
649
650static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
651 .type = MTK_SMI_GEN2,
652 .has_gals = true,
653 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
654 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
655};
656
657static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = {
658 .type = MTK_SMI_GEN2,
659 .bus_sel = F_MMU1_LARB(0),
660 .init = mtk_smi_common_mt6795_init,
661};
662
663static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
664 .type = MTK_SMI_GEN2,
665 .has_gals = true,
666 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
667 F_MMU1_LARB(7),
668};
669
670static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
671 .type = MTK_SMI_GEN2,
672 .has_gals = true,
673 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
674};
675
676static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = {
677 .type = MTK_SMI_GEN2,
678 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7),
679 .init = mtk_smi_common_mt8195_init,
680};
681
682static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
683 .type = MTK_SMI_GEN2,
684 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
685 .init = mtk_smi_common_mt8195_init,
686};
687
688static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
689 .type = MTK_SMI_GEN2,
690 .has_gals = true,
691 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
692 F_MMU1_LARB(6),
693};
694
695static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
696 .type = MTK_SMI_GEN2,
697 .has_gals = true,
698 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
699 F_MMU1_LARB(7),
700 .init = mtk_smi_common_mt8195_init,
701};
702
703static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
704 .type = MTK_SMI_GEN2,
705 .has_gals = true,
706 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
707 .init = mtk_smi_common_mt8195_init,
708};
709
710static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
711 .type = MTK_SMI_GEN2_SUB_COMM,
712 .has_gals = true,
713};
714
715static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = {
716 .type = MTK_SMI_GEN2,
717 .bus_sel = F_MMU1_LARB(2) | F_MMU1_LARB(4),
718};
719
720static const struct of_device_id mtk_smi_common_of_ids[] = {
721 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
722 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
723 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
724 {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795},
725 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
726 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
727 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
728 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
729 {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
730 {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
731 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
732 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
733 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
734 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
735 {.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365},
736 {}
737};
738
739static int mtk_smi_common_probe(struct platform_device *pdev)
740{
741 struct device *dev = &pdev->dev;
742 struct mtk_smi *common;
743 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR;
744
745 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
746 if (!common)
747 return -ENOMEM;
748 common->dev = dev;
749 common->plat = of_device_get_match_data(dev);
750
751 if (common->plat->has_gals) {
752 if (common->plat->type == MTK_SMI_GEN2)
753 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
754 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
755 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
756 }
757 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0);
758 if (ret)
759 return ret;
760
761 /*
762 * for mtk smi gen 1, we need to get the ao(always on) base to config
763 * m4u port, and we need to enable the aync clock for transform the smi
764 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
765 * base.
766 */
767 if (common->plat->type == MTK_SMI_GEN1) {
768 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0);
769 if (IS_ERR(common->smi_ao_base))
770 return PTR_ERR(common->smi_ao_base);
771
772 common->clk_async = devm_clk_get(dev, "async");
773 if (IS_ERR(common->clk_async))
774 return PTR_ERR(common->clk_async);
775
776 ret = clk_prepare_enable(common->clk_async);
777 if (ret)
778 return ret;
779 } else {
780 common->base = devm_platform_ioremap_resource(pdev, 0);
781 if (IS_ERR(common->base))
782 return PTR_ERR(common->base);
783 }
784
785 /* link its smi-common if this is smi-sub-common */
786 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
787 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
788 if (ret < 0)
789 return ret;
790 }
791
792 pm_runtime_enable(dev);
793 platform_set_drvdata(pdev, common);
794 return 0;
795}
796
797static void mtk_smi_common_remove(struct platform_device *pdev)
798{
799 struct mtk_smi *common = dev_get_drvdata(&pdev->dev);
800
801 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
802 device_link_remove(&pdev->dev, common->smi_common_dev);
803 pm_runtime_disable(&pdev->dev);
804}
805
806static int __maybe_unused mtk_smi_common_resume(struct device *dev)
807{
808 struct mtk_smi *common = dev_get_drvdata(dev);
809 const struct mtk_smi_reg_pair *init = common->plat->init;
810 u32 bus_sel = common->plat->bus_sel; /* default is 0 */
811 int ret, i;
812
813 ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
814 if (ret)
815 return ret;
816
817 if (common->plat->type != MTK_SMI_GEN2)
818 return 0;
819
820 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
821 writel_relaxed(init[i].value, common->base + init[i].offset);
822
823 writel(bus_sel, common->base + SMI_BUS_SEL);
824 return 0;
825}
826
827static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
828{
829 struct mtk_smi *common = dev_get_drvdata(dev);
830
831 clk_bulk_disable_unprepare(common->clk_num, common->clks);
832 return 0;
833}
834
835static const struct dev_pm_ops smi_common_pm_ops = {
836 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
837 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
838 pm_runtime_force_resume)
839};
840
841static struct platform_driver mtk_smi_common_driver = {
842 .probe = mtk_smi_common_probe,
843 .remove_new = mtk_smi_common_remove,
844 .driver = {
845 .name = "mtk-smi-common",
846 .of_match_table = mtk_smi_common_of_ids,
847 .pm = &smi_common_pm_ops,
848 }
849};
850
851static struct platform_driver * const smidrivers[] = {
852 &mtk_smi_common_driver,
853 &mtk_smi_larb_driver,
854};
855
856static int __init mtk_smi_init(void)
857{
858 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
859}
860module_init(mtk_smi_init);
861
862static void __exit mtk_smi_exit(void)
863{
864 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
865}
866module_exit(mtk_smi_exit);
867
868MODULE_DESCRIPTION("MediaTek SMI driver");
869MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (c) 2015-2016 MediaTek Inc.
3 * Author: Yong Wu <yong.wu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_platform.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <soc/mediatek/smi.h>
25#include <dt-bindings/memory/mt2701-larb-port.h>
26
27/* mt8173 */
28#define SMI_LARB_MMU_EN 0xf00
29
30/* mt2701 */
31#define REG_SMI_SECUR_CON_BASE 0x5c0
32
33/* every register control 8 port, register offset 0x4 */
34#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
35#define REG_SMI_SECUR_CON_ADDR(id) \
36 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
37
38/*
39 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
40 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
41 * or non-security.
42 */
43#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
44#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
45/* mt2701 domain should be set to 3 */
46#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
47
48/* mt2712 */
49#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
50#define F_MMU_EN BIT(0)
51
52struct mtk_smi_larb_gen {
53 bool need_larbid;
54 int port_in_larb[MTK_LARB_NR_MAX + 1];
55 void (*config_port)(struct device *);
56};
57
58struct mtk_smi {
59 struct device *dev;
60 struct clk *clk_apb, *clk_smi;
61 struct clk *clk_async; /*only needed by mt2701*/
62 void __iomem *smi_ao_base;
63};
64
65struct mtk_smi_larb { /* larb: local arbiter */
66 struct mtk_smi smi;
67 void __iomem *base;
68 struct device *smi_common_dev;
69 const struct mtk_smi_larb_gen *larb_gen;
70 int larbid;
71 u32 *mmu;
72};
73
74enum mtk_smi_gen {
75 MTK_SMI_GEN1,
76 MTK_SMI_GEN2
77};
78
79static int mtk_smi_enable(const struct mtk_smi *smi)
80{
81 int ret;
82
83 ret = pm_runtime_get_sync(smi->dev);
84 if (ret < 0)
85 return ret;
86
87 ret = clk_prepare_enable(smi->clk_apb);
88 if (ret)
89 goto err_put_pm;
90
91 ret = clk_prepare_enable(smi->clk_smi);
92 if (ret)
93 goto err_disable_apb;
94
95 return 0;
96
97err_disable_apb:
98 clk_disable_unprepare(smi->clk_apb);
99err_put_pm:
100 pm_runtime_put_sync(smi->dev);
101 return ret;
102}
103
104static void mtk_smi_disable(const struct mtk_smi *smi)
105{
106 clk_disable_unprepare(smi->clk_smi);
107 clk_disable_unprepare(smi->clk_apb);
108 pm_runtime_put_sync(smi->dev);
109}
110
111int mtk_smi_larb_get(struct device *larbdev)
112{
113 struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
114 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
115 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
116 int ret;
117
118 /* Enable the smi-common's power and clocks */
119 ret = mtk_smi_enable(common);
120 if (ret)
121 return ret;
122
123 /* Enable the larb's power and clocks */
124 ret = mtk_smi_enable(&larb->smi);
125 if (ret) {
126 mtk_smi_disable(common);
127 return ret;
128 }
129
130 /* Configure the iommu info for this larb */
131 larb_gen->config_port(larbdev);
132
133 return 0;
134}
135EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
136
137void mtk_smi_larb_put(struct device *larbdev)
138{
139 struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
140 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
141
142 /*
143 * Don't de-configure the iommu info for this larb since there may be
144 * several modules in this larb.
145 * The iommu info will be reset after power off.
146 */
147
148 mtk_smi_disable(&larb->smi);
149 mtk_smi_disable(common);
150}
151EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
152
153static int
154mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
155{
156 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
157 struct mtk_smi_iommu *smi_iommu = data;
158 unsigned int i;
159
160 if (larb->larb_gen->need_larbid) {
161 larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
162 return 0;
163 }
164
165 /*
166 * If there is no larbid property, Loop to find the corresponding
167 * iommu information.
168 */
169 for (i = 0; i < smi_iommu->larb_nr; i++) {
170 if (dev == smi_iommu->larb_imu[i].dev) {
171 /* The 'mmu' may be updated in iommu-attach/detach. */
172 larb->mmu = &smi_iommu->larb_imu[i].mmu;
173 return 0;
174 }
175 }
176 return -ENODEV;
177}
178
179static void mtk_smi_larb_config_port_mt2712(struct device *dev)
180{
181 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
182 u32 reg;
183 int i;
184
185 /*
186 * larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly.
187 * Don't need to set it again.
188 */
189 if (larb->larbid == 8 || larb->larbid == 9)
190 return;
191
192 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
193 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
194 reg |= F_MMU_EN;
195 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
196 }
197}
198
199static void mtk_smi_larb_config_port_mt8173(struct device *dev)
200{
201 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
202
203 writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
204}
205
206static void mtk_smi_larb_config_port_gen1(struct device *dev)
207{
208 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
209 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
210 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
211 int i, m4u_port_id, larb_port_num;
212 u32 sec_con_val, reg_val;
213
214 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
215 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
216 - larb_gen->port_in_larb[larb->larbid];
217
218 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
219 if (*larb->mmu & BIT(i)) {
220 /* bit[port + 3] controls the virtual or physical */
221 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
222 } else {
223 /* do not need to enable m4u for this port */
224 continue;
225 }
226 reg_val = readl(common->smi_ao_base
227 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
228 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
229 reg_val |= sec_con_val;
230 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
231 writel(reg_val,
232 common->smi_ao_base
233 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
234 }
235}
236
237static void
238mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
239{
240 /* Do nothing as the iommu is always enabled. */
241}
242
243static const struct component_ops mtk_smi_larb_component_ops = {
244 .bind = mtk_smi_larb_bind,
245 .unbind = mtk_smi_larb_unbind,
246};
247
248static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
249 /* mt8173 do not need the port in larb */
250 .config_port = mtk_smi_larb_config_port_mt8173,
251};
252
253static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
254 .need_larbid = true,
255 .port_in_larb = {
256 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
257 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
258 },
259 .config_port = mtk_smi_larb_config_port_gen1,
260};
261
262static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
263 .need_larbid = true,
264 .config_port = mtk_smi_larb_config_port_mt2712,
265};
266
267static const struct of_device_id mtk_smi_larb_of_ids[] = {
268 {
269 .compatible = "mediatek,mt8173-smi-larb",
270 .data = &mtk_smi_larb_mt8173
271 },
272 {
273 .compatible = "mediatek,mt2701-smi-larb",
274 .data = &mtk_smi_larb_mt2701
275 },
276 {
277 .compatible = "mediatek,mt2712-smi-larb",
278 .data = &mtk_smi_larb_mt2712
279 },
280 {}
281};
282
283static int mtk_smi_larb_probe(struct platform_device *pdev)
284{
285 struct mtk_smi_larb *larb;
286 struct resource *res;
287 struct device *dev = &pdev->dev;
288 struct device_node *smi_node;
289 struct platform_device *smi_pdev;
290 int err;
291
292 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
293 if (!larb)
294 return -ENOMEM;
295
296 larb->larb_gen = of_device_get_match_data(dev);
297 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
298 larb->base = devm_ioremap_resource(dev, res);
299 if (IS_ERR(larb->base))
300 return PTR_ERR(larb->base);
301
302 larb->smi.clk_apb = devm_clk_get(dev, "apb");
303 if (IS_ERR(larb->smi.clk_apb))
304 return PTR_ERR(larb->smi.clk_apb);
305
306 larb->smi.clk_smi = devm_clk_get(dev, "smi");
307 if (IS_ERR(larb->smi.clk_smi))
308 return PTR_ERR(larb->smi.clk_smi);
309 larb->smi.dev = dev;
310
311 if (larb->larb_gen->need_larbid) {
312 err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
313 &larb->larbid);
314 if (err) {
315 dev_err(dev, "missing larbid property\n");
316 return err;
317 }
318 }
319
320 smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
321 if (!smi_node)
322 return -EINVAL;
323
324 smi_pdev = of_find_device_by_node(smi_node);
325 of_node_put(smi_node);
326 if (smi_pdev) {
327 if (!platform_get_drvdata(smi_pdev))
328 return -EPROBE_DEFER;
329 larb->smi_common_dev = &smi_pdev->dev;
330 } else {
331 dev_err(dev, "Failed to get the smi_common device\n");
332 return -EINVAL;
333 }
334
335 pm_runtime_enable(dev);
336 platform_set_drvdata(pdev, larb);
337 return component_add(dev, &mtk_smi_larb_component_ops);
338}
339
340static int mtk_smi_larb_remove(struct platform_device *pdev)
341{
342 pm_runtime_disable(&pdev->dev);
343 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
344 return 0;
345}
346
347static struct platform_driver mtk_smi_larb_driver = {
348 .probe = mtk_smi_larb_probe,
349 .remove = mtk_smi_larb_remove,
350 .driver = {
351 .name = "mtk-smi-larb",
352 .of_match_table = mtk_smi_larb_of_ids,
353 }
354};
355
356static const struct of_device_id mtk_smi_common_of_ids[] = {
357 {
358 .compatible = "mediatek,mt8173-smi-common",
359 .data = (void *)MTK_SMI_GEN2
360 },
361 {
362 .compatible = "mediatek,mt2701-smi-common",
363 .data = (void *)MTK_SMI_GEN1
364 },
365 {
366 .compatible = "mediatek,mt2712-smi-common",
367 .data = (void *)MTK_SMI_GEN2
368 },
369 {}
370};
371
372static int mtk_smi_common_probe(struct platform_device *pdev)
373{
374 struct device *dev = &pdev->dev;
375 struct mtk_smi *common;
376 struct resource *res;
377 enum mtk_smi_gen smi_gen;
378 int ret;
379
380 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
381 if (!common)
382 return -ENOMEM;
383 common->dev = dev;
384
385 common->clk_apb = devm_clk_get(dev, "apb");
386 if (IS_ERR(common->clk_apb))
387 return PTR_ERR(common->clk_apb);
388
389 common->clk_smi = devm_clk_get(dev, "smi");
390 if (IS_ERR(common->clk_smi))
391 return PTR_ERR(common->clk_smi);
392
393 /*
394 * for mtk smi gen 1, we need to get the ao(always on) base to config
395 * m4u port, and we need to enable the aync clock for transform the smi
396 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
397 * base.
398 */
399 smi_gen = (enum mtk_smi_gen)of_device_get_match_data(dev);
400 if (smi_gen == MTK_SMI_GEN1) {
401 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
402 common->smi_ao_base = devm_ioremap_resource(dev, res);
403 if (IS_ERR(common->smi_ao_base))
404 return PTR_ERR(common->smi_ao_base);
405
406 common->clk_async = devm_clk_get(dev, "async");
407 if (IS_ERR(common->clk_async))
408 return PTR_ERR(common->clk_async);
409
410 ret = clk_prepare_enable(common->clk_async);
411 if (ret)
412 return ret;
413 }
414 pm_runtime_enable(dev);
415 platform_set_drvdata(pdev, common);
416 return 0;
417}
418
419static int mtk_smi_common_remove(struct platform_device *pdev)
420{
421 pm_runtime_disable(&pdev->dev);
422 return 0;
423}
424
425static struct platform_driver mtk_smi_common_driver = {
426 .probe = mtk_smi_common_probe,
427 .remove = mtk_smi_common_remove,
428 .driver = {
429 .name = "mtk-smi-common",
430 .of_match_table = mtk_smi_common_of_ids,
431 }
432};
433
434static int __init mtk_smi_init(void)
435{
436 int ret;
437
438 ret = platform_driver_register(&mtk_smi_common_driver);
439 if (ret != 0) {
440 pr_err("Failed to register SMI driver\n");
441 return ret;
442 }
443
444 ret = platform_driver_register(&mtk_smi_larb_driver);
445 if (ret != 0) {
446 pr_err("Failed to register SMI-LARB driver\n");
447 goto err_unreg_smi;
448 }
449 return ret;
450
451err_unreg_smi:
452 platform_driver_unregister(&mtk_smi_common_driver);
453 return ret;
454}
455
456module_init(mtk_smi_init);