1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2023 Intel Corporation
  4 */
  5
  6#include "xe_reg_whitelist.h"
  7
  8#include "regs/xe_engine_regs.h"
  9#include "regs/xe_gt_regs.h"
 10#include "xe_gt_types.h"
 11#include "xe_platform_types.h"
 12#include "xe_rtp.h"
 13
 14#undef XE_REG_MCR
 15#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
 16
 17static bool match_not_render(const struct xe_gt *gt,
 18			     const struct xe_hw_engine *hwe)
 19{
 20	return hwe->class != XE_ENGINE_CLASS_RENDER;
 21}
 22
 23static const struct xe_rtp_entry_sr register_whitelist[] = {
 24	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
 25	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 26	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
 27				   RING_FORCE_TO_NONPRIV_ACCESS_RD |
 28				   RING_FORCE_TO_NONPRIV_RANGE_4))
 29	},
 30	{ XE_RTP_NAME("1508744258, 14012131227, 1808121037"),
 31	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 32	  XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))
 33	},
 34	{ XE_RTP_NAME("1806527549"),
 35	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 36	  XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))
 37	},
 38	{ XE_RTP_NAME("allow_read_ctx_timestamp"),
 39	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)),
 40	  XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
 41				RING_FORCE_TO_NONPRIV_ACCESS_RD,
 42				XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 43	},
 44	{ XE_RTP_NAME("16014440446"),
 45	  XE_RTP_RULES(PLATFORM(PVC)),
 46	  XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
 47				   RING_FORCE_TO_NONPRIV_DENY |
 48				   RING_FORCE_TO_NONPRIV_RANGE_64),
 49			 WHITELIST(XE_REG(0x4500),
 50				   RING_FORCE_TO_NONPRIV_DENY |
 51				   RING_FORCE_TO_NONPRIV_RANGE_64))
 52	},
 53	{ XE_RTP_NAME("16017236439"),
 54	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY)),
 55	  XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0),
 56				   RING_FORCE_TO_NONPRIV_DENY,
 57				   XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 58	},
 59	{}
 60};
 61
 62/**
 63 * xe_reg_whitelist_process_engine - process table of registers to whitelist
 64 * @hwe: engine instance to process whitelist for
 65 *
 66 * Process wwhitelist table for this platform, saving in @hwe all the
 67 * registers that need to be whitelisted by the hardware so they can be accessed
 68 * by userspace.
 69 */
 70void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 71{
 72	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
 73
 74	xe_rtp_process_to_sr(&ctx, register_whitelist, &hwe->reg_whitelist);
 75}
 76
 77/**
 78 * xe_reg_whitelist_print_entry - print one whitelist entry
 79 * @p: DRM printer
 80 * @indent: indent level
 81 * @reg: register allowed/denied
 82 * @entry: save-restore entry
 83 *
 84 * Print details about the entry added to allow/deny access
 85 */
 86void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
 87				  u32 reg, struct xe_reg_sr_entry *entry)
 88{
 89	u32 val = entry->set_bits;
 90	const char *access_str = "(invalid)";
 91	unsigned int range_bit = 2;
 92	u32 range_start, range_end;
 93	bool deny;
 94
 95	deny = val & RING_FORCE_TO_NONPRIV_DENY;
 96
 97	switch (val & RING_FORCE_TO_NONPRIV_RANGE_MASK) {
 98	case RING_FORCE_TO_NONPRIV_RANGE_4:
 99		range_bit = 4;
100		break;
101	case RING_FORCE_TO_NONPRIV_RANGE_16:
102		range_bit = 6;
103		break;
104	case RING_FORCE_TO_NONPRIV_RANGE_64:
105		range_bit = 8;
106		break;
107	}
108
109	range_start = reg & REG_GENMASK(25, range_bit);
110	range_end = range_start | REG_GENMASK(range_bit, 0);
111
112	switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) {
113	case RING_FORCE_TO_NONPRIV_ACCESS_RW:
114		access_str = "rw";
115		break;
116	case RING_FORCE_TO_NONPRIV_ACCESS_RD:
117		access_str = "read";
118		break;
119	case RING_FORCE_TO_NONPRIV_ACCESS_WR:
120		access_str = "write";
121		break;
122	}
123
124	drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n",
125			  range_start, range_end,
126			  deny ? "deny" : "allow",
127			  access_str);
128}
129
130/**
131 * xe_reg_whitelist_dump - print all whitelist entries
132 * @sr: Save/restore entries
133 * @p: DRM printer
134 */
135void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p)
136{
137	struct xe_reg_sr_entry *entry;
138	unsigned long reg;
139
140	if (!sr->name || xa_empty(&sr->xa))
141		return;
142
143	drm_printf(p, "%s\n", sr->name);
144	xa_for_each(&sr->xa, reg, entry)
145		xe_reg_whitelist_print_entry(p, 1, reg, entry);
146}