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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
4 * Copyright (C) 2016 ROCKCHIP, Inc.
5 */
6
7#ifndef _CDN_DP_CORE_H
8#define _CDN_DP_CORE_H
9
10#include <drm/display/drm_dp_helper.h>
11#include <drm/drm_panel.h>
12#include <drm/drm_probe_helper.h>
13#include <sound/hdmi-codec.h>
14
15#include "rockchip_drm_drv.h"
16
17#define MAX_PHY 2
18
19enum audio_format {
20 AFMT_I2S = 0,
21 AFMT_SPDIF = 1,
22 AFMT_UNUSED,
23};
24
25struct audio_info {
26 enum audio_format format;
27 int sample_rate;
28 int channels;
29 int sample_width;
30};
31
32enum vic_pxl_encoding_format {
33 PXL_RGB = 0x1,
34 YCBCR_4_4_4 = 0x2,
35 YCBCR_4_2_2 = 0x4,
36 YCBCR_4_2_0 = 0x8,
37 Y_ONLY = 0x10,
38};
39
40struct video_info {
41 bool h_sync_polarity;
42 bool v_sync_polarity;
43 bool interlaced;
44 int color_depth;
45 enum vic_pxl_encoding_format color_fmt;
46};
47
48struct cdn_firmware_header {
49 u32 size_bytes; /* size of the entire header+image(s) in bytes */
50 u32 header_size; /* size of just the header in bytes */
51 u32 iram_size; /* size of iram */
52 u32 dram_size; /* size of dram */
53};
54
55struct cdn_dp_port {
56 struct cdn_dp_device *dp;
57 struct notifier_block event_nb;
58 struct extcon_dev *extcon;
59 struct phy *phy;
60 u8 lanes;
61 bool phy_enabled;
62 u8 id;
63};
64
65struct cdn_dp_device {
66 struct device *dev;
67 struct drm_device *drm_dev;
68 struct drm_connector connector;
69 struct rockchip_encoder encoder;
70 struct drm_display_mode mode;
71 struct platform_device *audio_pdev;
72 struct work_struct event_work;
73 struct edid *edid;
74
75 struct mutex lock;
76 bool connected;
77 bool active;
78 bool suspended;
79
80 const struct firmware *fw; /* cdn dp firmware */
81 unsigned int fw_version; /* cdn fw version */
82 bool fw_loaded;
83
84 void __iomem *regs;
85 struct regmap *grf;
86 struct clk *core_clk;
87 struct clk *pclk;
88 struct clk *spdif_clk;
89 struct clk *grf_clk;
90 struct reset_control *spdif_rst;
91 struct reset_control *dptx_rst;
92 struct reset_control *apb_rst;
93 struct reset_control *core_rst;
94 struct audio_info audio_info;
95 struct video_info video_info;
96 struct cdn_dp_port *port[MAX_PHY];
97 u8 ports;
98 u8 max_lanes;
99 unsigned int max_rate;
100 u8 lanes;
101 int active_port;
102
103 u8 dpcd[DP_RECEIVER_CAP_SIZE];
104 bool sink_has_audio;
105
106 hdmi_codec_plugged_cb plugged_cb;
107 struct device *codec_dev;
108};
109#endif /* _CDN_DP_CORE_H */
1/*
2 * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
3 * Copyright (C) 2016 ROCKCHIP, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _CDN_DP_CORE_H
16#define _CDN_DP_CORE_H
17
18#include <drm/drmP.h>
19#include <drm/drm_crtc_helper.h>
20#include <drm/drm_dp_helper.h>
21#include <drm/drm_panel.h>
22#include "rockchip_drm_drv.h"
23
24#define MAX_PHY 2
25
26enum audio_format {
27 AFMT_I2S = 0,
28 AFMT_SPDIF = 1,
29 AFMT_UNUSED,
30};
31
32struct audio_info {
33 enum audio_format format;
34 int sample_rate;
35 int channels;
36 int sample_width;
37};
38
39enum vic_pxl_encoding_format {
40 PXL_RGB = 0x1,
41 YCBCR_4_4_4 = 0x2,
42 YCBCR_4_2_2 = 0x4,
43 YCBCR_4_2_0 = 0x8,
44 Y_ONLY = 0x10,
45};
46
47struct video_info {
48 bool h_sync_polarity;
49 bool v_sync_polarity;
50 bool interlaced;
51 int color_depth;
52 enum vic_pxl_encoding_format color_fmt;
53};
54
55struct cdn_firmware_header {
56 u32 size_bytes; /* size of the entire header+image(s) in bytes */
57 u32 header_size; /* size of just the header in bytes */
58 u32 iram_size; /* size of iram */
59 u32 dram_size; /* size of dram */
60};
61
62struct cdn_dp_port {
63 struct cdn_dp_device *dp;
64 struct notifier_block event_nb;
65 struct extcon_dev *extcon;
66 struct phy *phy;
67 u8 lanes;
68 bool phy_enabled;
69 u8 id;
70};
71
72struct cdn_dp_device {
73 struct device *dev;
74 struct drm_device *drm_dev;
75 struct drm_connector connector;
76 struct drm_encoder encoder;
77 struct drm_display_mode mode;
78 struct platform_device *audio_pdev;
79 struct work_struct event_work;
80 struct edid *edid;
81
82 struct mutex lock;
83 bool connected;
84 bool active;
85 bool suspended;
86
87 const struct firmware *fw; /* cdn dp firmware */
88 unsigned int fw_version; /* cdn fw version */
89 bool fw_loaded;
90
91 void __iomem *regs;
92 struct regmap *grf;
93 struct clk *core_clk;
94 struct clk *pclk;
95 struct clk *spdif_clk;
96 struct clk *grf_clk;
97 struct reset_control *spdif_rst;
98 struct reset_control *dptx_rst;
99 struct reset_control *apb_rst;
100 struct reset_control *core_rst;
101 struct audio_info audio_info;
102 struct video_info video_info;
103 struct drm_dp_link link;
104 struct cdn_dp_port *port[MAX_PHY];
105 u8 ports;
106 u8 lanes;
107 int active_port;
108
109 u8 dpcd[DP_RECEIVER_CAP_SIZE];
110 bool sink_has_audio;
111};
112#endif /* _CDN_DP_CORE_H */