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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <drm/drm_drv.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_vpe.h"
29#include "vpe_v6_1.h"
30#include "soc15_common.h"
31#include "ivsrcid/vpe/irqsrcs_vpe_6_1.h"
32#include "vpe/vpe_6_1_0_offset.h"
33#include "vpe/vpe_6_1_0_sh_mask.h"
34
35MODULE_FIRMWARE("amdgpu/vpe_6_1_0.bin");
36
37#define VPE_THREAD1_UCODE_OFFSET 0x8000
38
39static uint32_t vpe_v6_1_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)
40{
41 uint32_t base;
42
43 base = vpe->ring.adev->reg_offset[VPE_HWIP][0][0];
44
45 return base + offset;
46}
47
48static void vpe_v6_1_halt(struct amdgpu_vpe *vpe, bool halt)
49{
50 struct amdgpu_device *adev = vpe->ring.adev;
51 uint32_t f32_cntl;
52
53 f32_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL));
54 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0);
55 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, halt ? 1 : 0);
56 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);
57}
58
59static int vpe_v6_1_irq_init(struct amdgpu_vpe *vpe)
60{
61 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
62 int ret;
63
64 ret = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VPE,
65 VPE_6_1_SRCID__VPE_TRAP,
66 &adev->vpe.trap_irq);
67 if (ret)
68 return ret;
69
70 return 0;
71}
72
73static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)
74{
75 struct amdgpu_device *adev = vpe->ring.adev;
76 const struct vpe_firmware_header_v1_0 *vpe_hdr;
77 const __le32 *data;
78 uint32_t ucode_offset[2], ucode_size[2];
79 uint32_t i, size_dw;
80 uint32_t ret;
81
82 // disable UMSCH_INT_ENABLE
83 ret = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));
84 ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0);
85 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), ret);
86
87 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
88 uint32_t f32_offset, f32_cntl;
89
90 f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);
91 f32_cntl = RREG32(f32_offset);
92 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);
93 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0);
94
95 adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;
96 adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;
97
98 amdgpu_vpe_psp_update_sram(adev);
99
100 /* Config DPM */
101 amdgpu_vpe_configure_dpm(vpe);
102
103 return 0;
104 }
105
106 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
107
108 /* Thread 0(command thread) ucode offset/size */
109 ucode_offset[0] = le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes);
110 ucode_size[0] = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes);
111 /* Thread 1(control thread) ucode offset/size */
112 ucode_offset[1] = le32_to_cpu(vpe_hdr->ctl_ucode_offset);
113 ucode_size[1] = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes);
114
115 vpe_v6_1_halt(vpe, true);
116
117 for (i = 0; i < 2; i++) {
118 if (i > 0)
119 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET);
120 else
121 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_ADDR), 0);
122
123 data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]);
124 size_dw = ucode_size[i] / sizeof(__le32);
125
126 while (size_dw--) {
127 if (amdgpu_emu_mode && size_dw % 500 == 0)
128 msleep(1);
129 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_DATA), le32_to_cpup(data++));
130 }
131
132 }
133
134 vpe_v6_1_halt(vpe, false);
135 /* Config DPM */
136 amdgpu_vpe_configure_dpm(vpe);
137
138 return 0;
139}
140
141static int vpe_v6_1_ring_start(struct amdgpu_vpe *vpe)
142{
143 struct amdgpu_ring *ring = &vpe->ring;
144 struct amdgpu_device *adev = ring->adev;
145 uint32_t rb_bufsz, rb_cntl;
146 uint32_t ib_cntl;
147 uint32_t doorbell, doorbell_offset;
148 int ret;
149
150 rb_bufsz = order_base_2(ring->ring_size / 4);
151 rb_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_CNTL));
152 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
153 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1);
154 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0);
155 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_CNTL), rb_cntl);
156
157 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_RPTR), 0);
158 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_RPTR_HI), 0);
159 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_WPTR), 0);
160 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_WPTR_HI), 0);
161
162 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_RPTR_ADDR_LO),
163 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
164 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_RPTR_ADDR_HI),
165 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
166
167 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
168 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
169
170 ring->wptr = 0;
171
172 /* before programing wptr to a less value, need set minor_ptr_update first */
173 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1);
174
175 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
176 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
177
178 /* set minor_ptr_update to 0 after wptr programed */
179 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0);
180
181 doorbell = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_DOORBELL));
182 doorbell_offset = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_DOORBELL_OFFSET));
183
184 doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0);
185 doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbell_index);
186
187 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_DOORBELL), doorbell);
188 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
189
190 adev->nbio.funcs->vpe_doorbell_range(adev, 0, ring->use_doorbell, ring->doorbell_index, 2);
191
192 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
193 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1);
194 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_CNTL), rb_cntl);
195
196 ib_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_IB_CNTL));
197 ib_cntl = REG_SET_FIELD(ib_cntl, VPEC_QUEUE0_IB_CNTL, IB_ENABLE, 1);
198 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_IB_CNTL), ib_cntl);
199
200 ring->sched.ready = true;
201
202 ret = amdgpu_ring_test_helper(ring);
203 if (ret) {
204 ring->sched.ready = false;
205 return ret;
206 }
207
208 return 0;
209}
210
211static int vpe_v_6_1_ring_stop(struct amdgpu_vpe *vpe)
212{
213 struct amdgpu_device *adev = vpe->ring.adev;
214 uint32_t queue_reset;
215 int ret;
216
217 queue_reset = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE_RESET_REQ));
218 queue_reset = REG_SET_FIELD(queue_reset, VPEC_QUEUE_RESET_REQ, QUEUE0_RESET, 1);
219 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE_RESET_REQ), queue_reset);
220
221 ret = SOC15_WAIT_ON_RREG(VPE, 0, regVPEC_QUEUE_RESET_REQ, 0,
222 VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK);
223 if (ret)
224 dev_err(adev->dev, "VPE queue reset failed\n");
225
226 vpe->ring.sched.ready = false;
227
228 return ret;
229}
230
231static int vpe_v6_1_set_trap_irq_state(struct amdgpu_device *adev,
232 struct amdgpu_irq_src *source,
233 unsigned int type,
234 enum amdgpu_interrupt_state state)
235{
236 struct amdgpu_vpe *vpe = &adev->vpe;
237 uint32_t vpe_cntl;
238
239 vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));
240 vpe_cntl = REG_SET_FIELD(vpe_cntl, VPEC_CNTL, TRAP_ENABLE,
241 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
242 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl);
243
244 return 0;
245}
246
247static int vpe_v6_1_process_trap_irq(struct amdgpu_device *adev,
248 struct amdgpu_irq_src *source,
249 struct amdgpu_iv_entry *entry)
250{
251
252 dev_dbg(adev->dev, "IH: VPE trap\n");
253
254 switch (entry->client_id) {
255 case SOC21_IH_CLIENTID_VPE:
256 amdgpu_fence_process(&adev->vpe.ring);
257 break;
258 default:
259 break;
260 }
261
262 return 0;
263}
264
265static int vpe_v6_1_set_regs(struct amdgpu_vpe *vpe)
266{
267 vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR;
268 vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI;
269 vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR;
270 vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI;
271 vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT;
272
273 vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2;
274 vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4;
275 vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3;
276 vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4;
277 vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2;
278 vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3;
279 vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1;
280 vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3;
281
282 return 0;
283}
284
285static const struct vpe_funcs vpe_v6_1_funcs = {
286 .get_reg_offset = vpe_v6_1_get_reg_offset,
287 .set_regs = vpe_v6_1_set_regs,
288 .irq_init = vpe_v6_1_irq_init,
289 .init_microcode = amdgpu_vpe_init_microcode,
290 .load_microcode = vpe_v6_1_load_microcode,
291 .ring_init = amdgpu_vpe_ring_init,
292 .ring_start = vpe_v6_1_ring_start,
293 .ring_stop = vpe_v_6_1_ring_stop,
294 .ring_fini = amdgpu_vpe_ring_fini,
295};
296
297static const struct amdgpu_irq_src_funcs vpe_v6_1_trap_irq_funcs = {
298 .set = vpe_v6_1_set_trap_irq_state,
299 .process = vpe_v6_1_process_trap_irq,
300};
301
302void vpe_v6_1_set_funcs(struct amdgpu_vpe *vpe)
303{
304 vpe->funcs = &vpe_v6_1_funcs;
305 vpe->trap_irq.funcs = &vpe_v6_1_trap_irq_funcs;
306}