1/*
  2 * Copyright 2019 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#ifndef _TA_RAS_IF_H
 25#define _TA_RAS_IF_H
 26
 27#define RAS_TA_HOST_IF_VER	0
 28
 29/* Responses have bit 31 set */
 30#define RSP_ID_MASK (1U << 31)
 31#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
 32
 33/* RAS related enumerations */
 34/**********************************************************/
 35enum ras_command {
 36	TA_RAS_COMMAND__ENABLE_FEATURES = 0,
 37	TA_RAS_COMMAND__DISABLE_FEATURES,
 38	TA_RAS_COMMAND__TRIGGER_ERROR,
 39};
 40
 41enum ta_ras_status {
 42	TA_RAS_STATUS__SUCCESS                          = 0x0000,
 43	TA_RAS_STATUS__RESET_NEEDED                     = 0xA001,
 44	TA_RAS_STATUS__ERROR_INVALID_PARAMETER          = 0xA002,
 45	TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE          = 0xA003,
 46	TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD          = 0xA004,
 47	TA_RAS_STATUS__ERROR_INJECTION_FAILED           = 0xA005,
 48	TA_RAS_STATUS__ERROR_ASD_READ_WRITE             = 0xA006,
 49	TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE           = 0xA007,
 50	TA_RAS_STATUS__ERROR_TIMEOUT                    = 0xA008,
 51	TA_RAS_STATUS__ERROR_BLOCK_DISABLED             = 0XA009,
 52	TA_RAS_STATUS__ERROR_GENERIC                    = 0xA00A,
 53	TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT             = 0xA00B,
 54	TA_RAS_STATUS__ERROR_GET_DEV_INFO               = 0xA00C,
 55	TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV            = 0xA00D,
 56	TA_RAS_STATUS__ERROR_NOT_INITIALIZED            = 0xA00E,
 57	TA_RAS_STATUS__ERROR_TEE_INTERNAL               = 0xA00F,
 58	TA_RAS_STATUS__ERROR_UNSUPPORTED_FUNCTION       = 0xA010,
 59	TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS         = 0xA011,
 60	TA_RAS_STATUS__ERROR_RAS_READ_WRITE             = 0xA012,
 61	TA_RAS_STATUS__ERROR_NULL_PTR                   = 0xA013,
 62	TA_RAS_STATUS__ERROR_UNSUPPORTED_IP             = 0xA014,
 63	TA_RAS_STATUS__ERROR_PCS_STATE_QUIET            = 0xA015,
 64	TA_RAS_STATUS__ERROR_PCS_STATE_ERROR            = 0xA016,
 65	TA_RAS_STATUS__ERROR_PCS_STATE_HANG             = 0xA017,
 66	TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN          = 0xA018,
 67	TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ      = 0xA019,
 68	TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED          = 0xA01A
 69};
 70
 71enum ta_ras_block {
 72	TA_RAS_BLOCK__UMC = 0,
 73	TA_RAS_BLOCK__SDMA,
 74	TA_RAS_BLOCK__GFX,
 75	TA_RAS_BLOCK__MMHUB,
 76	TA_RAS_BLOCK__ATHUB,
 77	TA_RAS_BLOCK__PCIE_BIF,
 78	TA_RAS_BLOCK__HDP,
 79	TA_RAS_BLOCK__XGMI_WAFL,
 80	TA_RAS_BLOCK__DF,
 81	TA_RAS_BLOCK__SMN,
 82	TA_RAS_BLOCK__SEM,
 83	TA_RAS_BLOCK__MP0,
 84	TA_RAS_BLOCK__MP1,
 85	TA_RAS_BLOCK__FUSE,
 86	TA_RAS_BLOCK__MCA,
 87	TA_RAS_BLOCK__VCN,
 88	TA_RAS_BLOCK__JPEG,
 89	TA_NUM_BLOCK_MAX
 90};
 91
 92enum ta_ras_mca_block {
 93	TA_RAS_MCA_BLOCK__MP0   = 0,
 94	TA_RAS_MCA_BLOCK__MP1   = 1,
 95	TA_RAS_MCA_BLOCK__MPIO  = 2,
 96	TA_RAS_MCA_BLOCK__IOHC  = 3,
 97	TA_MCA_NUM_BLOCK_MAX
 98};
 99
100enum ta_ras_error_type {
101	TA_RAS_ERROR__NONE			= 0,
102	TA_RAS_ERROR__PARITY			= 1,
103	TA_RAS_ERROR__SINGLE_CORRECTABLE	= 2,
104	TA_RAS_ERROR__MULTI_UNCORRECTABLE	= 4,
105	TA_RAS_ERROR__POISON			= 8,
106};
107
108/* Input/output structures for RAS commands */
109/**********************************************************/
110
111struct ta_ras_enable_features_input {
112	enum ta_ras_block	block_id;
113	enum ta_ras_error_type	error_type;
114};
115
116struct ta_ras_disable_features_input {
117	enum ta_ras_block	block_id;
118	enum ta_ras_error_type	error_type;
119};
120
121struct ta_ras_trigger_error_input {
122	enum ta_ras_block	block_id;		// ras-block. i.e. umc, gfx
123	enum ta_ras_error_type	inject_error_type;	// type of error. i.e. single_correctable
124	uint32_t		sub_block_index;	// mem block. i.e. hbm, sram etc.
125	uint64_t		address;		// explicit address of error
126	uint64_t		value;			// method if error injection. i.e persistent, coherent etc.
127};
128
129struct ta_ras_init_flags {
130	uint8_t poison_mode_en;
131	uint8_t dgpu_mode;
132	uint16_t xcc_mask;
133	uint8_t channel_dis_num;
134};
135
136struct ta_ras_output_flags {
137	uint8_t ras_init_success_flag;
138	uint8_t err_inject_switch_disable_flag;
139	uint8_t reg_access_failure_flag;
140};
141
142/* Common input structure for RAS callbacks */
143/**********************************************************/
144union ta_ras_cmd_input {
145	struct ta_ras_init_flags		init_flags;
146	struct ta_ras_enable_features_input	enable_features;
147	struct ta_ras_disable_features_input	disable_features;
148	struct ta_ras_trigger_error_input	trigger_error;
149
150	uint32_t reserve_pad[256];
151};
152
153union ta_ras_cmd_output {
154	struct ta_ras_output_flags flags;
155
156	uint32_t reserve_pad[256];
157};
158
159/* Shared Memory structures */
160/**********************************************************/
161struct ta_ras_shared_memory {
162	uint32_t		    cmd_id;
163	uint32_t		    resp_id;
164	uint32_t	    	    ras_status;
165	uint32_t		    if_version;
166	union ta_ras_cmd_input	    ras_in_message;
167	union ta_ras_cmd_output     ras_out_message;
168};
169
170#endif // TL_RAS_IF_H_