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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _AMDGPU_RAS_H
25#define _AMDGPU_RAS_H
26
27#include <linux/debugfs.h>
28#include <linux/list.h>
29#include "ta_ras_if.h"
30#include "amdgpu_ras_eeprom.h"
31#include "amdgpu_smuio.h"
32
33struct amdgpu_iv_entry;
34
35#define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0)
36/* position of instance value in sub_block_index of
37 * ta_ras_trigger_error_input, the sub block uses lower 12 bits
38 */
39#define AMDGPU_RAS_INST_MASK 0xfffff000
40#define AMDGPU_RAS_INST_SHIFT 0xc
41
42enum amdgpu_ras_block {
43 AMDGPU_RAS_BLOCK__UMC = 0,
44 AMDGPU_RAS_BLOCK__SDMA,
45 AMDGPU_RAS_BLOCK__GFX,
46 AMDGPU_RAS_BLOCK__MMHUB,
47 AMDGPU_RAS_BLOCK__ATHUB,
48 AMDGPU_RAS_BLOCK__PCIE_BIF,
49 AMDGPU_RAS_BLOCK__HDP,
50 AMDGPU_RAS_BLOCK__XGMI_WAFL,
51 AMDGPU_RAS_BLOCK__DF,
52 AMDGPU_RAS_BLOCK__SMN,
53 AMDGPU_RAS_BLOCK__SEM,
54 AMDGPU_RAS_BLOCK__MP0,
55 AMDGPU_RAS_BLOCK__MP1,
56 AMDGPU_RAS_BLOCK__FUSE,
57 AMDGPU_RAS_BLOCK__MCA,
58 AMDGPU_RAS_BLOCK__VCN,
59 AMDGPU_RAS_BLOCK__JPEG,
60
61 AMDGPU_RAS_BLOCK__LAST
62};
63
64enum amdgpu_ras_mca_block {
65 AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
66 AMDGPU_RAS_MCA_BLOCK__MP1,
67 AMDGPU_RAS_MCA_BLOCK__MPIO,
68 AMDGPU_RAS_MCA_BLOCK__IOHC,
69
70 AMDGPU_RAS_MCA_BLOCK__LAST
71};
72
73#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
74#define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST
75#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
76
77enum amdgpu_ras_gfx_subblock {
78 /* CPC */
79 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
80 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
81 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
82 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
83 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
84 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
85 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
86 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
87 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
88 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
89 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
90 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
91 /* CPF */
92 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
93 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
94 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
95 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
96 AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
97 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
98 /* CPG */
99 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
100 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
101 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
102 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
103 AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
104 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
105 /* GDS */
106 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
107 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
108 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
109 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
110 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
111 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
112 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
113 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
114 /* SPI */
115 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
116 /* SQ */
117 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
118 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
119 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
120 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
121 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
122 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
123 /* SQC (3 ranges) */
124 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
125 /* SQC range 0 */
126 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
127 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
128 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
129 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
130 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
131 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
132 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
133 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
134 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
135 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
136 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
137 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
138 /* SQC range 1 */
139 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
140 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
141 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
142 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
143 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
144 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
145 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
146 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
147 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
148 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
149 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
150 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
151 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
152 /* SQC range 2 */
153 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
154 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
155 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
156 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
157 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
158 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
159 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
160 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
161 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
162 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
163 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
164 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
165 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
166 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
167 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
168 /* TA */
169 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
170 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
171 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
172 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
173 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
174 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
175 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
176 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
177 /* TCA */
178 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
179 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
180 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
181 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
182 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
183 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
184 /* TCC (5 sub-ranges) */
185 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
186 /* TCC range 0 */
187 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
188 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
189 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
190 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
191 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
192 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
193 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
194 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
195 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
196 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
197 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
198 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
199 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
200 /* TCC range 1 */
201 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
202 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
203 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
204 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
205 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
206 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
207 /* TCC range 2 */
208 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
209 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
210 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
211 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
212 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
213 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
214 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
215 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
216 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
217 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
218 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
219 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
220 /* TCC range 3 */
221 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
222 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
223 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
224 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
225 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
226 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
227 /* TCC range 4 */
228 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
229 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
230 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
231 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
232 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
233 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
234 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
235 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
236 /* TCI */
237 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
238 /* TCP */
239 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
240 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
241 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
242 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
243 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
244 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
245 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
246 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
247 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
248 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
249 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
250 /* TD */
251 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
252 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
253 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
254 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
255 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
256 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
257 /* EA (3 sub-ranges) */
258 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
259 /* EA range 0 */
260 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
261 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
262 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
263 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
264 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
265 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
266 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
267 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
268 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
269 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
270 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
271 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
272 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
273 /* EA range 1 */
274 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
275 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
276 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
277 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
278 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
279 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
280 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
281 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
282 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
283 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
284 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
285 /* EA range 2 */
286 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
287 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
288 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
289 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
290 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
291 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
292 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
293 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
294 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
295 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
296 /* UTC VM L2 bank */
297 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
298 /* UTC VM walker */
299 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
300 /* UTC ATC L2 2MB cache */
301 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
302 /* UTC ATC L2 4KB cache */
303 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
304 AMDGPU_RAS_BLOCK__GFX_MAX
305};
306
307enum amdgpu_ras_error_type {
308 AMDGPU_RAS_ERROR__NONE = 0,
309 AMDGPU_RAS_ERROR__PARITY = 1,
310 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2,
311 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
312 AMDGPU_RAS_ERROR__POISON = 8,
313};
314
315enum amdgpu_ras_ret {
316 AMDGPU_RAS_SUCCESS = 0,
317 AMDGPU_RAS_FAIL,
318 AMDGPU_RAS_UE,
319 AMDGPU_RAS_CE,
320 AMDGPU_RAS_PT,
321};
322
323enum amdgpu_ras_error_query_mode {
324 AMDGPU_RAS_INVALID_ERROR_QUERY = 0,
325 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1,
326 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2,
327};
328
329/* ras error status reisger fields */
330#define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
331#define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
332#define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
333#define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
334#define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
335#define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
336#define ERR_STATUS__ERR_CNT__SHIFT 0x17
337#define ERR_STATUS__ERR_CNT_MASK 0x03800000L
338
339#define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
340 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
341
342#define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
343 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
344
345#define AMDGPU_RAS_ERR_INFO_VALID (1 << 0)
346#define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1)
347#define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2)
348
349#define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0)
350#define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1)
351
352struct amdgpu_ras_err_status_reg_entry {
353 uint32_t hwip;
354 uint32_t ip_inst;
355 uint32_t seg_lo;
356 uint32_t reg_lo;
357 uint32_t seg_hi;
358 uint32_t reg_hi;
359 uint32_t reg_inst;
360 uint32_t flags;
361 const char *block_name;
362};
363
364struct amdgpu_ras_memory_id_entry {
365 uint32_t memory_id;
366 const char *name;
367};
368
369struct ras_common_if {
370 enum amdgpu_ras_block block;
371 enum amdgpu_ras_error_type type;
372 uint32_t sub_block_index;
373 char name[32];
374};
375
376#define MAX_UMC_CHANNEL_NUM 32
377
378struct ecc_info_per_ch {
379 uint16_t ce_count_lo_chip;
380 uint16_t ce_count_hi_chip;
381 uint64_t mca_umc_status;
382 uint64_t mca_umc_addr;
383 uint64_t mca_ceumc_addr;
384};
385
386struct umc_ecc_info {
387 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
388
389 /* Determine smu ecctable whether support
390 * record correctable error address
391 */
392 int record_ce_addr_supported;
393};
394
395struct amdgpu_ras {
396 /* ras infrastructure */
397 /* for ras itself. */
398 uint32_t features;
399 uint32_t schema;
400 struct list_head head;
401 /* sysfs */
402 struct device_attribute features_attr;
403 struct device_attribute version_attr;
404 struct device_attribute schema_attr;
405 struct bin_attribute badpages_attr;
406 struct dentry *de_ras_eeprom_table;
407 /* block array */
408 struct ras_manager *objs;
409
410 /* gpu recovery */
411 struct work_struct recovery_work;
412 atomic_t in_recovery;
413 struct amdgpu_device *adev;
414 /* error handler data */
415 struct ras_err_handler_data *eh_data;
416 struct mutex recovery_lock;
417
418 uint32_t flags;
419 bool reboot;
420 struct amdgpu_ras_eeprom_control eeprom_control;
421
422 bool error_query_ready;
423
424 /* bad page count threshold */
425 uint32_t bad_page_cnt_threshold;
426
427 /* disable ras error count harvest in recovery */
428 bool disable_ras_err_cnt_harvest;
429
430 /* is poison mode supported */
431 bool poison_supported;
432
433 /* RAS count errors delayed work */
434 struct delayed_work ras_counte_delay_work;
435 atomic_t ras_ue_count;
436 atomic_t ras_ce_count;
437
438 /* record umc error info queried from smu */
439 struct umc_ecc_info umc_ecc;
440
441 /* Indicates smu whether need update bad channel info */
442 bool update_channel_flag;
443 /* Record status of smu mca debug mode */
444 bool is_mca_debug_mode;
445
446 /* Record special requirements of gpu reset caller */
447 uint32_t gpu_reset_flags;
448};
449
450struct ras_fs_data {
451 char sysfs_name[48];
452 char debugfs_name[32];
453};
454
455struct ras_err_addr {
456 uint64_t err_status;
457 uint64_t err_ipid;
458 uint64_t err_addr;
459};
460
461struct ras_err_info {
462 struct amdgpu_smuio_mcm_config_info mcm_info;
463 u64 ce_count;
464 u64 ue_count;
465 struct ras_err_addr err_addr;
466};
467
468struct ras_err_node {
469 struct list_head node;
470 struct ras_err_info err_info;
471};
472
473struct ras_err_data {
474 unsigned long ue_count;
475 unsigned long ce_count;
476 unsigned long err_addr_cnt;
477 struct eeprom_table_record *err_addr;
478 u32 err_list_count;
479 struct list_head err_node_list;
480};
481
482#define for_each_ras_error(err_node, err_data) \
483 list_for_each_entry(err_node, &(err_data)->err_node_list, node)
484
485struct ras_err_handler_data {
486 /* point to bad page records array */
487 struct eeprom_table_record *bps;
488 /* the count of entries */
489 int count;
490 /* the space can place new entries */
491 int space_left;
492};
493
494typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
495 void *err_data,
496 struct amdgpu_iv_entry *entry);
497
498struct ras_ih_data {
499 /* interrupt bottom half */
500 struct work_struct ih_work;
501 int inuse;
502 /* IP callback */
503 ras_ih_cb cb;
504 /* full of entries */
505 unsigned char *ring;
506 unsigned int ring_size;
507 unsigned int element_size;
508 unsigned int aligned_element_size;
509 unsigned int rptr;
510 unsigned int wptr;
511};
512
513struct ras_manager {
514 struct ras_common_if head;
515 /* reference count */
516 int use;
517 /* ras block link */
518 struct list_head node;
519 /* the device */
520 struct amdgpu_device *adev;
521 /* sysfs */
522 struct device_attribute sysfs_attr;
523 int attr_inuse;
524
525 /* fs node name */
526 struct ras_fs_data fs_data;
527
528 /* IH data */
529 struct ras_ih_data ih_data;
530
531 struct ras_err_data err_data;
532};
533
534struct ras_badpage {
535 unsigned int bp;
536 unsigned int size;
537 unsigned int flags;
538};
539
540/* interfaces for IP */
541struct ras_fs_if {
542 struct ras_common_if head;
543 const char* sysfs_name;
544 char debugfs_name[32];
545};
546
547struct ras_query_if {
548 struct ras_common_if head;
549 unsigned long ue_count;
550 unsigned long ce_count;
551};
552
553struct ras_inject_if {
554 struct ras_common_if head;
555 uint64_t address;
556 uint64_t value;
557 uint32_t instance_mask;
558};
559
560struct ras_cure_if {
561 struct ras_common_if head;
562 uint64_t address;
563};
564
565struct ras_ih_if {
566 struct ras_common_if head;
567 ras_ih_cb cb;
568};
569
570struct ras_dispatch_if {
571 struct ras_common_if head;
572 struct amdgpu_iv_entry *entry;
573};
574
575struct ras_debug_if {
576 union {
577 struct ras_common_if head;
578 struct ras_inject_if inject;
579 };
580 int op;
581};
582
583struct amdgpu_ras_block_object {
584 struct ras_common_if ras_comm;
585
586 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
587 enum amdgpu_ras_block block, uint32_t sub_block_index);
588 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
589 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
590 ras_ih_cb ras_cb;
591 const struct amdgpu_ras_block_hw_ops *hw_ops;
592};
593
594struct amdgpu_ras_block_hw_ops {
595 int (*ras_error_inject)(struct amdgpu_device *adev,
596 void *inject_if, uint32_t instance_mask);
597 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
598 void (*query_ras_error_status)(struct amdgpu_device *adev);
599 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
600 void (*reset_ras_error_count)(struct amdgpu_device *adev);
601 void (*reset_ras_error_status)(struct amdgpu_device *adev);
602 bool (*query_poison_status)(struct amdgpu_device *adev);
603 bool (*handle_poison_consumption)(struct amdgpu_device *adev);
604};
605
606/* work flow
607 * vbios
608 * 1: ras feature enable (enabled by default)
609 * psp
610 * 2: ras framework init (in ip_init)
611 * IP
612 * 3: IH add
613 * 4: debugfs/sysfs create
614 * 5: query/inject
615 * 6: debugfs/sysfs remove
616 * 7: IH remove
617 * 8: feature disable
618 */
619
620
621int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
622
623void amdgpu_ras_resume(struct amdgpu_device *adev);
624void amdgpu_ras_suspend(struct amdgpu_device *adev);
625
626int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
627 unsigned long *ce_count,
628 unsigned long *ue_count,
629 struct ras_query_if *query_info);
630
631/* error handling functions */
632int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
633 struct eeprom_table_record *bps, int pages);
634
635int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
636 unsigned long *new_cnt);
637
638static inline enum ta_ras_block
639amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
640 switch (block) {
641 case AMDGPU_RAS_BLOCK__UMC:
642 return TA_RAS_BLOCK__UMC;
643 case AMDGPU_RAS_BLOCK__SDMA:
644 return TA_RAS_BLOCK__SDMA;
645 case AMDGPU_RAS_BLOCK__GFX:
646 return TA_RAS_BLOCK__GFX;
647 case AMDGPU_RAS_BLOCK__MMHUB:
648 return TA_RAS_BLOCK__MMHUB;
649 case AMDGPU_RAS_BLOCK__ATHUB:
650 return TA_RAS_BLOCK__ATHUB;
651 case AMDGPU_RAS_BLOCK__PCIE_BIF:
652 return TA_RAS_BLOCK__PCIE_BIF;
653 case AMDGPU_RAS_BLOCK__HDP:
654 return TA_RAS_BLOCK__HDP;
655 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
656 return TA_RAS_BLOCK__XGMI_WAFL;
657 case AMDGPU_RAS_BLOCK__DF:
658 return TA_RAS_BLOCK__DF;
659 case AMDGPU_RAS_BLOCK__SMN:
660 return TA_RAS_BLOCK__SMN;
661 case AMDGPU_RAS_BLOCK__SEM:
662 return TA_RAS_BLOCK__SEM;
663 case AMDGPU_RAS_BLOCK__MP0:
664 return TA_RAS_BLOCK__MP0;
665 case AMDGPU_RAS_BLOCK__MP1:
666 return TA_RAS_BLOCK__MP1;
667 case AMDGPU_RAS_BLOCK__FUSE:
668 return TA_RAS_BLOCK__FUSE;
669 case AMDGPU_RAS_BLOCK__MCA:
670 return TA_RAS_BLOCK__MCA;
671 case AMDGPU_RAS_BLOCK__VCN:
672 return TA_RAS_BLOCK__VCN;
673 case AMDGPU_RAS_BLOCK__JPEG:
674 return TA_RAS_BLOCK__JPEG;
675 default:
676 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
677 return TA_RAS_BLOCK__UMC;
678 }
679}
680
681static inline enum ta_ras_error_type
682amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
683 switch (error) {
684 case AMDGPU_RAS_ERROR__NONE:
685 return TA_RAS_ERROR__NONE;
686 case AMDGPU_RAS_ERROR__PARITY:
687 return TA_RAS_ERROR__PARITY;
688 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
689 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
690 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
691 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
692 case AMDGPU_RAS_ERROR__POISON:
693 return TA_RAS_ERROR__POISON;
694 default:
695 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
696 return TA_RAS_ERROR__NONE;
697 }
698}
699
700/* called in ip_init and ip_fini */
701int amdgpu_ras_init(struct amdgpu_device *adev);
702int amdgpu_ras_late_init(struct amdgpu_device *adev);
703int amdgpu_ras_fini(struct amdgpu_device *adev);
704int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
705
706int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
707 struct ras_common_if *ras_block);
708
709void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
710 struct ras_common_if *ras_block);
711
712int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
713 struct ras_common_if *head, bool enable);
714
715int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
716 struct ras_common_if *head, bool enable);
717
718int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
719 struct ras_common_if *head);
720
721int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
722 struct ras_common_if *head);
723
724void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
725
726int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
727 struct ras_query_if *info);
728
729int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
730 enum amdgpu_ras_block block);
731int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
732 enum amdgpu_ras_block block);
733
734int amdgpu_ras_error_inject(struct amdgpu_device *adev,
735 struct ras_inject_if *info);
736
737int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
738 struct ras_common_if *head);
739
740int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
741 struct ras_common_if *head);
742
743int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
744 struct ras_dispatch_if *info);
745
746struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
747 struct ras_common_if *head);
748
749extern atomic_t amdgpu_ras_in_intr;
750
751static inline bool amdgpu_ras_intr_triggered(void)
752{
753 return !!atomic_read(&amdgpu_ras_in_intr);
754}
755
756static inline void amdgpu_ras_intr_cleared(void)
757{
758 atomic_set(&amdgpu_ras_in_intr, 0);
759}
760
761void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
762
763void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
764
765bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
766
767void amdgpu_release_ras_context(struct amdgpu_device *adev);
768
769int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
770
771const char *get_ras_block_str(struct ras_common_if *ras_block);
772
773bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
774
775int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
776
777int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
778
779struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
780
781int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
782
783int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);
784bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev);
785bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
786 unsigned int *mode);
787
788int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
789 struct amdgpu_ras_block_object *ras_block_obj);
790void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
791void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);
792bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
793 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
794 uint32_t instance,
795 uint32_t *memory_id);
796bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
797 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
798 uint32_t instance,
799 unsigned long *err_cnt);
800void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
801 const struct amdgpu_ras_err_status_reg_entry *reg_list,
802 uint32_t reg_list_size,
803 const struct amdgpu_ras_memory_id_entry *mem_list,
804 uint32_t mem_list_size,
805 uint32_t instance,
806 uint32_t err_type,
807 unsigned long *err_count);
808void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
809 const struct amdgpu_ras_err_status_reg_entry *reg_list,
810 uint32_t reg_list_size,
811 uint32_t instance);
812
813int amdgpu_ras_error_data_init(struct ras_err_data *err_data);
814void amdgpu_ras_error_data_fini(struct ras_err_data *err_data);
815int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
816 struct amdgpu_smuio_mcm_config_info *mcm_info,
817 struct ras_err_addr *err_addr, u64 count);
818int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
819 struct amdgpu_smuio_mcm_config_info *mcm_info,
820 struct ras_err_addr *err_addr, u64 count);
821
822#endif