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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2003-2015 Broadcom Corporation
4 * All Rights Reserved
5 */
6
7#include <linux/gpio/driver.h>
8#include <linux/platform_device.h>
9#include <linux/module.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/irqchip/chained_irq.h>
13#include <linux/acpi.h>
14
15/*
16 * XLP GPIO has multiple 32 bit registers for each feature where each register
17 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
18 * require 3 32-bit registers for each feature.
19 * Here we only define offset of the first register for each feature. Offset of
20 * the registers for pins greater than 32 can be calculated as following(Use
21 * GPIO_INT_STAT as example):
22 *
23 * offset = (gpio / XLP_GPIO_REGSZ) * 4;
24 * reg_addr = addr + offset;
25 *
26 * where addr is base address of the that feature register and gpio is the pin.
27 */
28#define GPIO_9XX_BYTESWAP 0X00
29#define GPIO_9XX_CTRL 0X04
30#define GPIO_9XX_OUTPUT_EN 0x14
31#define GPIO_9XX_PADDRV 0x24
32/*
33 * Only for 4 interrupt enable reg are defined for now,
34 * total reg available are 12.
35 */
36#define GPIO_9XX_INT_EN00 0x44
37#define GPIO_9XX_INT_EN10 0x54
38#define GPIO_9XX_INT_EN20 0x64
39#define GPIO_9XX_INT_EN30 0x74
40#define GPIO_9XX_INT_POL 0x104
41#define GPIO_9XX_INT_TYPE 0x114
42#define GPIO_9XX_INT_STAT 0x124
43
44/* Interrupt type register mask */
45#define XLP_GPIO_IRQ_TYPE_LVL 0x0
46#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
47
48/* Interrupt polarity register mask */
49#define XLP_GPIO_IRQ_POL_HIGH 0x0
50#define XLP_GPIO_IRQ_POL_LOW 0x1
51
52#define XLP_GPIO_REGSZ 32
53#define XLP_GPIO_IRQ_BASE 768
54#define XLP_MAX_NR_GPIO 96
55
56struct xlp_gpio_priv {
57 struct gpio_chip chip;
58 DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
59 void __iomem *gpio_intr_en; /* pointer to first intr enable reg */
60 void __iomem *gpio_intr_stat; /* pointer to first intr status reg */
61 void __iomem *gpio_intr_type; /* pointer to first intr type reg */
62 void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */
63 void __iomem *gpio_out_en; /* pointer to first output enable reg */
64 void __iomem *gpio_paddrv; /* pointer to first pad drive reg */
65 spinlock_t lock;
66};
67
68static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
69{
70 u32 pos, regset;
71
72 pos = gpio % XLP_GPIO_REGSZ;
73 regset = (gpio / XLP_GPIO_REGSZ) * 4;
74 return !!(readl(addr + regset) & BIT(pos));
75}
76
77static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
78{
79 u32 value, pos, regset;
80
81 pos = gpio % XLP_GPIO_REGSZ;
82 regset = (gpio / XLP_GPIO_REGSZ) * 4;
83 value = readl(addr + regset);
84
85 if (state)
86 value |= BIT(pos);
87 else
88 value &= ~BIT(pos);
89
90 writel(value, addr + regset);
91}
92
93static void xlp_gpio_irq_enable(struct irq_data *d)
94{
95 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
96
97 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
98}
99
100static void xlp_gpio_irq_disable(struct irq_data *d)
101{
102 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
103 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
104 unsigned long flags;
105
106 spin_lock_irqsave(&priv->lock, flags);
107 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
108 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
109 spin_unlock_irqrestore(&priv->lock, flags);
110 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
111}
112
113static void xlp_gpio_irq_mask_ack(struct irq_data *d)
114{
115 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
116 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
117 unsigned long flags;
118
119 spin_lock_irqsave(&priv->lock, flags);
120 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
121 xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
122 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
123 spin_unlock_irqrestore(&priv->lock, flags);
124}
125
126static void xlp_gpio_irq_unmask(struct irq_data *d)
127{
128 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
129 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
130 unsigned long flags;
131
132 spin_lock_irqsave(&priv->lock, flags);
133 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
134 __set_bit(d->hwirq, priv->gpio_enabled_mask);
135 spin_unlock_irqrestore(&priv->lock, flags);
136}
137
138static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
139{
140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
142 int pol, irq_type;
143
144 switch (type) {
145 case IRQ_TYPE_EDGE_RISING:
146 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
147 pol = XLP_GPIO_IRQ_POL_HIGH;
148 break;
149 case IRQ_TYPE_EDGE_FALLING:
150 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
151 pol = XLP_GPIO_IRQ_POL_LOW;
152 break;
153 case IRQ_TYPE_LEVEL_HIGH:
154 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
155 pol = XLP_GPIO_IRQ_POL_HIGH;
156 break;
157 case IRQ_TYPE_LEVEL_LOW:
158 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
159 pol = XLP_GPIO_IRQ_POL_LOW;
160 break;
161 default:
162 return -EINVAL;
163 }
164
165 xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
166 xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
167
168 return 0;
169}
170
171static struct irq_chip xlp_gpio_irq_chip = {
172 .name = "XLP-GPIO",
173 .irq_mask_ack = xlp_gpio_irq_mask_ack,
174 .irq_enable = xlp_gpio_irq_enable,
175 .irq_disable = xlp_gpio_irq_disable,
176 .irq_set_type = xlp_gpio_set_irq_type,
177 .irq_unmask = xlp_gpio_irq_unmask,
178 .flags = IRQCHIP_ONESHOT_SAFE | IRQCHIP_IMMUTABLE,
179 GPIOCHIP_IRQ_RESOURCE_HELPERS,
180};
181
182static void xlp_gpio_generic_handler(struct irq_desc *desc)
183{
184 struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
185 struct irq_chip *irqchip = irq_desc_get_chip(desc);
186 int gpio, regoff;
187 u32 gpio_stat;
188
189 regoff = -1;
190 gpio_stat = 0;
191
192 chained_irq_enter(irqchip, desc);
193 for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
194 if (regoff != gpio / XLP_GPIO_REGSZ) {
195 regoff = gpio / XLP_GPIO_REGSZ;
196 gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
197 }
198
199 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
200 generic_handle_domain_irq(priv->chip.irq.domain, gpio);
201 }
202 chained_irq_exit(irqchip, desc);
203}
204
205static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
206{
207 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
208
209 BUG_ON(gpio >= gc->ngpio);
210 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
211
212 return 0;
213}
214
215static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
216{
217 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
218
219 BUG_ON(gpio >= gc->ngpio);
220 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
221
222 return 0;
223}
224
225static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
226{
227 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
228
229 BUG_ON(gpio >= gc->ngpio);
230 return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
231}
232
233static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
234{
235 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
236
237 BUG_ON(gpio >= gc->ngpio);
238 xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
239}
240
241static int xlp_gpio_probe(struct platform_device *pdev)
242{
243 struct gpio_chip *gc;
244 struct gpio_irq_chip *girq;
245 struct xlp_gpio_priv *priv;
246 void __iomem *gpio_base;
247 int irq, err;
248
249 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
250 if (!priv)
251 return -ENOMEM;
252
253 gpio_base = devm_platform_ioremap_resource(pdev, 0);
254 if (IS_ERR(gpio_base))
255 return PTR_ERR(gpio_base);
256
257 irq = platform_get_irq(pdev, 0);
258 if (irq < 0)
259 return irq;
260
261 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
262 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
263 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
264 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
265 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
266 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
267
268 bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
269
270 gc = &priv->chip;
271
272 gc->owner = THIS_MODULE;
273 gc->label = dev_name(&pdev->dev);
274 gc->base = 0;
275 gc->parent = &pdev->dev;
276 gc->ngpio = 70;
277 gc->direction_output = xlp_gpio_dir_output;
278 gc->direction_input = xlp_gpio_dir_input;
279 gc->set = xlp_gpio_set;
280 gc->get = xlp_gpio_get;
281
282 spin_lock_init(&priv->lock);
283
284 girq = &gc->irq;
285 gpio_irq_chip_set_chip(girq, &xlp_gpio_irq_chip);
286 girq->parent_handler = xlp_gpio_generic_handler;
287 girq->num_parents = 1;
288 girq->parents = devm_kcalloc(&pdev->dev, 1,
289 sizeof(*girq->parents),
290 GFP_KERNEL);
291 if (!girq->parents)
292 return -ENOMEM;
293 girq->parents[0] = irq;
294 girq->first = 0;
295 girq->default_type = IRQ_TYPE_NONE;
296 girq->handler = handle_level_irq;
297
298 err = gpiochip_add_data(gc, priv);
299 if (err < 0)
300 return err;
301
302 dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
303
304 return 0;
305}
306
307#ifdef CONFIG_ACPI
308static const struct acpi_device_id xlp_gpio_acpi_match[] = {
309 { "BRCM9006" },
310 { "CAV9006" },
311 {},
312};
313MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
314#endif
315
316static struct platform_driver xlp_gpio_driver = {
317 .driver = {
318 .name = "xlp-gpio",
319 .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
320 },
321 .probe = xlp_gpio_probe,
322};
323module_platform_driver(xlp_gpio_driver);
324
325MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
326MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
327MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
328MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2003-2015 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/gpio.h>
16#include <linux/platform_device.h>
17#include <linux/of_device.h>
18#include <linux/module.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/acpi.h>
23
24/*
25 * XLP GPIO has multiple 32 bit registers for each feature where each register
26 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
27 * require 3 32-bit registers for each feature.
28 * Here we only define offset of the first register for each feature. Offset of
29 * the registers for pins greater than 32 can be calculated as following(Use
30 * GPIO_INT_STAT as example):
31 *
32 * offset = (gpio / XLP_GPIO_REGSZ) * 4;
33 * reg_addr = addr + offset;
34 *
35 * where addr is base address of the that feature register and gpio is the pin.
36 */
37#define GPIO_OUTPUT_EN 0x00
38#define GPIO_PADDRV 0x08
39#define GPIO_INT_EN00 0x18
40#define GPIO_INT_EN10 0x20
41#define GPIO_INT_EN20 0x28
42#define GPIO_INT_EN30 0x30
43#define GPIO_INT_POL 0x38
44#define GPIO_INT_TYPE 0x40
45#define GPIO_INT_STAT 0x48
46
47#define GPIO_9XX_BYTESWAP 0X00
48#define GPIO_9XX_CTRL 0X04
49#define GPIO_9XX_OUTPUT_EN 0x14
50#define GPIO_9XX_PADDRV 0x24
51/*
52 * Only for 4 interrupt enable reg are defined for now,
53 * total reg available are 12.
54 */
55#define GPIO_9XX_INT_EN00 0x44
56#define GPIO_9XX_INT_EN10 0x54
57#define GPIO_9XX_INT_EN20 0x64
58#define GPIO_9XX_INT_EN30 0x74
59#define GPIO_9XX_INT_POL 0x104
60#define GPIO_9XX_INT_TYPE 0x114
61#define GPIO_9XX_INT_STAT 0x124
62
63#define GPIO_3XX_INT_EN00 0x18
64#define GPIO_3XX_INT_EN10 0x20
65#define GPIO_3XX_INT_EN20 0x28
66#define GPIO_3XX_INT_EN30 0x30
67#define GPIO_3XX_INT_POL 0x78
68#define GPIO_3XX_INT_TYPE 0x80
69#define GPIO_3XX_INT_STAT 0x88
70
71/* Interrupt type register mask */
72#define XLP_GPIO_IRQ_TYPE_LVL 0x0
73#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
74
75/* Interrupt polarity register mask */
76#define XLP_GPIO_IRQ_POL_HIGH 0x0
77#define XLP_GPIO_IRQ_POL_LOW 0x1
78
79#define XLP_GPIO_REGSZ 32
80#define XLP_GPIO_IRQ_BASE 768
81#define XLP_MAX_NR_GPIO 96
82
83/* XLP variants supported by this driver */
84enum {
85 XLP_GPIO_VARIANT_XLP832 = 1,
86 XLP_GPIO_VARIANT_XLP316,
87 XLP_GPIO_VARIANT_XLP208,
88 XLP_GPIO_VARIANT_XLP980,
89 XLP_GPIO_VARIANT_XLP532,
90 GPIO_VARIANT_VULCAN
91};
92
93struct xlp_gpio_priv {
94 struct gpio_chip chip;
95 DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
96 void __iomem *gpio_intr_en; /* pointer to first intr enable reg */
97 void __iomem *gpio_intr_stat; /* pointer to first intr status reg */
98 void __iomem *gpio_intr_type; /* pointer to first intr type reg */
99 void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */
100 void __iomem *gpio_out_en; /* pointer to first output enable reg */
101 void __iomem *gpio_paddrv; /* pointer to first pad drive reg */
102 spinlock_t lock;
103};
104
105static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
106{
107 u32 pos, regset;
108
109 pos = gpio % XLP_GPIO_REGSZ;
110 regset = (gpio / XLP_GPIO_REGSZ) * 4;
111 return !!(readl(addr + regset) & BIT(pos));
112}
113
114static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
115{
116 u32 value, pos, regset;
117
118 pos = gpio % XLP_GPIO_REGSZ;
119 regset = (gpio / XLP_GPIO_REGSZ) * 4;
120 value = readl(addr + regset);
121
122 if (state)
123 value |= BIT(pos);
124 else
125 value &= ~BIT(pos);
126
127 writel(value, addr + regset);
128}
129
130static void xlp_gpio_irq_disable(struct irq_data *d)
131{
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
134 unsigned long flags;
135
136 spin_lock_irqsave(&priv->lock, flags);
137 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
138 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
139 spin_unlock_irqrestore(&priv->lock, flags);
140}
141
142static void xlp_gpio_irq_mask_ack(struct irq_data *d)
143{
144 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
145 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
146 unsigned long flags;
147
148 spin_lock_irqsave(&priv->lock, flags);
149 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
150 xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
151 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
152 spin_unlock_irqrestore(&priv->lock, flags);
153}
154
155static void xlp_gpio_irq_unmask(struct irq_data *d)
156{
157 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
158 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
159 unsigned long flags;
160
161 spin_lock_irqsave(&priv->lock, flags);
162 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
163 __set_bit(d->hwirq, priv->gpio_enabled_mask);
164 spin_unlock_irqrestore(&priv->lock, flags);
165}
166
167static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
168{
169 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
170 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
171 int pol, irq_type;
172
173 switch (type) {
174 case IRQ_TYPE_EDGE_RISING:
175 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
176 pol = XLP_GPIO_IRQ_POL_HIGH;
177 break;
178 case IRQ_TYPE_EDGE_FALLING:
179 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
180 pol = XLP_GPIO_IRQ_POL_LOW;
181 break;
182 case IRQ_TYPE_LEVEL_HIGH:
183 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
184 pol = XLP_GPIO_IRQ_POL_HIGH;
185 break;
186 case IRQ_TYPE_LEVEL_LOW:
187 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
188 pol = XLP_GPIO_IRQ_POL_LOW;
189 break;
190 default:
191 return -EINVAL;
192 }
193
194 xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
195 xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
196
197 return 0;
198}
199
200static struct irq_chip xlp_gpio_irq_chip = {
201 .name = "XLP-GPIO",
202 .irq_mask_ack = xlp_gpio_irq_mask_ack,
203 .irq_disable = xlp_gpio_irq_disable,
204 .irq_set_type = xlp_gpio_set_irq_type,
205 .irq_unmask = xlp_gpio_irq_unmask,
206 .flags = IRQCHIP_ONESHOT_SAFE,
207};
208
209static void xlp_gpio_generic_handler(struct irq_desc *desc)
210{
211 struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
212 struct irq_chip *irqchip = irq_desc_get_chip(desc);
213 int gpio, regoff;
214 u32 gpio_stat;
215
216 regoff = -1;
217 gpio_stat = 0;
218
219 chained_irq_enter(irqchip, desc);
220 for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
221 if (regoff != gpio / XLP_GPIO_REGSZ) {
222 regoff = gpio / XLP_GPIO_REGSZ;
223 gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
224 }
225
226 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
227 generic_handle_irq(irq_find_mapping(
228 priv->chip.irq.domain, gpio));
229 }
230 chained_irq_exit(irqchip, desc);
231}
232
233static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
234{
235 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
236
237 BUG_ON(gpio >= gc->ngpio);
238 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
239
240 return 0;
241}
242
243static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
244{
245 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
246
247 BUG_ON(gpio >= gc->ngpio);
248 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
249
250 return 0;
251}
252
253static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
254{
255 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
256
257 BUG_ON(gpio >= gc->ngpio);
258 return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
259}
260
261static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
262{
263 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
264
265 BUG_ON(gpio >= gc->ngpio);
266 xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
267}
268
269static const struct of_device_id xlp_gpio_of_ids[] = {
270 {
271 .compatible = "netlogic,xlp832-gpio",
272 .data = (void *)XLP_GPIO_VARIANT_XLP832,
273 },
274 {
275 .compatible = "netlogic,xlp316-gpio",
276 .data = (void *)XLP_GPIO_VARIANT_XLP316,
277 },
278 {
279 .compatible = "netlogic,xlp208-gpio",
280 .data = (void *)XLP_GPIO_VARIANT_XLP208,
281 },
282 {
283 .compatible = "netlogic,xlp980-gpio",
284 .data = (void *)XLP_GPIO_VARIANT_XLP980,
285 },
286 {
287 .compatible = "netlogic,xlp532-gpio",
288 .data = (void *)XLP_GPIO_VARIANT_XLP532,
289 },
290 {
291 .compatible = "brcm,vulcan-gpio",
292 .data = (void *)GPIO_VARIANT_VULCAN,
293 },
294 { /* sentinel */ },
295};
296MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
297
298static int xlp_gpio_probe(struct platform_device *pdev)
299{
300 struct gpio_chip *gc;
301 struct resource *iores;
302 struct xlp_gpio_priv *priv;
303 void __iomem *gpio_base;
304 int irq_base, irq, err;
305 int ngpio;
306 u32 soc_type;
307
308 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
309 if (!iores)
310 return -ENODEV;
311
312 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
313 if (!priv)
314 return -ENOMEM;
315
316 gpio_base = devm_ioremap_resource(&pdev->dev, iores);
317 if (IS_ERR(gpio_base))
318 return PTR_ERR(gpio_base);
319
320 irq = platform_get_irq(pdev, 0);
321 if (irq < 0)
322 return irq;
323
324 if (pdev->dev.of_node) {
325 const struct of_device_id *of_id;
326
327 of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev);
328 if (!of_id) {
329 dev_err(&pdev->dev, "Unable to match OF ID\n");
330 return -ENODEV;
331 }
332 soc_type = (uintptr_t) of_id->data;
333 } else {
334 const struct acpi_device_id *acpi_id;
335
336 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
337 &pdev->dev);
338 if (!acpi_id || !acpi_id->driver_data) {
339 dev_err(&pdev->dev, "Unable to match ACPI ID\n");
340 return -ENODEV;
341 }
342 soc_type = (uintptr_t) acpi_id->driver_data;
343 }
344
345 switch (soc_type) {
346 case XLP_GPIO_VARIANT_XLP832:
347 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
348 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
349 priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
350 priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
351 priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
352 priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
353 ngpio = 41;
354 break;
355 case XLP_GPIO_VARIANT_XLP208:
356 case XLP_GPIO_VARIANT_XLP316:
357 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
358 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
359 priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
360 priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
361 priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
362 priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
363
364 ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
365 break;
366 case XLP_GPIO_VARIANT_XLP980:
367 case XLP_GPIO_VARIANT_XLP532:
368 case GPIO_VARIANT_VULCAN:
369 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
370 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
371 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
372 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
373 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
374 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
375
376 if (soc_type == XLP_GPIO_VARIANT_XLP980)
377 ngpio = 66;
378 else if (soc_type == XLP_GPIO_VARIANT_XLP532)
379 ngpio = 67;
380 else
381 ngpio = 70;
382 break;
383 default:
384 dev_err(&pdev->dev, "Unknown Processor type!\n");
385 return -ENODEV;
386 }
387
388 bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
389
390 gc = &priv->chip;
391
392 gc->owner = THIS_MODULE;
393 gc->label = dev_name(&pdev->dev);
394 gc->base = 0;
395 gc->parent = &pdev->dev;
396 gc->ngpio = ngpio;
397 gc->of_node = pdev->dev.of_node;
398 gc->direction_output = xlp_gpio_dir_output;
399 gc->direction_input = xlp_gpio_dir_input;
400 gc->set = xlp_gpio_set;
401 gc->get = xlp_gpio_get;
402
403 spin_lock_init(&priv->lock);
404
405 /* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */
406 if (soc_type != GPIO_VARIANT_VULCAN) {
407 irq_base = devm_irq_alloc_descs(&pdev->dev, -1,
408 XLP_GPIO_IRQ_BASE,
409 gc->ngpio, 0);
410 if (irq_base < 0) {
411 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
412 return irq_base;
413 }
414 } else {
415 irq_base = 0;
416 }
417
418 err = gpiochip_add_data(gc, priv);
419 if (err < 0)
420 return err;
421
422 err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base,
423 handle_level_irq, IRQ_TYPE_NONE);
424 if (err) {
425 dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n");
426 goto out_gpio_remove;
427 }
428
429 gpiochip_set_chained_irqchip(gc, &xlp_gpio_irq_chip, irq,
430 xlp_gpio_generic_handler);
431
432 dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
433
434 return 0;
435
436out_gpio_remove:
437 gpiochip_remove(gc);
438 return err;
439}
440
441#ifdef CONFIG_ACPI
442static const struct acpi_device_id xlp_gpio_acpi_match[] = {
443 { "BRCM9006", GPIO_VARIANT_VULCAN },
444 { "CAV9006", GPIO_VARIANT_VULCAN },
445 {},
446};
447MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
448#endif
449
450static struct platform_driver xlp_gpio_driver = {
451 .driver = {
452 .name = "xlp-gpio",
453 .of_match_table = xlp_gpio_of_ids,
454 .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
455 },
456 .probe = xlp_gpio_probe,
457};
458module_platform_driver(xlp_gpio_driver);
459
460MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
461MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
462MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
463MODULE_LICENSE("GPL v2");