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1/*
2 * Intel MID GPIO driver
3 *
4 * Copyright (c) 2008-2014,2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/* Supports:
17 * Moorestown platform Langwell chip.
18 * Medfield platform Penwell chip.
19 * Clovertrail platform Cloverview chip.
20 */
21
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/gpio/driver.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32#include <linux/slab.h>
33#include <linux/stddef.h>
34
35#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
36#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
37
38/*
39 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
40 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
41 * registers to control them, so we only define the order here instead of a
42 * structure, to get a bit offset for a pin (use GPDR as an example):
43 *
44 * nreg = ngpio / 32;
45 * reg = offset / 32;
46 * bit = offset % 32;
47 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
48 *
49 * so the bit of reg_addr is to control pin offset's GPDR feature
50*/
51
52enum GPIO_REG {
53 GPLR = 0, /* pin level read-only */
54 GPDR, /* pin direction */
55 GPSR, /* pin set */
56 GPCR, /* pin clear */
57 GRER, /* rising edge detect */
58 GFER, /* falling edge detect */
59 GEDR, /* edge detect result */
60 GAFR, /* alt function */
61};
62
63/* intel_mid gpio driver data */
64struct intel_mid_gpio_ddata {
65 u16 ngpio; /* number of gpio pins */
66 u32 chip_irq_type; /* chip interrupt type */
67};
68
69struct intel_mid_gpio {
70 struct gpio_chip chip;
71 void __iomem *reg_base;
72 spinlock_t lock;
73 struct pci_dev *pdev;
74};
75
76static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
77 enum GPIO_REG reg_type)
78{
79 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
80 unsigned nreg = chip->ngpio / 32;
81 u8 reg = offset / 32;
82
83 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
84}
85
86static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
87 enum GPIO_REG reg_type)
88{
89 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
90 unsigned nreg = chip->ngpio / 32;
91 u8 reg = offset / 16;
92
93 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
94}
95
96static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
97{
98 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
99 u32 value = readl(gafr);
100 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
101
102 if (af) {
103 value &= ~(3 << shift);
104 writel(value, gafr);
105 }
106 return 0;
107}
108
109static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
110{
111 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
112
113 return !!(readl(gplr) & BIT(offset % 32));
114}
115
116static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
117{
118 void __iomem *gpsr, *gpcr;
119
120 if (value) {
121 gpsr = gpio_reg(chip, offset, GPSR);
122 writel(BIT(offset % 32), gpsr);
123 } else {
124 gpcr = gpio_reg(chip, offset, GPCR);
125 writel(BIT(offset % 32), gpcr);
126 }
127}
128
129static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
130{
131 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
132 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
133 u32 value;
134 unsigned long flags;
135
136 if (priv->pdev)
137 pm_runtime_get(&priv->pdev->dev);
138
139 spin_lock_irqsave(&priv->lock, flags);
140 value = readl(gpdr);
141 value &= ~BIT(offset % 32);
142 writel(value, gpdr);
143 spin_unlock_irqrestore(&priv->lock, flags);
144
145 if (priv->pdev)
146 pm_runtime_put(&priv->pdev->dev);
147
148 return 0;
149}
150
151static int intel_gpio_direction_output(struct gpio_chip *chip,
152 unsigned offset, int value)
153{
154 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
155 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
156 unsigned long flags;
157
158 intel_gpio_set(chip, offset, value);
159
160 if (priv->pdev)
161 pm_runtime_get(&priv->pdev->dev);
162
163 spin_lock_irqsave(&priv->lock, flags);
164 value = readl(gpdr);
165 value |= BIT(offset % 32);
166 writel(value, gpdr);
167 spin_unlock_irqrestore(&priv->lock, flags);
168
169 if (priv->pdev)
170 pm_runtime_put(&priv->pdev->dev);
171
172 return 0;
173}
174
175static int intel_mid_irq_type(struct irq_data *d, unsigned type)
176{
177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
178 struct intel_mid_gpio *priv = gpiochip_get_data(gc);
179 u32 gpio = irqd_to_hwirq(d);
180 unsigned long flags;
181 u32 value;
182 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
183 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
184
185 if (gpio >= priv->chip.ngpio)
186 return -EINVAL;
187
188 if (priv->pdev)
189 pm_runtime_get(&priv->pdev->dev);
190
191 spin_lock_irqsave(&priv->lock, flags);
192 if (type & IRQ_TYPE_EDGE_RISING)
193 value = readl(grer) | BIT(gpio % 32);
194 else
195 value = readl(grer) & (~BIT(gpio % 32));
196 writel(value, grer);
197
198 if (type & IRQ_TYPE_EDGE_FALLING)
199 value = readl(gfer) | BIT(gpio % 32);
200 else
201 value = readl(gfer) & (~BIT(gpio % 32));
202 writel(value, gfer);
203 spin_unlock_irqrestore(&priv->lock, flags);
204
205 if (priv->pdev)
206 pm_runtime_put(&priv->pdev->dev);
207
208 return 0;
209}
210
211static void intel_mid_irq_unmask(struct irq_data *d)
212{
213}
214
215static void intel_mid_irq_mask(struct irq_data *d)
216{
217}
218
219static struct irq_chip intel_mid_irqchip = {
220 .name = "INTEL_MID-GPIO",
221 .irq_mask = intel_mid_irq_mask,
222 .irq_unmask = intel_mid_irq_unmask,
223 .irq_set_type = intel_mid_irq_type,
224};
225
226static const struct intel_mid_gpio_ddata gpio_lincroft = {
227 .ngpio = 64,
228};
229
230static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
231 .ngpio = 96,
232 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
233};
234
235static const struct intel_mid_gpio_ddata gpio_penwell_core = {
236 .ngpio = 96,
237 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
238};
239
240static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
241 .ngpio = 96,
242 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
243};
244
245static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
246 .ngpio = 96,
247 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
248};
249
250static const struct pci_device_id intel_gpio_ids[] = {
251 {
252 /* Lincroft */
253 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
254 .driver_data = (kernel_ulong_t)&gpio_lincroft,
255 },
256 {
257 /* Penwell AON */
258 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
259 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
260 },
261 {
262 /* Penwell Core */
263 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
264 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
265 },
266 {
267 /* Cloverview Aon */
268 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
269 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
270 },
271 {
272 /* Cloverview Core */
273 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
274 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
275 },
276 { 0 }
277};
278MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
279
280static void intel_mid_irq_handler(struct irq_desc *desc)
281{
282 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
283 struct intel_mid_gpio *priv = gpiochip_get_data(gc);
284 struct irq_data *data = irq_desc_get_irq_data(desc);
285 struct irq_chip *chip = irq_data_get_irq_chip(data);
286 u32 base, gpio, mask;
287 unsigned long pending;
288 void __iomem *gedr;
289
290 /* check GPIO controller to check which pin triggered the interrupt */
291 for (base = 0; base < priv->chip.ngpio; base += 32) {
292 gedr = gpio_reg(&priv->chip, base, GEDR);
293 while ((pending = readl(gedr))) {
294 gpio = __ffs(pending);
295 mask = BIT(gpio);
296 /* Clear before handling so we can't lose an edge */
297 writel(mask, gedr);
298 generic_handle_irq(irq_find_mapping(gc->irq.domain,
299 base + gpio));
300 }
301 }
302
303 chip->irq_eoi(data);
304}
305
306static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
307{
308 void __iomem *reg;
309 unsigned base;
310
311 for (base = 0; base < priv->chip.ngpio; base += 32) {
312 /* Clear the rising-edge detect register */
313 reg = gpio_reg(&priv->chip, base, GRER);
314 writel(0, reg);
315 /* Clear the falling-edge detect register */
316 reg = gpio_reg(&priv->chip, base, GFER);
317 writel(0, reg);
318 /* Clear the edge detect status register */
319 reg = gpio_reg(&priv->chip, base, GEDR);
320 writel(~0, reg);
321 }
322}
323
324static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
325{
326 int err = pm_schedule_suspend(dev, 500);
327 return err ?: -EBUSY;
328}
329
330static const struct dev_pm_ops intel_gpio_pm_ops = {
331 SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
332};
333
334static int intel_gpio_probe(struct pci_dev *pdev,
335 const struct pci_device_id *id)
336{
337 void __iomem *base;
338 struct intel_mid_gpio *priv;
339 u32 gpio_base;
340 u32 irq_base;
341 int retval;
342 struct intel_mid_gpio_ddata *ddata =
343 (struct intel_mid_gpio_ddata *)id->driver_data;
344
345 retval = pcim_enable_device(pdev);
346 if (retval)
347 return retval;
348
349 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
350 if (retval) {
351 dev_err(&pdev->dev, "I/O memory mapping error\n");
352 return retval;
353 }
354
355 base = pcim_iomap_table(pdev)[1];
356
357 irq_base = readl(base);
358 gpio_base = readl(sizeof(u32) + base);
359
360 /* release the IO mapping, since we already get the info from bar1 */
361 pcim_iounmap_regions(pdev, 1 << 1);
362
363 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
364 if (!priv)
365 return -ENOMEM;
366
367 priv->reg_base = pcim_iomap_table(pdev)[0];
368 priv->chip.label = dev_name(&pdev->dev);
369 priv->chip.parent = &pdev->dev;
370 priv->chip.request = intel_gpio_request;
371 priv->chip.direction_input = intel_gpio_direction_input;
372 priv->chip.direction_output = intel_gpio_direction_output;
373 priv->chip.get = intel_gpio_get;
374 priv->chip.set = intel_gpio_set;
375 priv->chip.base = gpio_base;
376 priv->chip.ngpio = ddata->ngpio;
377 priv->chip.can_sleep = false;
378 priv->pdev = pdev;
379
380 spin_lock_init(&priv->lock);
381
382 pci_set_drvdata(pdev, priv);
383 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
384 if (retval) {
385 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
386 return retval;
387 }
388
389 retval = gpiochip_irqchip_add(&priv->chip,
390 &intel_mid_irqchip,
391 irq_base,
392 handle_simple_irq,
393 IRQ_TYPE_NONE);
394 if (retval) {
395 dev_err(&pdev->dev,
396 "could not connect irqchip to gpiochip\n");
397 return retval;
398 }
399
400 intel_mid_irq_init_hw(priv);
401
402 gpiochip_set_chained_irqchip(&priv->chip,
403 &intel_mid_irqchip,
404 pdev->irq,
405 intel_mid_irq_handler);
406
407 pm_runtime_put_noidle(&pdev->dev);
408 pm_runtime_allow(&pdev->dev);
409
410 return 0;
411}
412
413static struct pci_driver intel_gpio_driver = {
414 .name = "intel_mid_gpio",
415 .id_table = intel_gpio_ids,
416 .probe = intel_gpio_probe,
417 .driver = {
418 .pm = &intel_gpio_pm_ops,
419 },
420};
421
422builtin_pci_driver(intel_gpio_driver);