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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2016,2017 IBM Corporation.
4 */
5
6#define pr_fmt(fmt) "xive: " fmt
7
8#include <linux/types.h>
9#include <linux/threads.h>
10#include <linux/kernel.h>
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/debugfs.h>
14#include <linux/smp.h>
15#include <linux/interrupt.h>
16#include <linux/seq_file.h>
17#include <linux/init.h>
18#include <linux/cpu.h>
19#include <linux/of.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/msi.h>
23#include <linux/vmalloc.h>
24
25#include <asm/io.h>
26#include <asm/smp.h>
27#include <asm/machdep.h>
28#include <asm/irq.h>
29#include <asm/errno.h>
30#include <asm/xive.h>
31#include <asm/xive-regs.h>
32#include <asm/xmon.h>
33
34#include "xive-internal.h"
35
36#undef DEBUG_FLUSH
37#undef DEBUG_ALL
38
39#ifdef DEBUG_ALL
40#define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \
41 smp_processor_id(), ## __VA_ARGS__)
42#else
43#define DBG_VERBOSE(fmt...) do { } while(0)
44#endif
45
46bool __xive_enabled;
47EXPORT_SYMBOL_GPL(__xive_enabled);
48bool xive_cmdline_disabled;
49
50/* We use only one priority for now */
51static u8 xive_irq_priority;
52
53/* TIMA exported to KVM */
54void __iomem *xive_tima;
55EXPORT_SYMBOL_GPL(xive_tima);
56u32 xive_tima_offset;
57
58/* Backend ops */
59static const struct xive_ops *xive_ops;
60
61/* Our global interrupt domain */
62static struct irq_domain *xive_irq_domain;
63
64#ifdef CONFIG_SMP
65/* The IPIs use the same logical irq number when on the same chip */
66static struct xive_ipi_desc {
67 unsigned int irq;
68 char name[16];
69 atomic_t started;
70} *xive_ipis;
71
72/*
73 * Use early_cpu_to_node() for hot-plugged CPUs
74 */
75static unsigned int xive_ipi_cpu_to_irq(unsigned int cpu)
76{
77 return xive_ipis[early_cpu_to_node(cpu)].irq;
78}
79#endif
80
81/* Xive state for each CPU */
82static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
83
84/* An invalid CPU target */
85#define XIVE_INVALID_TARGET (-1)
86
87/*
88 * Global toggle to switch on/off StoreEOI
89 */
90static bool xive_store_eoi = true;
91
92static bool xive_is_store_eoi(struct xive_irq_data *xd)
93{
94 return xd->flags & XIVE_IRQ_FLAG_STORE_EOI && xive_store_eoi;
95}
96
97/*
98 * Read the next entry in a queue, return its content if it's valid
99 * or 0 if there is no new entry.
100 *
101 * The queue pointer is moved forward unless "just_peek" is set
102 */
103static u32 xive_read_eq(struct xive_q *q, bool just_peek)
104{
105 u32 cur;
106
107 if (!q->qpage)
108 return 0;
109 cur = be32_to_cpup(q->qpage + q->idx);
110
111 /* Check valid bit (31) vs current toggle polarity */
112 if ((cur >> 31) == q->toggle)
113 return 0;
114
115 /* If consuming from the queue ... */
116 if (!just_peek) {
117 /* Next entry */
118 q->idx = (q->idx + 1) & q->msk;
119
120 /* Wrap around: flip valid toggle */
121 if (q->idx == 0)
122 q->toggle ^= 1;
123 }
124 /* Mask out the valid bit (31) */
125 return cur & 0x7fffffff;
126}
127
128/*
129 * Scans all the queue that may have interrupts in them
130 * (based on "pending_prio") in priority order until an
131 * interrupt is found or all the queues are empty.
132 *
133 * Then updates the CPPR (Current Processor Priority
134 * Register) based on the most favored interrupt found
135 * (0xff if none) and return what was found (0 if none).
136 *
137 * If just_peek is set, return the most favored pending
138 * interrupt if any but don't update the queue pointers.
139 *
140 * Note: This function can operate generically on any number
141 * of queues (up to 8). The current implementation of the XIVE
142 * driver only uses a single queue however.
143 *
144 * Note2: This will also "flush" "the pending_count" of a queue
145 * into the "count" when that queue is observed to be empty.
146 * This is used to keep track of the amount of interrupts
147 * targetting a queue. When an interrupt is moved away from
148 * a queue, we only decrement that queue count once the queue
149 * has been observed empty to avoid races.
150 */
151static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
152{
153 u32 irq = 0;
154 u8 prio = 0;
155
156 /* Find highest pending priority */
157 while (xc->pending_prio != 0) {
158 struct xive_q *q;
159
160 prio = ffs(xc->pending_prio) - 1;
161 DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
162
163 /* Try to fetch */
164 irq = xive_read_eq(&xc->queue[prio], just_peek);
165
166 /* Found something ? That's it */
167 if (irq) {
168 if (just_peek || irq_to_desc(irq))
169 break;
170 /*
171 * We should never get here; if we do then we must
172 * have failed to synchronize the interrupt properly
173 * when shutting it down.
174 */
175 pr_crit("xive: got interrupt %d without descriptor, dropping\n",
176 irq);
177 WARN_ON(1);
178 continue;
179 }
180
181 /* Clear pending bits */
182 xc->pending_prio &= ~(1 << prio);
183
184 /*
185 * Check if the queue count needs adjusting due to
186 * interrupts being moved away. See description of
187 * xive_dec_target_count()
188 */
189 q = &xc->queue[prio];
190 if (atomic_read(&q->pending_count)) {
191 int p = atomic_xchg(&q->pending_count, 0);
192 if (p) {
193 WARN_ON(p > atomic_read(&q->count));
194 atomic_sub(p, &q->count);
195 }
196 }
197 }
198
199 /* If nothing was found, set CPPR to 0xff */
200 if (irq == 0)
201 prio = 0xff;
202
203 /* Update HW CPPR to match if necessary */
204 if (prio != xc->cppr) {
205 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
206 xc->cppr = prio;
207 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
208 }
209
210 return irq;
211}
212
213/*
214 * This is used to perform the magic loads from an ESB
215 * described in xive-regs.h
216 */
217static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
218{
219 u64 val;
220
221 if (offset == XIVE_ESB_SET_PQ_10 && xive_is_store_eoi(xd))
222 offset |= XIVE_ESB_LD_ST_MO;
223
224 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
225 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
226 else
227 val = in_be64(xd->eoi_mmio + offset);
228
229 return (u8)val;
230}
231
232static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
233{
234 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
235 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
236 else
237 out_be64(xd->eoi_mmio + offset, data);
238}
239
240#if defined(CONFIG_XMON) || defined(CONFIG_DEBUG_FS)
241static void xive_irq_data_dump(struct xive_irq_data *xd, char *buffer, size_t size)
242{
243 u64 val = xive_esb_read(xd, XIVE_ESB_GET);
244
245 snprintf(buffer, size, "flags=%c%c%c PQ=%c%c 0x%016llx 0x%016llx",
246 xive_is_store_eoi(xd) ? 'S' : ' ',
247 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
248 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
249 val & XIVE_ESB_VAL_P ? 'P' : '-',
250 val & XIVE_ESB_VAL_Q ? 'Q' : '-',
251 xd->trig_page, xd->eoi_page);
252}
253#endif
254
255#ifdef CONFIG_XMON
256static notrace void xive_dump_eq(const char *name, struct xive_q *q)
257{
258 u32 i0, i1, idx;
259
260 if (!q->qpage)
261 return;
262 idx = q->idx;
263 i0 = be32_to_cpup(q->qpage + idx);
264 idx = (idx + 1) & q->msk;
265 i1 = be32_to_cpup(q->qpage + idx);
266 xmon_printf("%s idx=%d T=%d %08x %08x ...", name,
267 q->idx, q->toggle, i0, i1);
268}
269
270notrace void xmon_xive_do_dump(int cpu)
271{
272 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
273
274 xmon_printf("CPU %d:", cpu);
275 if (xc) {
276 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
277
278#ifdef CONFIG_SMP
279 {
280 char buffer[128];
281
282 xive_irq_data_dump(&xc->ipi_data, buffer, sizeof(buffer));
283 xmon_printf("IPI=0x%08x %s", xc->hw_ipi, buffer);
284 }
285#endif
286 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]);
287 }
288 xmon_printf("\n");
289}
290
291static struct irq_data *xive_get_irq_data(u32 hw_irq)
292{
293 unsigned int irq = irq_find_mapping(xive_irq_domain, hw_irq);
294
295 return irq ? irq_get_irq_data(irq) : NULL;
296}
297
298int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
299{
300 int rc;
301 u32 target;
302 u8 prio;
303 u32 lirq;
304
305 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
306 if (rc) {
307 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
308 return rc;
309 }
310
311 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
312 hw_irq, target, prio, lirq);
313
314 if (!d)
315 d = xive_get_irq_data(hw_irq);
316
317 if (d) {
318 char buffer[128];
319
320 xive_irq_data_dump(irq_data_get_irq_handler_data(d),
321 buffer, sizeof(buffer));
322 xmon_printf("%s", buffer);
323 }
324
325 xmon_printf("\n");
326 return 0;
327}
328
329void xmon_xive_get_irq_all(void)
330{
331 unsigned int i;
332 struct irq_desc *desc;
333
334 for_each_irq_desc(i, desc) {
335 struct irq_data *d = irq_domain_get_irq_data(xive_irq_domain, i);
336
337 if (d)
338 xmon_xive_get_irq_config(irqd_to_hwirq(d), d);
339 }
340}
341
342#endif /* CONFIG_XMON */
343
344static unsigned int xive_get_irq(void)
345{
346 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
347 u32 irq;
348
349 /*
350 * This can be called either as a result of a HW interrupt or
351 * as a "replay" because EOI decided there was still something
352 * in one of the queues.
353 *
354 * First we perform an ACK cycle in order to update our mask
355 * of pending priorities. This will also have the effect of
356 * updating the CPPR to the most favored pending interrupts.
357 *
358 * In the future, if we have a way to differentiate a first
359 * entry (on HW interrupt) from a replay triggered by EOI,
360 * we could skip this on replays unless we soft-mask tells us
361 * that a new HW interrupt occurred.
362 */
363 xive_ops->update_pending(xc);
364
365 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
366
367 /* Scan our queue(s) for interrupts */
368 irq = xive_scan_interrupts(xc, false);
369
370 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
371 irq, xc->pending_prio);
372
373 /* Return pending interrupt if any */
374 if (irq == XIVE_BAD_IRQ)
375 return 0;
376 return irq;
377}
378
379/*
380 * After EOI'ing an interrupt, we need to re-check the queue
381 * to see if another interrupt is pending since multiple
382 * interrupts can coalesce into a single notification to the
383 * CPU.
384 *
385 * If we find that there is indeed more in there, we call
386 * force_external_irq_replay() to make Linux synthetize an
387 * external interrupt on the next call to local_irq_restore().
388 */
389static void xive_do_queue_eoi(struct xive_cpu *xc)
390{
391 if (xive_scan_interrupts(xc, true) != 0) {
392 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
393 force_external_irq_replay();
394 }
395}
396
397/*
398 * EOI an interrupt at the source. There are several methods
399 * to do this depending on the HW version and source type
400 */
401static void xive_do_source_eoi(struct xive_irq_data *xd)
402{
403 u8 eoi_val;
404
405 xd->stale_p = false;
406
407 /* If the XIVE supports the new "store EOI facility, use it */
408 if (xive_is_store_eoi(xd)) {
409 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
410 return;
411 }
412
413 /*
414 * For LSIs, we use the "EOI cycle" special load rather than
415 * PQ bits, as they are automatically re-triggered in HW when
416 * still pending.
417 */
418 if (xd->flags & XIVE_IRQ_FLAG_LSI) {
419 xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
420 return;
421 }
422
423 /*
424 * Otherwise, we use the special MMIO that does a clear of
425 * both P and Q and returns the old Q. This allows us to then
426 * do a re-trigger if Q was set rather than synthesizing an
427 * interrupt in software
428 */
429 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
430 DBG_VERBOSE("eoi_val=%x\n", eoi_val);
431
432 /* Re-trigger if needed */
433 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
434 out_be64(xd->trig_mmio, 0);
435}
436
437/* irq_chip eoi callback, called with irq descriptor lock held */
438static void xive_irq_eoi(struct irq_data *d)
439{
440 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
441 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
442
443 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
444 d->irq, irqd_to_hwirq(d), xc->pending_prio);
445
446 /*
447 * EOI the source if it hasn't been disabled and hasn't
448 * been passed-through to a KVM guest
449 */
450 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
451 !(xd->flags & XIVE_IRQ_FLAG_NO_EOI))
452 xive_do_source_eoi(xd);
453 else
454 xd->stale_p = true;
455
456 /*
457 * Clear saved_p to indicate that it's no longer occupying
458 * a queue slot on the target queue
459 */
460 xd->saved_p = false;
461
462 /* Check for more work in the queue */
463 xive_do_queue_eoi(xc);
464}
465
466/*
467 * Helper used to mask and unmask an interrupt source.
468 */
469static void xive_do_source_set_mask(struct xive_irq_data *xd,
470 bool mask)
471{
472 u64 val;
473
474 pr_debug("%s: HW 0x%x %smask\n", __func__, xd->hw_irq, mask ? "" : "un");
475
476 /*
477 * If the interrupt had P set, it may be in a queue.
478 *
479 * We need to make sure we don't re-enable it until it
480 * has been fetched from that queue and EOId. We keep
481 * a copy of that P state and use it to restore the
482 * ESB accordingly on unmask.
483 */
484 if (mask) {
485 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
486 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P))
487 xd->saved_p = true;
488 xd->stale_p = false;
489 } else if (xd->saved_p) {
490 xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
491 xd->saved_p = false;
492 } else {
493 xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
494 xd->stale_p = false;
495 }
496}
497
498/*
499 * Try to chose "cpu" as a new interrupt target. Increments
500 * the queue accounting for that target if it's not already
501 * full.
502 */
503static bool xive_try_pick_target(int cpu)
504{
505 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
506 struct xive_q *q = &xc->queue[xive_irq_priority];
507 int max;
508
509 /*
510 * Calculate max number of interrupts in that queue.
511 *
512 * We leave a gap of 1 just in case...
513 */
514 max = (q->msk + 1) - 1;
515 return !!atomic_add_unless(&q->count, 1, max);
516}
517
518/*
519 * Un-account an interrupt for a target CPU. We don't directly
520 * decrement q->count since the interrupt might still be present
521 * in the queue.
522 *
523 * Instead increment a separate counter "pending_count" which
524 * will be substracted from "count" later when that CPU observes
525 * the queue to be empty.
526 */
527static void xive_dec_target_count(int cpu)
528{
529 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
530 struct xive_q *q = &xc->queue[xive_irq_priority];
531
532 if (WARN_ON(cpu < 0 || !xc)) {
533 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
534 return;
535 }
536
537 /*
538 * We increment the "pending count" which will be used
539 * to decrement the target queue count whenever it's next
540 * processed and found empty. This ensure that we don't
541 * decrement while we still have the interrupt there
542 * occupying a slot.
543 */
544 atomic_inc(&q->pending_count);
545}
546
547/* Find a tentative CPU target in a CPU mask */
548static int xive_find_target_in_mask(const struct cpumask *mask,
549 unsigned int fuzz)
550{
551 int cpu, first, num, i;
552
553 /* Pick up a starting point CPU in the mask based on fuzz */
554 num = min_t(int, cpumask_weight(mask), nr_cpu_ids);
555 first = fuzz % num;
556
557 /* Locate it */
558 cpu = cpumask_first(mask);
559 for (i = 0; i < first && cpu < nr_cpu_ids; i++)
560 cpu = cpumask_next(cpu, mask);
561
562 /* Sanity check */
563 if (WARN_ON(cpu >= nr_cpu_ids))
564 cpu = cpumask_first(cpu_online_mask);
565
566 /* Remember first one to handle wrap-around */
567 first = cpu;
568
569 /*
570 * Now go through the entire mask until we find a valid
571 * target.
572 */
573 do {
574 /*
575 * We re-check online as the fallback case passes us
576 * an untested affinity mask
577 */
578 if (cpu_online(cpu) && xive_try_pick_target(cpu))
579 return cpu;
580 cpu = cpumask_next(cpu, mask);
581 /* Wrap around */
582 if (cpu >= nr_cpu_ids)
583 cpu = cpumask_first(mask);
584 } while (cpu != first);
585
586 return -1;
587}
588
589/*
590 * Pick a target CPU for an interrupt. This is done at
591 * startup or if the affinity is changed in a way that
592 * invalidates the current target.
593 */
594static int xive_pick_irq_target(struct irq_data *d,
595 const struct cpumask *affinity)
596{
597 static unsigned int fuzz;
598 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
599 cpumask_var_t mask;
600 int cpu = -1;
601
602 /*
603 * If we have chip IDs, first we try to build a mask of
604 * CPUs matching the CPU and find a target in there
605 */
606 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
607 zalloc_cpumask_var(&mask, GFP_ATOMIC)) {
608 /* Build a mask of matching chip IDs */
609 for_each_cpu_and(cpu, affinity, cpu_online_mask) {
610 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
611 if (xc->chip_id == xd->src_chip)
612 cpumask_set_cpu(cpu, mask);
613 }
614 /* Try to find a target */
615 if (cpumask_empty(mask))
616 cpu = -1;
617 else
618 cpu = xive_find_target_in_mask(mask, fuzz++);
619 free_cpumask_var(mask);
620 if (cpu >= 0)
621 return cpu;
622 fuzz--;
623 }
624
625 /* No chip IDs, fallback to using the affinity mask */
626 return xive_find_target_in_mask(affinity, fuzz++);
627}
628
629static unsigned int xive_irq_startup(struct irq_data *d)
630{
631 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
632 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
633 int target, rc;
634
635 xd->saved_p = false;
636 xd->stale_p = false;
637
638 pr_debug("%s: irq %d [0x%x] data @%p\n", __func__, d->irq, hw_irq, d);
639
640 /* Pick a target */
641 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d));
642 if (target == XIVE_INVALID_TARGET) {
643 /* Try again breaking affinity */
644 target = xive_pick_irq_target(d, cpu_online_mask);
645 if (target == XIVE_INVALID_TARGET)
646 return -ENXIO;
647 pr_warn("irq %d started with broken affinity\n", d->irq);
648 }
649
650 /* Sanity check */
651 if (WARN_ON(target == XIVE_INVALID_TARGET ||
652 target >= nr_cpu_ids))
653 target = smp_processor_id();
654
655 xd->target = target;
656
657 /*
658 * Configure the logical number to be the Linux IRQ number
659 * and set the target queue
660 */
661 rc = xive_ops->configure_irq(hw_irq,
662 get_hard_smp_processor_id(target),
663 xive_irq_priority, d->irq);
664 if (rc)
665 return rc;
666
667 /* Unmask the ESB */
668 xive_do_source_set_mask(xd, false);
669
670 return 0;
671}
672
673/* called with irq descriptor lock held */
674static void xive_irq_shutdown(struct irq_data *d)
675{
676 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
677 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
678
679 pr_debug("%s: irq %d [0x%x] data @%p\n", __func__, d->irq, hw_irq, d);
680
681 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
682 return;
683
684 /* Mask the interrupt at the source */
685 xive_do_source_set_mask(xd, true);
686
687 /*
688 * Mask the interrupt in HW in the IVT/EAS and set the number
689 * to be the "bad" IRQ number
690 */
691 xive_ops->configure_irq(hw_irq,
692 get_hard_smp_processor_id(xd->target),
693 0xff, XIVE_BAD_IRQ);
694
695 xive_dec_target_count(xd->target);
696 xd->target = XIVE_INVALID_TARGET;
697}
698
699static void xive_irq_unmask(struct irq_data *d)
700{
701 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
702
703 pr_debug("%s: irq %d data @%p\n", __func__, d->irq, xd);
704
705 xive_do_source_set_mask(xd, false);
706}
707
708static void xive_irq_mask(struct irq_data *d)
709{
710 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
711
712 pr_debug("%s: irq %d data @%p\n", __func__, d->irq, xd);
713
714 xive_do_source_set_mask(xd, true);
715}
716
717static int xive_irq_set_affinity(struct irq_data *d,
718 const struct cpumask *cpumask,
719 bool force)
720{
721 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
722 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
723 u32 target, old_target;
724 int rc = 0;
725
726 pr_debug("%s: irq %d/0x%x\n", __func__, d->irq, hw_irq);
727
728 /* Is this valid ? */
729 if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids)
730 return -EINVAL;
731
732 /*
733 * If existing target is already in the new mask, and is
734 * online then do nothing.
735 */
736 if (xd->target != XIVE_INVALID_TARGET &&
737 cpu_online(xd->target) &&
738 cpumask_test_cpu(xd->target, cpumask))
739 return IRQ_SET_MASK_OK;
740
741 /* Pick a new target */
742 target = xive_pick_irq_target(d, cpumask);
743
744 /* No target found */
745 if (target == XIVE_INVALID_TARGET)
746 return -ENXIO;
747
748 /* Sanity check */
749 if (WARN_ON(target >= nr_cpu_ids))
750 target = smp_processor_id();
751
752 old_target = xd->target;
753
754 /*
755 * Only configure the irq if it's not currently passed-through to
756 * a KVM guest
757 */
758 if (!irqd_is_forwarded_to_vcpu(d))
759 rc = xive_ops->configure_irq(hw_irq,
760 get_hard_smp_processor_id(target),
761 xive_irq_priority, d->irq);
762 if (rc < 0) {
763 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
764 return rc;
765 }
766
767 pr_debug(" target: 0x%x\n", target);
768 xd->target = target;
769
770 /* Give up previous target */
771 if (old_target != XIVE_INVALID_TARGET)
772 xive_dec_target_count(old_target);
773
774 return IRQ_SET_MASK_OK;
775}
776
777static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
778{
779 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
780
781 /*
782 * We only support these. This has really no effect other than setting
783 * the corresponding descriptor bits mind you but those will in turn
784 * affect the resend function when re-enabling an edge interrupt.
785 *
786 * Set the default to edge as explained in map().
787 */
788 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
789 flow_type = IRQ_TYPE_EDGE_RISING;
790
791 if (flow_type != IRQ_TYPE_EDGE_RISING &&
792 flow_type != IRQ_TYPE_LEVEL_LOW)
793 return -EINVAL;
794
795 irqd_set_trigger_type(d, flow_type);
796
797 /*
798 * Double check it matches what the FW thinks
799 *
800 * NOTE: We don't know yet if the PAPR interface will provide
801 * the LSI vs MSI information apart from the device-tree so
802 * this check might have to move into an optional backend call
803 * that is specific to the native backend
804 */
805 if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
806 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
807 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
808 d->irq, (u32)irqd_to_hwirq(d),
809 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
810 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
811 }
812
813 return IRQ_SET_MASK_OK_NOCOPY;
814}
815
816static int xive_irq_retrigger(struct irq_data *d)
817{
818 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
819
820 /* This should be only for MSIs */
821 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
822 return 0;
823
824 /*
825 * To perform a retrigger, we first set the PQ bits to
826 * 11, then perform an EOI.
827 */
828 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
829 xive_do_source_eoi(xd);
830
831 return 1;
832}
833
834/*
835 * Caller holds the irq descriptor lock, so this won't be called
836 * concurrently with xive_get_irqchip_state on the same interrupt.
837 */
838static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
839{
840 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
841 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
842 int rc;
843 u8 pq;
844
845 /*
846 * This is called by KVM with state non-NULL for enabling
847 * pass-through or NULL for disabling it
848 */
849 if (state) {
850 irqd_set_forwarded_to_vcpu(d);
851
852 /* Set it to PQ=10 state to prevent further sends */
853 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
854 if (!xd->stale_p) {
855 xd->saved_p = !!(pq & XIVE_ESB_VAL_P);
856 xd->stale_p = !xd->saved_p;
857 }
858
859 /* No target ? nothing to do */
860 if (xd->target == XIVE_INVALID_TARGET) {
861 /*
862 * An untargetted interrupt should have been
863 * also masked at the source
864 */
865 WARN_ON(xd->saved_p);
866
867 return 0;
868 }
869
870 /*
871 * If P was set, adjust state to PQ=11 to indicate
872 * that a resend is needed for the interrupt to reach
873 * the guest. Also remember the value of P.
874 *
875 * This also tells us that it's in flight to a host queue
876 * or has already been fetched but hasn't been EOIed yet
877 * by the host. This it's potentially using up a host
878 * queue slot. This is important to know because as long
879 * as this is the case, we must not hard-unmask it when
880 * "returning" that interrupt to the host.
881 *
882 * This saved_p is cleared by the host EOI, when we know
883 * for sure the queue slot is no longer in use.
884 */
885 if (xd->saved_p) {
886 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
887
888 /*
889 * Sync the XIVE source HW to ensure the interrupt
890 * has gone through the EAS before we change its
891 * target to the guest. That should guarantee us
892 * that we *will* eventually get an EOI for it on
893 * the host. Otherwise there would be a small window
894 * for P to be seen here but the interrupt going
895 * to the guest queue.
896 */
897 if (xive_ops->sync_source)
898 xive_ops->sync_source(hw_irq);
899 }
900 } else {
901 irqd_clr_forwarded_to_vcpu(d);
902
903 /* No host target ? hard mask and return */
904 if (xd->target == XIVE_INVALID_TARGET) {
905 xive_do_source_set_mask(xd, true);
906 return 0;
907 }
908
909 /*
910 * Sync the XIVE source HW to ensure the interrupt
911 * has gone through the EAS before we change its
912 * target to the host.
913 */
914 if (xive_ops->sync_source)
915 xive_ops->sync_source(hw_irq);
916
917 /*
918 * By convention we are called with the interrupt in
919 * a PQ=10 or PQ=11 state, ie, it won't fire and will
920 * have latched in Q whether there's a pending HW
921 * interrupt or not.
922 *
923 * First reconfigure the target.
924 */
925 rc = xive_ops->configure_irq(hw_irq,
926 get_hard_smp_processor_id(xd->target),
927 xive_irq_priority, d->irq);
928 if (rc)
929 return rc;
930
931 /*
932 * Then if saved_p is not set, effectively re-enable the
933 * interrupt with an EOI. If it is set, we know there is
934 * still a message in a host queue somewhere that will be
935 * EOId eventually.
936 *
937 * Note: We don't check irqd_irq_disabled(). Effectively,
938 * we *will* let the irq get through even if masked if the
939 * HW is still firing it in order to deal with the whole
940 * saved_p business properly. If the interrupt triggers
941 * while masked, the generic code will re-mask it anyway.
942 */
943 if (!xd->saved_p)
944 xive_do_source_eoi(xd);
945
946 }
947 return 0;
948}
949
950/* Called with irq descriptor lock held. */
951static int xive_get_irqchip_state(struct irq_data *data,
952 enum irqchip_irq_state which, bool *state)
953{
954 struct xive_irq_data *xd = irq_data_get_irq_handler_data(data);
955 u8 pq;
956
957 switch (which) {
958 case IRQCHIP_STATE_ACTIVE:
959 pq = xive_esb_read(xd, XIVE_ESB_GET);
960
961 /*
962 * The esb value being all 1's means we couldn't get
963 * the PQ state of the interrupt through mmio. It may
964 * happen, for example when querying a PHB interrupt
965 * while the PHB is in an error state. We consider the
966 * interrupt to be inactive in that case.
967 */
968 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&
969 (xd->saved_p || (!!(pq & XIVE_ESB_VAL_P) &&
970 !irqd_irq_disabled(data)));
971 return 0;
972 default:
973 return -EINVAL;
974 }
975}
976
977static struct irq_chip xive_irq_chip = {
978 .name = "XIVE-IRQ",
979 .irq_startup = xive_irq_startup,
980 .irq_shutdown = xive_irq_shutdown,
981 .irq_eoi = xive_irq_eoi,
982 .irq_mask = xive_irq_mask,
983 .irq_unmask = xive_irq_unmask,
984 .irq_set_affinity = xive_irq_set_affinity,
985 .irq_set_type = xive_irq_set_type,
986 .irq_retrigger = xive_irq_retrigger,
987 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
988 .irq_get_irqchip_state = xive_get_irqchip_state,
989};
990
991bool is_xive_irq(struct irq_chip *chip)
992{
993 return chip == &xive_irq_chip;
994}
995EXPORT_SYMBOL_GPL(is_xive_irq);
996
997void xive_cleanup_irq_data(struct xive_irq_data *xd)
998{
999 pr_debug("%s for HW 0x%x\n", __func__, xd->hw_irq);
1000
1001 if (xd->eoi_mmio) {
1002 iounmap(xd->eoi_mmio);
1003 if (xd->eoi_mmio == xd->trig_mmio)
1004 xd->trig_mmio = NULL;
1005 xd->eoi_mmio = NULL;
1006 }
1007 if (xd->trig_mmio) {
1008 iounmap(xd->trig_mmio);
1009 xd->trig_mmio = NULL;
1010 }
1011}
1012EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
1013
1014static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
1015{
1016 struct xive_irq_data *xd;
1017 int rc;
1018
1019 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
1020 if (!xd)
1021 return -ENOMEM;
1022 rc = xive_ops->populate_irq_data(hw, xd);
1023 if (rc) {
1024 kfree(xd);
1025 return rc;
1026 }
1027 xd->target = XIVE_INVALID_TARGET;
1028 irq_set_handler_data(virq, xd);
1029
1030 /*
1031 * Turn OFF by default the interrupt being mapped. A side
1032 * effect of this check is the mapping the ESB page of the
1033 * interrupt in the Linux address space. This prevents page
1034 * fault issues in the crash handler which masks all
1035 * interrupts.
1036 */
1037 xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
1038
1039 return 0;
1040}
1041
1042void xive_irq_free_data(unsigned int virq)
1043{
1044 struct xive_irq_data *xd = irq_get_handler_data(virq);
1045
1046 if (!xd)
1047 return;
1048 irq_set_handler_data(virq, NULL);
1049 xive_cleanup_irq_data(xd);
1050 kfree(xd);
1051}
1052EXPORT_SYMBOL_GPL(xive_irq_free_data);
1053
1054#ifdef CONFIG_SMP
1055
1056static void xive_cause_ipi(int cpu)
1057{
1058 struct xive_cpu *xc;
1059 struct xive_irq_data *xd;
1060
1061 xc = per_cpu(xive_cpu, cpu);
1062
1063 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
1064 smp_processor_id(), cpu, xc->hw_ipi);
1065
1066 xd = &xc->ipi_data;
1067 if (WARN_ON(!xd->trig_mmio))
1068 return;
1069 out_be64(xd->trig_mmio, 0);
1070}
1071
1072static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1073{
1074 return smp_ipi_demux();
1075}
1076
1077static void xive_ipi_eoi(struct irq_data *d)
1078{
1079 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1080
1081 /* Handle possible race with unplug and drop stale IPIs */
1082 if (!xc)
1083 return;
1084
1085 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1086 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1087
1088 xive_do_source_eoi(&xc->ipi_data);
1089 xive_do_queue_eoi(xc);
1090}
1091
1092static void xive_ipi_do_nothing(struct irq_data *d)
1093{
1094 /*
1095 * Nothing to do, we never mask/unmask IPIs, but the callback
1096 * has to exist for the struct irq_chip.
1097 */
1098}
1099
1100static struct irq_chip xive_ipi_chip = {
1101 .name = "XIVE-IPI",
1102 .irq_eoi = xive_ipi_eoi,
1103 .irq_mask = xive_ipi_do_nothing,
1104 .irq_unmask = xive_ipi_do_nothing,
1105};
1106
1107/*
1108 * IPIs are marked per-cpu. We use separate HW interrupts under the
1109 * hood but associated with the same "linux" interrupt
1110 */
1111struct xive_ipi_alloc_info {
1112 irq_hw_number_t hwirq;
1113};
1114
1115static int xive_ipi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1116 unsigned int nr_irqs, void *arg)
1117{
1118 struct xive_ipi_alloc_info *info = arg;
1119 int i;
1120
1121 for (i = 0; i < nr_irqs; i++) {
1122 irq_domain_set_info(domain, virq + i, info->hwirq + i, &xive_ipi_chip,
1123 domain->host_data, handle_percpu_irq,
1124 NULL, NULL);
1125 }
1126 return 0;
1127}
1128
1129static const struct irq_domain_ops xive_ipi_irq_domain_ops = {
1130 .alloc = xive_ipi_irq_domain_alloc,
1131};
1132
1133static int __init xive_init_ipis(void)
1134{
1135 struct fwnode_handle *fwnode;
1136 struct irq_domain *ipi_domain;
1137 unsigned int node;
1138 int ret = -ENOMEM;
1139
1140 fwnode = irq_domain_alloc_named_fwnode("XIVE-IPI");
1141 if (!fwnode)
1142 goto out;
1143
1144 ipi_domain = irq_domain_create_linear(fwnode, nr_node_ids,
1145 &xive_ipi_irq_domain_ops, NULL);
1146 if (!ipi_domain)
1147 goto out_free_fwnode;
1148
1149 xive_ipis = kcalloc(nr_node_ids, sizeof(*xive_ipis), GFP_KERNEL | __GFP_NOFAIL);
1150 if (!xive_ipis)
1151 goto out_free_domain;
1152
1153 for_each_node(node) {
1154 struct xive_ipi_desc *xid = &xive_ipis[node];
1155 struct xive_ipi_alloc_info info = { node };
1156
1157 /*
1158 * Map one IPI interrupt per node for all cpus of that node.
1159 * Since the HW interrupt number doesn't have any meaning,
1160 * simply use the node number.
1161 */
1162 ret = irq_domain_alloc_irqs(ipi_domain, 1, node, &info);
1163 if (ret < 0)
1164 goto out_free_xive_ipis;
1165 xid->irq = ret;
1166
1167 snprintf(xid->name, sizeof(xid->name), "IPI-%d", node);
1168 }
1169
1170 return ret;
1171
1172out_free_xive_ipis:
1173 kfree(xive_ipis);
1174out_free_domain:
1175 irq_domain_remove(ipi_domain);
1176out_free_fwnode:
1177 irq_domain_free_fwnode(fwnode);
1178out:
1179 return ret;
1180}
1181
1182static int xive_request_ipi(unsigned int cpu)
1183{
1184 struct xive_ipi_desc *xid = &xive_ipis[early_cpu_to_node(cpu)];
1185 int ret;
1186
1187 if (atomic_inc_return(&xid->started) > 1)
1188 return 0;
1189
1190 ret = request_irq(xid->irq, xive_muxed_ipi_action,
1191 IRQF_NO_DEBUG | IRQF_PERCPU | IRQF_NO_THREAD,
1192 xid->name, NULL);
1193
1194 WARN(ret < 0, "Failed to request IPI %d: %d\n", xid->irq, ret);
1195 return ret;
1196}
1197
1198static int xive_setup_cpu_ipi(unsigned int cpu)
1199{
1200 unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu);
1201 struct xive_cpu *xc;
1202 int rc;
1203
1204 pr_debug("Setting up IPI for CPU %d\n", cpu);
1205
1206 xc = per_cpu(xive_cpu, cpu);
1207
1208 /* Check if we are already setup */
1209 if (xc->hw_ipi != XIVE_BAD_IRQ)
1210 return 0;
1211
1212 /* Register the IPI */
1213 xive_request_ipi(cpu);
1214
1215 /* Grab an IPI from the backend, this will populate xc->hw_ipi */
1216 if (xive_ops->get_ipi(cpu, xc))
1217 return -EIO;
1218
1219 /*
1220 * Populate the IRQ data in the xive_cpu structure and
1221 * configure the HW / enable the IPIs.
1222 */
1223 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1224 if (rc) {
1225 pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1226 return -EIO;
1227 }
1228 rc = xive_ops->configure_irq(xc->hw_ipi,
1229 get_hard_smp_processor_id(cpu),
1230 xive_irq_priority, xive_ipi_irq);
1231 if (rc) {
1232 pr_err("Failed to map IPI CPU %d\n", cpu);
1233 return -EIO;
1234 }
1235 pr_debug("CPU %d HW IPI 0x%x, virq %d, trig_mmio=%p\n", cpu,
1236 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1237
1238 /* Unmask it */
1239 xive_do_source_set_mask(&xc->ipi_data, false);
1240
1241 return 0;
1242}
1243
1244noinstr static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1245{
1246 unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu);
1247
1248 /* Disable the IPI and free the IRQ data */
1249
1250 /* Already cleaned up ? */
1251 if (xc->hw_ipi == XIVE_BAD_IRQ)
1252 return;
1253
1254 /* TODO: clear IPI mapping */
1255
1256 /* Mask the IPI */
1257 xive_do_source_set_mask(&xc->ipi_data, true);
1258
1259 /*
1260 * Note: We don't call xive_cleanup_irq_data() to free
1261 * the mappings as this is called from an IPI on kexec
1262 * which is not a safe environment to call iounmap()
1263 */
1264
1265 /* Deconfigure/mask in the backend */
1266 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1267 0xff, xive_ipi_irq);
1268
1269 /* Free the IPIs in the backend */
1270 xive_ops->put_ipi(cpu, xc);
1271}
1272
1273void __init xive_smp_probe(void)
1274{
1275 smp_ops->cause_ipi = xive_cause_ipi;
1276
1277 /* Register the IPI */
1278 xive_init_ipis();
1279
1280 /* Allocate and setup IPI for the boot CPU */
1281 xive_setup_cpu_ipi(smp_processor_id());
1282}
1283
1284#endif /* CONFIG_SMP */
1285
1286static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1287 irq_hw_number_t hw)
1288{
1289 int rc;
1290
1291 /*
1292 * Mark interrupts as edge sensitive by default so that resend
1293 * actually works. Will fix that up below if needed.
1294 */
1295 irq_clear_status_flags(virq, IRQ_LEVEL);
1296
1297 rc = xive_irq_alloc_data(virq, hw);
1298 if (rc)
1299 return rc;
1300
1301 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq);
1302
1303 return 0;
1304}
1305
1306static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1307{
1308 xive_irq_free_data(virq);
1309}
1310
1311static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1312 const u32 *intspec, unsigned int intsize,
1313 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1314
1315{
1316 *out_hwirq = intspec[0];
1317
1318 /*
1319 * If intsize is at least 2, we look for the type in the second cell,
1320 * we assume the LSB indicates a level interrupt.
1321 */
1322 if (intsize > 1) {
1323 if (intspec[1] & 1)
1324 *out_flags = IRQ_TYPE_LEVEL_LOW;
1325 else
1326 *out_flags = IRQ_TYPE_EDGE_RISING;
1327 } else
1328 *out_flags = IRQ_TYPE_LEVEL_LOW;
1329
1330 return 0;
1331}
1332
1333static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1334 enum irq_domain_bus_token bus_token)
1335{
1336 return xive_ops->match(node);
1337}
1338
1339#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1340static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" };
1341
1342static const struct {
1343 u64 mask;
1344 char *name;
1345} xive_irq_flags[] = {
1346 { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
1347 { XIVE_IRQ_FLAG_LSI, "LSI" },
1348 { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
1349 { XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
1350};
1351
1352static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d,
1353 struct irq_data *irqd, int ind)
1354{
1355 struct xive_irq_data *xd;
1356 u64 val;
1357 int i;
1358
1359 /* No IRQ domain level information. To be done */
1360 if (!irqd)
1361 return;
1362
1363 if (!is_xive_irq(irq_data_get_irq_chip(irqd)))
1364 return;
1365
1366 seq_printf(m, "%*sXIVE:\n", ind, "");
1367 ind++;
1368
1369 xd = irq_data_get_irq_handler_data(irqd);
1370 if (!xd) {
1371 seq_printf(m, "%*snot assigned\n", ind, "");
1372 return;
1373 }
1374
1375 val = xive_esb_read(xd, XIVE_ESB_GET);
1376 seq_printf(m, "%*sESB: %s\n", ind, "", esb_names[val & 0x3]);
1377 seq_printf(m, "%*sPstate: %s %s\n", ind, "", xd->stale_p ? "stale" : "",
1378 xd->saved_p ? "saved" : "");
1379 seq_printf(m, "%*sTarget: %d\n", ind, "", xd->target);
1380 seq_printf(m, "%*sChip: %d\n", ind, "", xd->src_chip);
1381 seq_printf(m, "%*sTrigger: 0x%016llx\n", ind, "", xd->trig_page);
1382 seq_printf(m, "%*sEOI: 0x%016llx\n", ind, "", xd->eoi_page);
1383 seq_printf(m, "%*sFlags: 0x%llx\n", ind, "", xd->flags);
1384 for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {
1385 if (xd->flags & xive_irq_flags[i].mask)
1386 seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name);
1387 }
1388}
1389#endif
1390
1391#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1392static int xive_irq_domain_translate(struct irq_domain *d,
1393 struct irq_fwspec *fwspec,
1394 unsigned long *hwirq,
1395 unsigned int *type)
1396{
1397 return xive_irq_domain_xlate(d, to_of_node(fwspec->fwnode),
1398 fwspec->param, fwspec->param_count,
1399 hwirq, type);
1400}
1401
1402static int xive_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1403 unsigned int nr_irqs, void *arg)
1404{
1405 struct irq_fwspec *fwspec = arg;
1406 irq_hw_number_t hwirq;
1407 unsigned int type = IRQ_TYPE_NONE;
1408 int i, rc;
1409
1410 rc = xive_irq_domain_translate(domain, fwspec, &hwirq, &type);
1411 if (rc)
1412 return rc;
1413
1414 pr_debug("%s %d/0x%lx #%d\n", __func__, virq, hwirq, nr_irqs);
1415
1416 for (i = 0; i < nr_irqs; i++) {
1417 /* TODO: call xive_irq_domain_map() */
1418
1419 /*
1420 * Mark interrupts as edge sensitive by default so that resend
1421 * actually works. Will fix that up below if needed.
1422 */
1423 irq_clear_status_flags(virq, IRQ_LEVEL);
1424
1425 /* allocates and sets handler data */
1426 rc = xive_irq_alloc_data(virq + i, hwirq + i);
1427 if (rc)
1428 return rc;
1429
1430 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
1431 &xive_irq_chip, domain->host_data);
1432 irq_set_handler(virq + i, handle_fasteoi_irq);
1433 }
1434
1435 return 0;
1436}
1437
1438static void xive_irq_domain_free(struct irq_domain *domain,
1439 unsigned int virq, unsigned int nr_irqs)
1440{
1441 int i;
1442
1443 pr_debug("%s %d #%d\n", __func__, virq, nr_irqs);
1444
1445 for (i = 0; i < nr_irqs; i++)
1446 xive_irq_free_data(virq + i);
1447}
1448#endif
1449
1450static const struct irq_domain_ops xive_irq_domain_ops = {
1451#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1452 .alloc = xive_irq_domain_alloc,
1453 .free = xive_irq_domain_free,
1454 .translate = xive_irq_domain_translate,
1455#endif
1456 .match = xive_irq_domain_match,
1457 .map = xive_irq_domain_map,
1458 .unmap = xive_irq_domain_unmap,
1459 .xlate = xive_irq_domain_xlate,
1460#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1461 .debug_show = xive_irq_domain_debug_show,
1462#endif
1463};
1464
1465static void __init xive_init_host(struct device_node *np)
1466{
1467 xive_irq_domain = irq_domain_add_tree(np, &xive_irq_domain_ops, NULL);
1468 if (WARN_ON(xive_irq_domain == NULL))
1469 return;
1470 irq_set_default_host(xive_irq_domain);
1471}
1472
1473static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1474{
1475 if (xc->queue[xive_irq_priority].qpage)
1476 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1477}
1478
1479static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1480{
1481 int rc = 0;
1482
1483 /* We setup 1 queues for now with a 64k page */
1484 if (!xc->queue[xive_irq_priority].qpage)
1485 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1486
1487 return rc;
1488}
1489
1490static int xive_prepare_cpu(unsigned int cpu)
1491{
1492 struct xive_cpu *xc;
1493
1494 xc = per_cpu(xive_cpu, cpu);
1495 if (!xc) {
1496 xc = kzalloc_node(sizeof(struct xive_cpu),
1497 GFP_KERNEL, cpu_to_node(cpu));
1498 if (!xc)
1499 return -ENOMEM;
1500 xc->hw_ipi = XIVE_BAD_IRQ;
1501 xc->chip_id = XIVE_INVALID_CHIP_ID;
1502 if (xive_ops->prepare_cpu)
1503 xive_ops->prepare_cpu(cpu, xc);
1504
1505 per_cpu(xive_cpu, cpu) = xc;
1506 }
1507
1508 /* Setup EQs if not already */
1509 return xive_setup_cpu_queues(cpu, xc);
1510}
1511
1512static void xive_setup_cpu(void)
1513{
1514 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1515
1516 /* The backend might have additional things to do */
1517 if (xive_ops->setup_cpu)
1518 xive_ops->setup_cpu(smp_processor_id(), xc);
1519
1520 /* Set CPPR to 0xff to enable flow of interrupts */
1521 xc->cppr = 0xff;
1522 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1523}
1524
1525#ifdef CONFIG_SMP
1526void xive_smp_setup_cpu(void)
1527{
1528 pr_debug("SMP setup CPU %d\n", smp_processor_id());
1529
1530 /* This will have already been done on the boot CPU */
1531 if (smp_processor_id() != boot_cpuid)
1532 xive_setup_cpu();
1533
1534}
1535
1536int xive_smp_prepare_cpu(unsigned int cpu)
1537{
1538 int rc;
1539
1540 /* Allocate per-CPU data and queues */
1541 rc = xive_prepare_cpu(cpu);
1542 if (rc)
1543 return rc;
1544
1545 /* Allocate and setup IPI for the new CPU */
1546 return xive_setup_cpu_ipi(cpu);
1547}
1548
1549#ifdef CONFIG_HOTPLUG_CPU
1550static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1551{
1552 u32 irq;
1553
1554 /* We assume local irqs are disabled */
1555 WARN_ON(!irqs_disabled());
1556
1557 /* Check what's already in the CPU queue */
1558 while ((irq = xive_scan_interrupts(xc, false)) != 0) {
1559 /*
1560 * We need to re-route that interrupt to its new destination.
1561 * First get and lock the descriptor
1562 */
1563 struct irq_desc *desc = irq_to_desc(irq);
1564 struct irq_data *d = irq_desc_get_irq_data(desc);
1565 struct xive_irq_data *xd;
1566
1567 /*
1568 * Ignore anything that isn't a XIVE irq and ignore
1569 * IPIs, so can just be dropped.
1570 */
1571 if (d->domain != xive_irq_domain)
1572 continue;
1573
1574 /*
1575 * The IRQ should have already been re-routed, it's just a
1576 * stale in the old queue, so re-trigger it in order to make
1577 * it reach is new destination.
1578 */
1579#ifdef DEBUG_FLUSH
1580 pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1581 cpu, irq);
1582#endif
1583 raw_spin_lock(&desc->lock);
1584 xd = irq_desc_get_handler_data(desc);
1585
1586 /*
1587 * Clear saved_p to indicate that it's no longer pending
1588 */
1589 xd->saved_p = false;
1590
1591 /*
1592 * For LSIs, we EOI, this will cause a resend if it's
1593 * still asserted. Otherwise do an MSI retrigger.
1594 */
1595 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1596 xive_do_source_eoi(xd);
1597 else
1598 xive_irq_retrigger(d);
1599
1600 raw_spin_unlock(&desc->lock);
1601 }
1602}
1603
1604void xive_smp_disable_cpu(void)
1605{
1606 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1607 unsigned int cpu = smp_processor_id();
1608
1609 /* Migrate interrupts away from the CPU */
1610 irq_migrate_all_off_this_cpu();
1611
1612 /* Set CPPR to 0 to disable flow of interrupts */
1613 xc->cppr = 0;
1614 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1615
1616 /* Flush everything still in the queue */
1617 xive_flush_cpu_queue(cpu, xc);
1618
1619 /* Re-enable CPPR */
1620 xc->cppr = 0xff;
1621 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1622}
1623
1624void xive_flush_interrupt(void)
1625{
1626 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1627 unsigned int cpu = smp_processor_id();
1628
1629 /* Called if an interrupt occurs while the CPU is hot unplugged */
1630 xive_flush_cpu_queue(cpu, xc);
1631}
1632
1633#endif /* CONFIG_HOTPLUG_CPU */
1634
1635#endif /* CONFIG_SMP */
1636
1637noinstr void xive_teardown_cpu(void)
1638{
1639 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1640 unsigned int cpu = smp_processor_id();
1641
1642 /* Set CPPR to 0 to disable flow of interrupts */
1643 xc->cppr = 0;
1644 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1645
1646 if (xive_ops->teardown_cpu)
1647 xive_ops->teardown_cpu(cpu, xc);
1648
1649#ifdef CONFIG_SMP
1650 /* Get rid of IPI */
1651 xive_cleanup_cpu_ipi(cpu, xc);
1652#endif
1653
1654 /* Disable and free the queues */
1655 xive_cleanup_cpu_queues(cpu, xc);
1656}
1657
1658void xive_shutdown(void)
1659{
1660 xive_ops->shutdown();
1661}
1662
1663bool __init xive_core_init(struct device_node *np, const struct xive_ops *ops,
1664 void __iomem *area, u32 offset, u8 max_prio)
1665{
1666 xive_tima = area;
1667 xive_tima_offset = offset;
1668 xive_ops = ops;
1669 xive_irq_priority = max_prio;
1670
1671 ppc_md.get_irq = xive_get_irq;
1672 __xive_enabled = true;
1673
1674 pr_debug("Initializing host..\n");
1675 xive_init_host(np);
1676
1677 pr_debug("Initializing boot CPU..\n");
1678
1679 /* Allocate per-CPU data and queues */
1680 xive_prepare_cpu(smp_processor_id());
1681
1682 /* Get ready for interrupts */
1683 xive_setup_cpu();
1684
1685 pr_info("Interrupt handling initialized with %s backend\n",
1686 xive_ops->name);
1687 pr_info("Using priority %d for all interrupts\n", max_prio);
1688
1689 return true;
1690}
1691
1692__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1693{
1694 unsigned int alloc_order;
1695 struct page *pages;
1696 __be32 *qpage;
1697
1698 alloc_order = xive_alloc_order(queue_shift);
1699 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1700 if (!pages)
1701 return ERR_PTR(-ENOMEM);
1702 qpage = (__be32 *)page_address(pages);
1703 memset(qpage, 0, 1 << queue_shift);
1704
1705 return qpage;
1706}
1707
1708static int __init xive_off(char *arg)
1709{
1710 xive_cmdline_disabled = true;
1711 return 1;
1712}
1713__setup("xive=off", xive_off);
1714
1715static int __init xive_store_eoi_cmdline(char *arg)
1716{
1717 if (!arg)
1718 return 1;
1719
1720 if (strncmp(arg, "off", 3) == 0) {
1721 pr_info("StoreEOI disabled on kernel command line\n");
1722 xive_store_eoi = false;
1723 }
1724 return 1;
1725}
1726__setup("xive.store-eoi=", xive_store_eoi_cmdline);
1727
1728#ifdef CONFIG_DEBUG_FS
1729static void xive_debug_show_ipi(struct seq_file *m, int cpu)
1730{
1731 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1732
1733 seq_printf(m, "CPU %d: ", cpu);
1734 if (xc) {
1735 seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
1736
1737#ifdef CONFIG_SMP
1738 {
1739 char buffer[128];
1740
1741 xive_irq_data_dump(&xc->ipi_data, buffer, sizeof(buffer));
1742 seq_printf(m, "IPI=0x%08x %s", xc->hw_ipi, buffer);
1743 }
1744#endif
1745 }
1746 seq_puts(m, "\n");
1747}
1748
1749static void xive_debug_show_irq(struct seq_file *m, struct irq_data *d)
1750{
1751 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1752 int rc;
1753 u32 target;
1754 u8 prio;
1755 u32 lirq;
1756 char buffer[128];
1757
1758 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
1759 if (rc) {
1760 seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
1761 return;
1762 }
1763
1764 seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
1765 hw_irq, target, prio, lirq);
1766
1767 xive_irq_data_dump(irq_data_get_irq_handler_data(d), buffer, sizeof(buffer));
1768 seq_puts(m, buffer);
1769 seq_puts(m, "\n");
1770}
1771
1772static int xive_irq_debug_show(struct seq_file *m, void *private)
1773{
1774 unsigned int i;
1775 struct irq_desc *desc;
1776
1777 for_each_irq_desc(i, desc) {
1778 struct irq_data *d = irq_domain_get_irq_data(xive_irq_domain, i);
1779
1780 if (d)
1781 xive_debug_show_irq(m, d);
1782 }
1783 return 0;
1784}
1785DEFINE_SHOW_ATTRIBUTE(xive_irq_debug);
1786
1787static int xive_ipi_debug_show(struct seq_file *m, void *private)
1788{
1789 int cpu;
1790
1791 if (xive_ops->debug_show)
1792 xive_ops->debug_show(m, private);
1793
1794 for_each_online_cpu(cpu)
1795 xive_debug_show_ipi(m, cpu);
1796 return 0;
1797}
1798DEFINE_SHOW_ATTRIBUTE(xive_ipi_debug);
1799
1800static void xive_eq_debug_show_one(struct seq_file *m, struct xive_q *q, u8 prio)
1801{
1802 int i;
1803
1804 seq_printf(m, "EQ%d idx=%d T=%d\n", prio, q->idx, q->toggle);
1805 if (q->qpage) {
1806 for (i = 0; i < q->msk + 1; i++) {
1807 if (!(i % 8))
1808 seq_printf(m, "%05d ", i);
1809 seq_printf(m, "%08x%s", be32_to_cpup(q->qpage + i),
1810 (i + 1) % 8 ? " " : "\n");
1811 }
1812 }
1813 seq_puts(m, "\n");
1814}
1815
1816static int xive_eq_debug_show(struct seq_file *m, void *private)
1817{
1818 int cpu = (long)m->private;
1819 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1820
1821 if (xc)
1822 xive_eq_debug_show_one(m, &xc->queue[xive_irq_priority],
1823 xive_irq_priority);
1824 return 0;
1825}
1826DEFINE_SHOW_ATTRIBUTE(xive_eq_debug);
1827
1828static void xive_core_debugfs_create(void)
1829{
1830 struct dentry *xive_dir;
1831 struct dentry *xive_eq_dir;
1832 long cpu;
1833 char name[16];
1834
1835 xive_dir = debugfs_create_dir("xive", arch_debugfs_dir);
1836 if (IS_ERR(xive_dir))
1837 return;
1838
1839 debugfs_create_file("ipis", 0400, xive_dir,
1840 NULL, &xive_ipi_debug_fops);
1841 debugfs_create_file("interrupts", 0400, xive_dir,
1842 NULL, &xive_irq_debug_fops);
1843 xive_eq_dir = debugfs_create_dir("eqs", xive_dir);
1844 for_each_possible_cpu(cpu) {
1845 snprintf(name, sizeof(name), "cpu%ld", cpu);
1846 debugfs_create_file(name, 0400, xive_eq_dir, (void *)cpu,
1847 &xive_eq_debug_fops);
1848 }
1849 debugfs_create_bool("store-eoi", 0600, xive_dir, &xive_store_eoi);
1850
1851 if (xive_ops->debug_create)
1852 xive_ops->debug_create(xive_dir);
1853}
1854#else
1855static inline void xive_core_debugfs_create(void) { }
1856#endif /* CONFIG_DEBUG_FS */
1857
1858int xive_core_debug_init(void)
1859{
1860 if (xive_enabled() && IS_ENABLED(CONFIG_DEBUG_FS))
1861 xive_core_debugfs_create();
1862
1863 return 0;
1864}
1/*
2 * Copyright 2016,2017 IBM Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#define pr_fmt(fmt) "xive: " fmt
11
12#include <linux/types.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/debugfs.h>
17#include <linux/smp.h>
18#include <linux/interrupt.h>
19#include <linux/seq_file.h>
20#include <linux/init.h>
21#include <linux/cpu.h>
22#include <linux/of.h>
23#include <linux/slab.h>
24#include <linux/spinlock.h>
25#include <linux/msi.h>
26
27#include <asm/prom.h>
28#include <asm/io.h>
29#include <asm/smp.h>
30#include <asm/machdep.h>
31#include <asm/irq.h>
32#include <asm/errno.h>
33#include <asm/xive.h>
34#include <asm/xive-regs.h>
35#include <asm/xmon.h>
36
37#include "xive-internal.h"
38
39#undef DEBUG_FLUSH
40#undef DEBUG_ALL
41
42#ifdef DEBUG_ALL
43#define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \
44 smp_processor_id(), ## __VA_ARGS__)
45#else
46#define DBG_VERBOSE(fmt...) do { } while(0)
47#endif
48
49bool __xive_enabled;
50EXPORT_SYMBOL_GPL(__xive_enabled);
51bool xive_cmdline_disabled;
52
53/* We use only one priority for now */
54static u8 xive_irq_priority;
55
56/* TIMA exported to KVM */
57void __iomem *xive_tima;
58EXPORT_SYMBOL_GPL(xive_tima);
59u32 xive_tima_offset;
60
61/* Backend ops */
62static const struct xive_ops *xive_ops;
63
64/* Our global interrupt domain */
65static struct irq_domain *xive_irq_domain;
66
67#ifdef CONFIG_SMP
68/* The IPIs all use the same logical irq number */
69static u32 xive_ipi_irq;
70#endif
71
72/* Xive state for each CPU */
73static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
74
75/*
76 * A "disabled" interrupt should never fire, to catch problems
77 * we set its logical number to this
78 */
79#define XIVE_BAD_IRQ 0x7fffffff
80#define XIVE_MAX_IRQ (XIVE_BAD_IRQ - 1)
81
82/* An invalid CPU target */
83#define XIVE_INVALID_TARGET (-1)
84
85/*
86 * Read the next entry in a queue, return its content if it's valid
87 * or 0 if there is no new entry.
88 *
89 * The queue pointer is moved forward unless "just_peek" is set
90 */
91static u32 xive_read_eq(struct xive_q *q, bool just_peek)
92{
93 u32 cur;
94
95 if (!q->qpage)
96 return 0;
97 cur = be32_to_cpup(q->qpage + q->idx);
98
99 /* Check valid bit (31) vs current toggle polarity */
100 if ((cur >> 31) == q->toggle)
101 return 0;
102
103 /* If consuming from the queue ... */
104 if (!just_peek) {
105 /* Next entry */
106 q->idx = (q->idx + 1) & q->msk;
107
108 /* Wrap around: flip valid toggle */
109 if (q->idx == 0)
110 q->toggle ^= 1;
111 }
112 /* Mask out the valid bit (31) */
113 return cur & 0x7fffffff;
114}
115
116/*
117 * Scans all the queue that may have interrupts in them
118 * (based on "pending_prio") in priority order until an
119 * interrupt is found or all the queues are empty.
120 *
121 * Then updates the CPPR (Current Processor Priority
122 * Register) based on the most favored interrupt found
123 * (0xff if none) and return what was found (0 if none).
124 *
125 * If just_peek is set, return the most favored pending
126 * interrupt if any but don't update the queue pointers.
127 *
128 * Note: This function can operate generically on any number
129 * of queues (up to 8). The current implementation of the XIVE
130 * driver only uses a single queue however.
131 *
132 * Note2: This will also "flush" "the pending_count" of a queue
133 * into the "count" when that queue is observed to be empty.
134 * This is used to keep track of the amount of interrupts
135 * targetting a queue. When an interrupt is moved away from
136 * a queue, we only decrement that queue count once the queue
137 * has been observed empty to avoid races.
138 */
139static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
140{
141 u32 irq = 0;
142 u8 prio;
143
144 /* Find highest pending priority */
145 while (xc->pending_prio != 0) {
146 struct xive_q *q;
147
148 prio = ffs(xc->pending_prio) - 1;
149 DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
150
151 /* Try to fetch */
152 irq = xive_read_eq(&xc->queue[prio], just_peek);
153
154 /* Found something ? That's it */
155 if (irq)
156 break;
157
158 /* Clear pending bits */
159 xc->pending_prio &= ~(1 << prio);
160
161 /*
162 * Check if the queue count needs adjusting due to
163 * interrupts being moved away. See description of
164 * xive_dec_target_count()
165 */
166 q = &xc->queue[prio];
167 if (atomic_read(&q->pending_count)) {
168 int p = atomic_xchg(&q->pending_count, 0);
169 if (p) {
170 WARN_ON(p > atomic_read(&q->count));
171 atomic_sub(p, &q->count);
172 }
173 }
174 }
175
176 /* If nothing was found, set CPPR to 0xff */
177 if (irq == 0)
178 prio = 0xff;
179
180 /* Update HW CPPR to match if necessary */
181 if (prio != xc->cppr) {
182 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
183 xc->cppr = prio;
184 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
185 }
186
187 return irq;
188}
189
190/*
191 * This is used to perform the magic loads from an ESB
192 * described in xive.h
193 */
194static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
195{
196 u64 val;
197
198 /* Handle HW errata */
199 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
200 offset |= offset << 4;
201
202 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
203 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
204 else
205 val = in_be64(xd->eoi_mmio + offset);
206
207 return (u8)val;
208}
209
210static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
211{
212 /* Handle HW errata */
213 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
214 offset |= offset << 4;
215
216 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
217 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
218 else
219 out_be64(xd->eoi_mmio + offset, data);
220}
221
222#ifdef CONFIG_XMON
223static notrace void xive_dump_eq(const char *name, struct xive_q *q)
224{
225 u32 i0, i1, idx;
226
227 if (!q->qpage)
228 return;
229 idx = q->idx;
230 i0 = be32_to_cpup(q->qpage + idx);
231 idx = (idx + 1) & q->msk;
232 i1 = be32_to_cpup(q->qpage + idx);
233 xmon_printf(" %s Q T=%d %08x %08x ...\n", name,
234 q->toggle, i0, i1);
235}
236
237notrace void xmon_xive_do_dump(int cpu)
238{
239 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
240
241 xmon_printf("XIVE state for CPU %d:\n", cpu);
242 xmon_printf(" pp=%02x cppr=%02x\n", xc->pending_prio, xc->cppr);
243 xive_dump_eq("IRQ", &xc->queue[xive_irq_priority]);
244#ifdef CONFIG_SMP
245 {
246 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
247 xmon_printf(" IPI state: %x:%c%c\n", xc->hw_ipi,
248 val & XIVE_ESB_VAL_P ? 'P' : 'p',
249 val & XIVE_ESB_VAL_Q ? 'Q' : 'q');
250 }
251#endif
252}
253#endif /* CONFIG_XMON */
254
255static unsigned int xive_get_irq(void)
256{
257 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
258 u32 irq;
259
260 /*
261 * This can be called either as a result of a HW interrupt or
262 * as a "replay" because EOI decided there was still something
263 * in one of the queues.
264 *
265 * First we perform an ACK cycle in order to update our mask
266 * of pending priorities. This will also have the effect of
267 * updating the CPPR to the most favored pending interrupts.
268 *
269 * In the future, if we have a way to differenciate a first
270 * entry (on HW interrupt) from a replay triggered by EOI,
271 * we could skip this on replays unless we soft-mask tells us
272 * that a new HW interrupt occurred.
273 */
274 xive_ops->update_pending(xc);
275
276 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
277
278 /* Scan our queue(s) for interrupts */
279 irq = xive_scan_interrupts(xc, false);
280
281 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
282 irq, xc->pending_prio);
283
284 /* Return pending interrupt if any */
285 if (irq == XIVE_BAD_IRQ)
286 return 0;
287 return irq;
288}
289
290/*
291 * After EOI'ing an interrupt, we need to re-check the queue
292 * to see if another interrupt is pending since multiple
293 * interrupts can coalesce into a single notification to the
294 * CPU.
295 *
296 * If we find that there is indeed more in there, we call
297 * force_external_irq_replay() to make Linux synthetize an
298 * external interrupt on the next call to local_irq_restore().
299 */
300static void xive_do_queue_eoi(struct xive_cpu *xc)
301{
302 if (xive_scan_interrupts(xc, true) != 0) {
303 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
304 force_external_irq_replay();
305 }
306}
307
308/*
309 * EOI an interrupt at the source. There are several methods
310 * to do this depending on the HW version and source type
311 */
312void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
313{
314 /* If the XIVE supports the new "store EOI facility, use it */
315 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
316 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
317 else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
318 /*
319 * The FW told us to call it. This happens for some
320 * interrupt sources that need additional HW whacking
321 * beyond the ESB manipulation. For example LPC interrupts
322 * on P9 DD1.0 need a latch to be clared in the LPC bridge
323 * itself. The Firmware will take care of it.
324 */
325 if (WARN_ON_ONCE(!xive_ops->eoi))
326 return;
327 xive_ops->eoi(hw_irq);
328 } else {
329 u8 eoi_val;
330
331 /*
332 * Otherwise for EOI, we use the special MMIO that does
333 * a clear of both P and Q and returns the old Q,
334 * except for LSIs where we use the "EOI cycle" special
335 * load.
336 *
337 * This allows us to then do a re-trigger if Q was set
338 * rather than synthesizing an interrupt in software
339 *
340 * For LSIs, using the HW EOI cycle works around a problem
341 * on P9 DD1 PHBs where the other ESB accesses don't work
342 * properly.
343 */
344 if (xd->flags & XIVE_IRQ_FLAG_LSI)
345 xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
346 else {
347 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
348 DBG_VERBOSE("eoi_val=%x\n", eoi_val);
349
350 /* Re-trigger if needed */
351 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
352 out_be64(xd->trig_mmio, 0);
353 }
354 }
355}
356
357/* irq_chip eoi callback */
358static void xive_irq_eoi(struct irq_data *d)
359{
360 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
361 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
362
363 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
364 d->irq, irqd_to_hwirq(d), xc->pending_prio);
365
366 /*
367 * EOI the source if it hasn't been disabled and hasn't
368 * been passed-through to a KVM guest
369 */
370 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
371 !(xd->flags & XIVE_IRQ_NO_EOI))
372 xive_do_source_eoi(irqd_to_hwirq(d), xd);
373
374 /*
375 * Clear saved_p to indicate that it's no longer occupying
376 * a queue slot on the target queue
377 */
378 xd->saved_p = false;
379
380 /* Check for more work in the queue */
381 xive_do_queue_eoi(xc);
382}
383
384/*
385 * Helper used to mask and unmask an interrupt source. This
386 * is only called for normal interrupts that do not require
387 * masking/unmasking via firmware.
388 */
389static void xive_do_source_set_mask(struct xive_irq_data *xd,
390 bool mask)
391{
392 u64 val;
393
394 /*
395 * If the interrupt had P set, it may be in a queue.
396 *
397 * We need to make sure we don't re-enable it until it
398 * has been fetched from that queue and EOId. We keep
399 * a copy of that P state and use it to restore the
400 * ESB accordingly on unmask.
401 */
402 if (mask) {
403 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
404 xd->saved_p = !!(val & XIVE_ESB_VAL_P);
405 } else if (xd->saved_p)
406 xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
407 else
408 xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
409}
410
411/*
412 * Try to chose "cpu" as a new interrupt target. Increments
413 * the queue accounting for that target if it's not already
414 * full.
415 */
416static bool xive_try_pick_target(int cpu)
417{
418 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
419 struct xive_q *q = &xc->queue[xive_irq_priority];
420 int max;
421
422 /*
423 * Calculate max number of interrupts in that queue.
424 *
425 * We leave a gap of 1 just in case...
426 */
427 max = (q->msk + 1) - 1;
428 return !!atomic_add_unless(&q->count, 1, max);
429}
430
431/*
432 * Un-account an interrupt for a target CPU. We don't directly
433 * decrement q->count since the interrupt might still be present
434 * in the queue.
435 *
436 * Instead increment a separate counter "pending_count" which
437 * will be substracted from "count" later when that CPU observes
438 * the queue to be empty.
439 */
440static void xive_dec_target_count(int cpu)
441{
442 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
443 struct xive_q *q = &xc->queue[xive_irq_priority];
444
445 if (unlikely(WARN_ON(cpu < 0 || !xc))) {
446 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
447 return;
448 }
449
450 /*
451 * We increment the "pending count" which will be used
452 * to decrement the target queue count whenever it's next
453 * processed and found empty. This ensure that we don't
454 * decrement while we still have the interrupt there
455 * occupying a slot.
456 */
457 atomic_inc(&q->pending_count);
458}
459
460/* Find a tentative CPU target in a CPU mask */
461static int xive_find_target_in_mask(const struct cpumask *mask,
462 unsigned int fuzz)
463{
464 int cpu, first, num, i;
465
466 /* Pick up a starting point CPU in the mask based on fuzz */
467 num = min_t(int, cpumask_weight(mask), nr_cpu_ids);
468 first = fuzz % num;
469
470 /* Locate it */
471 cpu = cpumask_first(mask);
472 for (i = 0; i < first && cpu < nr_cpu_ids; i++)
473 cpu = cpumask_next(cpu, mask);
474
475 /* Sanity check */
476 if (WARN_ON(cpu >= nr_cpu_ids))
477 cpu = cpumask_first(cpu_online_mask);
478
479 /* Remember first one to handle wrap-around */
480 first = cpu;
481
482 /*
483 * Now go through the entire mask until we find a valid
484 * target.
485 */
486 for (;;) {
487 /*
488 * We re-check online as the fallback case passes us
489 * an untested affinity mask
490 */
491 if (cpu_online(cpu) && xive_try_pick_target(cpu))
492 return cpu;
493 cpu = cpumask_next(cpu, mask);
494 if (cpu == first)
495 break;
496 /* Wrap around */
497 if (cpu >= nr_cpu_ids)
498 cpu = cpumask_first(mask);
499 }
500 return -1;
501}
502
503/*
504 * Pick a target CPU for an interrupt. This is done at
505 * startup or if the affinity is changed in a way that
506 * invalidates the current target.
507 */
508static int xive_pick_irq_target(struct irq_data *d,
509 const struct cpumask *affinity)
510{
511 static unsigned int fuzz;
512 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
513 cpumask_var_t mask;
514 int cpu = -1;
515
516 /*
517 * If we have chip IDs, first we try to build a mask of
518 * CPUs matching the CPU and find a target in there
519 */
520 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
521 zalloc_cpumask_var(&mask, GFP_ATOMIC)) {
522 /* Build a mask of matching chip IDs */
523 for_each_cpu_and(cpu, affinity, cpu_online_mask) {
524 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
525 if (xc->chip_id == xd->src_chip)
526 cpumask_set_cpu(cpu, mask);
527 }
528 /* Try to find a target */
529 if (cpumask_empty(mask))
530 cpu = -1;
531 else
532 cpu = xive_find_target_in_mask(mask, fuzz++);
533 free_cpumask_var(mask);
534 if (cpu >= 0)
535 return cpu;
536 fuzz--;
537 }
538
539 /* No chip IDs, fallback to using the affinity mask */
540 return xive_find_target_in_mask(affinity, fuzz++);
541}
542
543static unsigned int xive_irq_startup(struct irq_data *d)
544{
545 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
546 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
547 int target, rc;
548
549 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n",
550 d->irq, hw_irq, d);
551
552#ifdef CONFIG_PCI_MSI
553 /*
554 * The generic MSI code returns with the interrupt disabled on the
555 * card, using the MSI mask bits. Firmware doesn't appear to unmask
556 * at that level, so we do it here by hand.
557 */
558 if (irq_data_get_msi_desc(d))
559 pci_msi_unmask_irq(d);
560#endif
561
562 /* Pick a target */
563 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d));
564 if (target == XIVE_INVALID_TARGET) {
565 /* Try again breaking affinity */
566 target = xive_pick_irq_target(d, cpu_online_mask);
567 if (target == XIVE_INVALID_TARGET)
568 return -ENXIO;
569 pr_warn("irq %d started with broken affinity\n", d->irq);
570 }
571
572 /* Sanity check */
573 if (WARN_ON(target == XIVE_INVALID_TARGET ||
574 target >= nr_cpu_ids))
575 target = smp_processor_id();
576
577 xd->target = target;
578
579 /*
580 * Configure the logical number to be the Linux IRQ number
581 * and set the target queue
582 */
583 rc = xive_ops->configure_irq(hw_irq,
584 get_hard_smp_processor_id(target),
585 xive_irq_priority, d->irq);
586 if (rc)
587 return rc;
588
589 /* Unmask the ESB */
590 xive_do_source_set_mask(xd, false);
591
592 return 0;
593}
594
595static void xive_irq_shutdown(struct irq_data *d)
596{
597 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
598 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
599
600 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n",
601 d->irq, hw_irq, d);
602
603 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
604 return;
605
606 /* Mask the interrupt at the source */
607 xive_do_source_set_mask(xd, true);
608
609 /*
610 * The above may have set saved_p. We clear it otherwise it
611 * will prevent re-enabling later on. It is ok to forget the
612 * fact that the interrupt might be in a queue because we are
613 * accounting that already in xive_dec_target_count() and will
614 * be re-routing it to a new queue with proper accounting when
615 * it's started up again
616 */
617 xd->saved_p = false;
618
619 /*
620 * Mask the interrupt in HW in the IVT/EAS and set the number
621 * to be the "bad" IRQ number
622 */
623 xive_ops->configure_irq(hw_irq,
624 get_hard_smp_processor_id(xd->target),
625 0xff, XIVE_BAD_IRQ);
626
627 xive_dec_target_count(xd->target);
628 xd->target = XIVE_INVALID_TARGET;
629}
630
631static void xive_irq_unmask(struct irq_data *d)
632{
633 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
634
635 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
636
637 /*
638 * This is a workaround for PCI LSI problems on P9, for
639 * these, we call FW to set the mask. The problems might
640 * be fixed by P9 DD2.0, if that is the case, firmware
641 * will no longer set that flag.
642 */
643 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
644 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
645 xive_ops->configure_irq(hw_irq,
646 get_hard_smp_processor_id(xd->target),
647 xive_irq_priority, d->irq);
648 return;
649 }
650
651 xive_do_source_set_mask(xd, false);
652}
653
654static void xive_irq_mask(struct irq_data *d)
655{
656 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
657
658 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
659
660 /*
661 * This is a workaround for PCI LSI problems on P9, for
662 * these, we call OPAL to set the mask. The problems might
663 * be fixed by P9 DD2.0, if that is the case, firmware
664 * will no longer set that flag.
665 */
666 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
667 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
668 xive_ops->configure_irq(hw_irq,
669 get_hard_smp_processor_id(xd->target),
670 0xff, d->irq);
671 return;
672 }
673
674 xive_do_source_set_mask(xd, true);
675}
676
677static int xive_irq_set_affinity(struct irq_data *d,
678 const struct cpumask *cpumask,
679 bool force)
680{
681 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
682 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
683 u32 target, old_target;
684 int rc = 0;
685
686 pr_devel("xive_irq_set_affinity: irq %d\n", d->irq);
687
688 /* Is this valid ? */
689 if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids)
690 return -EINVAL;
691
692 /* Don't do anything if the interrupt isn't started */
693 if (!irqd_is_started(d))
694 return IRQ_SET_MASK_OK;
695
696 /*
697 * If existing target is already in the new mask, and is
698 * online then do nothing.
699 */
700 if (xd->target != XIVE_INVALID_TARGET &&
701 cpu_online(xd->target) &&
702 cpumask_test_cpu(xd->target, cpumask))
703 return IRQ_SET_MASK_OK;
704
705 /* Pick a new target */
706 target = xive_pick_irq_target(d, cpumask);
707
708 /* No target found */
709 if (target == XIVE_INVALID_TARGET)
710 return -ENXIO;
711
712 /* Sanity check */
713 if (WARN_ON(target >= nr_cpu_ids))
714 target = smp_processor_id();
715
716 old_target = xd->target;
717
718 /*
719 * Only configure the irq if it's not currently passed-through to
720 * a KVM guest
721 */
722 if (!irqd_is_forwarded_to_vcpu(d))
723 rc = xive_ops->configure_irq(hw_irq,
724 get_hard_smp_processor_id(target),
725 xive_irq_priority, d->irq);
726 if (rc < 0) {
727 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
728 return rc;
729 }
730
731 pr_devel(" target: 0x%x\n", target);
732 xd->target = target;
733
734 /* Give up previous target */
735 if (old_target != XIVE_INVALID_TARGET)
736 xive_dec_target_count(old_target);
737
738 return IRQ_SET_MASK_OK;
739}
740
741static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
742{
743 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
744
745 /*
746 * We only support these. This has really no effect other than setting
747 * the corresponding descriptor bits mind you but those will in turn
748 * affect the resend function when re-enabling an edge interrupt.
749 *
750 * Set set the default to edge as explained in map().
751 */
752 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
753 flow_type = IRQ_TYPE_EDGE_RISING;
754
755 if (flow_type != IRQ_TYPE_EDGE_RISING &&
756 flow_type != IRQ_TYPE_LEVEL_LOW)
757 return -EINVAL;
758
759 irqd_set_trigger_type(d, flow_type);
760
761 /*
762 * Double check it matches what the FW thinks
763 *
764 * NOTE: We don't know yet if the PAPR interface will provide
765 * the LSI vs MSI information apart from the device-tree so
766 * this check might have to move into an optional backend call
767 * that is specific to the native backend
768 */
769 if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
770 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
771 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
772 d->irq, (u32)irqd_to_hwirq(d),
773 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
774 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
775 }
776
777 return IRQ_SET_MASK_OK_NOCOPY;
778}
779
780static int xive_irq_retrigger(struct irq_data *d)
781{
782 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
783
784 /* This should be only for MSIs */
785 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
786 return 0;
787
788 /*
789 * To perform a retrigger, we first set the PQ bits to
790 * 11, then perform an EOI.
791 */
792 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
793
794 /*
795 * Note: We pass "0" to the hw_irq argument in order to
796 * avoid calling into the backend EOI code which we don't
797 * want to do in the case of a re-trigger. Backends typically
798 * only do EOI for LSIs anyway.
799 */
800 xive_do_source_eoi(0, xd);
801
802 return 1;
803}
804
805static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
806{
807 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
808 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
809 int rc;
810 u8 pq;
811
812 /*
813 * We only support this on interrupts that do not require
814 * firmware calls for masking and unmasking
815 */
816 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW)
817 return -EIO;
818
819 /*
820 * This is called by KVM with state non-NULL for enabling
821 * pass-through or NULL for disabling it
822 */
823 if (state) {
824 irqd_set_forwarded_to_vcpu(d);
825
826 /* Set it to PQ=10 state to prevent further sends */
827 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
828
829 /* No target ? nothing to do */
830 if (xd->target == XIVE_INVALID_TARGET) {
831 /*
832 * An untargetted interrupt should have been
833 * also masked at the source
834 */
835 WARN_ON(pq & 2);
836
837 return 0;
838 }
839
840 /*
841 * If P was set, adjust state to PQ=11 to indicate
842 * that a resend is needed for the interrupt to reach
843 * the guest. Also remember the value of P.
844 *
845 * This also tells us that it's in flight to a host queue
846 * or has already been fetched but hasn't been EOIed yet
847 * by the host. This it's potentially using up a host
848 * queue slot. This is important to know because as long
849 * as this is the case, we must not hard-unmask it when
850 * "returning" that interrupt to the host.
851 *
852 * This saved_p is cleared by the host EOI, when we know
853 * for sure the queue slot is no longer in use.
854 */
855 if (pq & 2) {
856 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
857 xd->saved_p = true;
858
859 /*
860 * Sync the XIVE source HW to ensure the interrupt
861 * has gone through the EAS before we change its
862 * target to the guest. That should guarantee us
863 * that we *will* eventually get an EOI for it on
864 * the host. Otherwise there would be a small window
865 * for P to be seen here but the interrupt going
866 * to the guest queue.
867 */
868 if (xive_ops->sync_source)
869 xive_ops->sync_source(hw_irq);
870 } else
871 xd->saved_p = false;
872 } else {
873 irqd_clr_forwarded_to_vcpu(d);
874
875 /* No host target ? hard mask and return */
876 if (xd->target == XIVE_INVALID_TARGET) {
877 xive_do_source_set_mask(xd, true);
878 return 0;
879 }
880
881 /*
882 * Sync the XIVE source HW to ensure the interrupt
883 * has gone through the EAS before we change its
884 * target to the host.
885 */
886 if (xive_ops->sync_source)
887 xive_ops->sync_source(hw_irq);
888
889 /*
890 * By convention we are called with the interrupt in
891 * a PQ=10 or PQ=11 state, ie, it won't fire and will
892 * have latched in Q whether there's a pending HW
893 * interrupt or not.
894 *
895 * First reconfigure the target.
896 */
897 rc = xive_ops->configure_irq(hw_irq,
898 get_hard_smp_processor_id(xd->target),
899 xive_irq_priority, d->irq);
900 if (rc)
901 return rc;
902
903 /*
904 * Then if saved_p is not set, effectively re-enable the
905 * interrupt with an EOI. If it is set, we know there is
906 * still a message in a host queue somewhere that will be
907 * EOId eventually.
908 *
909 * Note: We don't check irqd_irq_disabled(). Effectively,
910 * we *will* let the irq get through even if masked if the
911 * HW is still firing it in order to deal with the whole
912 * saved_p business properly. If the interrupt triggers
913 * while masked, the generic code will re-mask it anyway.
914 */
915 if (!xd->saved_p)
916 xive_do_source_eoi(hw_irq, xd);
917
918 }
919 return 0;
920}
921
922static struct irq_chip xive_irq_chip = {
923 .name = "XIVE-IRQ",
924 .irq_startup = xive_irq_startup,
925 .irq_shutdown = xive_irq_shutdown,
926 .irq_eoi = xive_irq_eoi,
927 .irq_mask = xive_irq_mask,
928 .irq_unmask = xive_irq_unmask,
929 .irq_set_affinity = xive_irq_set_affinity,
930 .irq_set_type = xive_irq_set_type,
931 .irq_retrigger = xive_irq_retrigger,
932 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
933};
934
935bool is_xive_irq(struct irq_chip *chip)
936{
937 return chip == &xive_irq_chip;
938}
939EXPORT_SYMBOL_GPL(is_xive_irq);
940
941void xive_cleanup_irq_data(struct xive_irq_data *xd)
942{
943 if (xd->eoi_mmio) {
944 iounmap(xd->eoi_mmio);
945 if (xd->eoi_mmio == xd->trig_mmio)
946 xd->trig_mmio = NULL;
947 xd->eoi_mmio = NULL;
948 }
949 if (xd->trig_mmio) {
950 iounmap(xd->trig_mmio);
951 xd->trig_mmio = NULL;
952 }
953}
954EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
955
956static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
957{
958 struct xive_irq_data *xd;
959 int rc;
960
961 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
962 if (!xd)
963 return -ENOMEM;
964 rc = xive_ops->populate_irq_data(hw, xd);
965 if (rc) {
966 kfree(xd);
967 return rc;
968 }
969 xd->target = XIVE_INVALID_TARGET;
970 irq_set_handler_data(virq, xd);
971
972 return 0;
973}
974
975static void xive_irq_free_data(unsigned int virq)
976{
977 struct xive_irq_data *xd = irq_get_handler_data(virq);
978
979 if (!xd)
980 return;
981 irq_set_handler_data(virq, NULL);
982 xive_cleanup_irq_data(xd);
983 kfree(xd);
984}
985
986#ifdef CONFIG_SMP
987
988static void xive_cause_ipi(int cpu)
989{
990 struct xive_cpu *xc;
991 struct xive_irq_data *xd;
992
993 xc = per_cpu(xive_cpu, cpu);
994
995 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
996 smp_processor_id(), cpu, xc->hw_ipi);
997
998 xd = &xc->ipi_data;
999 if (WARN_ON(!xd->trig_mmio))
1000 return;
1001 out_be64(xd->trig_mmio, 0);
1002}
1003
1004static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1005{
1006 return smp_ipi_demux();
1007}
1008
1009static void xive_ipi_eoi(struct irq_data *d)
1010{
1011 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1012
1013 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1014 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1015
1016 /* Handle possible race with unplug and drop stale IPIs */
1017 if (!xc)
1018 return;
1019 xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data);
1020 xive_do_queue_eoi(xc);
1021}
1022
1023static void xive_ipi_do_nothing(struct irq_data *d)
1024{
1025 /*
1026 * Nothing to do, we never mask/unmask IPIs, but the callback
1027 * has to exist for the struct irq_chip.
1028 */
1029}
1030
1031static struct irq_chip xive_ipi_chip = {
1032 .name = "XIVE-IPI",
1033 .irq_eoi = xive_ipi_eoi,
1034 .irq_mask = xive_ipi_do_nothing,
1035 .irq_unmask = xive_ipi_do_nothing,
1036};
1037
1038static void __init xive_request_ipi(void)
1039{
1040 unsigned int virq;
1041
1042 /*
1043 * Initialization failed, move on, we might manage to
1044 * reach the point where we display our errors before
1045 * the system falls appart
1046 */
1047 if (!xive_irq_domain)
1048 return;
1049
1050 /* Initialize it */
1051 virq = irq_create_mapping(xive_irq_domain, 0);
1052 xive_ipi_irq = virq;
1053
1054 WARN_ON(request_irq(virq, xive_muxed_ipi_action,
1055 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
1056}
1057
1058static int xive_setup_cpu_ipi(unsigned int cpu)
1059{
1060 struct xive_cpu *xc;
1061 int rc;
1062
1063 pr_debug("Setting up IPI for CPU %d\n", cpu);
1064
1065 xc = per_cpu(xive_cpu, cpu);
1066
1067 /* Check if we are already setup */
1068 if (xc->hw_ipi != 0)
1069 return 0;
1070
1071 /* Grab an IPI from the backend, this will populate xc->hw_ipi */
1072 if (xive_ops->get_ipi(cpu, xc))
1073 return -EIO;
1074
1075 /*
1076 * Populate the IRQ data in the xive_cpu structure and
1077 * configure the HW / enable the IPIs.
1078 */
1079 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1080 if (rc) {
1081 pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1082 return -EIO;
1083 }
1084 rc = xive_ops->configure_irq(xc->hw_ipi,
1085 get_hard_smp_processor_id(cpu),
1086 xive_irq_priority, xive_ipi_irq);
1087 if (rc) {
1088 pr_err("Failed to map IPI CPU %d\n", cpu);
1089 return -EIO;
1090 }
1091 pr_devel("CPU %d HW IPI %x, virq %d, trig_mmio=%p\n", cpu,
1092 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1093
1094 /* Unmask it */
1095 xive_do_source_set_mask(&xc->ipi_data, false);
1096
1097 return 0;
1098}
1099
1100static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1101{
1102 /* Disable the IPI and free the IRQ data */
1103
1104 /* Already cleaned up ? */
1105 if (xc->hw_ipi == 0)
1106 return;
1107
1108 /* Mask the IPI */
1109 xive_do_source_set_mask(&xc->ipi_data, true);
1110
1111 /*
1112 * Note: We don't call xive_cleanup_irq_data() to free
1113 * the mappings as this is called from an IPI on kexec
1114 * which is not a safe environment to call iounmap()
1115 */
1116
1117 /* Deconfigure/mask in the backend */
1118 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1119 0xff, xive_ipi_irq);
1120
1121 /* Free the IPIs in the backend */
1122 xive_ops->put_ipi(cpu, xc);
1123}
1124
1125void __init xive_smp_probe(void)
1126{
1127 smp_ops->cause_ipi = xive_cause_ipi;
1128
1129 /* Register the IPI */
1130 xive_request_ipi();
1131
1132 /* Allocate and setup IPI for the boot CPU */
1133 xive_setup_cpu_ipi(smp_processor_id());
1134}
1135
1136#endif /* CONFIG_SMP */
1137
1138static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1139 irq_hw_number_t hw)
1140{
1141 int rc;
1142
1143 /*
1144 * Mark interrupts as edge sensitive by default so that resend
1145 * actually works. Will fix that up below if needed.
1146 */
1147 irq_clear_status_flags(virq, IRQ_LEVEL);
1148
1149#ifdef CONFIG_SMP
1150 /* IPIs are special and come up with HW number 0 */
1151 if (hw == 0) {
1152 /*
1153 * IPIs are marked per-cpu. We use separate HW interrupts under
1154 * the hood but associated with the same "linux" interrupt
1155 */
1156 irq_set_chip_and_handler(virq, &xive_ipi_chip,
1157 handle_percpu_irq);
1158 return 0;
1159 }
1160#endif
1161
1162 rc = xive_irq_alloc_data(virq, hw);
1163 if (rc)
1164 return rc;
1165
1166 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq);
1167
1168 return 0;
1169}
1170
1171static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1172{
1173 struct irq_data *data = irq_get_irq_data(virq);
1174 unsigned int hw_irq;
1175
1176 /* XXX Assign BAD number */
1177 if (!data)
1178 return;
1179 hw_irq = (unsigned int)irqd_to_hwirq(data);
1180 if (hw_irq)
1181 xive_irq_free_data(virq);
1182}
1183
1184static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1185 const u32 *intspec, unsigned int intsize,
1186 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1187
1188{
1189 *out_hwirq = intspec[0];
1190
1191 /*
1192 * If intsize is at least 2, we look for the type in the second cell,
1193 * we assume the LSB indicates a level interrupt.
1194 */
1195 if (intsize > 1) {
1196 if (intspec[1] & 1)
1197 *out_flags = IRQ_TYPE_LEVEL_LOW;
1198 else
1199 *out_flags = IRQ_TYPE_EDGE_RISING;
1200 } else
1201 *out_flags = IRQ_TYPE_LEVEL_LOW;
1202
1203 return 0;
1204}
1205
1206static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1207 enum irq_domain_bus_token bus_token)
1208{
1209 return xive_ops->match(node);
1210}
1211
1212static const struct irq_domain_ops xive_irq_domain_ops = {
1213 .match = xive_irq_domain_match,
1214 .map = xive_irq_domain_map,
1215 .unmap = xive_irq_domain_unmap,
1216 .xlate = xive_irq_domain_xlate,
1217};
1218
1219static void __init xive_init_host(void)
1220{
1221 xive_irq_domain = irq_domain_add_nomap(NULL, XIVE_MAX_IRQ,
1222 &xive_irq_domain_ops, NULL);
1223 if (WARN_ON(xive_irq_domain == NULL))
1224 return;
1225 irq_set_default_host(xive_irq_domain);
1226}
1227
1228static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1229{
1230 if (xc->queue[xive_irq_priority].qpage)
1231 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1232}
1233
1234static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1235{
1236 int rc = 0;
1237
1238 /* We setup 1 queues for now with a 64k page */
1239 if (!xc->queue[xive_irq_priority].qpage)
1240 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1241
1242 return rc;
1243}
1244
1245static int xive_prepare_cpu(unsigned int cpu)
1246{
1247 struct xive_cpu *xc;
1248
1249 xc = per_cpu(xive_cpu, cpu);
1250 if (!xc) {
1251 struct device_node *np;
1252
1253 xc = kzalloc_node(sizeof(struct xive_cpu),
1254 GFP_KERNEL, cpu_to_node(cpu));
1255 if (!xc)
1256 return -ENOMEM;
1257 np = of_get_cpu_node(cpu, NULL);
1258 if (np)
1259 xc->chip_id = of_get_ibm_chip_id(np);
1260 of_node_put(np);
1261
1262 per_cpu(xive_cpu, cpu) = xc;
1263 }
1264
1265 /* Setup EQs if not already */
1266 return xive_setup_cpu_queues(cpu, xc);
1267}
1268
1269static void xive_setup_cpu(void)
1270{
1271 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1272
1273 /* The backend might have additional things to do */
1274 if (xive_ops->setup_cpu)
1275 xive_ops->setup_cpu(smp_processor_id(), xc);
1276
1277 /* Set CPPR to 0xff to enable flow of interrupts */
1278 xc->cppr = 0xff;
1279 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1280}
1281
1282#ifdef CONFIG_SMP
1283void xive_smp_setup_cpu(void)
1284{
1285 pr_devel("SMP setup CPU %d\n", smp_processor_id());
1286
1287 /* This will have already been done on the boot CPU */
1288 if (smp_processor_id() != boot_cpuid)
1289 xive_setup_cpu();
1290
1291}
1292
1293int xive_smp_prepare_cpu(unsigned int cpu)
1294{
1295 int rc;
1296
1297 /* Allocate per-CPU data and queues */
1298 rc = xive_prepare_cpu(cpu);
1299 if (rc)
1300 return rc;
1301
1302 /* Allocate and setup IPI for the new CPU */
1303 return xive_setup_cpu_ipi(cpu);
1304}
1305
1306#ifdef CONFIG_HOTPLUG_CPU
1307static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1308{
1309 u32 irq;
1310
1311 /* We assume local irqs are disabled */
1312 WARN_ON(!irqs_disabled());
1313
1314 /* Check what's already in the CPU queue */
1315 while ((irq = xive_scan_interrupts(xc, false)) != 0) {
1316 /*
1317 * We need to re-route that interrupt to its new destination.
1318 * First get and lock the descriptor
1319 */
1320 struct irq_desc *desc = irq_to_desc(irq);
1321 struct irq_data *d = irq_desc_get_irq_data(desc);
1322 struct xive_irq_data *xd;
1323 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1324
1325 /*
1326 * Ignore anything that isn't a XIVE irq and ignore
1327 * IPIs, so can just be dropped.
1328 */
1329 if (d->domain != xive_irq_domain || hw_irq == 0)
1330 continue;
1331
1332 /*
1333 * The IRQ should have already been re-routed, it's just a
1334 * stale in the old queue, so re-trigger it in order to make
1335 * it reach is new destination.
1336 */
1337#ifdef DEBUG_FLUSH
1338 pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1339 cpu, irq);
1340#endif
1341 raw_spin_lock(&desc->lock);
1342 xd = irq_desc_get_handler_data(desc);
1343
1344 /*
1345 * For LSIs, we EOI, this will cause a resend if it's
1346 * still asserted. Otherwise do an MSI retrigger.
1347 */
1348 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1349 xive_do_source_eoi(irqd_to_hwirq(d), xd);
1350 else
1351 xive_irq_retrigger(d);
1352
1353 raw_spin_unlock(&desc->lock);
1354 }
1355}
1356
1357void xive_smp_disable_cpu(void)
1358{
1359 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1360 unsigned int cpu = smp_processor_id();
1361
1362 /* Migrate interrupts away from the CPU */
1363 irq_migrate_all_off_this_cpu();
1364
1365 /* Set CPPR to 0 to disable flow of interrupts */
1366 xc->cppr = 0;
1367 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1368
1369 /* Flush everything still in the queue */
1370 xive_flush_cpu_queue(cpu, xc);
1371
1372 /* Re-enable CPPR */
1373 xc->cppr = 0xff;
1374 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1375}
1376
1377void xive_flush_interrupt(void)
1378{
1379 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1380 unsigned int cpu = smp_processor_id();
1381
1382 /* Called if an interrupt occurs while the CPU is hot unplugged */
1383 xive_flush_cpu_queue(cpu, xc);
1384}
1385
1386#endif /* CONFIG_HOTPLUG_CPU */
1387
1388#endif /* CONFIG_SMP */
1389
1390void xive_teardown_cpu(void)
1391{
1392 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1393 unsigned int cpu = smp_processor_id();
1394
1395 /* Set CPPR to 0 to disable flow of interrupts */
1396 xc->cppr = 0;
1397 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1398
1399 if (xive_ops->teardown_cpu)
1400 xive_ops->teardown_cpu(cpu, xc);
1401
1402#ifdef CONFIG_SMP
1403 /* Get rid of IPI */
1404 xive_cleanup_cpu_ipi(cpu, xc);
1405#endif
1406
1407 /* Disable and free the queues */
1408 xive_cleanup_cpu_queues(cpu, xc);
1409}
1410
1411void xive_kexec_teardown_cpu(int secondary)
1412{
1413 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1414 unsigned int cpu = smp_processor_id();
1415
1416 /* Set CPPR to 0 to disable flow of interrupts */
1417 xc->cppr = 0;
1418 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1419
1420 /* Backend cleanup if any */
1421 if (xive_ops->teardown_cpu)
1422 xive_ops->teardown_cpu(cpu, xc);
1423
1424#ifdef CONFIG_SMP
1425 /* Get rid of IPI */
1426 xive_cleanup_cpu_ipi(cpu, xc);
1427#endif
1428
1429 /* Disable and free the queues */
1430 xive_cleanup_cpu_queues(cpu, xc);
1431}
1432
1433void xive_shutdown(void)
1434{
1435 xive_ops->shutdown();
1436}
1437
1438bool __init xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
1439 u8 max_prio)
1440{
1441 xive_tima = area;
1442 xive_tima_offset = offset;
1443 xive_ops = ops;
1444 xive_irq_priority = max_prio;
1445
1446 ppc_md.get_irq = xive_get_irq;
1447 __xive_enabled = true;
1448
1449 pr_devel("Initializing host..\n");
1450 xive_init_host();
1451
1452 pr_devel("Initializing boot CPU..\n");
1453
1454 /* Allocate per-CPU data and queues */
1455 xive_prepare_cpu(smp_processor_id());
1456
1457 /* Get ready for interrupts */
1458 xive_setup_cpu();
1459
1460 pr_info("Interrupt handling initialized with %s backend\n",
1461 xive_ops->name);
1462 pr_info("Using priority %d for all interrupts\n", max_prio);
1463
1464 return true;
1465}
1466
1467__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1468{
1469 unsigned int alloc_order;
1470 struct page *pages;
1471 __be32 *qpage;
1472
1473 alloc_order = xive_alloc_order(queue_shift);
1474 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1475 if (!pages)
1476 return ERR_PTR(-ENOMEM);
1477 qpage = (__be32 *)page_address(pages);
1478 memset(qpage, 0, 1 << queue_shift);
1479
1480 return qpage;
1481}
1482
1483static int __init xive_off(char *arg)
1484{
1485 xive_cmdline_disabled = true;
1486 return 0;
1487}
1488__setup("xive=off", xive_off);