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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * General Purpose functions for the global management of the
4 * Communication Processor Module.
5 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
6 *
7 * In addition to the individual control of the communication
8 * channels, there are a few functions that globally affect the
9 * communication processor.
10 *
11 * Buffer descriptors must be allocated from the dual ported memory
12 * space. The allocator for that is here. When the communication
13 * process is reset, we reclaim the memory available. There is
14 * currently no deallocator for this memory.
15 * The amount of space available is platform dependent. On the
16 * MBX, the EPPC software loads additional microcode into the
17 * communication processor, and uses some of the DP ram for this
18 * purpose. Current, the first 512 bytes and the last 256 bytes of
19 * memory are used. Right now I am conservative and only use the
20 * memory that can never be used for microcode. If there are
21 * applications that require more DP ram, we can expand the boundaries
22 * but then we have to be careful of any downloaded microcode.
23 */
24#include <linux/errno.h>
25#include <linux/sched.h>
26#include <linux/kernel.h>
27#include <linux/dma-mapping.h>
28#include <linux/param.h>
29#include <linux/string.h>
30#include <linux/mm.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/module.h>
34#include <linux/spinlock.h>
35#include <linux/slab.h>
36#include <asm/page.h>
37#include <asm/pgtable.h>
38#include <asm/8xx_immap.h>
39#include <asm/cpm1.h>
40#include <asm/io.h>
41#include <asm/tlbflush.h>
42#include <asm/rheap.h>
43#include <asm/prom.h>
44#include <asm/cpm.h>
45
46#include <asm/fs_pd.h>
47
48#ifdef CONFIG_8xx_GPIO
49#include <linux/of_gpio.h>
50#endif
51
52#define CPM_MAP_SIZE (0x4000)
53
54cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
55immap_t __iomem *mpc8xx_immr;
56static cpic8xx_t __iomem *cpic_reg;
57
58static struct irq_domain *cpm_pic_host;
59
60static void cpm_mask_irq(struct irq_data *d)
61{
62 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
63
64 clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
65}
66
67static void cpm_unmask_irq(struct irq_data *d)
68{
69 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
70
71 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
72}
73
74static void cpm_end_irq(struct irq_data *d)
75{
76 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
77
78 out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
79}
80
81static struct irq_chip cpm_pic = {
82 .name = "CPM PIC",
83 .irq_mask = cpm_mask_irq,
84 .irq_unmask = cpm_unmask_irq,
85 .irq_eoi = cpm_end_irq,
86};
87
88int cpm_get_irq(void)
89{
90 int cpm_vec;
91
92 /* Get the vector by setting the ACK bit and then reading
93 * the register.
94 */
95 out_be16(&cpic_reg->cpic_civr, 1);
96 cpm_vec = in_be16(&cpic_reg->cpic_civr);
97 cpm_vec >>= 11;
98
99 return irq_linear_revmap(cpm_pic_host, cpm_vec);
100}
101
102static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
103 irq_hw_number_t hw)
104{
105 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
106
107 irq_set_status_flags(virq, IRQ_LEVEL);
108 irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
109 return 0;
110}
111
112/* The CPM can generate the error interrupt when there is a race condition
113 * between generating and masking interrupts. All we have to do is ACK it
114 * and return. This is a no-op function so we don't need any special
115 * tests in the interrupt handler.
116 */
117static irqreturn_t cpm_error_interrupt(int irq, void *dev)
118{
119 return IRQ_HANDLED;
120}
121
122static struct irqaction cpm_error_irqaction = {
123 .handler = cpm_error_interrupt,
124 .flags = IRQF_NO_THREAD,
125 .name = "error",
126};
127
128static const struct irq_domain_ops cpm_pic_host_ops = {
129 .map = cpm_pic_host_map,
130};
131
132unsigned int cpm_pic_init(void)
133{
134 struct device_node *np = NULL;
135 struct resource res;
136 unsigned int sirq = 0, hwirq, eirq;
137 int ret;
138
139 pr_debug("cpm_pic_init\n");
140
141 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
142 if (np == NULL)
143 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
144 if (np == NULL) {
145 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
146 return sirq;
147 }
148
149 ret = of_address_to_resource(np, 0, &res);
150 if (ret)
151 goto end;
152
153 cpic_reg = ioremap(res.start, resource_size(&res));
154 if (cpic_reg == NULL)
155 goto end;
156
157 sirq = irq_of_parse_and_map(np, 0);
158 if (!sirq)
159 goto end;
160
161 /* Initialize the CPM interrupt controller. */
162 hwirq = (unsigned int)virq_to_hw(sirq);
163 out_be32(&cpic_reg->cpic_cicr,
164 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
165 ((hwirq/2) << 13) | CICR_HP_MASK);
166
167 out_be32(&cpic_reg->cpic_cimr, 0);
168
169 cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
170 if (cpm_pic_host == NULL) {
171 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
172 sirq = 0;
173 goto end;
174 }
175
176 /* Install our own error handler. */
177 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
178 if (np == NULL)
179 np = of_find_node_by_type(NULL, "cpm");
180 if (np == NULL) {
181 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
182 goto end;
183 }
184
185 eirq = irq_of_parse_and_map(np, 0);
186 if (!eirq)
187 goto end;
188
189 if (setup_irq(eirq, &cpm_error_irqaction))
190 printk(KERN_ERR "Could not allocate CPM error IRQ!");
191
192 setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
193
194end:
195 of_node_put(np);
196 return sirq;
197}
198
199void __init cpm_reset(void)
200{
201 sysconf8xx_t __iomem *siu_conf;
202
203 mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
204 if (!mpc8xx_immr) {
205 printk(KERN_CRIT "Could not map IMMR\n");
206 return;
207 }
208
209 cpmp = &mpc8xx_immr->im_cpm;
210
211#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
212 /* Perform a reset.
213 */
214 out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
215
216 /* Wait for it.
217 */
218 while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
219#endif
220
221#ifdef CONFIG_UCODE_PATCH
222 cpm_load_patch(cpmp);
223#endif
224
225 /* Set SDMA Bus Request priority 5.
226 * On 860T, this also enables FEC priority 6. I am not sure
227 * this is what we really want for some applications, but the
228 * manual recommends it.
229 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
230 */
231 siu_conf = immr_map(im_siu_conf);
232 if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
233 out_be32(&siu_conf->sc_sdcr, 0x40);
234 else
235 out_be32(&siu_conf->sc_sdcr, 1);
236 immr_unmap(siu_conf);
237}
238
239static DEFINE_SPINLOCK(cmd_lock);
240
241#define MAX_CR_CMD_LOOPS 10000
242
243int cpm_command(u32 command, u8 opcode)
244{
245 int i, ret;
246 unsigned long flags;
247
248 if (command & 0xffffff0f)
249 return -EINVAL;
250
251 spin_lock_irqsave(&cmd_lock, flags);
252
253 ret = 0;
254 out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
255 for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
256 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
257 goto out;
258
259 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
260 ret = -EIO;
261out:
262 spin_unlock_irqrestore(&cmd_lock, flags);
263 return ret;
264}
265EXPORT_SYMBOL(cpm_command);
266
267/* Set a baud rate generator. This needs lots of work. There are
268 * four BRGs, any of which can be wired to any channel.
269 * The internal baud rate clock is the system clock divided by 16.
270 * This assumes the baudrate is 16x oversampled by the uart.
271 */
272#define BRG_INT_CLK (get_brgfreq())
273#define BRG_UART_CLK (BRG_INT_CLK/16)
274#define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
275
276void
277cpm_setbrg(uint brg, uint rate)
278{
279 u32 __iomem *bp;
280
281 /* This is good enough to get SMCs running.....
282 */
283 bp = &cpmp->cp_brgc1;
284 bp += brg;
285 /* The BRG has a 12-bit counter. For really slow baud rates (or
286 * really fast processors), we may have to further divide by 16.
287 */
288 if (((BRG_UART_CLK / rate) - 1) < 4096)
289 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
290 else
291 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
292 CPM_BRG_EN | CPM_BRG_DIV16);
293}
294
295struct cpm_ioport16 {
296 __be16 dir, par, odr_sor, dat, intr;
297 __be16 res[3];
298};
299
300struct cpm_ioport32b {
301 __be32 dir, par, odr, dat;
302};
303
304struct cpm_ioport32e {
305 __be32 dir, par, sor, odr, dat;
306};
307
308static void cpm1_set_pin32(int port, int pin, int flags)
309{
310 struct cpm_ioport32e __iomem *iop;
311 pin = 1 << (31 - pin);
312
313 if (port == CPM_PORTB)
314 iop = (struct cpm_ioport32e __iomem *)
315 &mpc8xx_immr->im_cpm.cp_pbdir;
316 else
317 iop = (struct cpm_ioport32e __iomem *)
318 &mpc8xx_immr->im_cpm.cp_pedir;
319
320 if (flags & CPM_PIN_OUTPUT)
321 setbits32(&iop->dir, pin);
322 else
323 clrbits32(&iop->dir, pin);
324
325 if (!(flags & CPM_PIN_GPIO))
326 setbits32(&iop->par, pin);
327 else
328 clrbits32(&iop->par, pin);
329
330 if (port == CPM_PORTB) {
331 if (flags & CPM_PIN_OPENDRAIN)
332 setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
333 else
334 clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
335 }
336
337 if (port == CPM_PORTE) {
338 if (flags & CPM_PIN_SECONDARY)
339 setbits32(&iop->sor, pin);
340 else
341 clrbits32(&iop->sor, pin);
342
343 if (flags & CPM_PIN_OPENDRAIN)
344 setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
345 else
346 clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
347 }
348}
349
350static void cpm1_set_pin16(int port, int pin, int flags)
351{
352 struct cpm_ioport16 __iomem *iop =
353 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
354
355 pin = 1 << (15 - pin);
356
357 if (port != 0)
358 iop += port - 1;
359
360 if (flags & CPM_PIN_OUTPUT)
361 setbits16(&iop->dir, pin);
362 else
363 clrbits16(&iop->dir, pin);
364
365 if (!(flags & CPM_PIN_GPIO))
366 setbits16(&iop->par, pin);
367 else
368 clrbits16(&iop->par, pin);
369
370 if (port == CPM_PORTA) {
371 if (flags & CPM_PIN_OPENDRAIN)
372 setbits16(&iop->odr_sor, pin);
373 else
374 clrbits16(&iop->odr_sor, pin);
375 }
376 if (port == CPM_PORTC) {
377 if (flags & CPM_PIN_SECONDARY)
378 setbits16(&iop->odr_sor, pin);
379 else
380 clrbits16(&iop->odr_sor, pin);
381 if (flags & CPM_PIN_FALLEDGE)
382 setbits16(&iop->intr, pin);
383 else
384 clrbits16(&iop->intr, pin);
385 }
386}
387
388void cpm1_set_pin(enum cpm_port port, int pin, int flags)
389{
390 if (port == CPM_PORTB || port == CPM_PORTE)
391 cpm1_set_pin32(port, pin, flags);
392 else
393 cpm1_set_pin16(port, pin, flags);
394}
395
396int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
397{
398 int shift;
399 int i, bits = 0;
400 u32 __iomem *reg;
401 u32 mask = 7;
402
403 u8 clk_map[][3] = {
404 {CPM_CLK_SCC1, CPM_BRG1, 0},
405 {CPM_CLK_SCC1, CPM_BRG2, 1},
406 {CPM_CLK_SCC1, CPM_BRG3, 2},
407 {CPM_CLK_SCC1, CPM_BRG4, 3},
408 {CPM_CLK_SCC1, CPM_CLK1, 4},
409 {CPM_CLK_SCC1, CPM_CLK2, 5},
410 {CPM_CLK_SCC1, CPM_CLK3, 6},
411 {CPM_CLK_SCC1, CPM_CLK4, 7},
412
413 {CPM_CLK_SCC2, CPM_BRG1, 0},
414 {CPM_CLK_SCC2, CPM_BRG2, 1},
415 {CPM_CLK_SCC2, CPM_BRG3, 2},
416 {CPM_CLK_SCC2, CPM_BRG4, 3},
417 {CPM_CLK_SCC2, CPM_CLK1, 4},
418 {CPM_CLK_SCC2, CPM_CLK2, 5},
419 {CPM_CLK_SCC2, CPM_CLK3, 6},
420 {CPM_CLK_SCC2, CPM_CLK4, 7},
421
422 {CPM_CLK_SCC3, CPM_BRG1, 0},
423 {CPM_CLK_SCC3, CPM_BRG2, 1},
424 {CPM_CLK_SCC3, CPM_BRG3, 2},
425 {CPM_CLK_SCC3, CPM_BRG4, 3},
426 {CPM_CLK_SCC3, CPM_CLK5, 4},
427 {CPM_CLK_SCC3, CPM_CLK6, 5},
428 {CPM_CLK_SCC3, CPM_CLK7, 6},
429 {CPM_CLK_SCC3, CPM_CLK8, 7},
430
431 {CPM_CLK_SCC4, CPM_BRG1, 0},
432 {CPM_CLK_SCC4, CPM_BRG2, 1},
433 {CPM_CLK_SCC4, CPM_BRG3, 2},
434 {CPM_CLK_SCC4, CPM_BRG4, 3},
435 {CPM_CLK_SCC4, CPM_CLK5, 4},
436 {CPM_CLK_SCC4, CPM_CLK6, 5},
437 {CPM_CLK_SCC4, CPM_CLK7, 6},
438 {CPM_CLK_SCC4, CPM_CLK8, 7},
439
440 {CPM_CLK_SMC1, CPM_BRG1, 0},
441 {CPM_CLK_SMC1, CPM_BRG2, 1},
442 {CPM_CLK_SMC1, CPM_BRG3, 2},
443 {CPM_CLK_SMC1, CPM_BRG4, 3},
444 {CPM_CLK_SMC1, CPM_CLK1, 4},
445 {CPM_CLK_SMC1, CPM_CLK2, 5},
446 {CPM_CLK_SMC1, CPM_CLK3, 6},
447 {CPM_CLK_SMC1, CPM_CLK4, 7},
448
449 {CPM_CLK_SMC2, CPM_BRG1, 0},
450 {CPM_CLK_SMC2, CPM_BRG2, 1},
451 {CPM_CLK_SMC2, CPM_BRG3, 2},
452 {CPM_CLK_SMC2, CPM_BRG4, 3},
453 {CPM_CLK_SMC2, CPM_CLK5, 4},
454 {CPM_CLK_SMC2, CPM_CLK6, 5},
455 {CPM_CLK_SMC2, CPM_CLK7, 6},
456 {CPM_CLK_SMC2, CPM_CLK8, 7},
457 };
458
459 switch (target) {
460 case CPM_CLK_SCC1:
461 reg = &mpc8xx_immr->im_cpm.cp_sicr;
462 shift = 0;
463 break;
464
465 case CPM_CLK_SCC2:
466 reg = &mpc8xx_immr->im_cpm.cp_sicr;
467 shift = 8;
468 break;
469
470 case CPM_CLK_SCC3:
471 reg = &mpc8xx_immr->im_cpm.cp_sicr;
472 shift = 16;
473 break;
474
475 case CPM_CLK_SCC4:
476 reg = &mpc8xx_immr->im_cpm.cp_sicr;
477 shift = 24;
478 break;
479
480 case CPM_CLK_SMC1:
481 reg = &mpc8xx_immr->im_cpm.cp_simode;
482 shift = 12;
483 break;
484
485 case CPM_CLK_SMC2:
486 reg = &mpc8xx_immr->im_cpm.cp_simode;
487 shift = 28;
488 break;
489
490 default:
491 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
492 return -EINVAL;
493 }
494
495 for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
496 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
497 bits = clk_map[i][2];
498 break;
499 }
500 }
501
502 if (i == ARRAY_SIZE(clk_map)) {
503 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
504 return -EINVAL;
505 }
506
507 bits <<= shift;
508 mask <<= shift;
509
510 if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
511 if (mode == CPM_CLK_RTX) {
512 bits |= bits << 3;
513 mask |= mask << 3;
514 } else if (mode == CPM_CLK_RX) {
515 bits <<= 3;
516 mask <<= 3;
517 }
518 }
519
520 out_be32(reg, (in_be32(reg) & ~mask) | bits);
521
522 return 0;
523}
524
525/*
526 * GPIO LIB API implementation
527 */
528#ifdef CONFIG_8xx_GPIO
529
530struct cpm1_gpio16_chip {
531 struct of_mm_gpio_chip mm_gc;
532 spinlock_t lock;
533
534 /* shadowed data register to clear/set bits safely */
535 u16 cpdata;
536
537 /* IRQ associated with Pins when relevant */
538 int irq[16];
539};
540
541static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
542{
543 struct cpm1_gpio16_chip *cpm1_gc =
544 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
545 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
546
547 cpm1_gc->cpdata = in_be16(&iop->dat);
548}
549
550static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
551{
552 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
553 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
554 u16 pin_mask;
555
556 pin_mask = 1 << (15 - gpio);
557
558 return !!(in_be16(&iop->dat) & pin_mask);
559}
560
561static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
562 int value)
563{
564 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
565 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
566
567 if (value)
568 cpm1_gc->cpdata |= pin_mask;
569 else
570 cpm1_gc->cpdata &= ~pin_mask;
571
572 out_be16(&iop->dat, cpm1_gc->cpdata);
573}
574
575static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
576{
577 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
578 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
579 unsigned long flags;
580 u16 pin_mask = 1 << (15 - gpio);
581
582 spin_lock_irqsave(&cpm1_gc->lock, flags);
583
584 __cpm1_gpio16_set(mm_gc, pin_mask, value);
585
586 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
587}
588
589static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
590{
591 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
592 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
593
594 return cpm1_gc->irq[gpio] ? : -ENXIO;
595}
596
597static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
598{
599 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
600 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
601 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
602 unsigned long flags;
603 u16 pin_mask = 1 << (15 - gpio);
604
605 spin_lock_irqsave(&cpm1_gc->lock, flags);
606
607 setbits16(&iop->dir, pin_mask);
608 __cpm1_gpio16_set(mm_gc, pin_mask, val);
609
610 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
611
612 return 0;
613}
614
615static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
616{
617 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
618 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
619 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
620 unsigned long flags;
621 u16 pin_mask = 1 << (15 - gpio);
622
623 spin_lock_irqsave(&cpm1_gc->lock, flags);
624
625 clrbits16(&iop->dir, pin_mask);
626
627 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
628
629 return 0;
630}
631
632int cpm1_gpiochip_add16(struct device *dev)
633{
634 struct device_node *np = dev->of_node;
635 struct cpm1_gpio16_chip *cpm1_gc;
636 struct of_mm_gpio_chip *mm_gc;
637 struct gpio_chip *gc;
638 u16 mask;
639
640 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
641 if (!cpm1_gc)
642 return -ENOMEM;
643
644 spin_lock_init(&cpm1_gc->lock);
645
646 if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
647 int i, j;
648
649 for (i = 0, j = 0; i < 16; i++)
650 if (mask & (1 << (15 - i)))
651 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
652 }
653
654 mm_gc = &cpm1_gc->mm_gc;
655 gc = &mm_gc->gc;
656
657 mm_gc->save_regs = cpm1_gpio16_save_regs;
658 gc->ngpio = 16;
659 gc->direction_input = cpm1_gpio16_dir_in;
660 gc->direction_output = cpm1_gpio16_dir_out;
661 gc->get = cpm1_gpio16_get;
662 gc->set = cpm1_gpio16_set;
663 gc->to_irq = cpm1_gpio16_to_irq;
664 gc->parent = dev;
665 gc->owner = THIS_MODULE;
666
667 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
668}
669
670struct cpm1_gpio32_chip {
671 struct of_mm_gpio_chip mm_gc;
672 spinlock_t lock;
673
674 /* shadowed data register to clear/set bits safely */
675 u32 cpdata;
676};
677
678static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
679{
680 struct cpm1_gpio32_chip *cpm1_gc =
681 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
682 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
683
684 cpm1_gc->cpdata = in_be32(&iop->dat);
685}
686
687static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
688{
689 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
690 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
691 u32 pin_mask;
692
693 pin_mask = 1 << (31 - gpio);
694
695 return !!(in_be32(&iop->dat) & pin_mask);
696}
697
698static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
699 int value)
700{
701 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
702 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
703
704 if (value)
705 cpm1_gc->cpdata |= pin_mask;
706 else
707 cpm1_gc->cpdata &= ~pin_mask;
708
709 out_be32(&iop->dat, cpm1_gc->cpdata);
710}
711
712static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
713{
714 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
715 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
716 unsigned long flags;
717 u32 pin_mask = 1 << (31 - gpio);
718
719 spin_lock_irqsave(&cpm1_gc->lock, flags);
720
721 __cpm1_gpio32_set(mm_gc, pin_mask, value);
722
723 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
724}
725
726static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
727{
728 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
729 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
730 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
731 unsigned long flags;
732 u32 pin_mask = 1 << (31 - gpio);
733
734 spin_lock_irqsave(&cpm1_gc->lock, flags);
735
736 setbits32(&iop->dir, pin_mask);
737 __cpm1_gpio32_set(mm_gc, pin_mask, val);
738
739 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
740
741 return 0;
742}
743
744static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
745{
746 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
747 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
748 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
749 unsigned long flags;
750 u32 pin_mask = 1 << (31 - gpio);
751
752 spin_lock_irqsave(&cpm1_gc->lock, flags);
753
754 clrbits32(&iop->dir, pin_mask);
755
756 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
757
758 return 0;
759}
760
761int cpm1_gpiochip_add32(struct device *dev)
762{
763 struct device_node *np = dev->of_node;
764 struct cpm1_gpio32_chip *cpm1_gc;
765 struct of_mm_gpio_chip *mm_gc;
766 struct gpio_chip *gc;
767
768 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
769 if (!cpm1_gc)
770 return -ENOMEM;
771
772 spin_lock_init(&cpm1_gc->lock);
773
774 mm_gc = &cpm1_gc->mm_gc;
775 gc = &mm_gc->gc;
776
777 mm_gc->save_regs = cpm1_gpio32_save_regs;
778 gc->ngpio = 32;
779 gc->direction_input = cpm1_gpio32_dir_in;
780 gc->direction_output = cpm1_gpio32_dir_out;
781 gc->get = cpm1_gpio32_get;
782 gc->set = cpm1_gpio32_set;
783 gc->parent = dev;
784 gc->owner = THIS_MODULE;
785
786 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
787}
788
789#endif /* CONFIG_8xx_GPIO */