1/*
  2 * arch/powerpc/oprofile/op_model_7450.c
  3 *
  4 * Freescale 745x/744x oprofile support, based on fsl_booke support
  5 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
  6 *
  7 * Copyright (c) 2004 Freescale Semiconductor, Inc
  8 *
  9 * Author: Andy Fleming
 10 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
 11 *
 12 * This program is free software; you can redistribute it and/or
 13 * modify it under the terms of the GNU General Public License
 14 * as published by the Free Software Foundation; either version
 15 * 2 of the License, or (at your option) any later version.
 16 */
 17
 18#include <linux/oprofile.h>
 19#include <linux/smp.h>
 20#include <asm/ptrace.h>
 21#include <asm/processor.h>
 22#include <asm/cputable.h>
 23#include <asm/page.h>
 24#include <asm/pmc.h>
 25#include <asm/oprofile_impl.h>
 26
 27static unsigned long reset_value[OP_MAX_COUNTER];
 28
 29static int oprofile_running;
 30static u32 mmcr0_val, mmcr1_val, mmcr2_val, num_pmcs;
 31
 32#define MMCR0_PMC1_SHIFT	6
 33#define MMCR0_PMC2_SHIFT	0
 34#define MMCR1_PMC3_SHIFT	27
 35#define MMCR1_PMC4_SHIFT	22
 36#define MMCR1_PMC5_SHIFT	17
 37#define MMCR1_PMC6_SHIFT	11
 38
 39#define mmcr0_event1(event) \
 40	((event << MMCR0_PMC1_SHIFT) & MMCR0_PMC1SEL)
 41#define mmcr0_event2(event) \
 42	((event << MMCR0_PMC2_SHIFT) & MMCR0_PMC2SEL)
 43
 44#define mmcr1_event3(event) \
 45	((event << MMCR1_PMC3_SHIFT) & MMCR1_PMC3SEL)
 46#define mmcr1_event4(event) \
 47	((event << MMCR1_PMC4_SHIFT) & MMCR1_PMC4SEL)
 48#define mmcr1_event5(event) \
 49	((event << MMCR1_PMC5_SHIFT) & MMCR1_PMC5SEL)
 50#define mmcr1_event6(event) \
 51	((event << MMCR1_PMC6_SHIFT) & MMCR1_PMC6SEL)
 52
 53#define MMCR0_INIT (MMCR0_FC | MMCR0_FCS | MMCR0_FCP | MMCR0_FCM1 | MMCR0_FCM0)
 54
 55/* Unfreezes the counters on this CPU, enables the interrupt,
 56 * enables the counters to trigger the interrupt, and sets the
 57 * counters to only count when the mark bit is not set.
 58 */
 59static void pmc_start_ctrs(void)
 60{
 61	u32 mmcr0 = mfspr(SPRN_MMCR0);
 62
 63	mmcr0 &= ~(MMCR0_FC | MMCR0_FCM0);
 64	mmcr0 |= (MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);
 65
 66	mtspr(SPRN_MMCR0, mmcr0);
 67}
 68
 69/* Disables the counters on this CPU, and freezes them */
 70static void pmc_stop_ctrs(void)
 71{
 72	u32 mmcr0 = mfspr(SPRN_MMCR0);
 73
 74	mmcr0 |= MMCR0_FC;
 75	mmcr0 &= ~(MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);
 76
 77	mtspr(SPRN_MMCR0, mmcr0);
 78}
 79
 80/* Configures the counters on this CPU based on the global
 81 * settings */
 82static int fsl7450_cpu_setup(struct op_counter_config *ctr)
 83{
 84	/* freeze all counters */
 85	pmc_stop_ctrs();
 86
 87	mtspr(SPRN_MMCR0, mmcr0_val);
 88	mtspr(SPRN_MMCR1, mmcr1_val);
 89	if (num_pmcs > 4)
 90		mtspr(SPRN_MMCR2, mmcr2_val);
 91
 92	return 0;
 93}
 94
 95/* Configures the global settings for the countes on all CPUs. */
 96static int fsl7450_reg_setup(struct op_counter_config *ctr,
 97			     struct op_system_config *sys,
 98			     int num_ctrs)
 99{
100	int i;
101
102	num_pmcs = num_ctrs;
103	/* Our counters count up, and "count" refers to
104	 * how much before the next interrupt, and we interrupt
105	 * on overflow.  So we calculate the starting value
106	 * which will give us "count" until overflow.
107	 * Then we set the events on the enabled counters */
108	for (i = 0; i < num_ctrs; ++i)
109		reset_value[i] = 0x80000000UL - ctr[i].count;
110
111	/* Set events for Counters 1 & 2 */
112	mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event)
113		| mmcr0_event2(ctr[1].event);
114
115	/* Setup user/kernel bits */
116	if (sys->enable_kernel)
117		mmcr0_val &= ~(MMCR0_FCS);
118
119	if (sys->enable_user)
120		mmcr0_val &= ~(MMCR0_FCP);
121
122	/* Set events for Counters 3-6 */
123	mmcr1_val = mmcr1_event3(ctr[2].event)
124		| mmcr1_event4(ctr[3].event);
125	if (num_ctrs > 4)
126		mmcr1_val |= mmcr1_event5(ctr[4].event)
127			| mmcr1_event6(ctr[5].event);
128
129	mmcr2_val = 0;
130
131	return 0;
132}
133
134/* Sets the counters on this CPU to the chosen values, and starts them */
135static int fsl7450_start(struct op_counter_config *ctr)
136{
137	int i;
138
139	mtmsr(mfmsr() | MSR_PMM);
140
141	for (i = 0; i < num_pmcs; ++i) {
142		if (ctr[i].enabled)
143			classic_ctr_write(i, reset_value[i]);
144		else
145			classic_ctr_write(i, 0);
146	}
147
148	/* Clear the freeze bit, and enable the interrupt.
149	 * The counters won't actually start until the rfi clears
150	 * the PMM bit */
151	pmc_start_ctrs();
152
153	oprofile_running = 1;
154
155	return 0;
156}
157
158/* Stop the counters on this CPU */
159static void fsl7450_stop(void)
160{
161	/* freeze counters */
162	pmc_stop_ctrs();
163
164	oprofile_running = 0;
165
166	mb();
167}
168
169
170/* Handle the interrupt on this CPU, and log a sample for each
171 * event that triggered the interrupt */
172static void fsl7450_handle_interrupt(struct pt_regs *regs,
173				    struct op_counter_config *ctr)
174{
175	unsigned long pc;
176	int is_kernel;
177	int val;
178	int i;
179
180	/* set the PMM bit (see comment below) */
181	mtmsr(mfmsr() | MSR_PMM);
182
183	pc = mfspr(SPRN_SIAR);
184	is_kernel = is_kernel_addr(pc);
185
186	for (i = 0; i < num_pmcs; ++i) {
187		val = classic_ctr_read(i);
188		if (val < 0) {
189			if (oprofile_running && ctr[i].enabled) {
190				oprofile_add_ext_sample(pc, regs, i, is_kernel);
191				classic_ctr_write(i, reset_value[i]);
192			} else {
193				classic_ctr_write(i, 0);
194			}
195		}
196	}
197
198	/* The freeze bit was set by the interrupt. */
199	/* Clear the freeze bit, and reenable the interrupt.
200	 * The counters won't actually start until the rfi clears
201	 * the PM/M bit */
202	pmc_start_ctrs();
203}
204
205struct op_powerpc_model op_model_7450= {
206	.reg_setup		= fsl7450_reg_setup,
207	.cpu_setup		= fsl7450_cpu_setup,
208	.start			= fsl7450_start,
209	.stop			= fsl7450_stop,
210	.handle_interrupt	= fsl7450_handle_interrupt,
211};