1/*
  2 * GEFanuc C2K platform code.
  3 *
  4 * Author: Remi Machet <rmachet@slac.stanford.edu>
  5 *
  6 * Originated from prpmc2800.c
  7 *
  8 * 2008 (c) Stanford University
  9 * 2007 (c) MontaVista, Software, Inc.
 10 *
 11 * This program is free software; you can redistribute it and/or modify it
 12 * under the terms of the GNU General Public License version 2 as published
 13 * by the Free Software Foundation.
 14 */
 15
 16#include "types.h"
 17#include "stdio.h"
 18#include "io.h"
 19#include "ops.h"
 20#include "elf.h"
 21#include "mv64x60.h"
 22#include "cuboot.h"
 23#include "ppcboot.h"
 24
 25static u8 *bridge_base;
 26
 27static void c2k_bridge_setup(u32 mem_size)
 28{
 29	u32 i, v[30], enables, acc_bits;
 30	u32 pci_base_hi, pci_base_lo, size, buf[2];
 31	unsigned long cpu_base;
 32	int rc;
 33	void *devp, *mv64x60_devp;
 34	u8 *bridge_pbase, is_coherent;
 35	struct mv64x60_cpu2pci_win *tbl;
 36	int bus;
 37
 38	bridge_pbase = mv64x60_get_bridge_pbase();
 39	is_coherent = mv64x60_is_coherent();
 40
 41	if (is_coherent)
 42		acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
 43			| MV64x60_PCI_ACC_CNTL_SWAP_NONE
 44			| MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
 45			| MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 46	else
 47		acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
 48			| MV64x60_PCI_ACC_CNTL_SWAP_NONE
 49			| MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
 50			| MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 51
 52	mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
 53	mv64x60_devp = find_node_by_compatible(NULL, "marvell,mv64360");
 54	if (mv64x60_devp == NULL)
 55		fatal("Error: Missing marvell,mv64360 device tree node\n\r");
 56
 57	enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
 58	enables |= 0x007ffe00; /* Disable all cpu->pci windows */
 59	out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
 60
 61	/* Get the cpu -> pci i/o & mem mappings from the device tree */
 62	devp = NULL;
 63	for (bus = 0; ; bus++) {
 64		char name[] = "pci ";
 65
 66		name[strlen(name)-1] = bus+'0';
 67
 68		devp = find_node_by_alias(name);
 69		if (devp == NULL)
 70			break;
 71
 72		if (bus >= 2)
 73			fatal("Error: Only 2 PCI controllers are supported at" \
 74				" this time.\n");
 75
 76		mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0,
 77				mem_size, acc_bits);
 78
 79		rc = getprop(devp, "ranges", v, sizeof(v));
 80		if (rc == 0)
 81			fatal("Error: Can't find marvell,mv64360-pci ranges"
 82				" property\n\r");
 83
 84		/* Get the cpu -> pci i/o & mem mappings from the device tree */
 85
 86		for (i = 0; i < rc; i += 6) {
 87			switch (v[i] & 0xff000000) {
 88			case 0x01000000: /* PCI I/O Space */
 89				tbl = mv64x60_cpu2pci_io;
 90				break;
 91			case 0x02000000: /* PCI MEM Space */
 92				tbl = mv64x60_cpu2pci_mem;
 93				break;
 94			default:
 95				continue;
 96			}
 97
 98			pci_base_hi = v[i+1];
 99			pci_base_lo = v[i+2];
100			cpu_base = v[i+3];
101			size = v[i+5];
102
103			buf[0] = cpu_base;
104			buf[1] = size;
105
106			if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
107				fatal("Error: Can't translate PCI address " \
108						"0x%x\n\r", (u32)cpu_base);
109
110			mv64x60_config_cpu2pci_window(bridge_base, bus,
111				pci_base_hi, pci_base_lo, cpu_base, size, tbl);
112		}
113
114		enables &= ~(3<<(9+bus*5)); /* Enable cpu->pci<bus> i/o,
115						cpu->pci<bus> mem0 */
116		out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE),
117			enables);
118	};
119}
120
121static void c2k_fixups(void)
122{
123	u32 mem_size;
124
125	mem_size = mv64x60_get_mem_size(bridge_base);
126	c2k_bridge_setup(mem_size); /* Do necessary bridge setup */
127}
128
129#define MV64x60_MPP_CNTL_0	0xf000
130#define MV64x60_MPP_CNTL_2	0xf008
131#define MV64x60_GPP_IO_CNTL	0xf100
132#define MV64x60_GPP_LEVEL_CNTL	0xf110
133#define MV64x60_GPP_VALUE_SET	0xf118
134
135static void c2k_reset(void)
136{
137	u32 temp;
138
139	udelay(5000000);
140
141	if (bridge_base != 0) {
142		temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
143		temp &= 0xFFFF0FFF;
144		out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
145
146		temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
147		temp |= 0x00000004;
148		out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
149
150		temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
151		temp |= 0x00000004;
152		out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
153
154		temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
155		temp &= 0xFFFF0FFF;
156		out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
157
158		temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
159		temp |= 0x00080000;
160		out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
161
162		temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
163		temp |= 0x00080000;
164		out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
165
166		out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
167				0x00080004);
168	}
169
170	for (;;);
171}
172
173static bd_t bd;
174
175void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
176			unsigned long r6, unsigned long r7)
177{
178	CUBOOT_INIT();
179
180	fdt_init(_dtb_start);
181
182	bridge_base = mv64x60_get_bridge_base();
183
184	platform_ops.fixups = c2k_fixups;
185	platform_ops.exit = c2k_reset;
186
187	if (serial_console_init() < 0)
188		exit();
189}