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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ip22-mc.c: Routines for manipulating SGI Memory Controller.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
7 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
8 * Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28
9 */
10
11#include <linux/init.h>
12#include <linux/export.h>
13#include <linux/kernel.h>
14#include <linux/memblock.h>
15#include <linux/spinlock.h>
16
17#include <asm/io.h>
18#include <asm/bootinfo.h>
19#include <asm/sgialib.h>
20#include <asm/sgi/mc.h>
21#include <asm/sgi/hpc3.h>
22#include <asm/sgi/ip22.h>
23
24struct sgimc_regs *sgimc;
25
26EXPORT_SYMBOL(sgimc);
27
28static inline unsigned long get_bank_addr(unsigned int memconfig)
29{
30 return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22);
31}
32
33static inline unsigned long get_bank_size(unsigned int memconfig)
34{
35 return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
36}
37
38static inline unsigned int get_bank_config(int bank)
39{
40 unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
41 return bank % 2 ? res & 0xffff : res >> 16;
42}
43
44#if defined(CONFIG_SGI_IP28) || defined(CONFIG_32BIT)
45static void __init probe_memory(void)
46{
47 /* prom detects all usable memory */
48}
49#else
50/*
51 * Detect installed memory, which PROM misses
52 */
53static void __init probe_memory(void)
54{
55 unsigned long addr, size;
56 int i;
57
58 printk(KERN_INFO "MC: Probing memory configuration:\n");
59 for (i = 0; i < 4; i++) {
60 unsigned int tmp = get_bank_config(i);
61 if (!(tmp & SGIMC_MCONFIG_BVALID))
62 continue;
63
64 size = get_bank_size(tmp);
65 addr = get_bank_addr(tmp);
66 printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
67 i, size / 1024 / 1024, addr);
68
69 if (addr >= SGIMC_SEG1_BADDR)
70 memblock_add(addr, size);
71 }
72}
73#endif
74
75void __init sgimc_init(void)
76{
77 u32 tmp;
78
79 /* ioremap can't fail */
80 sgimc = (struct sgimc_regs *)
81 ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
82
83 printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
84 (int) sgimc->systemid & SGIMC_SYSID_MASKREV);
85
86 /* Place the MC into a known state. This must be done before
87 * interrupts are first enabled etc.
88 */
89
90 /* Step 0: Make sure we turn off the watchdog in case it's
91 * still running (which might be the case after a
92 * soft reboot).
93 */
94 tmp = sgimc->cpuctrl0;
95 tmp &= ~SGIMC_CCTRL0_WDOG;
96 sgimc->cpuctrl0 = tmp;
97
98 /* Step 1: The CPU/GIO error status registers will not latch
99 * up a new error status until the register has been
100 * cleared by the cpu. These status registers are
101 * cleared by writing any value to them.
102 */
103 sgimc->cstat = sgimc->gstat = 0;
104
105 /* Step 2: Enable all parity checking in cpu control register
106 * zero.
107 */
108 /* don't touch parity settings for IP28 */
109 tmp = sgimc->cpuctrl0;
110#ifndef CONFIG_SGI_IP28
111 tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
112#endif
113 tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
114 sgimc->cpuctrl0 = tmp;
115
116 /* Step 3: Setup the MC write buffer depth, this is controlled
117 * in cpu control register 1 in the lower 4 bits.
118 */
119 tmp = sgimc->cpuctrl1;
120 tmp &= ~0xf;
121 tmp |= 0xd;
122 sgimc->cpuctrl1 = tmp;
123
124 /* Step 4: Initialize the RPSS divider register to run as fast
125 * as it can correctly operate. The register is laid
126 * out as follows:
127 *
128 * ----------------------------------------
129 * | RESERVED | INCREMENT | DIVIDER |
130 * ----------------------------------------
131 * 31 16 15 8 7 0
132 *
133 * DIVIDER determines how often a 'tick' happens,
134 * INCREMENT determines by how the RPSS increment
135 * registers value increases at each 'tick'. Thus,
136 * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
137 */
138 sgimc->divider = 0x101;
139
140 /* Step 5: Initialize GIO64 arbitrator configuration register.
141 *
142 * NOTE: HPC init code in sgihpc_init() must run before us because
143 * we need to know Guiness vs. FullHouse and the board
144 * revision on this machine. You have been warned.
145 */
146
147 /* First the basic invariants across all GIO64 implementations. */
148 tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
149 tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
150 tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
151
152 if (ip22_is_fullhouse()) {
153 /* Fullhouse specific settings. */
154 if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
155 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
156 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */
157 tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
158 tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */
159 } else {
160 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
161 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
162 tmp |= SGIMC_GIOPAR_PLINEEXP1;
163 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
164 }
165 } else {
166 /* Guiness specific settings. */
167 tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
168 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
169 }
170 sgimc->giopar = tmp; /* poof */
171
172 probe_memory();
173}
174
175#ifdef CONFIG_SGI_IP28
176void __init prom_cleanup(void)
177{
178 u32 mconfig1;
179 unsigned long flags;
180 spinlock_t lock;
181
182 /*
183 * because ARCS accesses memory uncached we wait until ARCS
184 * isn't needed any longer, before we switch from slow to
185 * normal mode
186 */
187 spin_lock_irqsave(&lock, flags);
188 mconfig1 = sgimc->mconfig1;
189 /* map ECC register */
190 sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;
191 iob();
192 /* switch to normal mode */
193 *(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
194 iob();
195 /* reduce WR_COL */
196 sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;
197 iob();
198 /* restore old config */
199 sgimc->mconfig1 = mconfig1;
200 iob();
201 spin_unlock_irqrestore(&lock, flags);
202}
203#endif
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ip22-mc.c: Routines for manipulating SGI Memory Controller.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
7 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
8 * Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28
9 */
10
11#include <linux/init.h>
12#include <linux/export.h>
13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15
16#include <asm/io.h>
17#include <asm/bootinfo.h>
18#include <asm/sgialib.h>
19#include <asm/sgi/mc.h>
20#include <asm/sgi/hpc3.h>
21#include <asm/sgi/ip22.h>
22
23struct sgimc_regs *sgimc;
24
25EXPORT_SYMBOL(sgimc);
26
27static inline unsigned long get_bank_addr(unsigned int memconfig)
28{
29 return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22);
30}
31
32static inline unsigned long get_bank_size(unsigned int memconfig)
33{
34 return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
35}
36
37static inline unsigned int get_bank_config(int bank)
38{
39 unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
40 return bank % 2 ? res & 0xffff : res >> 16;
41}
42
43struct mem {
44 unsigned long addr;
45 unsigned long size;
46};
47
48/*
49 * Detect installed memory, do some sanity checks and notify kernel about it
50 */
51static void __init probe_memory(void)
52{
53 int i, j, found, cnt = 0;
54 struct mem bank[4];
55 struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}};
56
57 printk(KERN_INFO "MC: Probing memory configuration:\n");
58 for (i = 0; i < ARRAY_SIZE(bank); i++) {
59 unsigned int tmp = get_bank_config(i);
60 if (!(tmp & SGIMC_MCONFIG_BVALID))
61 continue;
62
63 bank[cnt].size = get_bank_size(tmp);
64 bank[cnt].addr = get_bank_addr(tmp);
65 printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
66 i, bank[cnt].size / 1024 / 1024, bank[cnt].addr);
67 cnt++;
68 }
69
70 /* And you thought bubble sort is dead algorithm... */
71 do {
72 unsigned long addr, size;
73
74 found = 0;
75 for (i = 1; i < cnt; i++)
76 if (bank[i-1].addr > bank[i].addr) {
77 addr = bank[i].addr;
78 size = bank[i].size;
79 bank[i].addr = bank[i-1].addr;
80 bank[i].size = bank[i-1].size;
81 bank[i-1].addr = addr;
82 bank[i-1].size = size;
83 found = 1;
84 }
85 } while (found);
86
87 /* Figure out how are memory banks mapped into spaces */
88 for (i = 0; i < cnt; i++) {
89 found = 0;
90 for (j = 0; j < ARRAY_SIZE(space) && !found; j++)
91 if (space[j].addr + space[j].size == bank[i].addr) {
92 space[j].size += bank[i].size;
93 found = 1;
94 }
95 /* There is either hole or overlapping memory */
96 if (!found)
97 printk(KERN_CRIT "MC: Memory configuration mismatch "
98 "(%08lx), expect Bus Error soon\n",
99 bank[i].addr);
100 }
101
102 for (i = 0; i < ARRAY_SIZE(space); i++)
103 if (space[i].size)
104 add_memory_region(space[i].addr, space[i].size,
105 BOOT_MEM_RAM);
106}
107
108void __init sgimc_init(void)
109{
110 u32 tmp;
111
112 /* ioremap can't fail */
113 sgimc = (struct sgimc_regs *)
114 ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
115
116 printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
117 (int) sgimc->systemid & SGIMC_SYSID_MASKREV);
118
119 /* Place the MC into a known state. This must be done before
120 * interrupts are first enabled etc.
121 */
122
123 /* Step 0: Make sure we turn off the watchdog in case it's
124 * still running (which might be the case after a
125 * soft reboot).
126 */
127 tmp = sgimc->cpuctrl0;
128 tmp &= ~SGIMC_CCTRL0_WDOG;
129 sgimc->cpuctrl0 = tmp;
130
131 /* Step 1: The CPU/GIO error status registers will not latch
132 * up a new error status until the register has been
133 * cleared by the cpu. These status registers are
134 * cleared by writing any value to them.
135 */
136 sgimc->cstat = sgimc->gstat = 0;
137
138 /* Step 2: Enable all parity checking in cpu control register
139 * zero.
140 */
141 /* don't touch parity settings for IP28 */
142 tmp = sgimc->cpuctrl0;
143#ifndef CONFIG_SGI_IP28
144 tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
145#endif
146 tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
147 sgimc->cpuctrl0 = tmp;
148
149 /* Step 3: Setup the MC write buffer depth, this is controlled
150 * in cpu control register 1 in the lower 4 bits.
151 */
152 tmp = sgimc->cpuctrl1;
153 tmp &= ~0xf;
154 tmp |= 0xd;
155 sgimc->cpuctrl1 = tmp;
156
157 /* Step 4: Initialize the RPSS divider register to run as fast
158 * as it can correctly operate. The register is laid
159 * out as follows:
160 *
161 * ----------------------------------------
162 * | RESERVED | INCREMENT | DIVIDER |
163 * ----------------------------------------
164 * 31 16 15 8 7 0
165 *
166 * DIVIDER determines how often a 'tick' happens,
167 * INCREMENT determines by how the RPSS increment
168 * registers value increases at each 'tick'. Thus,
169 * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
170 */
171 sgimc->divider = 0x101;
172
173 /* Step 5: Initialize GIO64 arbitrator configuration register.
174 *
175 * NOTE: HPC init code in sgihpc_init() must run before us because
176 * we need to know Guiness vs. FullHouse and the board
177 * revision on this machine. You have been warned.
178 */
179
180 /* First the basic invariants across all GIO64 implementations. */
181 tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
182 tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
183 tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
184
185 if (ip22_is_fullhouse()) {
186 /* Fullhouse specific settings. */
187 if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
188 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
189 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */
190 tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
191 tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */
192 } else {
193 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
194 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
195 tmp |= SGIMC_GIOPAR_PLINEEXP1;
196 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
197 }
198 } else {
199 /* Guiness specific settings. */
200 tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
201 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
202 }
203 sgimc->giopar = tmp; /* poof */
204
205 probe_memory();
206}
207
208void __init prom_meminit(void) {}
209void __init prom_free_prom_memory(void)
210{
211#ifdef CONFIG_SGI_IP28
212 u32 mconfig1;
213 unsigned long flags;
214 spinlock_t lock;
215
216 /*
217 * because ARCS accesses memory uncached we wait until ARCS
218 * isn't needed any longer, before we switch from slow to
219 * normal mode
220 */
221 spin_lock_irqsave(&lock, flags);
222 mconfig1 = sgimc->mconfig1;
223 /* map ECC register */
224 sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;
225 iob();
226 /* switch to normal mode */
227 *(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
228 iob();
229 /* reduce WR_COL */
230 sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;
231 iob();
232 /* restore old config */
233 sgimc->mconfig1 = mconfig1;
234 iob();
235 spin_unlock_irqrestore(&lock, flags);
236#endif
237}