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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2010 John Crispin <john@phrozen.org>
5 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
6 */
7
8#include <linux/interrupt.h>
9#include <linux/ioport.h>
10#include <linux/sched.h>
11#include <linux/irqchip.h>
12#include <linux/irqdomain.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16
17#include <asm/bootinfo.h>
18#include <asm/irq_cpu.h>
19
20#include <lantiq_soc.h>
21#include <irq.h>
22
23/* register definitions - internal irqs */
24#define LTQ_ICU_ISR 0x0000
25#define LTQ_ICU_IER 0x0008
26#define LTQ_ICU_IOSR 0x0010
27#define LTQ_ICU_IRSR 0x0018
28#define LTQ_ICU_IMR 0x0020
29
30#define LTQ_ICU_IM_SIZE 0x28
31
32/* register definitions - external irqs */
33#define LTQ_EIU_EXIN_C 0x0000
34#define LTQ_EIU_EXIN_INIC 0x0004
35#define LTQ_EIU_EXIN_INC 0x0008
36#define LTQ_EIU_EXIN_INEN 0x000C
37
38/* number of external interrupts */
39#define MAX_EIU 6
40
41/* the performance counter */
42#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
43
44/*
45 * irqs generated by devices attached to the EBU need to be acked in
46 * a special manner
47 */
48#define LTQ_ICU_EBU_IRQ 22
49
50#define ltq_icu_w32(vpe, m, x, y) \
51 ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
52
53#define ltq_icu_r32(vpe, m, x) \
54 ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
55
56#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
57#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
58
59/* we have a cascade of 8 irqs */
60#define MIPS_CPU_IRQ_CASCADE 8
61
62static int exin_avail;
63static u32 ltq_eiu_irq[MAX_EIU];
64static void __iomem *ltq_icu_membase[NR_CPUS];
65static void __iomem *ltq_eiu_membase;
66static struct irq_domain *ltq_domain;
67static DEFINE_SPINLOCK(ltq_eiu_lock);
68static DEFINE_RAW_SPINLOCK(ltq_icu_lock);
69static int ltq_perfcount_irq;
70
71int ltq_eiu_get_irq(int exin)
72{
73 if (exin < exin_avail)
74 return ltq_eiu_irq[exin];
75 return -1;
76}
77
78void ltq_disable_irq(struct irq_data *d)
79{
80 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
81 unsigned long im = offset / INT_NUM_IM_OFFSET;
82 unsigned long flags;
83 int vpe;
84
85 offset %= INT_NUM_IM_OFFSET;
86
87 raw_spin_lock_irqsave(<q_icu_lock, flags);
88 for_each_present_cpu(vpe) {
89 ltq_icu_w32(vpe, im,
90 ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
91 LTQ_ICU_IER);
92 }
93 raw_spin_unlock_irqrestore(<q_icu_lock, flags);
94}
95
96void ltq_mask_and_ack_irq(struct irq_data *d)
97{
98 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
99 unsigned long im = offset / INT_NUM_IM_OFFSET;
100 unsigned long flags;
101 int vpe;
102
103 offset %= INT_NUM_IM_OFFSET;
104
105 raw_spin_lock_irqsave(<q_icu_lock, flags);
106 for_each_present_cpu(vpe) {
107 ltq_icu_w32(vpe, im,
108 ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
109 LTQ_ICU_IER);
110 ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
111 }
112 raw_spin_unlock_irqrestore(<q_icu_lock, flags);
113}
114
115static void ltq_ack_irq(struct irq_data *d)
116{
117 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
118 unsigned long im = offset / INT_NUM_IM_OFFSET;
119 unsigned long flags;
120 int vpe;
121
122 offset %= INT_NUM_IM_OFFSET;
123
124 raw_spin_lock_irqsave(<q_icu_lock, flags);
125 for_each_present_cpu(vpe) {
126 ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
127 }
128 raw_spin_unlock_irqrestore(<q_icu_lock, flags);
129}
130
131void ltq_enable_irq(struct irq_data *d)
132{
133 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
134 unsigned long im = offset / INT_NUM_IM_OFFSET;
135 unsigned long flags;
136 int vpe;
137
138 offset %= INT_NUM_IM_OFFSET;
139
140 vpe = cpumask_first(irq_data_get_effective_affinity_mask(d));
141
142 /* This shouldn't be even possible, maybe during CPU hotplug spam */
143 if (unlikely(vpe >= nr_cpu_ids))
144 vpe = smp_processor_id();
145
146 raw_spin_lock_irqsave(<q_icu_lock, flags);
147
148 ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset),
149 LTQ_ICU_IER);
150
151 raw_spin_unlock_irqrestore(<q_icu_lock, flags);
152}
153
154static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
155{
156 int i;
157 unsigned long flags;
158
159 for (i = 0; i < exin_avail; i++) {
160 if (d->hwirq == ltq_eiu_irq[i]) {
161 int val = 0;
162 int edge = 0;
163
164 switch (type) {
165 case IRQF_TRIGGER_NONE:
166 break;
167 case IRQF_TRIGGER_RISING:
168 val = 1;
169 edge = 1;
170 break;
171 case IRQF_TRIGGER_FALLING:
172 val = 2;
173 edge = 1;
174 break;
175 case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
176 val = 3;
177 edge = 1;
178 break;
179 case IRQF_TRIGGER_HIGH:
180 val = 5;
181 break;
182 case IRQF_TRIGGER_LOW:
183 val = 6;
184 break;
185 default:
186 pr_err("invalid type %d for irq %ld\n",
187 type, d->hwirq);
188 return -EINVAL;
189 }
190
191 if (edge)
192 irq_set_handler(d->hwirq, handle_edge_irq);
193
194 spin_lock_irqsave(<q_eiu_lock, flags);
195 ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
196 (~(7 << (i * 4)))) | (val << (i * 4)),
197 LTQ_EIU_EXIN_C);
198 spin_unlock_irqrestore(<q_eiu_lock, flags);
199 }
200 }
201
202 return 0;
203}
204
205static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
206{
207 int i;
208
209 ltq_enable_irq(d);
210 for (i = 0; i < exin_avail; i++) {
211 if (d->hwirq == ltq_eiu_irq[i]) {
212 /* by default we are low level triggered */
213 ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
214 /* clear all pending */
215 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
216 LTQ_EIU_EXIN_INC);
217 /* enable */
218 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
219 LTQ_EIU_EXIN_INEN);
220 break;
221 }
222 }
223
224 return 0;
225}
226
227static void ltq_shutdown_eiu_irq(struct irq_data *d)
228{
229 int i;
230
231 ltq_disable_irq(d);
232 for (i = 0; i < exin_avail; i++) {
233 if (d->hwirq == ltq_eiu_irq[i]) {
234 /* disable */
235 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
236 LTQ_EIU_EXIN_INEN);
237 break;
238 }
239 }
240}
241
242#if defined(CONFIG_SMP)
243static int ltq_icu_irq_set_affinity(struct irq_data *d,
244 const struct cpumask *cpumask, bool force)
245{
246 struct cpumask tmask;
247
248 if (!cpumask_and(&tmask, cpumask, cpu_online_mask))
249 return -EINVAL;
250
251 irq_data_update_effective_affinity(d, &tmask);
252
253 return IRQ_SET_MASK_OK;
254}
255#endif
256
257static struct irq_chip ltq_irq_type = {
258 .name = "icu",
259 .irq_enable = ltq_enable_irq,
260 .irq_disable = ltq_disable_irq,
261 .irq_unmask = ltq_enable_irq,
262 .irq_ack = ltq_ack_irq,
263 .irq_mask = ltq_disable_irq,
264 .irq_mask_ack = ltq_mask_and_ack_irq,
265#if defined(CONFIG_SMP)
266 .irq_set_affinity = ltq_icu_irq_set_affinity,
267#endif
268};
269
270static struct irq_chip ltq_eiu_type = {
271 .name = "eiu",
272 .irq_startup = ltq_startup_eiu_irq,
273 .irq_shutdown = ltq_shutdown_eiu_irq,
274 .irq_enable = ltq_enable_irq,
275 .irq_disable = ltq_disable_irq,
276 .irq_unmask = ltq_enable_irq,
277 .irq_ack = ltq_ack_irq,
278 .irq_mask = ltq_disable_irq,
279 .irq_mask_ack = ltq_mask_and_ack_irq,
280 .irq_set_type = ltq_eiu_settype,
281#if defined(CONFIG_SMP)
282 .irq_set_affinity = ltq_icu_irq_set_affinity,
283#endif
284};
285
286static void ltq_hw_irq_handler(struct irq_desc *desc)
287{
288 unsigned int module = irq_desc_get_irq(desc) - 2;
289 u32 irq;
290 irq_hw_number_t hwirq;
291 int vpe = smp_processor_id();
292
293 irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR);
294 if (irq == 0)
295 return;
296
297 /*
298 * silicon bug causes only the msb set to 1 to be valid. all
299 * other bits might be bogus
300 */
301 irq = __fls(irq);
302 hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
303 generic_handle_domain_irq(ltq_domain, hwirq);
304
305 /* if this is a EBU irq, we need to ack it or get a deadlock */
306 if (irq == LTQ_ICU_EBU_IRQ && !module && LTQ_EBU_PCC_ISTAT != 0)
307 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
308 LTQ_EBU_PCC_ISTAT);
309}
310
311static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
312{
313 struct irq_chip *chip = <q_irq_type;
314 struct irq_data *data;
315 int i;
316
317 if (hw < MIPS_CPU_IRQ_CASCADE)
318 return 0;
319
320 for (i = 0; i < exin_avail; i++)
321 if (hw == ltq_eiu_irq[i])
322 chip = <q_eiu_type;
323
324 data = irq_get_irq_data(irq);
325
326 irq_data_update_effective_affinity(data, cpumask_of(0));
327
328 irq_set_chip_and_handler(irq, chip, handle_level_irq);
329
330 return 0;
331}
332
333static const struct irq_domain_ops irq_domain_ops = {
334 .xlate = irq_domain_xlate_onetwocell,
335 .map = icu_map,
336};
337
338int __init icu_of_init(struct device_node *node, struct device_node *parent)
339{
340 struct device_node *eiu_node;
341 struct resource res;
342 int i, ret, vpe;
343
344 /* load register regions of available ICUs */
345 for_each_possible_cpu(vpe) {
346 if (of_address_to_resource(node, vpe, &res))
347 panic("Failed to get icu%i memory range", vpe);
348
349 if (!request_mem_region(res.start, resource_size(&res),
350 res.name))
351 pr_err("Failed to request icu%i memory\n", vpe);
352
353 ltq_icu_membase[vpe] = ioremap(res.start,
354 resource_size(&res));
355
356 if (!ltq_icu_membase[vpe])
357 panic("Failed to remap icu%i memory", vpe);
358 }
359
360 /* turn off all irqs by default */
361 for_each_possible_cpu(vpe) {
362 for (i = 0; i < MAX_IM; i++) {
363 /* make sure all irqs are turned off by default */
364 ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER);
365
366 /* clear all possibly pending interrupts */
367 ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR);
368 ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR);
369
370 /* clear resend */
371 ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR);
372 }
373 }
374
375 mips_cpu_irq_init();
376
377 for (i = 0; i < MAX_IM; i++)
378 irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
379
380 ltq_domain = irq_domain_add_linear(node,
381 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
382 &irq_domain_ops, 0);
383
384 /* tell oprofile which irq to use */
385 ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
386
387 /* the external interrupts are optional and xway only */
388 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
389 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
390 /* find out how many external irq sources we have */
391 exin_avail = of_property_count_u32_elems(eiu_node,
392 "lantiq,eiu-irqs");
393
394 if (exin_avail > MAX_EIU)
395 exin_avail = MAX_EIU;
396
397 ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
398 ltq_eiu_irq, exin_avail);
399 if (ret)
400 panic("failed to load external irq resources");
401
402 if (!request_mem_region(res.start, resource_size(&res),
403 res.name))
404 pr_err("Failed to request eiu memory");
405
406 ltq_eiu_membase = ioremap(res.start,
407 resource_size(&res));
408 if (!ltq_eiu_membase)
409 panic("Failed to remap eiu memory");
410 }
411 of_node_put(eiu_node);
412
413 return 0;
414}
415
416int get_c0_perfcount_int(void)
417{
418 return ltq_perfcount_irq;
419}
420EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
421
422unsigned int get_c0_compare_int(void)
423{
424 return CP0_LEGACY_COMPARE_IRQ;
425}
426
427IRQCHIP_DECLARE(lantiq_icu, "lantiq,icu", icu_of_init);
428
429void __init arch_init_irq(void)
430{
431 irqchip_init();
432}
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
8 */
9
10#include <linux/interrupt.h>
11#include <linux/ioport.h>
12#include <linux/sched.h>
13#include <linux/irqdomain.h>
14#include <linux/of_platform.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17
18#include <asm/bootinfo.h>
19#include <asm/irq_cpu.h>
20
21#include <lantiq_soc.h>
22#include <irq.h>
23
24/* register definitions - internal irqs */
25#define LTQ_ICU_IM0_ISR 0x0000
26#define LTQ_ICU_IM0_IER 0x0008
27#define LTQ_ICU_IM0_IOSR 0x0010
28#define LTQ_ICU_IM0_IRSR 0x0018
29#define LTQ_ICU_IM0_IMR 0x0020
30#define LTQ_ICU_IM1_ISR 0x0028
31#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
32
33/* register definitions - external irqs */
34#define LTQ_EIU_EXIN_C 0x0000
35#define LTQ_EIU_EXIN_INIC 0x0004
36#define LTQ_EIU_EXIN_INC 0x0008
37#define LTQ_EIU_EXIN_INEN 0x000C
38
39/* number of external interrupts */
40#define MAX_EIU 6
41
42/* the performance counter */
43#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
44
45/*
46 * irqs generated by devices attached to the EBU need to be acked in
47 * a special manner
48 */
49#define LTQ_ICU_EBU_IRQ 22
50
51#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
52#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
53
54#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
55#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
56
57/* our 2 ipi interrupts for VSMP */
58#define MIPS_CPU_IPI_RESCHED_IRQ 0
59#define MIPS_CPU_IPI_CALL_IRQ 1
60
61/* we have a cascade of 8 irqs */
62#define MIPS_CPU_IRQ_CASCADE 8
63
64static int exin_avail;
65static u32 ltq_eiu_irq[MAX_EIU];
66static void __iomem *ltq_icu_membase[MAX_IM];
67static void __iomem *ltq_eiu_membase;
68static struct irq_domain *ltq_domain;
69static int ltq_perfcount_irq;
70
71int ltq_eiu_get_irq(int exin)
72{
73 if (exin < exin_avail)
74 return ltq_eiu_irq[exin];
75 return -1;
76}
77
78void ltq_disable_irq(struct irq_data *d)
79{
80 u32 ier = LTQ_ICU_IM0_IER;
81 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
82 int im = offset / INT_NUM_IM_OFFSET;
83
84 offset %= INT_NUM_IM_OFFSET;
85 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
86}
87
88void ltq_mask_and_ack_irq(struct irq_data *d)
89{
90 u32 ier = LTQ_ICU_IM0_IER;
91 u32 isr = LTQ_ICU_IM0_ISR;
92 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
93 int im = offset / INT_NUM_IM_OFFSET;
94
95 offset %= INT_NUM_IM_OFFSET;
96 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
97 ltq_icu_w32(im, BIT(offset), isr);
98}
99
100static void ltq_ack_irq(struct irq_data *d)
101{
102 u32 isr = LTQ_ICU_IM0_ISR;
103 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
104 int im = offset / INT_NUM_IM_OFFSET;
105
106 offset %= INT_NUM_IM_OFFSET;
107 ltq_icu_w32(im, BIT(offset), isr);
108}
109
110void ltq_enable_irq(struct irq_data *d)
111{
112 u32 ier = LTQ_ICU_IM0_IER;
113 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
114 int im = offset / INT_NUM_IM_OFFSET;
115
116 offset %= INT_NUM_IM_OFFSET;
117 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
118}
119
120static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
121{
122 int i;
123
124 for (i = 0; i < exin_avail; i++) {
125 if (d->hwirq == ltq_eiu_irq[i]) {
126 int val = 0;
127 int edge = 0;
128
129 switch (type) {
130 case IRQF_TRIGGER_NONE:
131 break;
132 case IRQF_TRIGGER_RISING:
133 val = 1;
134 edge = 1;
135 break;
136 case IRQF_TRIGGER_FALLING:
137 val = 2;
138 edge = 1;
139 break;
140 case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
141 val = 3;
142 edge = 1;
143 break;
144 case IRQF_TRIGGER_HIGH:
145 val = 5;
146 break;
147 case IRQF_TRIGGER_LOW:
148 val = 6;
149 break;
150 default:
151 pr_err("invalid type %d for irq %ld\n",
152 type, d->hwirq);
153 return -EINVAL;
154 }
155
156 if (edge)
157 irq_set_handler(d->hwirq, handle_edge_irq);
158
159 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
160 (val << (i * 4)), LTQ_EIU_EXIN_C);
161 }
162 }
163
164 return 0;
165}
166
167static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
168{
169 int i;
170
171 ltq_enable_irq(d);
172 for (i = 0; i < exin_avail; i++) {
173 if (d->hwirq == ltq_eiu_irq[i]) {
174 /* by default we are low level triggered */
175 ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
176 /* clear all pending */
177 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
178 LTQ_EIU_EXIN_INC);
179 /* enable */
180 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
181 LTQ_EIU_EXIN_INEN);
182 break;
183 }
184 }
185
186 return 0;
187}
188
189static void ltq_shutdown_eiu_irq(struct irq_data *d)
190{
191 int i;
192
193 ltq_disable_irq(d);
194 for (i = 0; i < exin_avail; i++) {
195 if (d->hwirq == ltq_eiu_irq[i]) {
196 /* disable */
197 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
198 LTQ_EIU_EXIN_INEN);
199 break;
200 }
201 }
202}
203
204static struct irq_chip ltq_irq_type = {
205 .name = "icu",
206 .irq_enable = ltq_enable_irq,
207 .irq_disable = ltq_disable_irq,
208 .irq_unmask = ltq_enable_irq,
209 .irq_ack = ltq_ack_irq,
210 .irq_mask = ltq_disable_irq,
211 .irq_mask_ack = ltq_mask_and_ack_irq,
212};
213
214static struct irq_chip ltq_eiu_type = {
215 .name = "eiu",
216 .irq_startup = ltq_startup_eiu_irq,
217 .irq_shutdown = ltq_shutdown_eiu_irq,
218 .irq_enable = ltq_enable_irq,
219 .irq_disable = ltq_disable_irq,
220 .irq_unmask = ltq_enable_irq,
221 .irq_ack = ltq_ack_irq,
222 .irq_mask = ltq_disable_irq,
223 .irq_mask_ack = ltq_mask_and_ack_irq,
224 .irq_set_type = ltq_eiu_settype,
225};
226
227static void ltq_hw_irqdispatch(int module)
228{
229 u32 irq;
230
231 irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
232 if (irq == 0)
233 return;
234
235 /*
236 * silicon bug causes only the msb set to 1 to be valid. all
237 * other bits might be bogus
238 */
239 irq = __fls(irq);
240 do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
241
242 /* if this is a EBU irq, we need to ack it or get a deadlock */
243 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
244 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
245 LTQ_EBU_PCC_ISTAT);
246}
247
248#define DEFINE_HWx_IRQDISPATCH(x) \
249 static void ltq_hw ## x ## _irqdispatch(void) \
250 { \
251 ltq_hw_irqdispatch(x); \
252 }
253DEFINE_HWx_IRQDISPATCH(0)
254DEFINE_HWx_IRQDISPATCH(1)
255DEFINE_HWx_IRQDISPATCH(2)
256DEFINE_HWx_IRQDISPATCH(3)
257DEFINE_HWx_IRQDISPATCH(4)
258
259#if MIPS_CPU_TIMER_IRQ == 7
260static void ltq_hw5_irqdispatch(void)
261{
262 do_IRQ(MIPS_CPU_TIMER_IRQ);
263}
264#else
265DEFINE_HWx_IRQDISPATCH(5)
266#endif
267
268static void ltq_hw_irq_handler(struct irq_desc *desc)
269{
270 ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
271}
272
273asmlinkage void plat_irq_dispatch(void)
274{
275 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
276 int irq;
277
278 if (!pending) {
279 spurious_interrupt();
280 return;
281 }
282
283 pending >>= CAUSEB_IP;
284 while (pending) {
285 irq = fls(pending) - 1;
286 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
287 pending &= ~BIT(irq);
288 }
289}
290
291static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
292{
293 struct irq_chip *chip = <q_irq_type;
294 int i;
295
296 if (hw < MIPS_CPU_IRQ_CASCADE)
297 return 0;
298
299 for (i = 0; i < exin_avail; i++)
300 if (hw == ltq_eiu_irq[i])
301 chip = <q_eiu_type;
302
303 irq_set_chip_and_handler(irq, chip, handle_level_irq);
304
305 return 0;
306}
307
308static const struct irq_domain_ops irq_domain_ops = {
309 .xlate = irq_domain_xlate_onetwocell,
310 .map = icu_map,
311};
312
313int __init icu_of_init(struct device_node *node, struct device_node *parent)
314{
315 struct device_node *eiu_node;
316 struct resource res;
317 int i, ret;
318
319 for (i = 0; i < MAX_IM; i++) {
320 if (of_address_to_resource(node, i, &res))
321 panic("Failed to get icu memory range");
322
323 if (!request_mem_region(res.start, resource_size(&res),
324 res.name))
325 pr_err("Failed to request icu memory");
326
327 ltq_icu_membase[i] = ioremap_nocache(res.start,
328 resource_size(&res));
329 if (!ltq_icu_membase[i])
330 panic("Failed to remap icu memory");
331 }
332
333 /* turn off all irqs by default */
334 for (i = 0; i < MAX_IM; i++) {
335 /* make sure all irqs are turned off by default */
336 ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
337 /* clear all possibly pending interrupts */
338 ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
339 }
340
341 mips_cpu_irq_init();
342
343 for (i = 0; i < MAX_IM; i++)
344 irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
345
346 if (cpu_has_vint) {
347 pr_info("Setting up vectored interrupts\n");
348 set_vi_handler(2, ltq_hw0_irqdispatch);
349 set_vi_handler(3, ltq_hw1_irqdispatch);
350 set_vi_handler(4, ltq_hw2_irqdispatch);
351 set_vi_handler(5, ltq_hw3_irqdispatch);
352 set_vi_handler(6, ltq_hw4_irqdispatch);
353 set_vi_handler(7, ltq_hw5_irqdispatch);
354 }
355
356 ltq_domain = irq_domain_add_linear(node,
357 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
358 &irq_domain_ops, 0);
359
360#ifndef CONFIG_MIPS_MT_SMP
361 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
362 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
363#else
364 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
365 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
366#endif
367
368 /* tell oprofile which irq to use */
369 ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
370
371 /*
372 * if the timer irq is not one of the mips irqs we need to
373 * create a mapping
374 */
375 if (MIPS_CPU_TIMER_IRQ != 7)
376 irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
377
378 /* the external interrupts are optional and xway only */
379 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
380 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
381 /* find out how many external irq sources we have */
382 exin_avail = of_property_count_u32_elems(eiu_node,
383 "lantiq,eiu-irqs");
384
385 if (exin_avail > MAX_EIU)
386 exin_avail = MAX_EIU;
387
388 ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
389 ltq_eiu_irq, exin_avail);
390 if (ret)
391 panic("failed to load external irq resources");
392
393 if (!request_mem_region(res.start, resource_size(&res),
394 res.name))
395 pr_err("Failed to request eiu memory");
396
397 ltq_eiu_membase = ioremap_nocache(res.start,
398 resource_size(&res));
399 if (!ltq_eiu_membase)
400 panic("Failed to remap eiu memory");
401 }
402
403 return 0;
404}
405
406int get_c0_perfcount_int(void)
407{
408 return ltq_perfcount_irq;
409}
410EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
411
412unsigned int get_c0_compare_int(void)
413{
414 return MIPS_CPU_TIMER_IRQ;
415}
416
417static struct of_device_id __initdata of_irq_ids[] = {
418 { .compatible = "lantiq,icu", .data = icu_of_init },
419 {},
420};
421
422void __init arch_init_irq(void)
423{
424 of_irq_init(of_irq_ids);
425}