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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
5 * Copyright (C) 2010 John Crispin <john@phrozen.org>
6 */
7#include <linux/io.h>
8#include <linux/export.h>
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/err.h>
15#include <linux/list.h>
16
17#include <asm/time.h>
18#include <asm/irq.h>
19#include <asm/div64.h>
20
21#include <lantiq_soc.h>
22
23#include "clk.h"
24#include "prom.h"
25
26/* lantiq socs have 3 static clocks */
27static struct clk cpu_clk_generic[4];
28
29void clkdev_add_static(unsigned long cpu, unsigned long fpi,
30 unsigned long io, unsigned long ppe)
31{
32 cpu_clk_generic[0].rate = cpu;
33 cpu_clk_generic[1].rate = fpi;
34 cpu_clk_generic[2].rate = io;
35 cpu_clk_generic[3].rate = ppe;
36}
37
38struct clk *clk_get_cpu(void)
39{
40 return &cpu_clk_generic[0];
41}
42
43struct clk *clk_get_fpi(void)
44{
45 return &cpu_clk_generic[1];
46}
47EXPORT_SYMBOL_GPL(clk_get_fpi);
48
49struct clk *clk_get_io(void)
50{
51 return &cpu_clk_generic[2];
52}
53EXPORT_SYMBOL_GPL(clk_get_io);
54
55struct clk *clk_get_ppe(void)
56{
57 return &cpu_clk_generic[3];
58}
59EXPORT_SYMBOL_GPL(clk_get_ppe);
60
61static inline int clk_good(struct clk *clk)
62{
63 return clk && !IS_ERR(clk);
64}
65
66unsigned long clk_get_rate(struct clk *clk)
67{
68 if (unlikely(!clk_good(clk)))
69 return 0;
70
71 if (clk->rate != 0)
72 return clk->rate;
73
74 if (clk->get_rate != NULL)
75 return clk->get_rate();
76
77 return 0;
78}
79EXPORT_SYMBOL(clk_get_rate);
80
81int clk_set_rate(struct clk *clk, unsigned long rate)
82{
83 if (unlikely(!clk_good(clk)))
84 return 0;
85 if (clk->rates && *clk->rates) {
86 unsigned long *r = clk->rates;
87
88 while (*r && (*r != rate))
89 r++;
90 if (!*r) {
91 pr_err("clk %s.%s: trying to set invalid rate %ld\n",
92 clk->cl.dev_id, clk->cl.con_id, rate);
93 return -1;
94 }
95 }
96 clk->rate = rate;
97 return 0;
98}
99EXPORT_SYMBOL(clk_set_rate);
100
101long clk_round_rate(struct clk *clk, unsigned long rate)
102{
103 if (unlikely(!clk_good(clk)))
104 return 0;
105 if (clk->rates && *clk->rates) {
106 unsigned long *r = clk->rates;
107
108 while (*r && (*r != rate))
109 r++;
110 if (!*r) {
111 return clk->rate;
112 }
113 }
114 return rate;
115}
116EXPORT_SYMBOL(clk_round_rate);
117
118int clk_enable(struct clk *clk)
119{
120 if (unlikely(!clk_good(clk)))
121 return -1;
122
123 if (clk->enable)
124 return clk->enable(clk);
125
126 return -1;
127}
128EXPORT_SYMBOL(clk_enable);
129
130void clk_disable(struct clk *clk)
131{
132 if (unlikely(!clk_good(clk)))
133 return;
134
135 if (clk->disable)
136 clk->disable(clk);
137}
138EXPORT_SYMBOL(clk_disable);
139
140int clk_activate(struct clk *clk)
141{
142 if (unlikely(!clk_good(clk)))
143 return -1;
144
145 if (clk->activate)
146 return clk->activate(clk);
147
148 return -1;
149}
150EXPORT_SYMBOL(clk_activate);
151
152void clk_deactivate(struct clk *clk)
153{
154 if (unlikely(!clk_good(clk)))
155 return;
156
157 if (clk->deactivate)
158 clk->deactivate(clk);
159}
160EXPORT_SYMBOL(clk_deactivate);
161
162struct clk *clk_get_parent(struct clk *clk)
163{
164 return NULL;
165}
166EXPORT_SYMBOL(clk_get_parent);
167
168int clk_set_parent(struct clk *clk, struct clk *parent)
169{
170 return 0;
171}
172EXPORT_SYMBOL(clk_set_parent);
173
174static inline u32 get_counter_resolution(void)
175{
176 u32 res;
177
178 __asm__ __volatile__(
179 ".set push\n"
180 ".set mips32r2\n"
181 "rdhwr %0, $3\n"
182 ".set pop\n"
183 : "=&r" (res)
184 : /* no input */
185 : "memory");
186
187 return res;
188}
189
190void __init plat_time_init(void)
191{
192 struct clk *clk;
193
194 ltq_soc_init();
195
196 clk = clk_get_cpu();
197 mips_hpt_frequency = clk_get_rate(clk) / get_counter_resolution();
198 write_c0_compare(read_c0_count());
199 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
200 clk_put(clk);
201}
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
7 * Copyright (C) 2010 John Crispin <john@phrozen.org>
8 */
9#include <linux/io.h>
10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/list.h>
18
19#include <asm/time.h>
20#include <asm/irq.h>
21#include <asm/div64.h>
22
23#include <lantiq_soc.h>
24
25#include "clk.h"
26#include "prom.h"
27
28/* lantiq socs have 3 static clocks */
29static struct clk cpu_clk_generic[4];
30
31void clkdev_add_static(unsigned long cpu, unsigned long fpi,
32 unsigned long io, unsigned long ppe)
33{
34 cpu_clk_generic[0].rate = cpu;
35 cpu_clk_generic[1].rate = fpi;
36 cpu_clk_generic[2].rate = io;
37 cpu_clk_generic[3].rate = ppe;
38}
39
40struct clk *clk_get_cpu(void)
41{
42 return &cpu_clk_generic[0];
43}
44
45struct clk *clk_get_fpi(void)
46{
47 return &cpu_clk_generic[1];
48}
49EXPORT_SYMBOL_GPL(clk_get_fpi);
50
51struct clk *clk_get_io(void)
52{
53 return &cpu_clk_generic[2];
54}
55
56struct clk *clk_get_ppe(void)
57{
58 return &cpu_clk_generic[3];
59}
60EXPORT_SYMBOL_GPL(clk_get_ppe);
61
62static inline int clk_good(struct clk *clk)
63{
64 return clk && !IS_ERR(clk);
65}
66
67unsigned long clk_get_rate(struct clk *clk)
68{
69 if (unlikely(!clk_good(clk)))
70 return 0;
71
72 if (clk->rate != 0)
73 return clk->rate;
74
75 if (clk->get_rate != NULL)
76 return clk->get_rate();
77
78 return 0;
79}
80EXPORT_SYMBOL(clk_get_rate);
81
82int clk_set_rate(struct clk *clk, unsigned long rate)
83{
84 if (unlikely(!clk_good(clk)))
85 return 0;
86 if (clk->rates && *clk->rates) {
87 unsigned long *r = clk->rates;
88
89 while (*r && (*r != rate))
90 r++;
91 if (!*r) {
92 pr_err("clk %s.%s: trying to set invalid rate %ld\n",
93 clk->cl.dev_id, clk->cl.con_id, rate);
94 return -1;
95 }
96 }
97 clk->rate = rate;
98 return 0;
99}
100EXPORT_SYMBOL(clk_set_rate);
101
102long clk_round_rate(struct clk *clk, unsigned long rate)
103{
104 if (unlikely(!clk_good(clk)))
105 return 0;
106 if (clk->rates && *clk->rates) {
107 unsigned long *r = clk->rates;
108
109 while (*r && (*r != rate))
110 r++;
111 if (!*r) {
112 return clk->rate;
113 }
114 }
115 return rate;
116}
117EXPORT_SYMBOL(clk_round_rate);
118
119int clk_enable(struct clk *clk)
120{
121 if (unlikely(!clk_good(clk)))
122 return -1;
123
124 if (clk->enable)
125 return clk->enable(clk);
126
127 return -1;
128}
129EXPORT_SYMBOL(clk_enable);
130
131void clk_disable(struct clk *clk)
132{
133 if (unlikely(!clk_good(clk)))
134 return;
135
136 if (clk->disable)
137 clk->disable(clk);
138}
139EXPORT_SYMBOL(clk_disable);
140
141int clk_activate(struct clk *clk)
142{
143 if (unlikely(!clk_good(clk)))
144 return -1;
145
146 if (clk->activate)
147 return clk->activate(clk);
148
149 return -1;
150}
151EXPORT_SYMBOL(clk_activate);
152
153void clk_deactivate(struct clk *clk)
154{
155 if (unlikely(!clk_good(clk)))
156 return;
157
158 if (clk->deactivate)
159 clk->deactivate(clk);
160}
161EXPORT_SYMBOL(clk_deactivate);
162
163static inline u32 get_counter_resolution(void)
164{
165 u32 res;
166
167 __asm__ __volatile__(
168 ".set push\n"
169 ".set mips32r2\n"
170 "rdhwr %0, $3\n"
171 ".set pop\n"
172 : "=&r" (res)
173 : /* no input */
174 : "memory");
175
176 return res;
177}
178
179void __init plat_time_init(void)
180{
181 struct clk *clk;
182
183 ltq_soc_init();
184
185 clk = clk_get_cpu();
186 mips_hpt_frequency = clk_get_rate(clk) / get_counter_resolution();
187 write_c0_compare(read_c0_count());
188 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
189 clk_put(clk);
190}