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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 */
7#include <linux/init.h>
8#include <linux/kernel.h>
9#include <linux/ptrace.h>
10#include <linux/smp.h>
11#include <linux/stddef.h>
12#include <linux/export.h>
13#include <linux/printk.h>
14#include <linux/uaccess.h>
15
16#include <asm/cpu-features.h>
17#include <asm/elf.h>
18#include <asm/fpu.h>
19#include <asm/loongarch.h>
20#include <asm/pgtable-bits.h>
21#include <asm/setup.h>
22
23/* Hardware capabilities */
24unsigned int elf_hwcap __read_mostly;
25EXPORT_SYMBOL_GPL(elf_hwcap);
26
27/*
28 * Determine the FCSR mask for FPU hardware.
29 */
30static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch *c)
31{
32 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
33
34 fcsr = c->fpu_csr0;
35 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
36
37 sr = read_csr_euen();
38 enable_fpu();
39
40 fcsr0 = fcsr & mask;
41 write_fcsr(LOONGARCH_FCSR0, fcsr0);
42 fcsr0 = read_fcsr(LOONGARCH_FCSR0);
43
44 fcsr1 = fcsr | ~mask;
45 write_fcsr(LOONGARCH_FCSR0, fcsr1);
46 fcsr1 = read_fcsr(LOONGARCH_FCSR0);
47
48 write_fcsr(LOONGARCH_FCSR0, fcsr);
49
50 write_csr_euen(sr);
51
52 c->fpu_mask = ~(fcsr0 ^ fcsr1) & ~mask;
53}
54
55static inline void set_elf_platform(int cpu, const char *plat)
56{
57 if (cpu == 0)
58 __elf_platform = plat;
59}
60
61/* MAP BASE */
62unsigned long vm_map_base;
63EXPORT_SYMBOL(vm_map_base);
64
65static void cpu_probe_addrbits(struct cpuinfo_loongarch *c)
66{
67#ifdef __NEED_ADDRBITS_PROBE
68 c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4;
69 c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12;
70 vm_map_base = 0UL - (1UL << c->vabits);
71#endif
72}
73
74static void set_isa(struct cpuinfo_loongarch *c, unsigned int isa)
75{
76 switch (isa) {
77 case LOONGARCH_CPU_ISA_LA64:
78 c->isa_level |= LOONGARCH_CPU_ISA_LA64;
79 fallthrough;
80 case LOONGARCH_CPU_ISA_LA32S:
81 c->isa_level |= LOONGARCH_CPU_ISA_LA32S;
82 fallthrough;
83 case LOONGARCH_CPU_ISA_LA32R:
84 c->isa_level |= LOONGARCH_CPU_ISA_LA32R;
85 break;
86 }
87}
88
89static void cpu_probe_common(struct cpuinfo_loongarch *c)
90{
91 unsigned int config;
92 unsigned long asid_mask;
93
94 c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR |
95 LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH;
96
97 elf_hwcap = HWCAP_LOONGARCH_CPUCFG;
98
99 config = read_cpucfg(LOONGARCH_CPUCFG1);
100 if (config & CPUCFG1_UAL) {
101 c->options |= LOONGARCH_CPU_UAL;
102 elf_hwcap |= HWCAP_LOONGARCH_UAL;
103 }
104 if (config & CPUCFG1_CRC32) {
105 c->options |= LOONGARCH_CPU_CRC32;
106 elf_hwcap |= HWCAP_LOONGARCH_CRC32;
107 }
108
109
110 config = read_cpucfg(LOONGARCH_CPUCFG2);
111 if (config & CPUCFG2_LAM) {
112 c->options |= LOONGARCH_CPU_LAM;
113 elf_hwcap |= HWCAP_LOONGARCH_LAM;
114 }
115 if (config & CPUCFG2_FP) {
116 c->options |= LOONGARCH_CPU_FPU;
117 elf_hwcap |= HWCAP_LOONGARCH_FPU;
118 }
119#ifdef CONFIG_CPU_HAS_LSX
120 if (config & CPUCFG2_LSX) {
121 c->options |= LOONGARCH_CPU_LSX;
122 elf_hwcap |= HWCAP_LOONGARCH_LSX;
123 }
124#endif
125#ifdef CONFIG_CPU_HAS_LASX
126 if (config & CPUCFG2_LASX) {
127 c->options |= LOONGARCH_CPU_LASX;
128 elf_hwcap |= HWCAP_LOONGARCH_LASX;
129 }
130#endif
131 if (config & CPUCFG2_COMPLEX) {
132 c->options |= LOONGARCH_CPU_COMPLEX;
133 elf_hwcap |= HWCAP_LOONGARCH_COMPLEX;
134 }
135 if (config & CPUCFG2_CRYPTO) {
136 c->options |= LOONGARCH_CPU_CRYPTO;
137 elf_hwcap |= HWCAP_LOONGARCH_CRYPTO;
138 }
139 if (config & CPUCFG2_PTW) {
140 c->options |= LOONGARCH_CPU_PTW;
141 elf_hwcap |= HWCAP_LOONGARCH_PTW;
142 }
143 if (config & CPUCFG2_LVZP) {
144 c->options |= LOONGARCH_CPU_LVZ;
145 elf_hwcap |= HWCAP_LOONGARCH_LVZ;
146 }
147#ifdef CONFIG_CPU_HAS_LBT
148 if (config & CPUCFG2_X86BT) {
149 c->options |= LOONGARCH_CPU_LBT_X86;
150 elf_hwcap |= HWCAP_LOONGARCH_LBT_X86;
151 }
152 if (config & CPUCFG2_ARMBT) {
153 c->options |= LOONGARCH_CPU_LBT_ARM;
154 elf_hwcap |= HWCAP_LOONGARCH_LBT_ARM;
155 }
156 if (config & CPUCFG2_MIPSBT) {
157 c->options |= LOONGARCH_CPU_LBT_MIPS;
158 elf_hwcap |= HWCAP_LOONGARCH_LBT_MIPS;
159 }
160#endif
161
162 config = read_cpucfg(LOONGARCH_CPUCFG6);
163 if (config & CPUCFG6_PMP)
164 c->options |= LOONGARCH_CPU_PMP;
165
166 config = iocsr_read32(LOONGARCH_IOCSR_FEATURES);
167 if (config & IOCSRF_CSRIPI)
168 c->options |= LOONGARCH_CPU_CSRIPI;
169 if (config & IOCSRF_EXTIOI)
170 c->options |= LOONGARCH_CPU_EXTIOI;
171 if (config & IOCSRF_FREQSCALE)
172 c->options |= LOONGARCH_CPU_SCALEFREQ;
173 if (config & IOCSRF_FLATMODE)
174 c->options |= LOONGARCH_CPU_FLATMODE;
175 if (config & IOCSRF_EIODECODE)
176 c->options |= LOONGARCH_CPU_EIODECODE;
177 if (config & IOCSRF_VM)
178 c->options |= LOONGARCH_CPU_HYPERVISOR;
179
180 config = csr_read32(LOONGARCH_CSR_ASID);
181 config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
182 asid_mask = GENMASK(config - 1, 0);
183 set_cpu_asid_mask(c, asid_mask);
184
185 config = read_csr_prcfg1();
186 c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0);
187 c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK);
188
189 config = read_csr_prcfg3();
190 switch (config & CSR_CONF3_TLBTYPE) {
191 case 0:
192 c->tlbsizemtlb = 0;
193 c->tlbsizestlbsets = 0;
194 c->tlbsizestlbways = 0;
195 c->tlbsize = 0;
196 break;
197 case 1:
198 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1;
199 c->tlbsizestlbsets = 0;
200 c->tlbsizestlbways = 0;
201 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways;
202 break;
203 case 2:
204 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1;
205 c->tlbsizestlbsets = 1 << ((config & CSR_CONF3_STLBIDX) >> CSR_CONF3_STLBIDX_SHIFT);
206 c->tlbsizestlbways = ((config & CSR_CONF3_STLBWAYS) >> CSR_CONF3_STLBWAYS_SHIFT) + 1;
207 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways;
208 break;
209 default:
210 pr_warn("Warning: unknown TLB type\n");
211 }
212}
213
214#define MAX_NAME_LEN 32
215#define VENDOR_OFFSET 0
216#define CPUNAME_OFFSET 9
217
218static char cpu_full_name[MAX_NAME_LEN] = " - ";
219
220static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int cpu)
221{
222 uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]);
223 uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]);
224
225 if (!__cpu_full_name[cpu])
226 __cpu_full_name[cpu] = cpu_full_name;
227
228 *vendor = iocsr_read64(LOONGARCH_IOCSR_VENDOR);
229 *cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME);
230
231 switch (c->processor_id & PRID_SERIES_MASK) {
232 case PRID_SERIES_LA132:
233 c->cputype = CPU_LOONGSON32;
234 set_isa(c, LOONGARCH_CPU_ISA_LA32S);
235 __cpu_family[cpu] = "Loongson-32bit";
236 pr_info("32-bit Loongson Processor probed (LA132 Core)\n");
237 break;
238 case PRID_SERIES_LA264:
239 c->cputype = CPU_LOONGSON64;
240 set_isa(c, LOONGARCH_CPU_ISA_LA64);
241 __cpu_family[cpu] = "Loongson-64bit";
242 pr_info("64-bit Loongson Processor probed (LA264 Core)\n");
243 break;
244 case PRID_SERIES_LA364:
245 c->cputype = CPU_LOONGSON64;
246 set_isa(c, LOONGARCH_CPU_ISA_LA64);
247 __cpu_family[cpu] = "Loongson-64bit";
248 pr_info("64-bit Loongson Processor probed (LA364 Core)\n");
249 break;
250 case PRID_SERIES_LA464:
251 c->cputype = CPU_LOONGSON64;
252 set_isa(c, LOONGARCH_CPU_ISA_LA64);
253 __cpu_family[cpu] = "Loongson-64bit";
254 pr_info("64-bit Loongson Processor probed (LA464 Core)\n");
255 break;
256 case PRID_SERIES_LA664:
257 c->cputype = CPU_LOONGSON64;
258 set_isa(c, LOONGARCH_CPU_ISA_LA64);
259 __cpu_family[cpu] = "Loongson-64bit";
260 pr_info("64-bit Loongson Processor probed (LA664 Core)\n");
261 break;
262 default: /* Default to 64 bit */
263 c->cputype = CPU_LOONGSON64;
264 set_isa(c, LOONGARCH_CPU_ISA_LA64);
265 __cpu_family[cpu] = "Loongson-64bit";
266 pr_info("64-bit Loongson Processor probed (Unknown Core)\n");
267 }
268}
269
270#ifdef CONFIG_64BIT
271/* For use by uaccess.h */
272u64 __ua_limit;
273EXPORT_SYMBOL(__ua_limit);
274#endif
275
276const char *__cpu_family[NR_CPUS];
277const char *__cpu_full_name[NR_CPUS];
278const char *__elf_platform;
279
280static void cpu_report(void)
281{
282 struct cpuinfo_loongarch *c = ¤t_cpu_data;
283
284 pr_info("CPU%d revision is: %08x (%s)\n",
285 smp_processor_id(), c->processor_id, cpu_family_string());
286 if (c->options & LOONGARCH_CPU_FPU)
287 pr_info("FPU%d revision is: %08x\n", smp_processor_id(), c->fpu_vers);
288}
289
290void cpu_probe(void)
291{
292 unsigned int cpu = smp_processor_id();
293 struct cpuinfo_loongarch *c = ¤t_cpu_data;
294
295 /*
296 * Set a default ELF platform, cpu probe may later
297 * overwrite it with a more precise value
298 */
299 set_elf_platform(cpu, "loongarch");
300
301 c->cputype = CPU_UNKNOWN;
302 c->processor_id = read_cpucfg(LOONGARCH_CPUCFG0);
303 c->fpu_vers = (read_cpucfg(LOONGARCH_CPUCFG2) & CPUCFG2_FPVERS) >> 3;
304
305 c->fpu_csr0 = FPU_CSR_RN;
306 c->fpu_mask = FPU_CSR_RSVD;
307
308 cpu_probe_common(c);
309
310 per_cpu_trap_init(cpu);
311
312 switch (c->processor_id & PRID_COMP_MASK) {
313 case PRID_COMP_LOONGSON:
314 cpu_probe_loongson(c, cpu);
315 break;
316 }
317
318 BUG_ON(!__cpu_family[cpu]);
319 BUG_ON(c->cputype == CPU_UNKNOWN);
320
321 cpu_probe_addrbits(c);
322
323#ifdef CONFIG_64BIT
324 if (cpu == 0)
325 __ua_limit = ~((1ull << cpu_vabits) - 1);
326#endif
327
328 cpu_report();
329}