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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright(c) 2022 Intel Corporation. All rights reserved.
4//
5// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
6//
7
8/*
9 * Hardware interface for audio DSP on Meteorlake.
10 */
11
12#include <linux/firmware.h>
13#include <sound/sof/ipc4/header.h>
14#include <trace/events/sof_intel.h>
15#include "../ipc4-priv.h"
16#include "../ops.h"
17#include "hda.h"
18#include "hda-ipc.h"
19#include "../sof-audio.h"
20#include "mtl.h"
21#include "telemetry.h"
22
23static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = {
24 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
25 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
26 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
27};
28
29static void mtl_ipc_host_done(struct snd_sof_dev *sdev)
30{
31 /*
32 * clear busy interrupt to tell dsp controller this interrupt has been accepted,
33 * not trigger it again
34 */
35 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR,
36 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY);
37 /*
38 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp
39 */
40 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA,
41 MTL_DSP_REG_HFIPCXTDA_BUSY, 0);
42}
43
44static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev)
45{
46 /*
47 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it,
48 * don't send more reply to host
49 */
50 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA,
51 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE);
52
53 /* unmask Done interrupt */
54 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
55 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE);
56}
57
58/* Check if an IPC IRQ occurred */
59bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
60{
61 u32 irq_status;
62 u32 hfintipptr;
63
64 if (sdev->dspless_mode_selected)
65 return false;
66
67 /* read Interrupt IP Pointer */
68 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
69 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
70
71 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
72
73 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC))
74 return true;
75
76 return false;
77}
78
79/* Check if an SDW IRQ occurred */
80static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
81{
82 u32 irq_status;
83 u32 hfintipptr;
84
85 /* read Interrupt IP Pointer */
86 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
87 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
88
89 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW))
90 return true;
91
92 return false;
93}
94
95int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
96{
97 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
98 struct sof_ipc4_msg *msg_data = msg->msg_data;
99
100 if (hda_ipc4_tx_is_busy(sdev)) {
101 hdev->delayed_ipc_tx_msg = msg;
102 return 0;
103 }
104
105 hdev->delayed_ipc_tx_msg = NULL;
106
107 /* send the message via mailbox */
108 if (msg_data->data_size)
109 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
110 msg_data->data_size);
111
112 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY,
113 msg_data->extension);
114 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR,
115 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY);
116
117 hda_dsp_ipc4_schedule_d0i3_work(hdev, msg);
118
119 return 0;
120}
121
122void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev)
123{
124 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
125 const struct sof_intel_dsp_desc *chip = hda->desc;
126
127 if (sdev->dspless_mode_selected)
128 return;
129
130 /* enable IPC DONE and BUSY interrupts */
131 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
132 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE,
133 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE);
134}
135
136void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev)
137{
138 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
139 const struct sof_intel_dsp_desc *chip = hda->desc;
140
141 if (sdev->dspless_mode_selected)
142 return;
143
144 /* disable IPC DONE and BUSY interrupts */
145 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
146 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0);
147}
148
149static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
150{
151 u32 hipcie;
152 u32 mask;
153 u32 val;
154 int ret;
155
156 if (sdev->dspless_mode_selected)
157 return;
158
159 /* Enable/Disable SoundWire interrupt */
160 mask = MTL_DSP_REG_HfSNDWIE_IE_MASK;
161 if (enable)
162 val = mask;
163 else
164 val = 0;
165
166 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val);
167
168 /* check if operation was successful */
169 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
170 (hipcie & mask) == val,
171 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
172 if (ret < 0)
173 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n",
174 enable ? "enable" : "disable");
175}
176
177int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable)
178{
179 u32 hfintipptr;
180 u32 irqinten;
181 u32 hipcie;
182 u32 mask;
183 u32 val;
184 int ret;
185
186 if (sdev->dspless_mode_selected)
187 return 0;
188
189 /* read Interrupt IP Pointer */
190 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
191
192 /* Enable/Disable Host IPC and SOUNDWIRE */
193 mask = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;
194 if (enable)
195 val = mask;
196 else
197 val = 0;
198
199 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val);
200
201 /* check if operation was successful */
202 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
203 (irqinten & mask) == val,
204 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
205 if (ret < 0) {
206 dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n",
207 enable ? "enable" : "disable");
208 return ret;
209 }
210
211 /* Enable/Disable Host IPC interrupt*/
212 mask = MTL_DSP_REG_HfHIPCIE_IE_MASK;
213 if (enable)
214 val = mask;
215 else
216 val = 0;
217
218 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val);
219
220 /* check if operation was successful */
221 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
222 (hipcie & mask) == val,
223 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
224 if (ret < 0) {
225 dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n",
226 enable ? "enable" : "disable");
227 return ret;
228 }
229
230 return ret;
231}
232
233/* pre fw run operations */
234int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
235{
236 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
237 u32 dsphfpwrsts;
238 u32 dsphfdsscs;
239 u32 cpa;
240 u32 pgs;
241 int ret;
242
243 /* Set the DSP subsystem power on */
244 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
245 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK);
246
247 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
248 usleep_range(1000, 1010);
249
250 /* poll with timeout to check if operation successful */
251 cpa = MTL_HFDSSCS_CPA_MASK;
252 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
253 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
254 HDA_DSP_RESET_TIMEOUT_US);
255 if (ret < 0) {
256 dev_err(sdev->dev, "failed to enable DSP subsystem\n");
257 return ret;
258 }
259
260 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */
261 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
262 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG);
263
264 usleep_range(1000, 1010);
265
266 /* poll with timeout to check if operation successful */
267 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;
268 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts,
269 (dsphfpwrsts & pgs) == pgs,
270 HDA_DSP_REG_POLL_INTERVAL_US,
271 HDA_DSP_RESET_TIMEOUT_US);
272 if (ret < 0)
273 dev_err(sdev->dev, "failed to power up gated DSP domain\n");
274
275 /* if SoundWire is used, make sure it is not power-gated */
276 if (hdev->info.handle && hdev->info.link_mask > 0)
277 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
278 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1));
279
280 return ret;
281}
282
283int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
284{
285 int ret;
286
287 if (sdev->first_boot) {
288 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
289
290 ret = hda_sdw_startup(sdev);
291 if (ret < 0) {
292 dev_err(sdev->dev, "could not startup SoundWire links\n");
293 return ret;
294 }
295
296 /* Check if IMR boot is usable */
297 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT))
298 hdev->imrboot_supported = true;
299 }
300
301 hda_sdw_int_enable(sdev, true);
302 return 0;
303}
304
305void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
306{
307 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
308 u32 romdbgsts;
309 u32 romdbgerr;
310 u32 fwsts;
311 u32 fwlec;
312
313 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS);
314 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR);
315 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY);
316 romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR);
317
318 dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec);
319 dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts,
320 romdbgerr);
321 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3);
322 dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n",
323 romdbgsts & BIT(24) ? "" : " not");
324
325 sof_ipc4_intel_dump_telemetry_state(sdev, flags);
326}
327
328static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev)
329{
330 int val;
331
332 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE);
333 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK)
334 return true;
335
336 return false;
337}
338
339static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core)
340{
341 unsigned int cpa;
342 u32 dspcxctl;
343 int ret;
344
345 /* Only the primary core can be powered up by the host */
346 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev))
347 return 0;
348
349 /* Program the owner of the IP & shim registers (10: Host CPU) */
350 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
351 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL,
352 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT);
353
354 /* enable SPA bit */
355 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
356 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK,
357 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK);
358
359 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
360 usleep_range(1000, 1010);
361
362 /* poll with timeout to check if operation successful */
363 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK;
364 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
365 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
366 HDA_DSP_RESET_TIMEOUT_US);
367 if (ret < 0) {
368 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n",
369 __func__);
370 return ret;
371 }
372
373 /* set primary core mask and refcount to 1 */
374 sdev->enabled_cores_mask = BIT(SOF_DSP_PRIMARY_CORE);
375 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 1;
376
377 return 0;
378}
379
380static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core)
381{
382 u32 dspcxctl;
383 int ret;
384
385 /* Only the primary core can be powered down by the host */
386 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev))
387 return 0;
388
389 /* disable SPA bit */
390 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
391 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0);
392
393 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
394 usleep_range(1000, 1010);
395
396 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
397 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK),
398 HDA_DSP_REG_POLL_INTERVAL_US,
399 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
400 if (ret < 0) {
401 dev_err(sdev->dev, "failed to power down primary core\n");
402 return ret;
403 }
404
405 sdev->enabled_cores_mask = 0;
406 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 0;
407
408 return 0;
409}
410
411int mtl_power_down_dsp(struct snd_sof_dev *sdev)
412{
413 u32 dsphfdsscs, cpa;
414 int ret;
415
416 /* first power down core */
417 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
418 if (ret) {
419 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret);
420 return ret;
421 }
422
423 /* Set the DSP subsystem power down */
424 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
425 MTL_HFDSSCS_SPA_MASK, 0);
426
427 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
428 usleep_range(1000, 1010);
429
430 /* poll with timeout to check if operation successful */
431 cpa = MTL_HFDSSCS_CPA_MASK;
432 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
433 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
434 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,
435 HDA_DSP_RESET_TIMEOUT_US);
436}
437
438int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
439{
440 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
441 const struct sof_intel_dsp_desc *chip = hda->desc;
442 unsigned int status;
443 u32 ipc_hdr, flags;
444 char *dump_msg;
445 int ret;
446
447 /* step 1: purge FW request */
448 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
449 if (!imr_boot)
450 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
451
452 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
453
454 /* step 2: power up primary core */
455 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
456 if (ret < 0) {
457 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
458 dev_err(sdev->dev, "dsp core 0/1 power up failed\n");
459 goto err;
460 }
461
462 dev_dbg(sdev->dev, "Primary core power up successful\n");
463
464 /* step 3: wait for IPC DONE bit from ROM */
465 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status,
466 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask),
467 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_INIT_TIMEOUT_US);
468 if (ret < 0) {
469 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
470 dev_err(sdev->dev, "timeout waiting for purge IPC done\n");
471 goto err;
472 }
473
474 /* set DONE bit to clear the reply IPC message */
475 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask,
476 chip->ipc_ack_mask);
477
478 /* step 4: enable interrupts */
479 ret = mtl_enable_interrupts(sdev, true);
480 if (ret < 0) {
481 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
482 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__);
483 goto err;
484 }
485
486 mtl_enable_ipc_interrupts(sdev);
487
488 /*
489 * ACE workaround: don't wait for ROM INIT.
490 * The platform cannot catch ROM_INIT_DONE because of a very short
491 * timing window. Follow the recommendations and skip this part.
492 */
493
494 return 0;
495
496err:
497 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL;
498
499 /* after max boot attempts make sure that the dump is printed */
500 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
501 flags &= ~SOF_DBG_DUMP_OPTIONAL;
502
503 dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d",
504 hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS);
505 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
506 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
507
508 kfree(dump_msg);
509 return ret;
510}
511
512irqreturn_t mtl_ipc_irq_thread(int irq, void *context)
513{
514 struct sof_ipc4_msg notification_data = {{ 0 }};
515 struct snd_sof_dev *sdev = context;
516 bool ack_received = false;
517 bool ipc_irq = false;
518 u32 hipcida;
519 u32 hipctdr;
520
521 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
522 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
523
524 /* reply message from DSP */
525 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) {
526 /* DSP received the message */
527 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
528 MTL_DSP_REG_HFIPCXCTL_DONE, 0);
529
530 mtl_ipc_dsp_done(sdev);
531
532 ipc_irq = true;
533 ack_received = true;
534 }
535
536 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) {
537 /* Message from DSP (reply or notification) */
538 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
539 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK;
540
541 /*
542 * ACE fw sends a new fw ipc message to host to
543 * notify the status of the last host ipc message
544 */
545 if (primary & SOF_IPC4_MSG_DIR_MASK) {
546 /* Reply received */
547 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
548 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
549
550 data->primary = primary;
551 data->extension = extension;
552
553 spin_lock_irq(&sdev->ipc_lock);
554
555 snd_sof_ipc_get_reply(sdev);
556 mtl_ipc_host_done(sdev);
557 snd_sof_ipc_reply(sdev, data->primary);
558
559 spin_unlock_irq(&sdev->ipc_lock);
560 } else {
561 dev_dbg_ratelimited(sdev->dev,
562 "IPC reply before FW_READY: %#x|%#x\n",
563 primary, extension);
564 }
565 } else {
566 /* Notification received */
567 notification_data.primary = primary;
568 notification_data.extension = extension;
569
570 sdev->ipc->msg.rx_data = ¬ification_data;
571 snd_sof_ipc_msgs_rx(sdev);
572 sdev->ipc->msg.rx_data = NULL;
573
574 mtl_ipc_host_done(sdev);
575 }
576
577 ipc_irq = true;
578 }
579
580 if (!ipc_irq) {
581 /* This interrupt is not shared so no need to return IRQ_NONE. */
582 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
583 }
584
585 if (ack_received) {
586 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
587
588 if (hdev->delayed_ipc_tx_msg)
589 mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg);
590 }
591
592 return IRQ_HANDLED;
593}
594
595int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
596{
597 return MTL_DSP_MBOX_UPLINK_OFFSET;
598}
599
600int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
601{
602 return MTL_SRAM_WINDOW_OFFSET(id);
603}
604
605void mtl_ipc_dump(struct snd_sof_dev *sdev)
606{
607 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl;
608
609 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR);
610 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY);
611 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
612 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
613 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
614 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA);
615 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL);
616
617 dev_err(sdev->dev,
618 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
619 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
620}
621
622static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
623{
624 mtl_enable_sdw_irq(sdev, false);
625 mtl_disable_ipc_interrupts(sdev);
626 return mtl_enable_interrupts(sdev, false);
627}
628
629u64 mtl_dsp_get_stream_hda_link_position(struct snd_sof_dev *sdev,
630 struct snd_soc_component *component,
631 struct snd_pcm_substream *substream)
632{
633 struct hdac_stream *hstream = substream->runtime->private_data;
634 u32 llp_l, llp_u;
635
636 llp_l = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, MTL_PPLCLLPL(hstream->index));
637 llp_u = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, MTL_PPLCLLPU(hstream->index));
638 return ((u64)llp_u << 32) | llp_l;
639}
640
641int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core)
642{
643 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
644
645 if (core == SOF_DSP_PRIMARY_CORE)
646 return mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
647
648 if (pm_ops->set_core_state)
649 return pm_ops->set_core_state(sdev, core, true);
650
651 return 0;
652}
653
654int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core)
655{
656 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
657 int ret;
658
659 if (pm_ops->set_core_state) {
660 ret = pm_ops->set_core_state(sdev, core, false);
661 if (ret < 0)
662 return ret;
663 }
664
665 if (core == SOF_DSP_PRIMARY_CORE)
666 return mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
667
668 return 0;
669}
670
671/* Meteorlake ops */
672struct snd_sof_dsp_ops sof_mtl_ops;
673EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
674
675int sof_mtl_ops_init(struct snd_sof_dev *sdev)
676{
677 struct sof_ipc4_fw_data *ipc4_data;
678
679 /* common defaults */
680 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
681
682 /* shutdown */
683 sof_mtl_ops.shutdown = hda_dsp_shutdown;
684
685 /* doorbell */
686 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread;
687
688 /* ipc */
689 sof_mtl_ops.send_msg = mtl_ipc_send_msg;
690 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
691 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;
692
693 /* debug */
694 sof_mtl_ops.debug_map = mtl_dsp_debugfs;
695 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs);
696 sof_mtl_ops.dbg_dump = mtl_dsp_dump;
697 sof_mtl_ops.ipc_dump = mtl_ipc_dump;
698
699 /* pre/post fw run */
700 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
701 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run;
702
703 /* parse platform specific extended manifest */
704 sof_mtl_ops.parse_platform_ext_manifest = NULL;
705
706 /* dsp core get/put */
707 sof_mtl_ops.core_get = mtl_dsp_core_get;
708 sof_mtl_ops.core_put = mtl_dsp_core_put;
709
710 sof_mtl_ops.get_stream_position = mtl_dsp_get_stream_hda_link_position;
711
712 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
713 if (!sdev->private)
714 return -ENOMEM;
715
716 ipc4_data = sdev->private;
717 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
718
719 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
720
721 ipc4_data->fw_context_save = true;
722
723 /* External library loading support */
724 ipc4_data->load_library = hda_dsp_ipc4_load_library;
725
726 /* set DAI ops */
727 hda_set_dai_drv_ops(sdev, &sof_mtl_ops);
728
729 sof_mtl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
730
731 return 0;
732};
733EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
734
735const struct sof_intel_dsp_desc mtl_chip_info = {
736 .cores_num = 3,
737 .init_core_mask = BIT(0),
738 .host_managed_cores_mask = BIT(0),
739 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
740 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
741 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
742 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
743 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
744 .rom_status_reg = MTL_DSP_ROM_STS,
745 .rom_init_timeout = 300,
746 .ssp_count = MTL_SSP_COUNT,
747 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
748 .sdw_shim_base = SDW_SHIM_BASE_ACE,
749 .sdw_alh_base = SDW_ALH_BASE_ACE,
750 .d0i3_offset = MTL_HDA_VS_D0I3C,
751 .read_sdw_lcount = hda_sdw_check_lcount_common,
752 .enable_sdw_irq = mtl_enable_sdw_irq,
753 .check_sdw_irq = mtl_dsp_check_sdw_irq,
754 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
755 .check_ipc_irq = mtl_dsp_check_ipc_irq,
756 .cl_init = mtl_dsp_cl_init,
757 .power_down_dsp = mtl_power_down_dsp,
758 .disable_interrupts = mtl_dsp_disable_interrupts,
759 .hw_ip_version = SOF_INTEL_ACE_1_0,
760};
761EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
762
763const struct sof_intel_dsp_desc arl_s_chip_info = {
764 .cores_num = 2,
765 .init_core_mask = BIT(0),
766 .host_managed_cores_mask = BIT(0),
767 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
768 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
769 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
770 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
771 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
772 .rom_status_reg = MTL_DSP_ROM_STS,
773 .rom_init_timeout = 300,
774 .ssp_count = MTL_SSP_COUNT,
775 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
776 .sdw_shim_base = SDW_SHIM_BASE_ACE,
777 .sdw_alh_base = SDW_ALH_BASE_ACE,
778 .d0i3_offset = MTL_HDA_VS_D0I3C,
779 .read_sdw_lcount = hda_sdw_check_lcount_common,
780 .enable_sdw_irq = mtl_enable_sdw_irq,
781 .check_sdw_irq = mtl_dsp_check_sdw_irq,
782 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
783 .check_ipc_irq = mtl_dsp_check_ipc_irq,
784 .cl_init = mtl_dsp_cl_init,
785 .power_down_dsp = mtl_power_down_dsp,
786 .disable_interrupts = mtl_dsp_disable_interrupts,
787 .hw_ip_version = SOF_INTEL_ACE_1_0,
788};
789EXPORT_SYMBOL_NS(arl_s_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);