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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Marvell Armada-3700 SPI controller driver
4 *
5 * Copyright (C) 2016 Marvell Ltd.
6 *
7 * Author: Wilson Ding <dingwei@marvell.com>
8 * Author: Romain Perier <romain.perier@free-electrons.com>
9 */
10
11#include <linux/clk.h>
12#include <linux/completion.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/spi/spi.h>
23
24#define DRIVER_NAME "armada_3700_spi"
25
26#define A3700_SPI_MAX_SPEED_HZ 100000000
27#define A3700_SPI_MAX_PRESCALE 30
28#define A3700_SPI_TIMEOUT 10
29
30/* SPI Register Offest */
31#define A3700_SPI_IF_CTRL_REG 0x00
32#define A3700_SPI_IF_CFG_REG 0x04
33#define A3700_SPI_DATA_OUT_REG 0x08
34#define A3700_SPI_DATA_IN_REG 0x0C
35#define A3700_SPI_IF_INST_REG 0x10
36#define A3700_SPI_IF_ADDR_REG 0x14
37#define A3700_SPI_IF_RMODE_REG 0x18
38#define A3700_SPI_IF_HDR_CNT_REG 0x1C
39#define A3700_SPI_IF_DIN_CNT_REG 0x20
40#define A3700_SPI_IF_TIME_REG 0x24
41#define A3700_SPI_INT_STAT_REG 0x28
42#define A3700_SPI_INT_MASK_REG 0x2C
43
44/* A3700_SPI_IF_CTRL_REG */
45#define A3700_SPI_EN BIT(16)
46#define A3700_SPI_ADDR_NOT_CONFIG BIT(12)
47#define A3700_SPI_WFIFO_OVERFLOW BIT(11)
48#define A3700_SPI_WFIFO_UNDERFLOW BIT(10)
49#define A3700_SPI_RFIFO_OVERFLOW BIT(9)
50#define A3700_SPI_RFIFO_UNDERFLOW BIT(8)
51#define A3700_SPI_WFIFO_FULL BIT(7)
52#define A3700_SPI_WFIFO_EMPTY BIT(6)
53#define A3700_SPI_RFIFO_FULL BIT(5)
54#define A3700_SPI_RFIFO_EMPTY BIT(4)
55#define A3700_SPI_WFIFO_RDY BIT(3)
56#define A3700_SPI_RFIFO_RDY BIT(2)
57#define A3700_SPI_XFER_RDY BIT(1)
58#define A3700_SPI_XFER_DONE BIT(0)
59
60/* A3700_SPI_IF_CFG_REG */
61#define A3700_SPI_WFIFO_THRS BIT(28)
62#define A3700_SPI_RFIFO_THRS BIT(24)
63#define A3700_SPI_AUTO_CS BIT(20)
64#define A3700_SPI_DMA_RD_EN BIT(18)
65#define A3700_SPI_FIFO_MODE BIT(17)
66#define A3700_SPI_SRST BIT(16)
67#define A3700_SPI_XFER_START BIT(15)
68#define A3700_SPI_XFER_STOP BIT(14)
69#define A3700_SPI_INST_PIN BIT(13)
70#define A3700_SPI_ADDR_PIN BIT(12)
71#define A3700_SPI_DATA_PIN1 BIT(11)
72#define A3700_SPI_DATA_PIN0 BIT(10)
73#define A3700_SPI_FIFO_FLUSH BIT(9)
74#define A3700_SPI_RW_EN BIT(8)
75#define A3700_SPI_CLK_POL BIT(7)
76#define A3700_SPI_CLK_PHA BIT(6)
77#define A3700_SPI_BYTE_LEN BIT(5)
78#define A3700_SPI_CLK_PRESCALE BIT(0)
79#define A3700_SPI_CLK_PRESCALE_MASK (0x1f)
80#define A3700_SPI_CLK_EVEN_OFFS (0x10)
81
82#define A3700_SPI_WFIFO_THRS_BIT 28
83#define A3700_SPI_RFIFO_THRS_BIT 24
84#define A3700_SPI_FIFO_THRS_MASK 0x7
85
86#define A3700_SPI_DATA_PIN_MASK 0x3
87
88/* A3700_SPI_IF_HDR_CNT_REG */
89#define A3700_SPI_DUMMY_CNT_BIT 12
90#define A3700_SPI_DUMMY_CNT_MASK 0x7
91#define A3700_SPI_RMODE_CNT_BIT 8
92#define A3700_SPI_RMODE_CNT_MASK 0x3
93#define A3700_SPI_ADDR_CNT_BIT 4
94#define A3700_SPI_ADDR_CNT_MASK 0x7
95#define A3700_SPI_INSTR_CNT_BIT 0
96#define A3700_SPI_INSTR_CNT_MASK 0x3
97
98/* A3700_SPI_IF_TIME_REG */
99#define A3700_SPI_CLK_CAPT_EDGE BIT(7)
100
101struct a3700_spi {
102 struct spi_controller *host;
103 void __iomem *base;
104 struct clk *clk;
105 unsigned int irq;
106 unsigned int flags;
107 bool xmit_data;
108 const u8 *tx_buf;
109 u8 *rx_buf;
110 size_t buf_len;
111 u8 byte_len;
112 u32 wait_mask;
113 struct completion done;
114};
115
116static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
117{
118 return readl(a3700_spi->base + offset);
119}
120
121static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
122{
123 writel(data, a3700_spi->base + offset);
124}
125
126static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
127{
128 u32 val;
129
130 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
131 val &= ~A3700_SPI_AUTO_CS;
132 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
133}
134
135static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
136{
137 u32 val;
138
139 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
140 val |= (A3700_SPI_EN << cs);
141 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
142}
143
144static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
145 unsigned int cs)
146{
147 u32 val;
148
149 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
150 val &= ~(A3700_SPI_EN << cs);
151 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
152}
153
154static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
155 unsigned int pin_mode, bool receiving)
156{
157 u32 val;
158
159 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
160 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
161 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
162
163 switch (pin_mode) {
164 case SPI_NBITS_SINGLE:
165 break;
166 case SPI_NBITS_DUAL:
167 val |= A3700_SPI_DATA_PIN0;
168 break;
169 case SPI_NBITS_QUAD:
170 val |= A3700_SPI_DATA_PIN1;
171 /* RX during address reception uses 4-pin */
172 if (receiving)
173 val |= A3700_SPI_ADDR_PIN;
174 break;
175 default:
176 dev_err(&a3700_spi->host->dev, "wrong pin mode %u", pin_mode);
177 return -EINVAL;
178 }
179
180 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
181
182 return 0;
183}
184
185static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable)
186{
187 u32 val;
188
189 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
190 if (enable)
191 val |= A3700_SPI_FIFO_MODE;
192 else
193 val &= ~A3700_SPI_FIFO_MODE;
194 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
195}
196
197static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
198 unsigned int mode_bits)
199{
200 u32 val;
201
202 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
203
204 if (mode_bits & SPI_CPOL)
205 val |= A3700_SPI_CLK_POL;
206 else
207 val &= ~A3700_SPI_CLK_POL;
208
209 if (mode_bits & SPI_CPHA)
210 val |= A3700_SPI_CLK_PHA;
211 else
212 val &= ~A3700_SPI_CLK_PHA;
213
214 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
215}
216
217static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
218 unsigned int speed_hz)
219{
220 u32 val;
221 u32 prescale;
222
223 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
224
225 /* For prescaler values over 15, we can only set it by steps of 2.
226 * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to
227 * 30. We only use this range from 16 to 30.
228 */
229 if (prescale > 15)
230 prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2);
231
232 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
233 val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
234
235 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
236 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
237
238 if (prescale <= 2) {
239 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
240 val |= A3700_SPI_CLK_CAPT_EDGE;
241 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
242 }
243}
244
245static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
246{
247 u32 val;
248
249 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
250 if (len == 4)
251 val |= A3700_SPI_BYTE_LEN;
252 else
253 val &= ~A3700_SPI_BYTE_LEN;
254 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
255
256 a3700_spi->byte_len = len;
257}
258
259static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
260{
261 int timeout = A3700_SPI_TIMEOUT;
262 u32 val;
263
264 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
265 val |= A3700_SPI_FIFO_FLUSH;
266 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
267
268 while (--timeout) {
269 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
270 if (!(val & A3700_SPI_FIFO_FLUSH))
271 return 0;
272 udelay(1);
273 }
274
275 return -ETIMEDOUT;
276}
277
278static void a3700_spi_init(struct a3700_spi *a3700_spi)
279{
280 struct spi_controller *host = a3700_spi->host;
281 u32 val;
282 int i;
283
284 /* Reset SPI unit */
285 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
286 val |= A3700_SPI_SRST;
287 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
288
289 udelay(A3700_SPI_TIMEOUT);
290
291 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
292 val &= ~A3700_SPI_SRST;
293 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
294
295 /* Disable AUTO_CS and deactivate all chip-selects */
296 a3700_spi_auto_cs_unset(a3700_spi);
297 for (i = 0; i < host->num_chipselect; i++)
298 a3700_spi_deactivate_cs(a3700_spi, i);
299
300 /* Enable FIFO mode */
301 a3700_spi_fifo_mode_set(a3700_spi, true);
302
303 /* Set SPI mode */
304 a3700_spi_mode_set(a3700_spi, host->mode_bits);
305
306 /* Reset counters */
307 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
308 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
309
310 /* Mask the interrupts and clear cause bits */
311 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
312 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
313}
314
315static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
316{
317 struct spi_controller *host = dev_id;
318 struct a3700_spi *a3700_spi;
319 u32 cause;
320
321 a3700_spi = spi_controller_get_devdata(host);
322
323 /* Get interrupt causes */
324 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
325
326 if (!cause || !(a3700_spi->wait_mask & cause))
327 return IRQ_NONE;
328
329 /* mask and acknowledge the SPI interrupts */
330 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
331 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
332
333 /* Wake up the transfer */
334 complete(&a3700_spi->done);
335
336 return IRQ_HANDLED;
337}
338
339static bool a3700_spi_wait_completion(struct spi_device *spi)
340{
341 struct a3700_spi *a3700_spi;
342 unsigned int timeout;
343 unsigned int ctrl_reg;
344 unsigned long timeout_jiffies;
345
346 a3700_spi = spi_controller_get_devdata(spi->controller);
347
348 /* SPI interrupt is edge-triggered, which means an interrupt will
349 * be generated only when detecting a specific status bit changed
350 * from '0' to '1'. So when we start waiting for a interrupt, we
351 * need to check status bit in control reg first, if it is already 1,
352 * then we do not need to wait for interrupt
353 */
354 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
355 if (a3700_spi->wait_mask & ctrl_reg)
356 return true;
357
358 reinit_completion(&a3700_spi->done);
359
360 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
361 a3700_spi->wait_mask);
362
363 timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT);
364 timeout = wait_for_completion_timeout(&a3700_spi->done,
365 timeout_jiffies);
366
367 a3700_spi->wait_mask = 0;
368
369 if (timeout)
370 return true;
371
372 /* there might be the case that right after we checked the
373 * status bits in this routine and before start to wait for
374 * interrupt by wait_for_completion_timeout, the interrupt
375 * happens, to avoid missing it we need to double check
376 * status bits in control reg, if it is already 1, then
377 * consider that we have the interrupt successfully and
378 * return true.
379 */
380 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
381 if (a3700_spi->wait_mask & ctrl_reg)
382 return true;
383
384 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
385
386 /* Timeout was reached */
387 return false;
388}
389
390static bool a3700_spi_transfer_wait(struct spi_device *spi,
391 unsigned int bit_mask)
392{
393 struct a3700_spi *a3700_spi;
394
395 a3700_spi = spi_controller_get_devdata(spi->controller);
396 a3700_spi->wait_mask = bit_mask;
397
398 return a3700_spi_wait_completion(spi);
399}
400
401static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
402 unsigned int bytes)
403{
404 u32 val;
405
406 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
407 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
408 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
409 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
410 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
411 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
412}
413
414static void a3700_spi_transfer_setup(struct spi_device *spi,
415 struct spi_transfer *xfer)
416{
417 struct a3700_spi *a3700_spi;
418
419 a3700_spi = spi_controller_get_devdata(spi->controller);
420
421 a3700_spi_clock_set(a3700_spi, xfer->speed_hz);
422
423 /* Use 4 bytes long transfers. Each transfer method has its way to deal
424 * with the remaining bytes for non 4-bytes aligned transfers.
425 */
426 a3700_spi_bytelen_set(a3700_spi, 4);
427
428 /* Initialize the working buffers */
429 a3700_spi->tx_buf = xfer->tx_buf;
430 a3700_spi->rx_buf = xfer->rx_buf;
431 a3700_spi->buf_len = xfer->len;
432}
433
434static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
435{
436 struct a3700_spi *a3700_spi = spi_controller_get_devdata(spi->controller);
437
438 if (!enable)
439 a3700_spi_activate_cs(a3700_spi, spi_get_chipselect(spi, 0));
440 else
441 a3700_spi_deactivate_cs(a3700_spi, spi_get_chipselect(spi, 0));
442}
443
444static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
445{
446 unsigned int addr_cnt;
447 u32 val = 0;
448
449 /* Clear the header registers */
450 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
451 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
452 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
453 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
454
455 /* Set header counters */
456 if (a3700_spi->tx_buf) {
457 /*
458 * when tx data is not 4 bytes aligned, there will be unexpected
459 * bytes out of SPI output register, since it always shifts out
460 * as whole 4 bytes. This might cause incorrect transaction with
461 * some devices. To avoid that, use SPI header count feature to
462 * transfer up to 3 bytes of data first, and then make the rest
463 * of data 4-byte aligned.
464 */
465 addr_cnt = a3700_spi->buf_len % 4;
466 if (addr_cnt) {
467 val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK)
468 << A3700_SPI_ADDR_CNT_BIT;
469 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
470
471 /* Update the buffer length to be transferred */
472 a3700_spi->buf_len -= addr_cnt;
473
474 /* transfer 1~3 bytes through address count */
475 val = 0;
476 while (addr_cnt--) {
477 val = (val << 8) | a3700_spi->tx_buf[0];
478 a3700_spi->tx_buf++;
479 }
480 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
481 }
482 }
483}
484
485static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
486{
487 u32 val;
488
489 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
490 return (val & A3700_SPI_WFIFO_FULL);
491}
492
493static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
494{
495 u32 val;
496
497 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
498 val = *(u32 *)a3700_spi->tx_buf;
499 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val));
500 a3700_spi->buf_len -= 4;
501 a3700_spi->tx_buf += 4;
502 }
503
504 return 0;
505}
506
507static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
508{
509 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
510
511 return (val & A3700_SPI_RFIFO_EMPTY);
512}
513
514static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
515{
516 u32 val;
517
518 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
519 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
520 if (a3700_spi->buf_len >= 4) {
521 val = le32_to_cpu(val);
522 memcpy(a3700_spi->rx_buf, &val, 4);
523
524 a3700_spi->buf_len -= 4;
525 a3700_spi->rx_buf += 4;
526 } else {
527 /*
528 * When remain bytes is not larger than 4, we should
529 * avoid memory overwriting and just write the left rx
530 * buffer bytes.
531 */
532 while (a3700_spi->buf_len) {
533 *a3700_spi->rx_buf = val & 0xff;
534 val >>= 8;
535
536 a3700_spi->buf_len--;
537 a3700_spi->rx_buf++;
538 }
539 }
540 }
541
542 return 0;
543}
544
545static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
546{
547 int timeout = A3700_SPI_TIMEOUT;
548 u32 val;
549
550 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
551 val |= A3700_SPI_XFER_STOP;
552 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
553
554 while (--timeout) {
555 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
556 if (!(val & A3700_SPI_XFER_START))
557 break;
558 udelay(1);
559 }
560
561 a3700_spi_fifo_flush(a3700_spi);
562
563 val &= ~A3700_SPI_XFER_STOP;
564 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
565}
566
567static int a3700_spi_prepare_message(struct spi_controller *host,
568 struct spi_message *message)
569{
570 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
571 struct spi_device *spi = message->spi;
572 int ret;
573
574 ret = clk_enable(a3700_spi->clk);
575 if (ret) {
576 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret);
577 return ret;
578 }
579
580 /* Flush the FIFOs */
581 ret = a3700_spi_fifo_flush(a3700_spi);
582 if (ret)
583 return ret;
584
585 a3700_spi_mode_set(a3700_spi, spi->mode);
586
587 return 0;
588}
589
590static int a3700_spi_transfer_one_fifo(struct spi_controller *host,
591 struct spi_device *spi,
592 struct spi_transfer *xfer)
593{
594 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
595 int ret = 0, timeout = A3700_SPI_TIMEOUT;
596 unsigned int nbits = 0, byte_len;
597 u32 val;
598
599 /* Make sure we use FIFO mode */
600 a3700_spi_fifo_mode_set(a3700_spi, true);
601
602 /* Configure FIFO thresholds */
603 byte_len = xfer->bits_per_word >> 3;
604 a3700_spi_fifo_thres_set(a3700_spi, byte_len);
605
606 if (xfer->tx_buf)
607 nbits = xfer->tx_nbits;
608 else if (xfer->rx_buf)
609 nbits = xfer->rx_nbits;
610
611 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false);
612
613 /* Flush the FIFOs */
614 a3700_spi_fifo_flush(a3700_spi);
615
616 /* Transfer first bytes of data when buffer is not 4-byte aligned */
617 a3700_spi_header_set(a3700_spi);
618
619 if (xfer->rx_buf) {
620 /* Clear WFIFO, since it's last 2 bytes are shifted out during
621 * a read operation
622 */
623 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
624
625 /* Set read data length */
626 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
627 a3700_spi->buf_len);
628 /* Start READ transfer */
629 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
630 val &= ~A3700_SPI_RW_EN;
631 val |= A3700_SPI_XFER_START;
632 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
633 } else if (xfer->tx_buf) {
634 /* Start Write transfer */
635 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
636 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
637 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
638
639 /*
640 * If there are data to be written to the SPI device, xmit_data
641 * flag is set true; otherwise the instruction in SPI_INSTR does
642 * not require data to be written to the SPI device, then
643 * xmit_data flag is set false.
644 */
645 a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
646 }
647
648 while (a3700_spi->buf_len) {
649 if (a3700_spi->tx_buf) {
650 /* Wait wfifo ready */
651 if (!a3700_spi_transfer_wait(spi,
652 A3700_SPI_WFIFO_RDY)) {
653 dev_err(&spi->dev,
654 "wait wfifo ready timed out\n");
655 ret = -ETIMEDOUT;
656 goto error;
657 }
658 /* Fill up the wfifo */
659 ret = a3700_spi_fifo_write(a3700_spi);
660 if (ret)
661 goto error;
662 } else if (a3700_spi->rx_buf) {
663 /* Wait rfifo ready */
664 if (!a3700_spi_transfer_wait(spi,
665 A3700_SPI_RFIFO_RDY)) {
666 dev_err(&spi->dev,
667 "wait rfifo ready timed out\n");
668 ret = -ETIMEDOUT;
669 goto error;
670 }
671 /* Drain out the rfifo */
672 ret = a3700_spi_fifo_read(a3700_spi);
673 if (ret)
674 goto error;
675 }
676 }
677
678 /*
679 * Stop a write transfer in fifo mode:
680 * - wait all the bytes in wfifo to be shifted out
681 * - set XFER_STOP bit
682 * - wait XFER_START bit clear
683 * - clear XFER_STOP bit
684 * Stop a read transfer in fifo mode:
685 * - the hardware is to reset the XFER_START bit
686 * after the number of bytes indicated in DIN_CNT
687 * register
688 * - just wait XFER_START bit clear
689 */
690 if (a3700_spi->tx_buf) {
691 if (a3700_spi->xmit_data) {
692 /*
693 * If there are data written to the SPI device, wait
694 * until SPI_WFIFO_EMPTY is 1 to wait for all data to
695 * transfer out of write FIFO.
696 */
697 if (!a3700_spi_transfer_wait(spi,
698 A3700_SPI_WFIFO_EMPTY)) {
699 dev_err(&spi->dev, "wait wfifo empty timed out\n");
700 return -ETIMEDOUT;
701 }
702 }
703
704 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
705 dev_err(&spi->dev, "wait xfer ready timed out\n");
706 return -ETIMEDOUT;
707 }
708
709 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
710 val |= A3700_SPI_XFER_STOP;
711 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
712 }
713
714 while (--timeout) {
715 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
716 if (!(val & A3700_SPI_XFER_START))
717 break;
718 udelay(1);
719 }
720
721 if (timeout == 0) {
722 dev_err(&spi->dev, "wait transfer start clear timed out\n");
723 ret = -ETIMEDOUT;
724 goto error;
725 }
726
727 val &= ~A3700_SPI_XFER_STOP;
728 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
729 goto out;
730
731error:
732 a3700_spi_transfer_abort_fifo(a3700_spi);
733out:
734 spi_finalize_current_transfer(host);
735
736 return ret;
737}
738
739static int a3700_spi_transfer_one_full_duplex(struct spi_controller *host,
740 struct spi_device *spi,
741 struct spi_transfer *xfer)
742{
743 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
744 u32 val;
745
746 /* Disable FIFO mode */
747 a3700_spi_fifo_mode_set(a3700_spi, false);
748
749 while (a3700_spi->buf_len) {
750
751 /* When we have less than 4 bytes to transfer, switch to 1 byte
752 * mode. This is reset after each transfer
753 */
754 if (a3700_spi->buf_len < 4)
755 a3700_spi_bytelen_set(a3700_spi, 1);
756
757 if (a3700_spi->byte_len == 1)
758 val = *a3700_spi->tx_buf;
759 else
760 val = *(u32 *)a3700_spi->tx_buf;
761
762 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
763
764 /* Wait for all the data to be shifted in / out */
765 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) &
766 A3700_SPI_XFER_DONE))
767 cpu_relax();
768
769 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
770
771 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);
772
773 a3700_spi->buf_len -= a3700_spi->byte_len;
774 a3700_spi->tx_buf += a3700_spi->byte_len;
775 a3700_spi->rx_buf += a3700_spi->byte_len;
776
777 }
778
779 spi_finalize_current_transfer(host);
780
781 return 0;
782}
783
784static int a3700_spi_transfer_one(struct spi_controller *host,
785 struct spi_device *spi,
786 struct spi_transfer *xfer)
787{
788 a3700_spi_transfer_setup(spi, xfer);
789
790 if (xfer->tx_buf && xfer->rx_buf)
791 return a3700_spi_transfer_one_full_duplex(host, spi, xfer);
792
793 return a3700_spi_transfer_one_fifo(host, spi, xfer);
794}
795
796static int a3700_spi_unprepare_message(struct spi_controller *host,
797 struct spi_message *message)
798{
799 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
800
801 clk_disable(a3700_spi->clk);
802
803 return 0;
804}
805
806static const struct of_device_id a3700_spi_dt_ids[] = {
807 { .compatible = "marvell,armada-3700-spi", .data = NULL },
808 {},
809};
810
811MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids);
812
813static int a3700_spi_probe(struct platform_device *pdev)
814{
815 struct device *dev = &pdev->dev;
816 struct device_node *of_node = dev->of_node;
817 struct spi_controller *host;
818 struct a3700_spi *spi;
819 u32 num_cs = 0;
820 int irq, ret = 0;
821
822 host = spi_alloc_host(dev, sizeof(*spi));
823 if (!host) {
824 dev_err(dev, "host allocation failed\n");
825 ret = -ENOMEM;
826 goto out;
827 }
828
829 if (of_property_read_u32(of_node, "num-cs", &num_cs)) {
830 dev_err(dev, "could not find num-cs\n");
831 ret = -ENXIO;
832 goto error;
833 }
834
835 host->bus_num = pdev->id;
836 host->dev.of_node = of_node;
837 host->mode_bits = SPI_MODE_3;
838 host->num_chipselect = num_cs;
839 host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
840 host->prepare_message = a3700_spi_prepare_message;
841 host->transfer_one = a3700_spi_transfer_one;
842 host->unprepare_message = a3700_spi_unprepare_message;
843 host->set_cs = a3700_spi_set_cs;
844 host->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL |
845 SPI_RX_QUAD | SPI_TX_QUAD);
846
847 platform_set_drvdata(pdev, host);
848
849 spi = spi_controller_get_devdata(host);
850
851 spi->host = host;
852
853 spi->base = devm_platform_ioremap_resource(pdev, 0);
854 if (IS_ERR(spi->base)) {
855 ret = PTR_ERR(spi->base);
856 goto error;
857 }
858
859 irq = platform_get_irq(pdev, 0);
860 if (irq < 0) {
861 ret = -ENXIO;
862 goto error;
863 }
864 spi->irq = irq;
865
866 init_completion(&spi->done);
867
868 spi->clk = devm_clk_get_prepared(dev, NULL);
869 if (IS_ERR(spi->clk)) {
870 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk));
871 goto error;
872 }
873
874 host->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ,
875 clk_get_rate(spi->clk));
876 host->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk),
877 A3700_SPI_MAX_PRESCALE);
878
879 a3700_spi_init(spi);
880
881 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0,
882 dev_name(dev), host);
883 if (ret) {
884 dev_err(dev, "could not request IRQ: %d\n", ret);
885 goto error;
886 }
887
888 ret = devm_spi_register_controller(dev, host);
889 if (ret) {
890 dev_err(dev, "Failed to register host\n");
891 goto error;
892 }
893
894 return 0;
895
896error:
897 spi_controller_put(host);
898out:
899 return ret;
900}
901
902static struct platform_driver a3700_spi_driver = {
903 .driver = {
904 .name = DRIVER_NAME,
905 .of_match_table = of_match_ptr(a3700_spi_dt_ids),
906 },
907 .probe = a3700_spi_probe,
908};
909
910module_platform_driver(a3700_spi_driver);
911
912MODULE_DESCRIPTION("Armada-3700 SPI driver");
913MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
914MODULE_LICENSE("GPL");
915MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Marvell Armada-3700 SPI controller driver
3 *
4 * Copyright (C) 2016 Marvell Ltd.
5 *
6 * Author: Wilson Ding <dingwei@marvell.com>
7 * Author: Romain Perier <romain.perier@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/clk.h>
15#include <linux/completion.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_device.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/spi/spi.h>
27
28#define DRIVER_NAME "armada_3700_spi"
29
30#define A3700_SPI_MAX_SPEED_HZ 100000000
31#define A3700_SPI_MAX_PRESCALE 30
32#define A3700_SPI_TIMEOUT 10
33
34/* SPI Register Offest */
35#define A3700_SPI_IF_CTRL_REG 0x00
36#define A3700_SPI_IF_CFG_REG 0x04
37#define A3700_SPI_DATA_OUT_REG 0x08
38#define A3700_SPI_DATA_IN_REG 0x0C
39#define A3700_SPI_IF_INST_REG 0x10
40#define A3700_SPI_IF_ADDR_REG 0x14
41#define A3700_SPI_IF_RMODE_REG 0x18
42#define A3700_SPI_IF_HDR_CNT_REG 0x1C
43#define A3700_SPI_IF_DIN_CNT_REG 0x20
44#define A3700_SPI_IF_TIME_REG 0x24
45#define A3700_SPI_INT_STAT_REG 0x28
46#define A3700_SPI_INT_MASK_REG 0x2C
47
48/* A3700_SPI_IF_CTRL_REG */
49#define A3700_SPI_EN BIT(16)
50#define A3700_SPI_ADDR_NOT_CONFIG BIT(12)
51#define A3700_SPI_WFIFO_OVERFLOW BIT(11)
52#define A3700_SPI_WFIFO_UNDERFLOW BIT(10)
53#define A3700_SPI_RFIFO_OVERFLOW BIT(9)
54#define A3700_SPI_RFIFO_UNDERFLOW BIT(8)
55#define A3700_SPI_WFIFO_FULL BIT(7)
56#define A3700_SPI_WFIFO_EMPTY BIT(6)
57#define A3700_SPI_RFIFO_FULL BIT(5)
58#define A3700_SPI_RFIFO_EMPTY BIT(4)
59#define A3700_SPI_WFIFO_RDY BIT(3)
60#define A3700_SPI_RFIFO_RDY BIT(2)
61#define A3700_SPI_XFER_RDY BIT(1)
62#define A3700_SPI_XFER_DONE BIT(0)
63
64/* A3700_SPI_IF_CFG_REG */
65#define A3700_SPI_WFIFO_THRS BIT(28)
66#define A3700_SPI_RFIFO_THRS BIT(24)
67#define A3700_SPI_AUTO_CS BIT(20)
68#define A3700_SPI_DMA_RD_EN BIT(18)
69#define A3700_SPI_FIFO_MODE BIT(17)
70#define A3700_SPI_SRST BIT(16)
71#define A3700_SPI_XFER_START BIT(15)
72#define A3700_SPI_XFER_STOP BIT(14)
73#define A3700_SPI_INST_PIN BIT(13)
74#define A3700_SPI_ADDR_PIN BIT(12)
75#define A3700_SPI_DATA_PIN1 BIT(11)
76#define A3700_SPI_DATA_PIN0 BIT(10)
77#define A3700_SPI_FIFO_FLUSH BIT(9)
78#define A3700_SPI_RW_EN BIT(8)
79#define A3700_SPI_CLK_POL BIT(7)
80#define A3700_SPI_CLK_PHA BIT(6)
81#define A3700_SPI_BYTE_LEN BIT(5)
82#define A3700_SPI_CLK_PRESCALE BIT(0)
83#define A3700_SPI_CLK_PRESCALE_MASK (0x1f)
84#define A3700_SPI_CLK_EVEN_OFFS (0x10)
85
86#define A3700_SPI_WFIFO_THRS_BIT 28
87#define A3700_SPI_RFIFO_THRS_BIT 24
88#define A3700_SPI_FIFO_THRS_MASK 0x7
89
90#define A3700_SPI_DATA_PIN_MASK 0x3
91
92/* A3700_SPI_IF_HDR_CNT_REG */
93#define A3700_SPI_DUMMY_CNT_BIT 12
94#define A3700_SPI_DUMMY_CNT_MASK 0x7
95#define A3700_SPI_RMODE_CNT_BIT 8
96#define A3700_SPI_RMODE_CNT_MASK 0x3
97#define A3700_SPI_ADDR_CNT_BIT 4
98#define A3700_SPI_ADDR_CNT_MASK 0x7
99#define A3700_SPI_INSTR_CNT_BIT 0
100#define A3700_SPI_INSTR_CNT_MASK 0x3
101
102/* A3700_SPI_IF_TIME_REG */
103#define A3700_SPI_CLK_CAPT_EDGE BIT(7)
104
105struct a3700_spi {
106 struct spi_master *master;
107 void __iomem *base;
108 struct clk *clk;
109 unsigned int irq;
110 unsigned int flags;
111 bool xmit_data;
112 const u8 *tx_buf;
113 u8 *rx_buf;
114 size_t buf_len;
115 u8 byte_len;
116 u32 wait_mask;
117 struct completion done;
118};
119
120static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
121{
122 return readl(a3700_spi->base + offset);
123}
124
125static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
126{
127 writel(data, a3700_spi->base + offset);
128}
129
130static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
131{
132 u32 val;
133
134 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
135 val &= ~A3700_SPI_AUTO_CS;
136 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
137}
138
139static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
140{
141 u32 val;
142
143 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
144 val |= (A3700_SPI_EN << cs);
145 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
146}
147
148static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
149 unsigned int cs)
150{
151 u32 val;
152
153 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
154 val &= ~(A3700_SPI_EN << cs);
155 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
156}
157
158static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
159 unsigned int pin_mode, bool receiving)
160{
161 u32 val;
162
163 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
164 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
165 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
166
167 switch (pin_mode) {
168 case SPI_NBITS_SINGLE:
169 break;
170 case SPI_NBITS_DUAL:
171 val |= A3700_SPI_DATA_PIN0;
172 break;
173 case SPI_NBITS_QUAD:
174 val |= A3700_SPI_DATA_PIN1;
175 /* RX during address reception uses 4-pin */
176 if (receiving)
177 val |= A3700_SPI_ADDR_PIN;
178 break;
179 default:
180 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode);
181 return -EINVAL;
182 }
183
184 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
185
186 return 0;
187}
188
189static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable)
190{
191 u32 val;
192
193 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
194 if (enable)
195 val |= A3700_SPI_FIFO_MODE;
196 else
197 val &= ~A3700_SPI_FIFO_MODE;
198 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
199}
200
201static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
202 unsigned int mode_bits)
203{
204 u32 val;
205
206 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
207
208 if (mode_bits & SPI_CPOL)
209 val |= A3700_SPI_CLK_POL;
210 else
211 val &= ~A3700_SPI_CLK_POL;
212
213 if (mode_bits & SPI_CPHA)
214 val |= A3700_SPI_CLK_PHA;
215 else
216 val &= ~A3700_SPI_CLK_PHA;
217
218 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
219}
220
221static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
222 unsigned int speed_hz)
223{
224 u32 val;
225 u32 prescale;
226
227 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
228
229 /* For prescaler values over 15, we can only set it by steps of 2.
230 * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to
231 * 30. We only use this range from 16 to 30.
232 */
233 if (prescale > 15)
234 prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2);
235
236 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
237 val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
238
239 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
240 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
241
242 if (prescale <= 2) {
243 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
244 val |= A3700_SPI_CLK_CAPT_EDGE;
245 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
246 }
247}
248
249static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
250{
251 u32 val;
252
253 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
254 if (len == 4)
255 val |= A3700_SPI_BYTE_LEN;
256 else
257 val &= ~A3700_SPI_BYTE_LEN;
258 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
259
260 a3700_spi->byte_len = len;
261}
262
263static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
264{
265 int timeout = A3700_SPI_TIMEOUT;
266 u32 val;
267
268 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
269 val |= A3700_SPI_FIFO_FLUSH;
270 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
271
272 while (--timeout) {
273 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
274 if (!(val & A3700_SPI_FIFO_FLUSH))
275 return 0;
276 udelay(1);
277 }
278
279 return -ETIMEDOUT;
280}
281
282static int a3700_spi_init(struct a3700_spi *a3700_spi)
283{
284 struct spi_master *master = a3700_spi->master;
285 u32 val;
286 int i, ret = 0;
287
288 /* Reset SPI unit */
289 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
290 val |= A3700_SPI_SRST;
291 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
292
293 udelay(A3700_SPI_TIMEOUT);
294
295 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
296 val &= ~A3700_SPI_SRST;
297 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
298
299 /* Disable AUTO_CS and deactivate all chip-selects */
300 a3700_spi_auto_cs_unset(a3700_spi);
301 for (i = 0; i < master->num_chipselect; i++)
302 a3700_spi_deactivate_cs(a3700_spi, i);
303
304 /* Enable FIFO mode */
305 a3700_spi_fifo_mode_set(a3700_spi, true);
306
307 /* Set SPI mode */
308 a3700_spi_mode_set(a3700_spi, master->mode_bits);
309
310 /* Reset counters */
311 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
312 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
313
314 /* Mask the interrupts and clear cause bits */
315 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
316 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
317
318 return ret;
319}
320
321static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
322{
323 struct spi_master *master = dev_id;
324 struct a3700_spi *a3700_spi;
325 u32 cause;
326
327 a3700_spi = spi_master_get_devdata(master);
328
329 /* Get interrupt causes */
330 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
331
332 if (!cause || !(a3700_spi->wait_mask & cause))
333 return IRQ_NONE;
334
335 /* mask and acknowledge the SPI interrupts */
336 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
337 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
338
339 /* Wake up the transfer */
340 complete(&a3700_spi->done);
341
342 return IRQ_HANDLED;
343}
344
345static bool a3700_spi_wait_completion(struct spi_device *spi)
346{
347 struct a3700_spi *a3700_spi;
348 unsigned int timeout;
349 unsigned int ctrl_reg;
350 unsigned long timeout_jiffies;
351
352 a3700_spi = spi_master_get_devdata(spi->master);
353
354 /* SPI interrupt is edge-triggered, which means an interrupt will
355 * be generated only when detecting a specific status bit changed
356 * from '0' to '1'. So when we start waiting for a interrupt, we
357 * need to check status bit in control reg first, if it is already 1,
358 * then we do not need to wait for interrupt
359 */
360 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
361 if (a3700_spi->wait_mask & ctrl_reg)
362 return true;
363
364 reinit_completion(&a3700_spi->done);
365
366 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
367 a3700_spi->wait_mask);
368
369 timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT);
370 timeout = wait_for_completion_timeout(&a3700_spi->done,
371 timeout_jiffies);
372
373 a3700_spi->wait_mask = 0;
374
375 if (timeout)
376 return true;
377
378 /* there might be the case that right after we checked the
379 * status bits in this routine and before start to wait for
380 * interrupt by wait_for_completion_timeout, the interrupt
381 * happens, to avoid missing it we need to double check
382 * status bits in control reg, if it is already 1, then
383 * consider that we have the interrupt successfully and
384 * return true.
385 */
386 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
387 if (a3700_spi->wait_mask & ctrl_reg)
388 return true;
389
390 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
391
392 /* Timeout was reached */
393 return false;
394}
395
396static bool a3700_spi_transfer_wait(struct spi_device *spi,
397 unsigned int bit_mask)
398{
399 struct a3700_spi *a3700_spi;
400
401 a3700_spi = spi_master_get_devdata(spi->master);
402 a3700_spi->wait_mask = bit_mask;
403
404 return a3700_spi_wait_completion(spi);
405}
406
407static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
408 unsigned int bytes)
409{
410 u32 val;
411
412 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
413 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
414 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
415 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
416 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
417 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
418}
419
420static void a3700_spi_transfer_setup(struct spi_device *spi,
421 struct spi_transfer *xfer)
422{
423 struct a3700_spi *a3700_spi;
424
425 a3700_spi = spi_master_get_devdata(spi->master);
426
427 a3700_spi_clock_set(a3700_spi, xfer->speed_hz);
428
429 /* Use 4 bytes long transfers. Each transfer method has its way to deal
430 * with the remaining bytes for non 4-bytes aligned transfers.
431 */
432 a3700_spi_bytelen_set(a3700_spi, 4);
433
434 /* Initialize the working buffers */
435 a3700_spi->tx_buf = xfer->tx_buf;
436 a3700_spi->rx_buf = xfer->rx_buf;
437 a3700_spi->buf_len = xfer->len;
438}
439
440static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
441{
442 struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master);
443
444 if (!enable)
445 a3700_spi_activate_cs(a3700_spi, spi->chip_select);
446 else
447 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
448}
449
450static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
451{
452 unsigned int addr_cnt;
453 u32 val = 0;
454
455 /* Clear the header registers */
456 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
457 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
458 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
459 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
460
461 /* Set header counters */
462 if (a3700_spi->tx_buf) {
463 /*
464 * when tx data is not 4 bytes aligned, there will be unexpected
465 * bytes out of SPI output register, since it always shifts out
466 * as whole 4 bytes. This might cause incorrect transaction with
467 * some devices. To avoid that, use SPI header count feature to
468 * transfer up to 3 bytes of data first, and then make the rest
469 * of data 4-byte aligned.
470 */
471 addr_cnt = a3700_spi->buf_len % 4;
472 if (addr_cnt) {
473 val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK)
474 << A3700_SPI_ADDR_CNT_BIT;
475 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
476
477 /* Update the buffer length to be transferred */
478 a3700_spi->buf_len -= addr_cnt;
479
480 /* transfer 1~3 bytes through address count */
481 val = 0;
482 while (addr_cnt--) {
483 val = (val << 8) | a3700_spi->tx_buf[0];
484 a3700_spi->tx_buf++;
485 }
486 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
487 }
488 }
489}
490
491static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
492{
493 u32 val;
494
495 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
496 return (val & A3700_SPI_WFIFO_FULL);
497}
498
499static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
500{
501 u32 val;
502
503 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
504 val = *(u32 *)a3700_spi->tx_buf;
505 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
506 a3700_spi->buf_len -= 4;
507 a3700_spi->tx_buf += 4;
508 }
509
510 return 0;
511}
512
513static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
514{
515 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
516
517 return (val & A3700_SPI_RFIFO_EMPTY);
518}
519
520static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
521{
522 u32 val;
523
524 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
525 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
526 if (a3700_spi->buf_len >= 4) {
527
528 memcpy(a3700_spi->rx_buf, &val, 4);
529
530 a3700_spi->buf_len -= 4;
531 a3700_spi->rx_buf += 4;
532 } else {
533 /*
534 * When remain bytes is not larger than 4, we should
535 * avoid memory overwriting and just write the left rx
536 * buffer bytes.
537 */
538 while (a3700_spi->buf_len) {
539 *a3700_spi->rx_buf = val & 0xff;
540 val >>= 8;
541
542 a3700_spi->buf_len--;
543 a3700_spi->rx_buf++;
544 }
545 }
546 }
547
548 return 0;
549}
550
551static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
552{
553 int timeout = A3700_SPI_TIMEOUT;
554 u32 val;
555
556 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
557 val |= A3700_SPI_XFER_STOP;
558 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
559
560 while (--timeout) {
561 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
562 if (!(val & A3700_SPI_XFER_START))
563 break;
564 udelay(1);
565 }
566
567 a3700_spi_fifo_flush(a3700_spi);
568
569 val &= ~A3700_SPI_XFER_STOP;
570 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
571}
572
573static int a3700_spi_prepare_message(struct spi_master *master,
574 struct spi_message *message)
575{
576 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
577 struct spi_device *spi = message->spi;
578 int ret;
579
580 ret = clk_enable(a3700_spi->clk);
581 if (ret) {
582 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret);
583 return ret;
584 }
585
586 /* Flush the FIFOs */
587 ret = a3700_spi_fifo_flush(a3700_spi);
588 if (ret)
589 return ret;
590
591 a3700_spi_mode_set(a3700_spi, spi->mode);
592
593 return 0;
594}
595
596static int a3700_spi_transfer_one_fifo(struct spi_master *master,
597 struct spi_device *spi,
598 struct spi_transfer *xfer)
599{
600 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
601 int ret = 0, timeout = A3700_SPI_TIMEOUT;
602 unsigned int nbits = 0, byte_len;
603 u32 val;
604
605 /* Make sure we use FIFO mode */
606 a3700_spi_fifo_mode_set(a3700_spi, true);
607
608 /* Configure FIFO thresholds */
609 byte_len = xfer->bits_per_word >> 3;
610 a3700_spi_fifo_thres_set(a3700_spi, byte_len);
611
612 if (xfer->tx_buf)
613 nbits = xfer->tx_nbits;
614 else if (xfer->rx_buf)
615 nbits = xfer->rx_nbits;
616
617 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false);
618
619 /* Flush the FIFOs */
620 a3700_spi_fifo_flush(a3700_spi);
621
622 /* Transfer first bytes of data when buffer is not 4-byte aligned */
623 a3700_spi_header_set(a3700_spi);
624
625 if (xfer->rx_buf) {
626 /* Clear WFIFO, since it's last 2 bytes are shifted out during
627 * a read operation
628 */
629 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
630
631 /* Set read data length */
632 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
633 a3700_spi->buf_len);
634 /* Start READ transfer */
635 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
636 val &= ~A3700_SPI_RW_EN;
637 val |= A3700_SPI_XFER_START;
638 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
639 } else if (xfer->tx_buf) {
640 /* Start Write transfer */
641 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
642 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
643 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
644
645 /*
646 * If there are data to be written to the SPI device, xmit_data
647 * flag is set true; otherwise the instruction in SPI_INSTR does
648 * not require data to be written to the SPI device, then
649 * xmit_data flag is set false.
650 */
651 a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
652 }
653
654 while (a3700_spi->buf_len) {
655 if (a3700_spi->tx_buf) {
656 /* Wait wfifo ready */
657 if (!a3700_spi_transfer_wait(spi,
658 A3700_SPI_WFIFO_RDY)) {
659 dev_err(&spi->dev,
660 "wait wfifo ready timed out\n");
661 ret = -ETIMEDOUT;
662 goto error;
663 }
664 /* Fill up the wfifo */
665 ret = a3700_spi_fifo_write(a3700_spi);
666 if (ret)
667 goto error;
668 } else if (a3700_spi->rx_buf) {
669 /* Wait rfifo ready */
670 if (!a3700_spi_transfer_wait(spi,
671 A3700_SPI_RFIFO_RDY)) {
672 dev_err(&spi->dev,
673 "wait rfifo ready timed out\n");
674 ret = -ETIMEDOUT;
675 goto error;
676 }
677 /* Drain out the rfifo */
678 ret = a3700_spi_fifo_read(a3700_spi);
679 if (ret)
680 goto error;
681 }
682 }
683
684 /*
685 * Stop a write transfer in fifo mode:
686 * - wait all the bytes in wfifo to be shifted out
687 * - set XFER_STOP bit
688 * - wait XFER_START bit clear
689 * - clear XFER_STOP bit
690 * Stop a read transfer in fifo mode:
691 * - the hardware is to reset the XFER_START bit
692 * after the number of bytes indicated in DIN_CNT
693 * register
694 * - just wait XFER_START bit clear
695 */
696 if (a3700_spi->tx_buf) {
697 if (a3700_spi->xmit_data) {
698 /*
699 * If there are data written to the SPI device, wait
700 * until SPI_WFIFO_EMPTY is 1 to wait for all data to
701 * transfer out of write FIFO.
702 */
703 if (!a3700_spi_transfer_wait(spi,
704 A3700_SPI_WFIFO_EMPTY)) {
705 dev_err(&spi->dev, "wait wfifo empty timed out\n");
706 return -ETIMEDOUT;
707 }
708 }
709
710 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
711 dev_err(&spi->dev, "wait xfer ready timed out\n");
712 return -ETIMEDOUT;
713 }
714
715 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
716 val |= A3700_SPI_XFER_STOP;
717 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
718 }
719
720 while (--timeout) {
721 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
722 if (!(val & A3700_SPI_XFER_START))
723 break;
724 udelay(1);
725 }
726
727 if (timeout == 0) {
728 dev_err(&spi->dev, "wait transfer start clear timed out\n");
729 ret = -ETIMEDOUT;
730 goto error;
731 }
732
733 val &= ~A3700_SPI_XFER_STOP;
734 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
735 goto out;
736
737error:
738 a3700_spi_transfer_abort_fifo(a3700_spi);
739out:
740 spi_finalize_current_transfer(master);
741
742 return ret;
743}
744
745static int a3700_spi_transfer_one_full_duplex(struct spi_master *master,
746 struct spi_device *spi,
747 struct spi_transfer *xfer)
748{
749 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
750 u32 val;
751
752 /* Disable FIFO mode */
753 a3700_spi_fifo_mode_set(a3700_spi, false);
754
755 while (a3700_spi->buf_len) {
756
757 /* When we have less than 4 bytes to transfer, switch to 1 byte
758 * mode. This is reset after each transfer
759 */
760 if (a3700_spi->buf_len < 4)
761 a3700_spi_bytelen_set(a3700_spi, 1);
762
763 if (a3700_spi->byte_len == 1)
764 val = *a3700_spi->tx_buf;
765 else
766 val = *(u32 *)a3700_spi->tx_buf;
767
768 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
769
770 /* Wait for all the data to be shifted in / out */
771 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) &
772 A3700_SPI_XFER_DONE))
773 cpu_relax();
774
775 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
776
777 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);
778
779 a3700_spi->buf_len -= a3700_spi->byte_len;
780 a3700_spi->tx_buf += a3700_spi->byte_len;
781 a3700_spi->rx_buf += a3700_spi->byte_len;
782
783 }
784
785 spi_finalize_current_transfer(master);
786
787 return 0;
788}
789
790static int a3700_spi_transfer_one(struct spi_master *master,
791 struct spi_device *spi,
792 struct spi_transfer *xfer)
793{
794 a3700_spi_transfer_setup(spi, xfer);
795
796 if (xfer->tx_buf && xfer->rx_buf)
797 return a3700_spi_transfer_one_full_duplex(master, spi, xfer);
798
799 return a3700_spi_transfer_one_fifo(master, spi, xfer);
800}
801
802static int a3700_spi_unprepare_message(struct spi_master *master,
803 struct spi_message *message)
804{
805 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
806
807 clk_disable(a3700_spi->clk);
808
809 return 0;
810}
811
812static const struct of_device_id a3700_spi_dt_ids[] = {
813 { .compatible = "marvell,armada-3700-spi", .data = NULL },
814 {},
815};
816
817MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids);
818
819static int a3700_spi_probe(struct platform_device *pdev)
820{
821 struct device *dev = &pdev->dev;
822 struct device_node *of_node = dev->of_node;
823 struct resource *res;
824 struct spi_master *master;
825 struct a3700_spi *spi;
826 u32 num_cs = 0;
827 int irq, ret = 0;
828
829 master = spi_alloc_master(dev, sizeof(*spi));
830 if (!master) {
831 dev_err(dev, "master allocation failed\n");
832 ret = -ENOMEM;
833 goto out;
834 }
835
836 if (of_property_read_u32(of_node, "num-cs", &num_cs)) {
837 dev_err(dev, "could not find num-cs\n");
838 ret = -ENXIO;
839 goto error;
840 }
841
842 master->bus_num = pdev->id;
843 master->dev.of_node = of_node;
844 master->mode_bits = SPI_MODE_3;
845 master->num_chipselect = num_cs;
846 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
847 master->prepare_message = a3700_spi_prepare_message;
848 master->transfer_one = a3700_spi_transfer_one;
849 master->unprepare_message = a3700_spi_unprepare_message;
850 master->set_cs = a3700_spi_set_cs;
851 master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL |
852 SPI_RX_QUAD | SPI_TX_QUAD);
853
854 platform_set_drvdata(pdev, master);
855
856 spi = spi_master_get_devdata(master);
857 memset(spi, 0, sizeof(struct a3700_spi));
858
859 spi->master = master;
860
861 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
862 spi->base = devm_ioremap_resource(dev, res);
863 if (IS_ERR(spi->base)) {
864 ret = PTR_ERR(spi->base);
865 goto error;
866 }
867
868 irq = platform_get_irq(pdev, 0);
869 if (irq < 0) {
870 dev_err(dev, "could not get irq: %d\n", irq);
871 ret = -ENXIO;
872 goto error;
873 }
874 spi->irq = irq;
875
876 init_completion(&spi->done);
877
878 spi->clk = devm_clk_get(dev, NULL);
879 if (IS_ERR(spi->clk)) {
880 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk));
881 goto error;
882 }
883
884 ret = clk_prepare(spi->clk);
885 if (ret) {
886 dev_err(dev, "could not prepare clk: %d\n", ret);
887 goto error;
888 }
889
890 master->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ,
891 clk_get_rate(spi->clk));
892 master->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk),
893 A3700_SPI_MAX_PRESCALE);
894
895 ret = a3700_spi_init(spi);
896 if (ret)
897 goto error_clk;
898
899 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0,
900 dev_name(dev), master);
901 if (ret) {
902 dev_err(dev, "could not request IRQ: %d\n", ret);
903 goto error_clk;
904 }
905
906 ret = devm_spi_register_master(dev, master);
907 if (ret) {
908 dev_err(dev, "Failed to register master\n");
909 goto error_clk;
910 }
911
912 return 0;
913
914error_clk:
915 clk_disable_unprepare(spi->clk);
916error:
917 spi_master_put(master);
918out:
919 return ret;
920}
921
922static int a3700_spi_remove(struct platform_device *pdev)
923{
924 struct spi_master *master = platform_get_drvdata(pdev);
925 struct a3700_spi *spi = spi_master_get_devdata(master);
926
927 clk_unprepare(spi->clk);
928
929 return 0;
930}
931
932static struct platform_driver a3700_spi_driver = {
933 .driver = {
934 .name = DRIVER_NAME,
935 .of_match_table = of_match_ptr(a3700_spi_dt_ids),
936 },
937 .probe = a3700_spi_probe,
938 .remove = a3700_spi_remove,
939};
940
941module_platform_driver(a3700_spi_driver);
942
943MODULE_DESCRIPTION("Armada-3700 SPI driver");
944MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
945MODULE_LICENSE("GPL");
946MODULE_ALIAS("platform:" DRIVER_NAME);