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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 *
5 *
6 * Name: mpi2.h
7 * Title: MPI Message independent structures and definitions
8 * including System Interface Register Set and
9 * scatter/gather formats.
10 * Creation Date: June 21, 2006
11 *
12 * mpi2.h Version: 02.00.54
13 *
14 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
15 * prefix are for use only on MPI v2.5 products, and must not be used
16 * with MPI v2.0 products. Unless otherwise noted, names beginning with
17 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
18 *
19 * Version History
20 * ---------------
21 *
22 * Date Version Description
23 * -------- -------- ------------------------------------------------------
24 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
25 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
27 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Moved ReplyPostHostIndex register to offset 0x6C of the
29 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
30 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
31 * Added union of request descriptors.
32 * Added union of reply descriptors.
33 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
34 * Added define for MPI2_VERSION_02_00.
35 * Fixed the size of the FunctionDependent5 field in the
36 * MPI2_DEFAULT_REPLY structure.
37 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
38 * Removed the MPI-defined Fault Codes and extended the
39 * product specific codes up to 0xEFFF.
40 * Added a sixth key value for the WriteSequence register
41 * and changed the flush value to 0x0.
42 * Added message function codes for Diagnostic Buffer Post
43 * and Diagnsotic Release.
44 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
45 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
46 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
48 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
49 * Added #defines for marking a reply descriptor as unused.
50 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
51 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
52 * Moved LUN field defines from mpi2_init.h.
53 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
54 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
55 * In all request and reply descriptors, replaced VF_ID
56 * field with MSIxIndex field.
57 * Removed DevHandle field from
58 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
59 * bytes reserved.
60 * Added RAID Accelerator functionality.
61 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
62 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
63 * Added MSI-x index mask and shift for Reply Post Host
64 * Index register.
65 * Added function code for Host Based Discovery Action.
66 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
67 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
68 * Added defines for product-specific range of message
69 * function codes, 0xF0 to 0xFF.
70 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
71 * Added alternative defines for the SGE Direction bit.
72 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
73 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
74 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
75 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
76 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
77 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
80 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
81 * Incorporating additions for MPI v2.5.
82 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
83 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
84 * Added Hard Reset delay timings.
85 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
88 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
89 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
90 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
91 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
92 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
93 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
94 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT
95 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
96 * 11-18-14 02.00.36 Updated copyright information.
97 * Bumped MPI2_HEADER_VERSION_UNIT.
98 * 03-16-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT.
99 * Added Scratchpad registers to
100 * MPI2_SYSTEM_INTERFACE_REGS.
101 * Added MPI2_DIAG_SBR_RELOAD.
102 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
103 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT.
104 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
105 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
106 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
107 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines
108 * to be unique within first 32 characters.
109 * Removed AHCI support.
110 * Removed SOP support.
111 * Bumped MPI2_HEADER_VERSION_UNIT.
112 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT.
113 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT.
114 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT.
115 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT.
116 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT.
117 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT.
118 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT.
119 * 07-22-18 02.00.51 Added SECURE_BOOT define.
120 * Bumped MPI2_HEADER_VERSION_UNIT
121 * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT.
122 * 08-28-18 02.00.53 Bumped MPI2_HEADER_VERSION_UNIT.
123 * Added MPI2_IOCSTATUS_FAILURE
124 * 12-17-18 02.00.54 Bumped MPI2_HEADER_VERSION_UNIT
125 * 06-24-19 02.00.55 Bumped MPI2_HEADER_VERSION_UNIT
126 * 08-01-19 02.00.56 Bumped MPI2_HEADER_VERSION_UNIT
127 * 10-02-19 02.00.57 Bumped MPI2_HEADER_VERSION_UNIT
128 * --------------------------------------------------------------------------
129 */
130
131#ifndef MPI2_H
132#define MPI2_H
133
134/*****************************************************************************
135*
136* MPI Version Definitions
137*
138*****************************************************************************/
139
140#define MPI2_VERSION_MAJOR_MASK (0xFF00)
141#define MPI2_VERSION_MAJOR_SHIFT (8)
142#define MPI2_VERSION_MINOR_MASK (0x00FF)
143#define MPI2_VERSION_MINOR_SHIFT (0)
144
145/*major version for all MPI v2.x */
146#define MPI2_VERSION_MAJOR (0x02)
147
148/*minor version for MPI v2.0 compatible products */
149#define MPI2_VERSION_MINOR (0x00)
150#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
151 MPI2_VERSION_MINOR)
152#define MPI2_VERSION_02_00 (0x0200)
153
154/*minor version for MPI v2.5 compatible products */
155#define MPI25_VERSION_MINOR (0x05)
156#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
157 MPI25_VERSION_MINOR)
158#define MPI2_VERSION_02_05 (0x0205)
159
160/*minor version for MPI v2.6 compatible products */
161#define MPI26_VERSION_MINOR (0x06)
162#define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
163 MPI26_VERSION_MINOR)
164#define MPI2_VERSION_02_06 (0x0206)
165
166
167/* Unit and Dev versioning for this MPI header set */
168#define MPI2_HEADER_VERSION_UNIT (0x39)
169#define MPI2_HEADER_VERSION_DEV (0x00)
170#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
171#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
172#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
173#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
174#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
175 MPI2_HEADER_VERSION_DEV)
176
177/*****************************************************************************
178*
179* IOC State Definitions
180*
181*****************************************************************************/
182
183#define MPI2_IOC_STATE_RESET (0x00000000)
184#define MPI2_IOC_STATE_READY (0x10000000)
185#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
186#define MPI2_IOC_STATE_FAULT (0x40000000)
187#define MPI2_IOC_STATE_COREDUMP (0x50000000)
188
189#define MPI2_IOC_STATE_MASK (0xF0000000)
190#define MPI2_IOC_STATE_SHIFT (28)
191
192/*Fault state range for prodcut specific codes */
193#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
194#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
195
196/*****************************************************************************
197*
198* System Interface Register Definitions
199*
200*****************************************************************************/
201
202typedef struct _MPI2_SYSTEM_INTERFACE_REGS {
203 U32 Doorbell; /*0x00 */
204 U32 WriteSequence; /*0x04 */
205 U32 HostDiagnostic; /*0x08 */
206 U32 Reserved1; /*0x0C */
207 U32 DiagRWData; /*0x10 */
208 U32 DiagRWAddressLow; /*0x14 */
209 U32 DiagRWAddressHigh; /*0x18 */
210 U32 Reserved2[5]; /*0x1C */
211 U32 HostInterruptStatus; /*0x30 */
212 U32 HostInterruptMask; /*0x34 */
213 U32 DCRData; /*0x38 */
214 U32 DCRAddress; /*0x3C */
215 U32 Reserved3[2]; /*0x40 */
216 U32 ReplyFreeHostIndex; /*0x48 */
217 U32 Reserved4[8]; /*0x4C */
218 U32 ReplyPostHostIndex; /*0x6C */
219 U32 Reserved5; /*0x70 */
220 U32 HCBSize; /*0x74 */
221 U32 HCBAddressLow; /*0x78 */
222 U32 HCBAddressHigh; /*0x7C */
223 U32 Reserved6[12]; /*0x80 */
224 U32 Scratchpad[4]; /*0xB0 */
225 U32 RequestDescriptorPostLow; /*0xC0 */
226 U32 RequestDescriptorPostHigh; /*0xC4 */
227 U32 AtomicRequestDescriptorPost;/*0xC8 */
228 U32 Reserved7[13]; /*0xCC */
229} MPI2_SYSTEM_INTERFACE_REGS,
230 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
231 Mpi2SystemInterfaceRegs_t,
232 *pMpi2SystemInterfaceRegs_t;
233
234/*
235 *Defines for working with the Doorbell register.
236 */
237#define MPI2_DOORBELL_OFFSET (0x00000000)
238
239/*IOC --> System values */
240#define MPI2_DOORBELL_USED (0x08000000)
241#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
242#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
243#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
244#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
245
246/*System --> IOC values */
247#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
248#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
249#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
250#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
251
252/*
253 *Defines for the WriteSequence register
254 */
255#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
256#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
257#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
258#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
259#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
260#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
261#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
262#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
263#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
264
265/*
266 *Defines for the HostDiagnostic register
267 */
268#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
269
270#define MPI26_DIAG_SECURE_BOOT (0x80000000)
271
272#define MPI2_DIAG_SBR_RELOAD (0x00002000)
273
274#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
275#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
276#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
277
278/* Defines for V7A/V7R HostDiagnostic Register */
279#define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
280#define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
281#define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
282#define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
283
284#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
285#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
286#define MPI2_DIAG_HCB_MODE (0x00000100)
287#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
288#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
289#define MPI2_DIAG_RESET_HISTORY (0x00000020)
290#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
291#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
292#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
293
294/*
295 *Offsets for DiagRWData and address
296 */
297#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
298#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
299#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
300
301/*
302 *Defines for the HostInterruptStatus register
303 */
304#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
305#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
306#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
307#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
308#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
309#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
310#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
311
312/*
313 *Defines for the HostInterruptMask register
314 */
315#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
316#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
317#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
318#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
319#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
320#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
321
322/*
323 *Offsets for DCRData and address
324 */
325#define MPI2_DCR_DATA_OFFSET (0x00000038)
326#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
327
328/*
329 *Offset for the Reply Free Queue
330 */
331#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
332
333/*
334 *Defines for the Reply Descriptor Post Queue
335 */
336#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
337#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
338#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
339#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
340#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
341
342
343/*
344 *Defines for the HCBSize and address
345 */
346#define MPI2_HCB_SIZE_OFFSET (0x00000074)
347#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
348#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
349
350#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
351#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
352
353/*
354 *Offsets for the Scratchpad registers
355 */
356#define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
357#define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
358#define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
359#define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
360
361/*
362 *Offsets for the Request Descriptor Post Queue
363 */
364#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
365#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
366#define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
367
368/*Hard Reset delay timings */
369#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
370#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
371#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
372
373/*****************************************************************************
374*
375* Message Descriptors
376*
377*****************************************************************************/
378
379/*Request Descriptors */
380
381/*Default Request Descriptor */
382typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
383 U8 RequestFlags; /*0x00 */
384 U8 MSIxIndex; /*0x01 */
385 U16 SMID; /*0x02 */
386 U16 LMID; /*0x04 */
387 U16 DescriptorTypeDependent; /*0x06 */
388} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
389 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
390 Mpi2DefaultRequestDescriptor_t,
391 *pMpi2DefaultRequestDescriptor_t;
392
393/*defines for the RequestFlags field */
394#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
395#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1)
396#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
397#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
398#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
399#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
400#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
401#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
402#define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
403
404#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
405
406/*High Priority Request Descriptor */
407typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
408 U8 RequestFlags; /*0x00 */
409 U8 MSIxIndex; /*0x01 */
410 U16 SMID; /*0x02 */
411 U16 LMID; /*0x04 */
412 U16 Reserved1; /*0x06 */
413} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
414 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
415 Mpi2HighPriorityRequestDescriptor_t,
416 *pMpi2HighPriorityRequestDescriptor_t;
417
418/*SCSI IO Request Descriptor */
419typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
420 U8 RequestFlags; /*0x00 */
421 U8 MSIxIndex; /*0x01 */
422 U16 SMID; /*0x02 */
423 U16 LMID; /*0x04 */
424 U16 DevHandle; /*0x06 */
425} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
426 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
427 Mpi2SCSIIORequestDescriptor_t,
428 *pMpi2SCSIIORequestDescriptor_t;
429
430/*SCSI Target Request Descriptor */
431typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
432 U8 RequestFlags; /*0x00 */
433 U8 MSIxIndex; /*0x01 */
434 U16 SMID; /*0x02 */
435 U16 LMID; /*0x04 */
436 U16 IoIndex; /*0x06 */
437} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
438 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
439 Mpi2SCSITargetRequestDescriptor_t,
440 *pMpi2SCSITargetRequestDescriptor_t;
441
442/*RAID Accelerator Request Descriptor */
443typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
444 U8 RequestFlags; /*0x00 */
445 U8 MSIxIndex; /*0x01 */
446 U16 SMID; /*0x02 */
447 U16 LMID; /*0x04 */
448 U16 Reserved; /*0x06 */
449} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
450 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
451 Mpi2RAIDAcceleratorRequestDescriptor_t,
452 *pMpi2RAIDAcceleratorRequestDescriptor_t;
453
454/*Fast Path SCSI IO Request Descriptor */
455typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
456 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
457 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
458 Mpi25FastPathSCSIIORequestDescriptor_t,
459 *pMpi25FastPathSCSIIORequestDescriptor_t;
460
461/*PCIe Encapsulated Request Descriptor */
462typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
463 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
464 *PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
465 Mpi26PCIeEncapsulatedRequestDescriptor_t,
466 *pMpi26PCIeEncapsulatedRequestDescriptor_t;
467
468/*union of Request Descriptors */
469typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
470 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
471 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
472 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
473 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
474 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
475 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
476 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated;
477 U64 Words;
478} MPI2_REQUEST_DESCRIPTOR_UNION,
479 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
480 Mpi2RequestDescriptorUnion_t,
481 *pMpi2RequestDescriptorUnion_t;
482
483/*Atomic Request Descriptors */
484
485/*
486 * All Atomic Request Descriptors have the same format, so the following
487 * structure is used for all Atomic Request Descriptors:
488 * Atomic Default Request Descriptor
489 * Atomic High Priority Request Descriptor
490 * Atomic SCSI IO Request Descriptor
491 * Atomic SCSI Target Request Descriptor
492 * Atomic RAID Accelerator Request Descriptor
493 * Atomic Fast Path SCSI IO Request Descriptor
494 * Atomic PCIe Encapsulated Request Descriptor
495 */
496
497/*Atomic Request Descriptor */
498typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR {
499 U8 RequestFlags; /* 0x00 */
500 U8 MSIxIndex; /* 0x01 */
501 U16 SMID; /* 0x02 */
502} MPI26_ATOMIC_REQUEST_DESCRIPTOR,
503 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
504 Mpi26AtomicRequestDescriptor_t,
505 *pMpi26AtomicRequestDescriptor_t;
506
507/*for the RequestFlags field, use the same
508 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR
509 */
510
511/*Reply Descriptors */
512
513/*Default Reply Descriptor */
514typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
515 U8 ReplyFlags; /*0x00 */
516 U8 MSIxIndex; /*0x01 */
517 U16 DescriptorTypeDependent1; /*0x02 */
518 U32 DescriptorTypeDependent2; /*0x04 */
519} MPI2_DEFAULT_REPLY_DESCRIPTOR,
520 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
521 Mpi2DefaultReplyDescriptor_t,
522 *pMpi2DefaultReplyDescriptor_t;
523
524/*defines for the ReplyFlags field */
525#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
526#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
527#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
528#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
529#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
530#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
531#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
532#define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
533#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
534
535/*values for marking a reply descriptor as unused */
536#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
537#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
538
539/*Address Reply Descriptor */
540typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
541 U8 ReplyFlags; /*0x00 */
542 U8 MSIxIndex; /*0x01 */
543 U16 SMID; /*0x02 */
544 U32 ReplyFrameAddress; /*0x04 */
545} MPI2_ADDRESS_REPLY_DESCRIPTOR,
546 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
547 Mpi2AddressReplyDescriptor_t,
548 *pMpi2AddressReplyDescriptor_t;
549
550#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
551
552/*SCSI IO Success Reply Descriptor */
553typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
554 U8 ReplyFlags; /*0x00 */
555 U8 MSIxIndex; /*0x01 */
556 U16 SMID; /*0x02 */
557 U16 TaskTag; /*0x04 */
558 U16 Reserved1; /*0x06 */
559} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
560 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
561 Mpi2SCSIIOSuccessReplyDescriptor_t,
562 *pMpi2SCSIIOSuccessReplyDescriptor_t;
563
564/*TargetAssist Success Reply Descriptor */
565typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
566 U8 ReplyFlags; /*0x00 */
567 U8 MSIxIndex; /*0x01 */
568 U16 SMID; /*0x02 */
569 U8 SequenceNumber; /*0x04 */
570 U8 Reserved1; /*0x05 */
571 U16 IoIndex; /*0x06 */
572} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
573 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
574 Mpi2TargetAssistSuccessReplyDescriptor_t,
575 *pMpi2TargetAssistSuccessReplyDescriptor_t;
576
577/*Target Command Buffer Reply Descriptor */
578typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
579 U8 ReplyFlags; /*0x00 */
580 U8 MSIxIndex; /*0x01 */
581 U8 VP_ID; /*0x02 */
582 U8 Flags; /*0x03 */
583 U16 InitiatorDevHandle; /*0x04 */
584 U16 IoIndex; /*0x06 */
585} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
586 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
587 Mpi2TargetCommandBufferReplyDescriptor_t,
588 *pMpi2TargetCommandBufferReplyDescriptor_t;
589
590/*defines for Flags field */
591#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
592
593/*RAID Accelerator Success Reply Descriptor */
594typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
595 U8 ReplyFlags; /*0x00 */
596 U8 MSIxIndex; /*0x01 */
597 U16 SMID; /*0x02 */
598 U32 Reserved; /*0x04 */
599} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
600 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
601 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
602 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
603
604/*Fast Path SCSI IO Success Reply Descriptor */
605typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
606 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
607 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
608 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
609 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
610
611/*PCIe Encapsulated Success Reply Descriptor */
612typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
613 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
614 *PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
615 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t,
616 *pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t;
617
618/*union of Reply Descriptors */
619typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
620 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
621 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
622 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
623 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
624 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
625 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
626 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
627 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR
628 PCIeEncapsulatedSuccess;
629 U64 Words;
630} MPI2_REPLY_DESCRIPTORS_UNION,
631 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
632 Mpi2ReplyDescriptorsUnion_t,
633 *pMpi2ReplyDescriptorsUnion_t;
634
635/*****************************************************************************
636*
637* Message Functions
638*
639*****************************************************************************/
640
641#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
642#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
643#define MPI2_FUNCTION_IOC_INIT (0x02)
644#define MPI2_FUNCTION_IOC_FACTS (0x03)
645#define MPI2_FUNCTION_CONFIG (0x04)
646#define MPI2_FUNCTION_PORT_FACTS (0x05)
647#define MPI2_FUNCTION_PORT_ENABLE (0x06)
648#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
649#define MPI2_FUNCTION_EVENT_ACK (0x08)
650#define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
651#define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
652#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
653#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
654#define MPI2_FUNCTION_FW_UPLOAD (0x12)
655#define MPI2_FUNCTION_RAID_ACTION (0x15)
656#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
657#define MPI2_FUNCTION_TOOLBOX (0x17)
658#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
659#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
660#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
661#define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B)
662#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
663#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
664#define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
665#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
666#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
667#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
668#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
669#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
670#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
671#define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33)
672#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
673#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
674
675/*Doorbell functions */
676#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
677#define MPI2_FUNCTION_HANDSHAKE (0x42)
678
679/*****************************************************************************
680*
681* IOC Status Values
682*
683*****************************************************************************/
684
685/*mask for IOCStatus status value */
686#define MPI2_IOCSTATUS_MASK (0x7FFF)
687
688/****************************************************************************
689* Common IOCStatus values for all replies
690****************************************************************************/
691
692#define MPI2_IOCSTATUS_SUCCESS (0x0000)
693#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
694#define MPI2_IOCSTATUS_BUSY (0x0002)
695#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
696#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
697#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
698#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
699#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
700#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
701#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
702/*MPI v2.6 and later */
703#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
704#define MPI2_IOCSTATUS_FAILURE (0x000F)
705
706/****************************************************************************
707* Config IOCStatus values
708****************************************************************************/
709
710#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
711#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
712#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
713#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
714#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
715#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
716
717/****************************************************************************
718* SCSI IO Reply
719****************************************************************************/
720
721#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
722#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
723#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
724#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
725#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
726#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
727#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
728#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
729#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
730#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
731#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
732#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
733
734/****************************************************************************
735* For use by SCSI Initiator and SCSI Target end-to-end data protection
736****************************************************************************/
737
738#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
739#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
740#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
741
742/****************************************************************************
743* SCSI Target values
744****************************************************************************/
745
746#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
747#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
748#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
749#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
750#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
751#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
752#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
753#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
754#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
755#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
756
757/****************************************************************************
758* Serial Attached SCSI values
759****************************************************************************/
760
761#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
762#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
763
764/****************************************************************************
765* Diagnostic Buffer Post / Diagnostic Release values
766****************************************************************************/
767
768#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
769
770/****************************************************************************
771* RAID Accelerator values
772****************************************************************************/
773
774#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
775
776/****************************************************************************
777* IOCStatus flag to indicate that log info is available
778****************************************************************************/
779
780#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
781
782/****************************************************************************
783* IOCLogInfo Types
784****************************************************************************/
785
786#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
787#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
788#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
789#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
790#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
791#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
792#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
793#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
794
795/*****************************************************************************
796*
797* Standard Message Structures
798*
799*****************************************************************************/
800
801/****************************************************************************
802*Request Message Header for all request messages
803****************************************************************************/
804
805typedef struct _MPI2_REQUEST_HEADER {
806 U16 FunctionDependent1; /*0x00 */
807 U8 ChainOffset; /*0x02 */
808 U8 Function; /*0x03 */
809 U16 FunctionDependent2; /*0x04 */
810 U8 FunctionDependent3; /*0x06 */
811 U8 MsgFlags; /*0x07 */
812 U8 VP_ID; /*0x08 */
813 U8 VF_ID; /*0x09 */
814 U16 Reserved1; /*0x0A */
815} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
816 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
817
818/****************************************************************************
819* Default Reply
820****************************************************************************/
821
822typedef struct _MPI2_DEFAULT_REPLY {
823 U16 FunctionDependent1; /*0x00 */
824 U8 MsgLength; /*0x02 */
825 U8 Function; /*0x03 */
826 U16 FunctionDependent2; /*0x04 */
827 U8 FunctionDependent3; /*0x06 */
828 U8 MsgFlags; /*0x07 */
829 U8 VP_ID; /*0x08 */
830 U8 VF_ID; /*0x09 */
831 U16 Reserved1; /*0x0A */
832 U16 FunctionDependent5; /*0x0C */
833 U16 IOCStatus; /*0x0E */
834 U32 IOCLogInfo; /*0x10 */
835} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
836 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
837
838/*common version structure/union used in messages and configuration pages */
839
840typedef struct _MPI2_VERSION_STRUCT {
841 U8 Dev; /*0x00 */
842 U8 Unit; /*0x01 */
843 U8 Minor; /*0x02 */
844 U8 Major; /*0x03 */
845} MPI2_VERSION_STRUCT;
846
847typedef union _MPI2_VERSION_UNION {
848 MPI2_VERSION_STRUCT Struct;
849 U32 Word;
850} MPI2_VERSION_UNION;
851
852/*LUN field defines, common to many structures */
853#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
854#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
855#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
856#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
857#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
858#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
859
860/*****************************************************************************
861*
862* Fusion-MPT MPI Scatter Gather Elements
863*
864*****************************************************************************/
865
866/****************************************************************************
867* MPI Simple Element structures
868****************************************************************************/
869
870typedef struct _MPI2_SGE_SIMPLE32 {
871 U32 FlagsLength;
872 U32 Address;
873} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
874 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
875
876typedef struct _MPI2_SGE_SIMPLE64 {
877 U32 FlagsLength;
878 U64 Address;
879} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
880 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
881
882typedef struct _MPI2_SGE_SIMPLE_UNION {
883 U32 FlagsLength;
884 union {
885 U32 Address32;
886 U64 Address64;
887 } u;
888} MPI2_SGE_SIMPLE_UNION,
889 *PTR_MPI2_SGE_SIMPLE_UNION,
890 Mpi2SGESimpleUnion_t,
891 *pMpi2SGESimpleUnion_t;
892
893/****************************************************************************
894* MPI Chain Element structures - for MPI v2.0 products only
895****************************************************************************/
896
897typedef struct _MPI2_SGE_CHAIN32 {
898 U16 Length;
899 U8 NextChainOffset;
900 U8 Flags;
901 U32 Address;
902} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
903 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
904
905typedef struct _MPI2_SGE_CHAIN64 {
906 U16 Length;
907 U8 NextChainOffset;
908 U8 Flags;
909 U64 Address;
910} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
911 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
912
913typedef struct _MPI2_SGE_CHAIN_UNION {
914 U16 Length;
915 U8 NextChainOffset;
916 U8 Flags;
917 union {
918 U32 Address32;
919 U64 Address64;
920 } u;
921} MPI2_SGE_CHAIN_UNION,
922 *PTR_MPI2_SGE_CHAIN_UNION,
923 Mpi2SGEChainUnion_t,
924 *pMpi2SGEChainUnion_t;
925
926/****************************************************************************
927* MPI Transaction Context Element structures - for MPI v2.0 products only
928****************************************************************************/
929
930typedef struct _MPI2_SGE_TRANSACTION32 {
931 U8 Reserved;
932 U8 ContextSize;
933 U8 DetailsLength;
934 U8 Flags;
935 U32 TransactionContext[1];
936 U32 TransactionDetails[1];
937} MPI2_SGE_TRANSACTION32,
938 *PTR_MPI2_SGE_TRANSACTION32,
939 Mpi2SGETransaction32_t,
940 *pMpi2SGETransaction32_t;
941
942typedef struct _MPI2_SGE_TRANSACTION64 {
943 U8 Reserved;
944 U8 ContextSize;
945 U8 DetailsLength;
946 U8 Flags;
947 U32 TransactionContext[2];
948 U32 TransactionDetails[1];
949} MPI2_SGE_TRANSACTION64,
950 *PTR_MPI2_SGE_TRANSACTION64,
951 Mpi2SGETransaction64_t,
952 *pMpi2SGETransaction64_t;
953
954typedef struct _MPI2_SGE_TRANSACTION96 {
955 U8 Reserved;
956 U8 ContextSize;
957 U8 DetailsLength;
958 U8 Flags;
959 U32 TransactionContext[3];
960 U32 TransactionDetails[1];
961} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
962 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
963
964typedef struct _MPI2_SGE_TRANSACTION128 {
965 U8 Reserved;
966 U8 ContextSize;
967 U8 DetailsLength;
968 U8 Flags;
969 U32 TransactionContext[4];
970 U32 TransactionDetails[1];
971} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
972 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
973
974typedef struct _MPI2_SGE_TRANSACTION_UNION {
975 U8 Reserved;
976 U8 ContextSize;
977 U8 DetailsLength;
978 U8 Flags;
979 union {
980 U32 TransactionContext32[1];
981 U32 TransactionContext64[2];
982 U32 TransactionContext96[3];
983 U32 TransactionContext128[4];
984 } u;
985 U32 TransactionDetails[1];
986} MPI2_SGE_TRANSACTION_UNION,
987 *PTR_MPI2_SGE_TRANSACTION_UNION,
988 Mpi2SGETransactionUnion_t,
989 *pMpi2SGETransactionUnion_t;
990
991/****************************************************************************
992* MPI SGE union for IO SGL's - for MPI v2.0 products only
993****************************************************************************/
994
995typedef struct _MPI2_MPI_SGE_IO_UNION {
996 union {
997 MPI2_SGE_SIMPLE_UNION Simple;
998 MPI2_SGE_CHAIN_UNION Chain;
999 } u;
1000} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
1001 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
1002
1003/****************************************************************************
1004* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1005****************************************************************************/
1006
1007typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
1008 union {
1009 MPI2_SGE_SIMPLE_UNION Simple;
1010 MPI2_SGE_TRANSACTION_UNION Transaction;
1011 } u;
1012} MPI2_SGE_TRANS_SIMPLE_UNION,
1013 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
1014 Mpi2SGETransSimpleUnion_t,
1015 *pMpi2SGETransSimpleUnion_t;
1016
1017/****************************************************************************
1018* All MPI SGE types union
1019****************************************************************************/
1020
1021typedef struct _MPI2_MPI_SGE_UNION {
1022 union {
1023 MPI2_SGE_SIMPLE_UNION Simple;
1024 MPI2_SGE_CHAIN_UNION Chain;
1025 MPI2_SGE_TRANSACTION_UNION Transaction;
1026 } u;
1027} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
1028 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
1029
1030/****************************************************************************
1031* MPI SGE field definition and masks
1032****************************************************************************/
1033
1034/*Flags field bit definitions */
1035
1036#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
1037#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
1038#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1039#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1040#define MPI2_SGE_FLAGS_DIRECTION (0x04)
1041#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1042#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1043
1044#define MPI2_SGE_FLAGS_SHIFT (24)
1045
1046#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1047#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1048
1049/*Element Type */
1050
1051#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
1052#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1053#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
1054#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1055
1056/*Address location */
1057
1058#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1059
1060/*Direction */
1061
1062#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1063#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1064
1065#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1066#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1067
1068/*Address Size */
1069
1070#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1071#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1072
1073/*Context Size */
1074
1075#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1076#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1077#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1078#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1079
1080#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1081#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
1082
1083/****************************************************************************
1084* MPI SGE operation Macros
1085****************************************************************************/
1086
1087/*SIMPLE FlagsLength manipulations... */
1088#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1089#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
1090 MPI2_SGE_FLAGS_SHIFT)
1091#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1092#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1093
1094#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
1095 MPI2_SGE_LENGTH(l))
1096
1097#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1098#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1099#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1100 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
1101
1102/*CAUTION - The following are READ-MODIFY-WRITE! */
1103#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1104 MPI2_SGE_SET_FLAGS(f))
1105#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1106 MPI2_SGE_LENGTH(l))
1107
1108#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
1109 MPI2_SGE_CHAIN_OFFSET_SHIFT)
1110
1111/*****************************************************************************
1112*
1113* Fusion-MPT IEEE Scatter Gather Elements
1114*
1115*****************************************************************************/
1116
1117/****************************************************************************
1118* IEEE Simple Element structures
1119****************************************************************************/
1120
1121/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1122typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1123 U32 Address;
1124 U32 FlagsLength;
1125} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1126 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1127
1128typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1129 U64 Address;
1130 U32 Length;
1131 U16 Reserved1;
1132 U8 Reserved2;
1133 U8 Flags;
1134} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1135 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1136
1137typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1138 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1139 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1140} MPI2_IEEE_SGE_SIMPLE_UNION,
1141 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1142 Mpi2IeeeSgeSimpleUnion_t,
1143 *pMpi2IeeeSgeSimpleUnion_t;
1144
1145/****************************************************************************
1146* IEEE Chain Element structures
1147****************************************************************************/
1148
1149/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1150typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1151
1152/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1153typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1154
1155typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1156 MPI2_IEEE_SGE_CHAIN32 Chain32;
1157 MPI2_IEEE_SGE_CHAIN64 Chain64;
1158} MPI2_IEEE_SGE_CHAIN_UNION,
1159 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1160 Mpi2IeeeSgeChainUnion_t,
1161 *pMpi2IeeeSgeChainUnion_t;
1162
1163/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1164typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1165 U64 Address;
1166 U32 Length;
1167 U16 Reserved1;
1168 U8 NextChainOffset;
1169 U8 Flags;
1170} MPI25_IEEE_SGE_CHAIN64,
1171 *PTR_MPI25_IEEE_SGE_CHAIN64,
1172 Mpi25IeeeSgeChain64_t,
1173 *pMpi25IeeeSgeChain64_t;
1174
1175/****************************************************************************
1176* All IEEE SGE types union
1177****************************************************************************/
1178
1179/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1180typedef struct _MPI2_IEEE_SGE_UNION {
1181 union {
1182 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1183 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1184 } u;
1185} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1186 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1187
1188/****************************************************************************
1189* IEEE SGE union for IO SGL's
1190****************************************************************************/
1191
1192typedef union _MPI25_SGE_IO_UNION {
1193 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1194 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1195} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1196 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1197
1198/****************************************************************************
1199* IEEE SGE field definitions and masks
1200****************************************************************************/
1201
1202/*Flags field bit definitions */
1203
1204#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1205#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1206
1207#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1208
1209#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1210
1211/*Element Type */
1212
1213#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1214#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1215
1216/*Next Segment Format */
1217
1218#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1219#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1220#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1221#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1222
1223/*Data Location Address Space */
1224
1225#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1226#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1227#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1228#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1229#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1230#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1231#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1232 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1233#define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02)
1234
1235/****************************************************************************
1236* IEEE SGE operation Macros
1237****************************************************************************/
1238
1239/*SIMPLE FlagsLength manipulations... */
1240#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1241#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1242 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1243#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1244
1245#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1246 MPI2_IEEE32_SGE_LENGTH(l))
1247
1248#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1249 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1250#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1251 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1252#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1253 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1254
1255/*CAUTION - The following are READ-MODIFY-WRITE! */
1256#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1257 MPI2_IEEE32_SGE_SET_FLAGS(f))
1258#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1259 MPI2_IEEE32_SGE_LENGTH(l))
1260
1261/*****************************************************************************
1262*
1263* Fusion-MPT MPI/IEEE Scatter Gather Unions
1264*
1265*****************************************************************************/
1266
1267typedef union _MPI2_SIMPLE_SGE_UNION {
1268 MPI2_SGE_SIMPLE_UNION MpiSimple;
1269 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1270} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1271 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1272
1273typedef union _MPI2_SGE_IO_UNION {
1274 MPI2_SGE_SIMPLE_UNION MpiSimple;
1275 MPI2_SGE_CHAIN_UNION MpiChain;
1276 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1277 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1278} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1279 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1280
1281/****************************************************************************
1282*
1283* Values for SGLFlags field, used in many request messages with an SGL
1284*
1285****************************************************************************/
1286
1287/*values for MPI SGL Data Location Address Space subfield */
1288#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1289#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1290#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1291#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1292#define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1293#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1294/*values for SGL Type subfield */
1295#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1296#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1297#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1298#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1299
1300#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2000-2015 Avago Technologies. All rights reserved.
4 *
5 *
6 * Name: mpi2.h
7 * Title: MPI Message independent structures and definitions
8 * including System Interface Register Set and
9 * scatter/gather formats.
10 * Creation Date: June 21, 2006
11 *
12 * mpi2.h Version: 02.00.48
13 *
14 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
15 * prefix are for use only on MPI v2.5 products, and must not be used
16 * with MPI v2.0 products. Unless otherwise noted, names beginning with
17 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
18 *
19 * Version History
20 * ---------------
21 *
22 * Date Version Description
23 * -------- -------- ------------------------------------------------------
24 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
25 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
27 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Moved ReplyPostHostIndex register to offset 0x6C of the
29 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
30 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
31 * Added union of request descriptors.
32 * Added union of reply descriptors.
33 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
34 * Added define for MPI2_VERSION_02_00.
35 * Fixed the size of the FunctionDependent5 field in the
36 * MPI2_DEFAULT_REPLY structure.
37 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
38 * Removed the MPI-defined Fault Codes and extended the
39 * product specific codes up to 0xEFFF.
40 * Added a sixth key value for the WriteSequence register
41 * and changed the flush value to 0x0.
42 * Added message function codes for Diagnostic Buffer Post
43 * and Diagnsotic Release.
44 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
45 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
46 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
48 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
49 * Added #defines for marking a reply descriptor as unused.
50 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
51 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
52 * Moved LUN field defines from mpi2_init.h.
53 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
54 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
55 * In all request and reply descriptors, replaced VF_ID
56 * field with MSIxIndex field.
57 * Removed DevHandle field from
58 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
59 * bytes reserved.
60 * Added RAID Accelerator functionality.
61 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
62 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
63 * Added MSI-x index mask and shift for Reply Post Host
64 * Index register.
65 * Added function code for Host Based Discovery Action.
66 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
67 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
68 * Added defines for product-specific range of message
69 * function codes, 0xF0 to 0xFF.
70 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
71 * Added alternative defines for the SGE Direction bit.
72 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
73 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
74 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
75 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
76 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
77 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
80 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
81 * Incorporating additions for MPI v2.5.
82 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
83 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
84 * Added Hard Reset delay timings.
85 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
88 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
89 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
90 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
91 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
92 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
93 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
94 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT
95 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
96 * 11-18-14 02.00.36 Updated copyright information.
97 * Bumped MPI2_HEADER_VERSION_UNIT.
98 * 03-16-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT.
99 * Added Scratchpad registers to
100 * MPI2_SYSTEM_INTERFACE_REGS.
101 * Added MPI2_DIAG_SBR_RELOAD.
102 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
103 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT.
104 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
105 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
106 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
107 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines
108 * to be unique within first 32 characters.
109 * Removed AHCI support.
110 * Removed SOP support.
111 * Bumped MPI2_HEADER_VERSION_UNIT.
112 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT.
113 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT.
114 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT.
115 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT.
116 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT.
117 * --------------------------------------------------------------------------
118 */
119
120#ifndef MPI2_H
121#define MPI2_H
122
123/*****************************************************************************
124*
125* MPI Version Definitions
126*
127*****************************************************************************/
128
129#define MPI2_VERSION_MAJOR_MASK (0xFF00)
130#define MPI2_VERSION_MAJOR_SHIFT (8)
131#define MPI2_VERSION_MINOR_MASK (0x00FF)
132#define MPI2_VERSION_MINOR_SHIFT (0)
133
134/*major version for all MPI v2.x */
135#define MPI2_VERSION_MAJOR (0x02)
136
137/*minor version for MPI v2.0 compatible products */
138#define MPI2_VERSION_MINOR (0x00)
139#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
140 MPI2_VERSION_MINOR)
141#define MPI2_VERSION_02_00 (0x0200)
142
143/*minor version for MPI v2.5 compatible products */
144#define MPI25_VERSION_MINOR (0x05)
145#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
146 MPI25_VERSION_MINOR)
147#define MPI2_VERSION_02_05 (0x0205)
148
149/*minor version for MPI v2.6 compatible products */
150#define MPI26_VERSION_MINOR (0x06)
151#define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
152 MPI26_VERSION_MINOR)
153#define MPI2_VERSION_02_06 (0x0206)
154
155/*Unit and Dev versioning for this MPI header set */
156#define MPI2_HEADER_VERSION_UNIT (0x30)
157#define MPI2_HEADER_VERSION_DEV (0x00)
158#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
159#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
160#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
161#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
162#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
163 MPI2_HEADER_VERSION_DEV)
164
165/*****************************************************************************
166*
167* IOC State Definitions
168*
169*****************************************************************************/
170
171#define MPI2_IOC_STATE_RESET (0x00000000)
172#define MPI2_IOC_STATE_READY (0x10000000)
173#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
174#define MPI2_IOC_STATE_FAULT (0x40000000)
175
176#define MPI2_IOC_STATE_MASK (0xF0000000)
177#define MPI2_IOC_STATE_SHIFT (28)
178
179/*Fault state range for prodcut specific codes */
180#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
181#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
182
183/*****************************************************************************
184*
185* System Interface Register Definitions
186*
187*****************************************************************************/
188
189typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
190 U32 Doorbell; /*0x00 */
191 U32 WriteSequence; /*0x04 */
192 U32 HostDiagnostic; /*0x08 */
193 U32 Reserved1; /*0x0C */
194 U32 DiagRWData; /*0x10 */
195 U32 DiagRWAddressLow; /*0x14 */
196 U32 DiagRWAddressHigh; /*0x18 */
197 U32 Reserved2[5]; /*0x1C */
198 U32 HostInterruptStatus; /*0x30 */
199 U32 HostInterruptMask; /*0x34 */
200 U32 DCRData; /*0x38 */
201 U32 DCRAddress; /*0x3C */
202 U32 Reserved3[2]; /*0x40 */
203 U32 ReplyFreeHostIndex; /*0x48 */
204 U32 Reserved4[8]; /*0x4C */
205 U32 ReplyPostHostIndex; /*0x6C */
206 U32 Reserved5; /*0x70 */
207 U32 HCBSize; /*0x74 */
208 U32 HCBAddressLow; /*0x78 */
209 U32 HCBAddressHigh; /*0x7C */
210 U32 Reserved6[12]; /*0x80 */
211 U32 Scratchpad[4]; /*0xB0 */
212 U32 RequestDescriptorPostLow; /*0xC0 */
213 U32 RequestDescriptorPostHigh; /*0xC4 */
214 U32 AtomicRequestDescriptorPost;/*0xC8 */
215 U32 Reserved7[13]; /*0xCC */
216} MPI2_SYSTEM_INTERFACE_REGS,
217 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
218 Mpi2SystemInterfaceRegs_t,
219 *pMpi2SystemInterfaceRegs_t;
220
221/*
222 *Defines for working with the Doorbell register.
223 */
224#define MPI2_DOORBELL_OFFSET (0x00000000)
225
226/*IOC --> System values */
227#define MPI2_DOORBELL_USED (0x08000000)
228#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
229#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
230#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
231#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
232
233/*System --> IOC values */
234#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
235#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
236#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
237#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
238
239/*
240 *Defines for the WriteSequence register
241 */
242#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
243#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
244#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
245#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
246#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
247#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
248#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
249#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
250#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
251
252/*
253 *Defines for the HostDiagnostic register
254 */
255#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
256
257#define MPI2_DIAG_SBR_RELOAD (0x00002000)
258
259#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
260#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
261#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
262
263/* Defines for V7A/V7R HostDiagnostic Register */
264#define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
265#define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
266#define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
267#define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
268
269#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
270#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
271#define MPI2_DIAG_HCB_MODE (0x00000100)
272#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
273#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
274#define MPI2_DIAG_RESET_HISTORY (0x00000020)
275#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
276#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
277#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
278
279/*
280 *Offsets for DiagRWData and address
281 */
282#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
283#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
284#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
285
286/*
287 *Defines for the HostInterruptStatus register
288 */
289#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
290#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
291#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
292#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
293#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
294#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
295#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
296
297/*
298 *Defines for the HostInterruptMask register
299 */
300#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
301#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
302#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
303#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
304#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
305#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
306
307/*
308 *Offsets for DCRData and address
309 */
310#define MPI2_DCR_DATA_OFFSET (0x00000038)
311#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
312
313/*
314 *Offset for the Reply Free Queue
315 */
316#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
317
318/*
319 *Defines for the Reply Descriptor Post Queue
320 */
321#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
322#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
323#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
324#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
325#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
326
327
328/*
329 *Defines for the HCBSize and address
330 */
331#define MPI2_HCB_SIZE_OFFSET (0x00000074)
332#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
333#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
334
335#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
336#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
337
338/*
339 *Offsets for the Scratchpad registers
340 */
341#define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
342#define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
343#define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
344#define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
345
346/*
347 *Offsets for the Request Descriptor Post Queue
348 */
349#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
350#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
351#define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
352
353/*Hard Reset delay timings */
354#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
355#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
356#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
357
358/*****************************************************************************
359*
360* Message Descriptors
361*
362*****************************************************************************/
363
364/*Request Descriptors */
365
366/*Default Request Descriptor */
367typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
368 U8 RequestFlags; /*0x00 */
369 U8 MSIxIndex; /*0x01 */
370 U16 SMID; /*0x02 */
371 U16 LMID; /*0x04 */
372 U16 DescriptorTypeDependent; /*0x06 */
373} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
374 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
375 Mpi2DefaultRequestDescriptor_t,
376 *pMpi2DefaultRequestDescriptor_t;
377
378/*defines for the RequestFlags field */
379#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
380#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1)
381#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
382#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
383#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
384#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
385#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
386#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
387#define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
388
389#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
390
391/*High Priority Request Descriptor */
392typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
393 U8 RequestFlags; /*0x00 */
394 U8 MSIxIndex; /*0x01 */
395 U16 SMID; /*0x02 */
396 U16 LMID; /*0x04 */
397 U16 Reserved1; /*0x06 */
398} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
399 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
400 Mpi2HighPriorityRequestDescriptor_t,
401 *pMpi2HighPriorityRequestDescriptor_t;
402
403/*SCSI IO Request Descriptor */
404typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
405 U8 RequestFlags; /*0x00 */
406 U8 MSIxIndex; /*0x01 */
407 U16 SMID; /*0x02 */
408 U16 LMID; /*0x04 */
409 U16 DevHandle; /*0x06 */
410} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
411 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
412 Mpi2SCSIIORequestDescriptor_t,
413 *pMpi2SCSIIORequestDescriptor_t;
414
415/*SCSI Target Request Descriptor */
416typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
417 U8 RequestFlags; /*0x00 */
418 U8 MSIxIndex; /*0x01 */
419 U16 SMID; /*0x02 */
420 U16 LMID; /*0x04 */
421 U16 IoIndex; /*0x06 */
422} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
423 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
424 Mpi2SCSITargetRequestDescriptor_t,
425 *pMpi2SCSITargetRequestDescriptor_t;
426
427/*RAID Accelerator Request Descriptor */
428typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
429 U8 RequestFlags; /*0x00 */
430 U8 MSIxIndex; /*0x01 */
431 U16 SMID; /*0x02 */
432 U16 LMID; /*0x04 */
433 U16 Reserved; /*0x06 */
434} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
435 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
436 Mpi2RAIDAcceleratorRequestDescriptor_t,
437 *pMpi2RAIDAcceleratorRequestDescriptor_t;
438
439/*Fast Path SCSI IO Request Descriptor */
440typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
441 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
442 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
443 Mpi25FastPathSCSIIORequestDescriptor_t,
444 *pMpi25FastPathSCSIIORequestDescriptor_t;
445
446/*PCIe Encapsulated Request Descriptor */
447typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
448 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
449 *PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
450 Mpi26PCIeEncapsulatedRequestDescriptor_t,
451 *pMpi26PCIeEncapsulatedRequestDescriptor_t;
452
453/*union of Request Descriptors */
454typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
455 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
456 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
457 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
458 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
459 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
460 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
461 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated;
462 U64 Words;
463} MPI2_REQUEST_DESCRIPTOR_UNION,
464 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
465 Mpi2RequestDescriptorUnion_t,
466 *pMpi2RequestDescriptorUnion_t;
467
468/*Atomic Request Descriptors */
469
470/*
471 * All Atomic Request Descriptors have the same format, so the following
472 * structure is used for all Atomic Request Descriptors:
473 * Atomic Default Request Descriptor
474 * Atomic High Priority Request Descriptor
475 * Atomic SCSI IO Request Descriptor
476 * Atomic SCSI Target Request Descriptor
477 * Atomic RAID Accelerator Request Descriptor
478 * Atomic Fast Path SCSI IO Request Descriptor
479 * Atomic PCIe Encapsulated Request Descriptor
480 */
481
482/*Atomic Request Descriptor */
483typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR {
484 U8 RequestFlags; /* 0x00 */
485 U8 MSIxIndex; /* 0x01 */
486 U16 SMID; /* 0x02 */
487} MPI26_ATOMIC_REQUEST_DESCRIPTOR,
488 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
489 Mpi26AtomicRequestDescriptor_t,
490 *pMpi26AtomicRequestDescriptor_t;
491
492/*for the RequestFlags field, use the same
493 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR
494 */
495
496/*Reply Descriptors */
497
498/*Default Reply Descriptor */
499typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
500 U8 ReplyFlags; /*0x00 */
501 U8 MSIxIndex; /*0x01 */
502 U16 DescriptorTypeDependent1; /*0x02 */
503 U32 DescriptorTypeDependent2; /*0x04 */
504} MPI2_DEFAULT_REPLY_DESCRIPTOR,
505 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
506 Mpi2DefaultReplyDescriptor_t,
507 *pMpi2DefaultReplyDescriptor_t;
508
509/*defines for the ReplyFlags field */
510#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
511#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
512#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
513#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
514#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
515#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
516#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
517#define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
518#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
519
520/*values for marking a reply descriptor as unused */
521#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
522#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
523
524/*Address Reply Descriptor */
525typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
526 U8 ReplyFlags; /*0x00 */
527 U8 MSIxIndex; /*0x01 */
528 U16 SMID; /*0x02 */
529 U32 ReplyFrameAddress; /*0x04 */
530} MPI2_ADDRESS_REPLY_DESCRIPTOR,
531 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
532 Mpi2AddressReplyDescriptor_t,
533 *pMpi2AddressReplyDescriptor_t;
534
535#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
536
537/*SCSI IO Success Reply Descriptor */
538typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
539 U8 ReplyFlags; /*0x00 */
540 U8 MSIxIndex; /*0x01 */
541 U16 SMID; /*0x02 */
542 U16 TaskTag; /*0x04 */
543 U16 Reserved1; /*0x06 */
544} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
545 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
546 Mpi2SCSIIOSuccessReplyDescriptor_t,
547 *pMpi2SCSIIOSuccessReplyDescriptor_t;
548
549/*TargetAssist Success Reply Descriptor */
550typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
551 U8 ReplyFlags; /*0x00 */
552 U8 MSIxIndex; /*0x01 */
553 U16 SMID; /*0x02 */
554 U8 SequenceNumber; /*0x04 */
555 U8 Reserved1; /*0x05 */
556 U16 IoIndex; /*0x06 */
557} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
558 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
559 Mpi2TargetAssistSuccessReplyDescriptor_t,
560 *pMpi2TargetAssistSuccessReplyDescriptor_t;
561
562/*Target Command Buffer Reply Descriptor */
563typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
564 U8 ReplyFlags; /*0x00 */
565 U8 MSIxIndex; /*0x01 */
566 U8 VP_ID; /*0x02 */
567 U8 Flags; /*0x03 */
568 U16 InitiatorDevHandle; /*0x04 */
569 U16 IoIndex; /*0x06 */
570} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
571 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
572 Mpi2TargetCommandBufferReplyDescriptor_t,
573 *pMpi2TargetCommandBufferReplyDescriptor_t;
574
575/*defines for Flags field */
576#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
577
578/*RAID Accelerator Success Reply Descriptor */
579typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
580 U8 ReplyFlags; /*0x00 */
581 U8 MSIxIndex; /*0x01 */
582 U16 SMID; /*0x02 */
583 U32 Reserved; /*0x04 */
584} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
585 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
586 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
587 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
588
589/*Fast Path SCSI IO Success Reply Descriptor */
590typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
591 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
592 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
593 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
594 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
595
596/*PCIe Encapsulated Success Reply Descriptor */
597typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
598 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
599 *PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
600 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t,
601 *pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t;
602
603/*union of Reply Descriptors */
604typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
605 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
606 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
607 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
608 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
609 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
610 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
611 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
612 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR
613 PCIeEncapsulatedSuccess;
614 U64 Words;
615} MPI2_REPLY_DESCRIPTORS_UNION,
616 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
617 Mpi2ReplyDescriptorsUnion_t,
618 *pMpi2ReplyDescriptorsUnion_t;
619
620/*****************************************************************************
621*
622* Message Functions
623*
624*****************************************************************************/
625
626#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
627#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
628#define MPI2_FUNCTION_IOC_INIT (0x02)
629#define MPI2_FUNCTION_IOC_FACTS (0x03)
630#define MPI2_FUNCTION_CONFIG (0x04)
631#define MPI2_FUNCTION_PORT_FACTS (0x05)
632#define MPI2_FUNCTION_PORT_ENABLE (0x06)
633#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
634#define MPI2_FUNCTION_EVENT_ACK (0x08)
635#define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
636#define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
637#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
638#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
639#define MPI2_FUNCTION_FW_UPLOAD (0x12)
640#define MPI2_FUNCTION_RAID_ACTION (0x15)
641#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
642#define MPI2_FUNCTION_TOOLBOX (0x17)
643#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
644#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
645#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
646#define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B)
647#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
648#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
649#define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
650#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
651#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
652#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
653#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
654#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
655#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
656#define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33)
657#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
658#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
659
660/*Doorbell functions */
661#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
662#define MPI2_FUNCTION_HANDSHAKE (0x42)
663
664/*****************************************************************************
665*
666* IOC Status Values
667*
668*****************************************************************************/
669
670/*mask for IOCStatus status value */
671#define MPI2_IOCSTATUS_MASK (0x7FFF)
672
673/****************************************************************************
674* Common IOCStatus values for all replies
675****************************************************************************/
676
677#define MPI2_IOCSTATUS_SUCCESS (0x0000)
678#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
679#define MPI2_IOCSTATUS_BUSY (0x0002)
680#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
681#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
682#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
683#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
684#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
685#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
686#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
687#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
688
689/****************************************************************************
690* Config IOCStatus values
691****************************************************************************/
692
693#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
694#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
695#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
696#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
697#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
698#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
699
700/****************************************************************************
701* SCSI IO Reply
702****************************************************************************/
703
704#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
705#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
706#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
707#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
708#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
709#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
710#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
711#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
712#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
713#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
714#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
715#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
716
717/****************************************************************************
718* For use by SCSI Initiator and SCSI Target end-to-end data protection
719****************************************************************************/
720
721#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
722#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
723#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
724
725/****************************************************************************
726* SCSI Target values
727****************************************************************************/
728
729#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
730#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
731#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
732#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
733#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
734#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
735#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
736#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
737#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
738#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
739
740/****************************************************************************
741* Serial Attached SCSI values
742****************************************************************************/
743
744#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
745#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
746
747/****************************************************************************
748* Diagnostic Buffer Post / Diagnostic Release values
749****************************************************************************/
750
751#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
752
753/****************************************************************************
754* RAID Accelerator values
755****************************************************************************/
756
757#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
758
759/****************************************************************************
760* IOCStatus flag to indicate that log info is available
761****************************************************************************/
762
763#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
764
765/****************************************************************************
766* IOCLogInfo Types
767****************************************************************************/
768
769#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
770#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
771#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
772#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
773#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
774#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
775#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
776#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
777
778/*****************************************************************************
779*
780* Standard Message Structures
781*
782*****************************************************************************/
783
784/****************************************************************************
785*Request Message Header for all request messages
786****************************************************************************/
787
788typedef struct _MPI2_REQUEST_HEADER {
789 U16 FunctionDependent1; /*0x00 */
790 U8 ChainOffset; /*0x02 */
791 U8 Function; /*0x03 */
792 U16 FunctionDependent2; /*0x04 */
793 U8 FunctionDependent3; /*0x06 */
794 U8 MsgFlags; /*0x07 */
795 U8 VP_ID; /*0x08 */
796 U8 VF_ID; /*0x09 */
797 U16 Reserved1; /*0x0A */
798} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
799 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
800
801/****************************************************************************
802* Default Reply
803****************************************************************************/
804
805typedef struct _MPI2_DEFAULT_REPLY {
806 U16 FunctionDependent1; /*0x00 */
807 U8 MsgLength; /*0x02 */
808 U8 Function; /*0x03 */
809 U16 FunctionDependent2; /*0x04 */
810 U8 FunctionDependent3; /*0x06 */
811 U8 MsgFlags; /*0x07 */
812 U8 VP_ID; /*0x08 */
813 U8 VF_ID; /*0x09 */
814 U16 Reserved1; /*0x0A */
815 U16 FunctionDependent5; /*0x0C */
816 U16 IOCStatus; /*0x0E */
817 U32 IOCLogInfo; /*0x10 */
818} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
819 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
820
821/*common version structure/union used in messages and configuration pages */
822
823typedef struct _MPI2_VERSION_STRUCT {
824 U8 Dev; /*0x00 */
825 U8 Unit; /*0x01 */
826 U8 Minor; /*0x02 */
827 U8 Major; /*0x03 */
828} MPI2_VERSION_STRUCT;
829
830typedef union _MPI2_VERSION_UNION {
831 MPI2_VERSION_STRUCT Struct;
832 U32 Word;
833} MPI2_VERSION_UNION;
834
835/*LUN field defines, common to many structures */
836#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
837#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
838#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
839#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
840#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
841#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
842
843/*****************************************************************************
844*
845* Fusion-MPT MPI Scatter Gather Elements
846*
847*****************************************************************************/
848
849/****************************************************************************
850* MPI Simple Element structures
851****************************************************************************/
852
853typedef struct _MPI2_SGE_SIMPLE32 {
854 U32 FlagsLength;
855 U32 Address;
856} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
857 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
858
859typedef struct _MPI2_SGE_SIMPLE64 {
860 U32 FlagsLength;
861 U64 Address;
862} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
863 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
864
865typedef struct _MPI2_SGE_SIMPLE_UNION {
866 U32 FlagsLength;
867 union {
868 U32 Address32;
869 U64 Address64;
870 } u;
871} MPI2_SGE_SIMPLE_UNION,
872 *PTR_MPI2_SGE_SIMPLE_UNION,
873 Mpi2SGESimpleUnion_t,
874 *pMpi2SGESimpleUnion_t;
875
876/****************************************************************************
877* MPI Chain Element structures - for MPI v2.0 products only
878****************************************************************************/
879
880typedef struct _MPI2_SGE_CHAIN32 {
881 U16 Length;
882 U8 NextChainOffset;
883 U8 Flags;
884 U32 Address;
885} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
886 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
887
888typedef struct _MPI2_SGE_CHAIN64 {
889 U16 Length;
890 U8 NextChainOffset;
891 U8 Flags;
892 U64 Address;
893} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
894 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
895
896typedef struct _MPI2_SGE_CHAIN_UNION {
897 U16 Length;
898 U8 NextChainOffset;
899 U8 Flags;
900 union {
901 U32 Address32;
902 U64 Address64;
903 } u;
904} MPI2_SGE_CHAIN_UNION,
905 *PTR_MPI2_SGE_CHAIN_UNION,
906 Mpi2SGEChainUnion_t,
907 *pMpi2SGEChainUnion_t;
908
909/****************************************************************************
910* MPI Transaction Context Element structures - for MPI v2.0 products only
911****************************************************************************/
912
913typedef struct _MPI2_SGE_TRANSACTION32 {
914 U8 Reserved;
915 U8 ContextSize;
916 U8 DetailsLength;
917 U8 Flags;
918 U32 TransactionContext[1];
919 U32 TransactionDetails[1];
920} MPI2_SGE_TRANSACTION32,
921 *PTR_MPI2_SGE_TRANSACTION32,
922 Mpi2SGETransaction32_t,
923 *pMpi2SGETransaction32_t;
924
925typedef struct _MPI2_SGE_TRANSACTION64 {
926 U8 Reserved;
927 U8 ContextSize;
928 U8 DetailsLength;
929 U8 Flags;
930 U32 TransactionContext[2];
931 U32 TransactionDetails[1];
932} MPI2_SGE_TRANSACTION64,
933 *PTR_MPI2_SGE_TRANSACTION64,
934 Mpi2SGETransaction64_t,
935 *pMpi2SGETransaction64_t;
936
937typedef struct _MPI2_SGE_TRANSACTION96 {
938 U8 Reserved;
939 U8 ContextSize;
940 U8 DetailsLength;
941 U8 Flags;
942 U32 TransactionContext[3];
943 U32 TransactionDetails[1];
944} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
945 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
946
947typedef struct _MPI2_SGE_TRANSACTION128 {
948 U8 Reserved;
949 U8 ContextSize;
950 U8 DetailsLength;
951 U8 Flags;
952 U32 TransactionContext[4];
953 U32 TransactionDetails[1];
954} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
955 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
956
957typedef struct _MPI2_SGE_TRANSACTION_UNION {
958 U8 Reserved;
959 U8 ContextSize;
960 U8 DetailsLength;
961 U8 Flags;
962 union {
963 U32 TransactionContext32[1];
964 U32 TransactionContext64[2];
965 U32 TransactionContext96[3];
966 U32 TransactionContext128[4];
967 } u;
968 U32 TransactionDetails[1];
969} MPI2_SGE_TRANSACTION_UNION,
970 *PTR_MPI2_SGE_TRANSACTION_UNION,
971 Mpi2SGETransactionUnion_t,
972 *pMpi2SGETransactionUnion_t;
973
974/****************************************************************************
975* MPI SGE union for IO SGL's - for MPI v2.0 products only
976****************************************************************************/
977
978typedef struct _MPI2_MPI_SGE_IO_UNION {
979 union {
980 MPI2_SGE_SIMPLE_UNION Simple;
981 MPI2_SGE_CHAIN_UNION Chain;
982 } u;
983} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
984 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
985
986/****************************************************************************
987* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
988****************************************************************************/
989
990typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
991 union {
992 MPI2_SGE_SIMPLE_UNION Simple;
993 MPI2_SGE_TRANSACTION_UNION Transaction;
994 } u;
995} MPI2_SGE_TRANS_SIMPLE_UNION,
996 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
997 Mpi2SGETransSimpleUnion_t,
998 *pMpi2SGETransSimpleUnion_t;
999
1000/****************************************************************************
1001* All MPI SGE types union
1002****************************************************************************/
1003
1004typedef struct _MPI2_MPI_SGE_UNION {
1005 union {
1006 MPI2_SGE_SIMPLE_UNION Simple;
1007 MPI2_SGE_CHAIN_UNION Chain;
1008 MPI2_SGE_TRANSACTION_UNION Transaction;
1009 } u;
1010} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
1011 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
1012
1013/****************************************************************************
1014* MPI SGE field definition and masks
1015****************************************************************************/
1016
1017/*Flags field bit definitions */
1018
1019#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
1020#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
1021#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1022#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1023#define MPI2_SGE_FLAGS_DIRECTION (0x04)
1024#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1025#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1026
1027#define MPI2_SGE_FLAGS_SHIFT (24)
1028
1029#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1030#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1031
1032/*Element Type */
1033
1034#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
1035#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1036#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
1037#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1038
1039/*Address location */
1040
1041#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1042
1043/*Direction */
1044
1045#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1046#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1047
1048#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1049#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1050
1051/*Address Size */
1052
1053#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1054#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1055
1056/*Context Size */
1057
1058#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1059#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1060#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1061#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1062
1063#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1064#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
1065
1066/****************************************************************************
1067* MPI SGE operation Macros
1068****************************************************************************/
1069
1070/*SIMPLE FlagsLength manipulations... */
1071#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1072#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
1073 MPI2_SGE_FLAGS_SHIFT)
1074#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1075#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1076
1077#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
1078 MPI2_SGE_LENGTH(l))
1079
1080#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1081#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1082#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1083 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
1084
1085/*CAUTION - The following are READ-MODIFY-WRITE! */
1086#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1087 MPI2_SGE_SET_FLAGS(f))
1088#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1089 MPI2_SGE_LENGTH(l))
1090
1091#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
1092 MPI2_SGE_CHAIN_OFFSET_SHIFT)
1093
1094/*****************************************************************************
1095*
1096* Fusion-MPT IEEE Scatter Gather Elements
1097*
1098*****************************************************************************/
1099
1100/****************************************************************************
1101* IEEE Simple Element structures
1102****************************************************************************/
1103
1104/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1105typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1106 U32 Address;
1107 U32 FlagsLength;
1108} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1109 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1110
1111typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1112 U64 Address;
1113 U32 Length;
1114 U16 Reserved1;
1115 U8 Reserved2;
1116 U8 Flags;
1117} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1118 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1119
1120typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1121 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1122 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1123} MPI2_IEEE_SGE_SIMPLE_UNION,
1124 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1125 Mpi2IeeeSgeSimpleUnion_t,
1126 *pMpi2IeeeSgeSimpleUnion_t;
1127
1128/****************************************************************************
1129* IEEE Chain Element structures
1130****************************************************************************/
1131
1132/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1133typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1134
1135/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1136typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1137
1138typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1139 MPI2_IEEE_SGE_CHAIN32 Chain32;
1140 MPI2_IEEE_SGE_CHAIN64 Chain64;
1141} MPI2_IEEE_SGE_CHAIN_UNION,
1142 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1143 Mpi2IeeeSgeChainUnion_t,
1144 *pMpi2IeeeSgeChainUnion_t;
1145
1146/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1147typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1148 U64 Address;
1149 U32 Length;
1150 U16 Reserved1;
1151 U8 NextChainOffset;
1152 U8 Flags;
1153} MPI25_IEEE_SGE_CHAIN64,
1154 *PTR_MPI25_IEEE_SGE_CHAIN64,
1155 Mpi25IeeeSgeChain64_t,
1156 *pMpi25IeeeSgeChain64_t;
1157
1158/****************************************************************************
1159* All IEEE SGE types union
1160****************************************************************************/
1161
1162/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1163typedef struct _MPI2_IEEE_SGE_UNION {
1164 union {
1165 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1166 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1167 } u;
1168} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1169 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1170
1171/****************************************************************************
1172* IEEE SGE union for IO SGL's
1173****************************************************************************/
1174
1175typedef union _MPI25_SGE_IO_UNION {
1176 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1177 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1178} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1179 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1180
1181/****************************************************************************
1182* IEEE SGE field definitions and masks
1183****************************************************************************/
1184
1185/*Flags field bit definitions */
1186
1187#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1188#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1189
1190#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1191
1192#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1193
1194/*Element Type */
1195
1196#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1197#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1198
1199/*Next Segment Format */
1200
1201#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1202#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1203#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1204#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1205
1206/*Data Location Address Space */
1207
1208#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1209#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1210#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1211#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1212#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1213#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1214#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1215 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1216#define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02)
1217
1218/****************************************************************************
1219* IEEE SGE operation Macros
1220****************************************************************************/
1221
1222/*SIMPLE FlagsLength manipulations... */
1223#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1224#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1225 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1226#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1227
1228#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1229 MPI2_IEEE32_SGE_LENGTH(l))
1230
1231#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1232 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1233#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1234 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1235#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1236 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1237
1238/*CAUTION - The following are READ-MODIFY-WRITE! */
1239#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1240 MPI2_IEEE32_SGE_SET_FLAGS(f))
1241#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1242 MPI2_IEEE32_SGE_LENGTH(l))
1243
1244/*****************************************************************************
1245*
1246* Fusion-MPT MPI/IEEE Scatter Gather Unions
1247*
1248*****************************************************************************/
1249
1250typedef union _MPI2_SIMPLE_SGE_UNION {
1251 MPI2_SGE_SIMPLE_UNION MpiSimple;
1252 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1253} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1254 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1255
1256typedef union _MPI2_SGE_IO_UNION {
1257 MPI2_SGE_SIMPLE_UNION MpiSimple;
1258 MPI2_SGE_CHAIN_UNION MpiChain;
1259 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1260 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1261} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1262 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1263
1264/****************************************************************************
1265*
1266* Values for SGLFlags field, used in many request messages with an SGL
1267*
1268****************************************************************************/
1269
1270/*values for MPI SGL Data Location Address Space subfield */
1271#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1272#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1273#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1274#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1275#define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1276#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1277/*values for SGL Type subfield */
1278#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1279#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1280#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1281#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1282
1283#endif